2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3 * Copyright 2005 Stephane Marchesin
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
35 #include "drm_sarea.h"
37 #include "nouveau_drv.h"
38 #include "nouveau_pm.h"
39 #include "nouveau_mm.h"
40 #include "nouveau_vm.h"
43 * NV10-NV40 tiling helpers
47 nv10_mem_update_tile_region(struct drm_device *dev,
48 struct nouveau_tile_reg *tile, uint32_t addr,
49 uint32_t size, uint32_t pitch, uint32_t flags)
51 struct drm_nouveau_private *dev_priv = dev->dev_private;
52 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
53 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
54 int i = tile - dev_priv->tile.reg, j;
57 nouveau_fence_unref(&tile->fence);
60 pfb->free_tile_region(dev, i);
63 pfb->init_tile_region(dev, i, addr, size, pitch, flags);
65 spin_lock_irqsave(&dev_priv->context_switch_lock, save);
66 pfifo->reassign(dev, false);
67 pfifo->cache_pull(dev, false);
69 nouveau_wait_for_idle(dev);
71 pfb->set_tile_region(dev, i);
72 for (j = 0; j < NVOBJ_ENGINE_NR; j++) {
73 if (dev_priv->eng[j] && dev_priv->eng[j]->set_tile_region)
74 dev_priv->eng[j]->set_tile_region(dev, i);
77 pfifo->cache_pull(dev, true);
78 pfifo->reassign(dev, true);
79 spin_unlock_irqrestore(&dev_priv->context_switch_lock, save);
82 static struct nouveau_tile_reg *
83 nv10_mem_get_tile_region(struct drm_device *dev, int i)
85 struct drm_nouveau_private *dev_priv = dev->dev_private;
86 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
88 spin_lock(&dev_priv->tile.lock);
91 (!tile->fence || nouveau_fence_signalled(tile->fence)))
96 spin_unlock(&dev_priv->tile.lock);
101 nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile,
102 struct nouveau_fence *fence)
104 struct drm_nouveau_private *dev_priv = dev->dev_private;
107 spin_lock(&dev_priv->tile.lock);
109 /* Mark it as pending. */
111 nouveau_fence_ref(fence);
115 spin_unlock(&dev_priv->tile.lock);
119 struct nouveau_tile_reg *
120 nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
121 uint32_t pitch, uint32_t flags)
123 struct drm_nouveau_private *dev_priv = dev->dev_private;
124 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
125 struct nouveau_tile_reg *tile, *found = NULL;
128 for (i = 0; i < pfb->num_tiles; i++) {
129 tile = nv10_mem_get_tile_region(dev, i);
131 if (pitch && !found) {
135 } else if (tile && tile->pitch) {
136 /* Kill an unused tile region. */
137 nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0);
140 nv10_mem_put_tile_region(dev, tile, NULL);
144 nv10_mem_update_tile_region(dev, found, addr, size,
153 nouveau_mem_vram_fini(struct drm_device *dev)
155 struct drm_nouveau_private *dev_priv = dev->dev_private;
157 ttm_bo_device_release(&dev_priv->ttm.bdev);
159 nouveau_ttm_global_release(dev_priv);
161 if (dev_priv->fb_mtrr >= 0) {
162 drm_mtrr_del(dev_priv->fb_mtrr,
163 pci_resource_start(dev->pdev, 1),
164 pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
165 dev_priv->fb_mtrr = -1;
170 nouveau_mem_gart_fini(struct drm_device *dev)
172 nouveau_sgdma_takedown(dev);
174 if (drm_core_has_AGP(dev) && dev->agp) {
175 struct drm_agp_mem *entry, *tempe;
177 /* Remove AGP resources, but leave dev->agp
178 intact until drv_cleanup is called. */
179 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
181 drm_unbind_agp(entry->memory);
182 drm_free_agp(entry->memory, entry->pages);
185 INIT_LIST_HEAD(&dev->agp->memory);
187 if (dev->agp->acquired)
188 drm_agp_release(dev);
190 dev->agp->acquired = 0;
191 dev->agp->enabled = 0;
196 nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
198 if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK))
206 get_agp_mode(struct drm_device *dev, unsigned long mode)
208 struct drm_nouveau_private *dev_priv = dev->dev_private;
211 * FW seems to be broken on nv18, it makes the card lock up
214 if (dev_priv->chipset == 0x18)
215 mode &= ~PCI_AGP_COMMAND_FW;
218 * AGP mode set in the command line.
220 if (nouveau_agpmode > 0) {
221 bool agpv3 = mode & 0x8;
222 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
224 mode = (mode & ~0x7) | (rate & 0x7);
232 nouveau_mem_reset_agp(struct drm_device *dev)
235 uint32_t saved_pci_nv_1, pmc_enable;
238 /* First of all, disable fast writes, otherwise if it's
239 * already enabled in the AGP bridge and we disable the card's
240 * AGP controller we might be locking ourselves out of it. */
241 if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
242 dev->agp->mode) & PCI_AGP_COMMAND_FW) {
243 struct drm_agp_info info;
244 struct drm_agp_mode mode;
246 ret = drm_agp_info(dev, &info);
250 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
251 ret = drm_agp_enable(dev, mode);
256 saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
258 /* clear busmaster bit */
259 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
261 nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
263 /* power cycle pgraph, if enabled */
264 pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
265 if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
266 nv_wr32(dev, NV03_PMC_ENABLE,
267 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
268 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
269 NV_PMC_ENABLE_PGRAPH);
272 /* and restore (gives effect of resetting AGP) */
273 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
280 nouveau_mem_init_agp(struct drm_device *dev)
283 struct drm_nouveau_private *dev_priv = dev->dev_private;
284 struct drm_agp_info info;
285 struct drm_agp_mode mode;
288 if (!dev->agp->acquired) {
289 ret = drm_agp_acquire(dev);
291 NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
296 nouveau_mem_reset_agp(dev);
298 ret = drm_agp_info(dev, &info);
300 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
304 /* see agp.h for the AGPSTAT_* modes available */
305 mode.mode = get_agp_mode(dev, info.mode);
306 ret = drm_agp_enable(dev, mode);
308 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
312 dev_priv->gart_info.type = NOUVEAU_GART_AGP;
313 dev_priv->gart_info.aper_base = info.aperture_base;
314 dev_priv->gart_info.aper_size = info.aperture_size;
319 static const struct vram_types {
322 } vram_type_map[] = {
323 { NV_MEM_TYPE_STOLEN , "stolen system memory" },
324 { NV_MEM_TYPE_SGRAM , "SGRAM" },
325 { NV_MEM_TYPE_SDRAM , "SDRAM" },
326 { NV_MEM_TYPE_DDR1 , "DDR1" },
327 { NV_MEM_TYPE_DDR2 , "DDR2" },
328 { NV_MEM_TYPE_DDR3 , "DDR3" },
329 { NV_MEM_TYPE_GDDR2 , "GDDR2" },
330 { NV_MEM_TYPE_GDDR3 , "GDDR3" },
331 { NV_MEM_TYPE_GDDR4 , "GDDR4" },
332 { NV_MEM_TYPE_GDDR5 , "GDDR5" },
333 { NV_MEM_TYPE_UNKNOWN, "unknown type" }
337 nouveau_mem_vram_init(struct drm_device *dev)
339 struct drm_nouveau_private *dev_priv = dev->dev_private;
340 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
341 const struct vram_types *vram_type;
345 if (dev_priv->card_type >= NV_50) {
346 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
349 if (0 && pci_is_pcie(dev->pdev) &&
350 dev_priv->chipset > 0x40 &&
351 dev_priv->chipset != 0x45) {
352 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
356 ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
359 ret = pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
361 /* Reset to default value. */
362 pci_set_consistent_dma_mask(dev->pdev, DMA_BIT_MASK(32));
366 ret = nouveau_ttm_global_init(dev_priv);
370 ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
371 dev_priv->ttm.bo_global_ref.ref.object,
372 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
373 dma_bits <= 32 ? true : false);
375 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
379 vram_type = vram_type_map;
380 while (vram_type->value != NV_MEM_TYPE_UNKNOWN) {
381 if (nouveau_vram_type) {
382 if (!strcasecmp(nouveau_vram_type, vram_type->name))
384 dev_priv->vram_type = vram_type->value;
386 if (vram_type->value == dev_priv->vram_type)
392 NV_INFO(dev, "Detected %dMiB VRAM (%s)\n",
393 (int)(dev_priv->vram_size >> 20), vram_type->name);
394 if (dev_priv->vram_sys_base) {
395 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
396 dev_priv->vram_sys_base);
399 dev_priv->fb_available_size = dev_priv->vram_size;
400 dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
401 if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
402 dev_priv->fb_mappable_pages = pci_resource_len(dev->pdev, 1);
403 dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
405 dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
406 dev_priv->fb_aper_free = dev_priv->fb_available_size;
409 ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
410 dev_priv->fb_available_size >> PAGE_SHIFT);
412 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
416 if (dev_priv->card_type < NV_50) {
417 ret = nouveau_bo_new(dev, 256*1024, 0, TTM_PL_FLAG_VRAM,
418 0, 0, &dev_priv->vga_ram);
420 ret = nouveau_bo_pin(dev_priv->vga_ram,
424 NV_WARN(dev, "failed to reserve VGA memory\n");
425 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
429 dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
430 pci_resource_len(dev->pdev, 1),
436 nouveau_mem_gart_init(struct drm_device *dev)
438 struct drm_nouveau_private *dev_priv = dev->dev_private;
439 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
442 dev_priv->gart_info.type = NOUVEAU_GART_NONE;
444 #if !defined(__powerpc__) && !defined(__ia64__)
445 if (drm_pci_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
446 ret = nouveau_mem_init_agp(dev);
448 NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
452 if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
453 ret = nouveau_sgdma_init(dev);
455 NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
460 NV_INFO(dev, "%d MiB GART (aperture)\n",
461 (int)(dev_priv->gart_info.aper_size >> 20));
462 dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
464 ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
465 dev_priv->gart_info.aper_size >> PAGE_SHIFT);
467 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
474 /* XXX: For now a dummy. More samples required, possibly even a card
475 * Called from nouveau_perf.c */
476 void nv30_mem_timing_entry(struct drm_device *dev,
477 struct nouveau_pm_tbl_header *hdr,
478 struct nouveau_pm_tbl_entry *e, uint8_t magic_number,
479 struct nouveau_pm_memtiming *timing)
482 NV_DEBUG(dev, "Timing entry format unknown, "
483 "please contact nouveau developers");
486 void nv40_mem_timing_entry(struct drm_device *dev,
487 struct nouveau_pm_tbl_header *hdr,
488 struct nouveau_pm_tbl_entry *e,
489 struct nouveau_pm_memtiming *timing)
492 timing->reg_0 = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
494 /* XXX: I don't trust the -1's and +1's... they must come
496 timing->reg_1 = (e->tWR + 2 + (timing->tCWL - 1)) << 24 |
498 (e->tWTR + 2 + (timing->tCWL - 1)) << 8 |
499 (e->tCL + 2 - (timing->tCWL - 1));
501 timing->reg_2 = 0x20200000 | ((timing->tCWL - 1) << 24 |
502 e->tRRD << 16 | e->tRCDWR << 8 | e->tRCDRD);
504 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x\n", timing->id,
505 timing->reg_0, timing->reg_1, timing->reg_2);
508 void nv50_mem_timing_entry(struct drm_device *dev, struct bit_entry *P,
509 struct nouveau_pm_tbl_header *hdr,
510 struct nouveau_pm_tbl_entry *e,
511 struct nouveau_pm_memtiming *timing)
513 struct drm_nouveau_private *dev_priv = dev->dev_private;
519 switch (min(hdr->entry_len, (u8) 22)) {
526 timing->tCWL = e->tCWL;
532 timing->reg_0 = (e->tRP << 24 | e->tRAS << 16 | e->tRFC << 8 | e->tRC);
534 timing->reg_1 = (e->tWR + 2 + (timing->tCWL - 1)) << 24 |
535 max(unk18, (u8) 1) << 16 |
536 (e->tWTR + 2 + (timing->tCWL - 1)) << 8;
538 timing->reg_2 = ((timing->tCWL - 1) << 24 | e->tRRD << 16 |
539 e->tRCDWR << 8 | e->tRCDRD);
541 timing->reg_4 = e->tUNK_13 << 8 | e->tUNK_13;
543 timing->reg_5 = (e->tRFC << 24 | max(e->tRCDRD, e->tRCDWR) << 16 |
546 timing->reg_8 = (nv_rd32(dev, 0x100240) & 0xffffff00);
548 if (P->version == 1) {
549 timing->reg_1 |= (e->tCL + 2 - (timing->tCWL - 1));
551 timing->reg_3 = (0x14 + e->tCL) << 24 |
556 timing->reg_4 |= (nv_rd32(dev, 0x100230) & 0xffff0000);
558 timing->reg_6 = (0x33 - timing->tCWL) << 16 |
560 (0x2E + e->tCL - timing->tCWL);
562 timing->reg_7 = 0x4000202 | (e->tCL - 1) << 16;
564 /* XXX: P.version == 1 only has DDR2 and GDDR3? */
565 if (dev_priv->vram_type == NV_MEM_TYPE_DDR2) {
566 timing->reg_5 |= (e->tCL + 3) << 8;
567 timing->reg_6 |= (timing->tCWL - 2) << 8;
568 timing->reg_8 |= (e->tCL - 4);
570 timing->reg_5 |= (e->tCL + 2) << 8;
571 timing->reg_6 |= timing->tCWL << 8;
572 timing->reg_8 |= (e->tCL - 2);
575 timing->reg_1 |= (5 + e->tCL - (timing->tCWL));
577 /* XXX: 0xb? 0x30? */
578 timing->reg_3 = (0x30 + e->tCL) << 24 |
579 (nv_rd32(dev, 0x10022c) & 0x00ff0000) |
580 (0xB + e->tCL) << 8 |
583 timing->reg_4 |= (unk20 << 24 | unk21 << 16);
586 timing->reg_5 |= (timing->tCWL + 6) << 8;
588 timing->reg_6 = (0x5A + e->tCL) << 16 |
589 (6 - e->tCL + timing->tCWL) << 8 |
590 (0x50 + e->tCL - timing->tCWL);
592 tmp7_3 = (nv_rd32(dev, 0x10023c) & 0xff000000) >> 24;
593 timing->reg_7 = (tmp7_3 << 24) |
594 ((tmp7_3 - 6 + e->tCL) << 16) |
598 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", timing->id,
599 timing->reg_0, timing->reg_1,
600 timing->reg_2, timing->reg_3);
601 NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
602 timing->reg_4, timing->reg_5,
603 timing->reg_6, timing->reg_7);
604 NV_DEBUG(dev, " 240: %08x\n", timing->reg_8);
607 void nvc0_mem_timing_entry(struct drm_device *dev,
608 struct nouveau_pm_tbl_header *hdr,
609 struct nouveau_pm_tbl_entry *e,
610 struct nouveau_pm_memtiming *timing)
612 timing->tCWL = e->tCWL;
614 timing->reg_0 = (e->tRP << 24 | (e->tRAS & 0x7f) << 17 |
615 e->tRFC << 8 | e->tRC);
617 timing->reg_1 = (nv_rd32(dev, 0x10f294) & 0xff000000) |
618 (e->tRCDWR & 0x0f) << 20 |
619 (e->tRCDRD & 0x0f) << 14 |
623 timing->reg_2 = (nv_rd32(dev, 0x10f298) & 0xff0000ff) |
624 e->tWR << 16 | e->tWTR << 8;
626 timing->reg_3 = (e->tUNK_20&0xf) << 9 |
627 (e->tUNK_21 & 0xf) << 5 |
630 timing->reg_4 = (nv_rd32(dev, 0x10f2a0) & 0xfff00fff) |
631 (e->tRRD&0x1f) << 15;
633 NV_DEBUG(dev, "Entry %d: 290: %08x %08x %08x %08x\n", timing->id,
634 timing->reg_0, timing->reg_1,
635 timing->reg_2, timing->reg_3);
636 NV_DEBUG(dev, " 2a0: %08x\n",
641 nouveau_mem_features_entry(uint8_t p_version, struct nouveau_pm_tbl_header *hdr,
642 struct nouveau_pm_tbl_entry *e,
643 struct nouveau_pm_memtiming *timing)
645 if (p_version == 1) {
647 } else if (p_version == 2) {
648 timing->odt = e->RAM_FT1 & 0x1;
649 timing->dll_disable = (e->RAM_FT1 & 0x2) >> 1;
650 timing->ron_pull = (e->RAM_FT1 & 0x4) >> 2;
655 * Processes the Memory Timing BIOS table, stores generated
657 * @pre init scripts were run, memtiming regs are initialized
660 nouveau_mem_timing_init(struct drm_device *dev)
662 struct drm_nouveau_private *dev_priv = dev->dev_private;
663 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
664 struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
665 struct nvbios *bios = &dev_priv->vbios;
667 struct nouveau_pm_tbl_header *hdr = NULL;
672 if (bios->type == NVBIOS_BIT) {
673 if (bit_table(dev, 'P', &P))
677 hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev,
679 else if (P.version == 2)
680 hdr = (struct nouveau_pm_tbl_header *) ROMPTR(dev,
683 NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
685 NV_DEBUG(dev, "BMP version too old for memory\n");
690 NV_DEBUG(dev, "memory timing table pointer invalid\n");
694 if (hdr->version != 0x10) {
695 NV_WARN(dev, "memory timing table 0x%02x unknown\n",
700 /* validate record length */
701 if (hdr->entry_len < 15) {
702 NV_ERROR(dev, "mem timing table length unknown: %d\n",
707 /* parse vbios entries into common format */
708 memtimings->timing = kcalloc(hdr->entry_cnt,
709 sizeof(*memtimings->timing), GFP_KERNEL);
710 if (!memtimings->timing)
713 /* Get tCWL from the timing reg for NV_40 and NV_50
714 * Used in calculations later... source unknown */
716 if (dev_priv->card_type < NV_C0)
717 tCWL = ((nv_rd32(dev, 0x100228) & 0x0f000000) >> 24) + 1;
719 entry = (u8 *) hdr + hdr->header_len;
720 for (i = 0; i < hdr->entry_cnt; i++, entry += hdr->entry_len) {
721 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
722 struct nouveau_pm_tbl_entry *entry_struct =
723 (struct nouveau_pm_tbl_entry *) entry;
728 timing->WR = entry[0];
729 timing->CL = entry[2];
732 nouveau_mem_features_entry(P.version, hdr, entry_struct,
733 &pm->memtimings.timing[i]);
735 if (dev_priv->card_type <= NV_40) {
736 nv40_mem_timing_entry(dev, hdr, entry_struct,
737 &pm->memtimings.timing[i]);
738 } else if (dev_priv->card_type == NV_50) {
739 nv50_mem_timing_entry(dev, &P, hdr, entry_struct,
740 &pm->memtimings.timing[i]);
741 } else if (dev_priv->card_type == NV_C0) {
742 nvc0_mem_timing_entry(dev, hdr, entry_struct,
743 &pm->memtimings.timing[i]);
747 memtimings->nr_timing = hdr->entry_cnt;
748 memtimings->supported = (P.version == 1);
752 nouveau_mem_timing_fini(struct drm_device *dev)
754 struct drm_nouveau_private *dev_priv = dev->dev_private;
755 struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
762 nouveau_mem_vbios_type(struct drm_device *dev)
765 u8 ramcfg = (nv_rd32(dev, 0x101000) & 0x0000003c) >> 2;
766 if (!bit_table(dev, 'M', &M) || M.version != 2 || M.length < 5) {
767 u8 *table = ROMPTR(dev, M.data[3]);
768 if (table && table[0] == 0x10 && ramcfg < table[3]) {
769 u8 *entry = table + table[1] + (ramcfg * table[2]);
770 switch (entry[0] & 0x0f) {
771 case 0: return NV_MEM_TYPE_DDR2;
772 case 1: return NV_MEM_TYPE_DDR3;
773 case 2: return NV_MEM_TYPE_GDDR3;
774 case 3: return NV_MEM_TYPE_GDDR5;
781 return NV_MEM_TYPE_UNKNOWN;
785 nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
792 nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
799 nouveau_mem_node_cleanup(struct nouveau_mem *node)
801 if (node->vma[0].node) {
802 nouveau_vm_unmap(&node->vma[0]);
803 nouveau_vm_put(&node->vma[0]);
806 if (node->vma[1].node) {
807 nouveau_vm_unmap(&node->vma[1]);
808 nouveau_vm_put(&node->vma[1]);
813 nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
814 struct ttm_mem_reg *mem)
816 struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
817 struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
818 struct drm_device *dev = dev_priv->dev;
820 nouveau_mem_node_cleanup(mem->mm_node);
821 vram->put(dev, (struct nouveau_mem **)&mem->mm_node);
825 nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
826 struct ttm_buffer_object *bo,
827 struct ttm_placement *placement,
828 struct ttm_mem_reg *mem)
830 struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
831 struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
832 struct drm_device *dev = dev_priv->dev;
833 struct nouveau_bo *nvbo = nouveau_bo(bo);
834 struct nouveau_mem *node;
838 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
839 size_nc = 1 << nvbo->page_shift;
841 ret = vram->get(dev, mem->num_pages << PAGE_SHIFT,
842 mem->page_alignment << PAGE_SHIFT, size_nc,
843 (nvbo->tile_flags >> 8) & 0x3ff, &node);
846 return (ret == -ENOSPC) ? 0 : ret;
849 node->page_shift = nvbo->page_shift;
852 mem->start = node->offset >> PAGE_SHIFT;
857 nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
859 struct nouveau_mm *mm = man->priv;
860 struct nouveau_mm_node *r;
861 u32 total = 0, free = 0;
863 mutex_lock(&mm->mutex);
864 list_for_each_entry(r, &mm->nodes, nl_entry) {
865 printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
866 prefix, r->type, ((u64)r->offset << 12),
867 (((u64)r->offset + r->length) << 12));
873 mutex_unlock(&mm->mutex);
875 printk(KERN_DEBUG "%s total: 0x%010llx free: 0x%010llx\n",
876 prefix, (u64)total << 12, (u64)free << 12);
877 printk(KERN_DEBUG "%s block: 0x%08x\n",
878 prefix, mm->block_size << 12);
881 const struct ttm_mem_type_manager_func nouveau_vram_manager = {
882 nouveau_vram_manager_init,
883 nouveau_vram_manager_fini,
884 nouveau_vram_manager_new,
885 nouveau_vram_manager_del,
886 nouveau_vram_manager_debug
890 nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
896 nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
902 nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
903 struct ttm_mem_reg *mem)
905 nouveau_mem_node_cleanup(mem->mm_node);
911 nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
912 struct ttm_buffer_object *bo,
913 struct ttm_placement *placement,
914 struct ttm_mem_reg *mem)
916 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
917 struct nouveau_mem *node;
919 if (unlikely((mem->num_pages << PAGE_SHIFT) >=
920 dev_priv->gart_info.aper_size))
923 node = kzalloc(sizeof(*node), GFP_KERNEL);
926 node->page_shift = 12;
934 nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
938 const struct ttm_mem_type_manager_func nouveau_gart_manager = {
939 nouveau_gart_manager_init,
940 nouveau_gart_manager_fini,
941 nouveau_gart_manager_new,
942 nouveau_gart_manager_del,
943 nouveau_gart_manager_debug