drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include <nouveau_drm.h>
  37 #include "nouveau_agp.h"
  38 #include "nouveau_fbcon.h"
  39 #include <core/ramht.h>
  40 #include <subdev/gpio.h>
  41 #include "nouveau_pm.h"
  42 #include "nv50_display.h"
  43 #include <engine/fifo.h>
  44 #include "nouveau_fence.h"
  45 #include "nouveau_software.h"
  46
  47 static void nouveau_stub_takedown(struct drm_device *dev) {}
  48 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  49
  50 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  51 {
  52         struct drm_nouveau_private *dev_priv = dev->dev_private;
  53         struct nouveau_engine *engine = &dev_priv->engine;
  54
  55         switch (dev_priv->chipset & 0xf0) {
  56         case 0x00:
  57                 engine->instmem.init            = nv04_instmem_init;
  58                 engine->instmem.takedown        = nv04_instmem_takedown;
  59                 engine->instmem.suspend         = nv04_instmem_suspend;
  60                 engine->instmem.resume          = nv04_instmem_resume;
  61                 engine->instmem.get             = nv04_instmem_get;
  62                 engine->instmem.put             = nv04_instmem_put;
  63                 engine->instmem.map             = nv04_instmem_map;
  64                 engine->instmem.unmap           = nv04_instmem_unmap;
  65                 engine->instmem.flush           = nv04_instmem_flush;
  66                 engine->mc.init                 = nv04_mc_init;
  67                 engine->mc.takedown             = nv04_mc_takedown;
  68                 engine->timer.init              = nv04_timer_init;
  69                 engine->timer.read              = nv04_timer_read;
  70                 engine->timer.takedown          = nv04_timer_takedown;
  71                 engine->fb.init                 = nv04_fb_init;
  72                 engine->fb.takedown             = nv04_fb_takedown;
  73                 engine->display.early_init      = nv04_display_early_init;
  74                 engine->display.late_takedown   = nv04_display_late_takedown;
  75                 engine->display.create          = nv04_display_create;
  76                 engine->display.destroy         = nv04_display_destroy;
  77                 engine->display.init            = nv04_display_init;
  78                 engine->display.fini            = nv04_display_fini;
  79                 engine->pm.clocks_get           = nv04_pm_clocks_get;
  80                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
  81                 engine->pm.clocks_set           = nv04_pm_clocks_set;
  82                 engine->vram.init               = nv04_fb_vram_init;
  83                 engine->vram.takedown           = nouveau_stub_takedown;
  84                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
  85                 break;
  86         case 0x10:
  87                 engine->instmem.init            = nv04_instmem_init;
  88                 engine->instmem.takedown        = nv04_instmem_takedown;
  89                 engine->instmem.suspend         = nv04_instmem_suspend;
  90                 engine->instmem.resume          = nv04_instmem_resume;
  91                 engine->instmem.get             = nv04_instmem_get;
  92                 engine->instmem.put             = nv04_instmem_put;
  93                 engine->instmem.map             = nv04_instmem_map;
  94                 engine->instmem.unmap           = nv04_instmem_unmap;
  95                 engine->instmem.flush           = nv04_instmem_flush;
  96                 engine->mc.init                 = nv04_mc_init;
  97                 engine->mc.takedown             = nv04_mc_takedown;
  98                 engine->timer.init              = nv04_timer_init;
  99                 engine->timer.read              = nv04_timer_read;
 100                 engine->timer.takedown          = nv04_timer_takedown;
 101                 engine->fb.init                 = nv10_fb_init;
 102                 engine->fb.takedown             = nv10_fb_takedown;
 103                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 104                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 105                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 106                 engine->display.early_init      = nv04_display_early_init;
 107                 engine->display.late_takedown   = nv04_display_late_takedown;
 108                 engine->display.create          = nv04_display_create;
 109                 engine->display.destroy         = nv04_display_destroy;
 110                 engine->display.init            = nv04_display_init;
 111                 engine->display.fini            = nv04_display_fini;
 112                 engine->gpio.drive              = nv10_gpio_drive;
 113                 engine->gpio.sense              = nv10_gpio_sense;
 114                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 115                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 116                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 117                 if (dev_priv->chipset == 0x1a ||
 118                     dev_priv->chipset == 0x1f)
 119                         engine->vram.init       = nv1a_fb_vram_init;
 120                 else
 121                         engine->vram.init       = nv10_fb_vram_init;
 122                 engine->vram.takedown           = nouveau_stub_takedown;
 123                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 124                 break;
 125         case 0x20:
 126                 engine->instmem.init            = nv04_instmem_init;
 127                 engine->instmem.takedown        = nv04_instmem_takedown;
 128                 engine->instmem.suspend         = nv04_instmem_suspend;
 129                 engine->instmem.resume          = nv04_instmem_resume;
 130                 engine->instmem.get             = nv04_instmem_get;
 131                 engine->instmem.put             = nv04_instmem_put;
 132                 engine->instmem.map             = nv04_instmem_map;
 133                 engine->instmem.unmap           = nv04_instmem_unmap;
 134                 engine->instmem.flush           = nv04_instmem_flush;
 135                 engine->mc.init                 = nv04_mc_init;
 136                 engine->mc.takedown             = nv04_mc_takedown;
 137                 engine->timer.init              = nv04_timer_init;
 138                 engine->timer.read              = nv04_timer_read;
 139                 engine->timer.takedown          = nv04_timer_takedown;
 140                 engine->fb.init                 = nv20_fb_init;
 141                 engine->fb.takedown             = nv20_fb_takedown;
 142                 engine->fb.init_tile_region     = nv20_fb_init_tile_region;
 143                 engine->fb.set_tile_region      = nv20_fb_set_tile_region;
 144                 engine->fb.free_tile_region     = nv20_fb_free_tile_region;
 145                 engine->display.early_init      = nv04_display_early_init;
 146                 engine->display.late_takedown   = nv04_display_late_takedown;
 147                 engine->display.create          = nv04_display_create;
 148                 engine->display.destroy         = nv04_display_destroy;
 149                 engine->display.init            = nv04_display_init;
 150                 engine->display.fini            = nv04_display_fini;
 151                 engine->gpio.drive              = nv10_gpio_drive;
 152                 engine->gpio.sense              = nv10_gpio_sense;
 153                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 154                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 155                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 156                 engine->vram.init               = nv20_fb_vram_init;
 157                 engine->vram.takedown           = nouveau_stub_takedown;
 158                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 159                 break;
 160         case 0x30:
 161                 engine->instmem.init            = nv04_instmem_init;
 162                 engine->instmem.takedown        = nv04_instmem_takedown;
 163                 engine->instmem.suspend         = nv04_instmem_suspend;
 164                 engine->instmem.resume          = nv04_instmem_resume;
 165                 engine->instmem.get             = nv04_instmem_get;
 166                 engine->instmem.put             = nv04_instmem_put;
 167                 engine->instmem.map             = nv04_instmem_map;
 168                 engine->instmem.unmap           = nv04_instmem_unmap;
 169                 engine->instmem.flush           = nv04_instmem_flush;
 170                 engine->mc.init                 = nv04_mc_init;
 171                 engine->mc.takedown             = nv04_mc_takedown;
 172                 engine->timer.init              = nv04_timer_init;
 173                 engine->timer.read              = nv04_timer_read;
 174                 engine->timer.takedown          = nv04_timer_takedown;
 175                 engine->fb.init                 = nv30_fb_init;
 176                 engine->fb.takedown             = nv30_fb_takedown;
 177                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 178                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 179                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 180                 engine->display.early_init      = nv04_display_early_init;
 181                 engine->display.late_takedown   = nv04_display_late_takedown;
 182                 engine->display.create          = nv04_display_create;
 183                 engine->display.destroy         = nv04_display_destroy;
 184                 engine->display.init            = nv04_display_init;
 185                 engine->display.fini            = nv04_display_fini;
 186                 engine->gpio.drive              = nv10_gpio_drive;
 187                 engine->gpio.sense              = nv10_gpio_sense;
 188                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 189                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 190                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 191                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 192                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 193                 engine->vram.init               = nv20_fb_vram_init;
 194                 engine->vram.takedown           = nouveau_stub_takedown;
 195                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 196                 break;
 197         case 0x40:
 198         case 0x60:
 199                 engine->instmem.init            = nv04_instmem_init;
 200                 engine->instmem.takedown        = nv04_instmem_takedown;
 201                 engine->instmem.suspend         = nv04_instmem_suspend;
 202                 engine->instmem.resume          = nv04_instmem_resume;
 203                 engine->instmem.get             = nv04_instmem_get;
 204                 engine->instmem.put             = nv04_instmem_put;
 205                 engine->instmem.map             = nv04_instmem_map;
 206                 engine->instmem.unmap           = nv04_instmem_unmap;
 207                 engine->instmem.flush           = nv04_instmem_flush;
 208                 engine->mc.init                 = nv40_mc_init;
 209                 engine->mc.takedown             = nv40_mc_takedown;
 210                 engine->timer.init              = nv04_timer_init;
 211                 engine->timer.read              = nv04_timer_read;
 212                 engine->timer.takedown          = nv04_timer_takedown;
 213                 engine->fb.init                 = nv40_fb_init;
 214                 engine->fb.takedown             = nv40_fb_takedown;
 215                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 216                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 217                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 218                 engine->display.early_init      = nv04_display_early_init;
 219                 engine->display.late_takedown   = nv04_display_late_takedown;
 220                 engine->display.create          = nv04_display_create;
 221                 engine->display.destroy         = nv04_display_destroy;
 222                 engine->display.init            = nv04_display_init;
 223                 engine->display.fini            = nv04_display_fini;
 224                 engine->gpio.init               = nv10_gpio_init;
 225                 engine->gpio.fini               = nv10_gpio_fini;
 226                 engine->gpio.drive              = nv10_gpio_drive;
 227                 engine->gpio.sense              = nv10_gpio_sense;
 228                 engine->gpio.irq_enable         = nv10_gpio_irq_enable;
 229                 engine->pm.clocks_get           = nv40_pm_clocks_get;
 230                 engine->pm.clocks_pre           = nv40_pm_clocks_pre;
 231                 engine->pm.clocks_set           = nv40_pm_clocks_set;
 232                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 233                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 234                 engine->pm.temp_get             = nv40_temp_get;
 235                 engine->pm.pwm_get              = nv40_pm_pwm_get;
 236                 engine->pm.pwm_set              = nv40_pm_pwm_set;
 237                 engine->vram.init               = nv40_fb_vram_init;
 238                 engine->vram.takedown           = nouveau_stub_takedown;
 239                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 240                 break;
 241         case 0x50:
 242         case 0x80: /* gotta love NVIDIA's consistency.. */
 243         case 0x90:
 244         case 0xa0:
 245                 engine->instmem.init            = nv50_instmem_init;
 246                 engine->instmem.takedown        = nv50_instmem_takedown;
 247                 engine->instmem.suspend         = nv50_instmem_suspend;
 248                 engine->instmem.resume          = nv50_instmem_resume;
 249                 engine->instmem.get             = nv50_instmem_get;
 250                 engine->instmem.put             = nv50_instmem_put;
 251                 engine->instmem.map             = nv50_instmem_map;
 252                 engine->instmem.unmap           = nv50_instmem_unmap;
 253                 if (dev_priv->chipset == 0x50)
 254                         engine->instmem.flush   = nv50_instmem_flush;
 255                 else
 256                         engine->instmem.flush   = nv84_instmem_flush;
 257                 engine->mc.init                 = nv50_mc_init;
 258                 engine->mc.takedown             = nv50_mc_takedown;
 259                 engine->timer.init              = nv04_timer_init;
 260                 engine->timer.read              = nv04_timer_read;
 261                 engine->timer.takedown          = nv04_timer_takedown;
 262                 engine->fb.init                 = nv50_fb_init;
 263                 engine->fb.takedown             = nv50_fb_takedown;
 264                 engine->display.early_init      = nv50_display_early_init;
 265                 engine->display.late_takedown   = nv50_display_late_takedown;
 266                 engine->display.create          = nv50_display_create;
 267                 engine->display.destroy         = nv50_display_destroy;
 268                 engine->display.init            = nv50_display_init;
 269                 engine->display.fini            = nv50_display_fini;
 270                 engine->gpio.init               = nv50_gpio_init;
 271                 engine->gpio.fini               = nv50_gpio_fini;
 272                 engine->gpio.drive              = nv50_gpio_drive;
 273                 engine->gpio.sense              = nv50_gpio_sense;
 274                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 275                 switch (dev_priv->chipset) {
 276                 case 0x84:
 277                 case 0x86:
 278                 case 0x92:
 279                 case 0x94:
 280                 case 0x96:
 281                 case 0x98:
 282                 case 0xa0:
 283                 case 0xaa:
 284                 case 0xac:
 285                 case 0x50:
 286                         engine->pm.clocks_get   = nv50_pm_clocks_get;
 287                         engine->pm.clocks_pre   = nv50_pm_clocks_pre;
 288                         engine->pm.clocks_set   = nv50_pm_clocks_set;
 289                         break;
 290                 default:
 291                         engine->pm.clocks_get   = nva3_pm_clocks_get;
 292                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
 293                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 294                         break;
 295                 }
 296                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 297                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 298                 if (dev_priv->chipset >= 0x84)
 299                         engine->pm.temp_get     = nv84_temp_get;
 300                 else
 301                         engine->pm.temp_get     = nv40_temp_get;
 302                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 303                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 304                 engine->vram.init               = nv50_vram_init;
 305                 engine->vram.takedown           = nv50_vram_fini;
 306                 engine->vram.get                = nv50_vram_new;
 307                 engine->vram.put                = nv50_vram_del;
 308                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 309                 break;
 310         case 0xc0:
 311                 engine->instmem.init            = nvc0_instmem_init;
 312                 engine->instmem.takedown        = nvc0_instmem_takedown;
 313                 engine->instmem.suspend         = nvc0_instmem_suspend;
 314                 engine->instmem.resume          = nvc0_instmem_resume;
 315                 engine->instmem.get             = nv50_instmem_get;
 316                 engine->instmem.put             = nv50_instmem_put;
 317                 engine->instmem.map             = nv50_instmem_map;
 318                 engine->instmem.unmap           = nv50_instmem_unmap;
 319                 engine->instmem.flush           = nv84_instmem_flush;
 320                 engine->mc.init                 = nv50_mc_init;
 321                 engine->mc.takedown             = nv50_mc_takedown;
 322                 engine->timer.init              = nv04_timer_init;
 323                 engine->timer.read              = nv04_timer_read;
 324                 engine->timer.takedown          = nv04_timer_takedown;
 325                 engine->fb.init                 = nvc0_fb_init;
 326                 engine->fb.takedown             = nvc0_fb_takedown;
 327                 engine->display.early_init      = nv50_display_early_init;
 328                 engine->display.late_takedown   = nv50_display_late_takedown;
 329                 engine->display.create          = nv50_display_create;
 330                 engine->display.destroy         = nv50_display_destroy;
 331                 engine->display.init            = nv50_display_init;
 332                 engine->display.fini            = nv50_display_fini;
 333                 engine->gpio.init               = nv50_gpio_init;
 334                 engine->gpio.fini               = nv50_gpio_fini;
 335                 engine->gpio.drive              = nv50_gpio_drive;
 336                 engine->gpio.sense              = nv50_gpio_sense;
 337                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 338                 engine->vram.init               = nvc0_vram_init;
 339                 engine->vram.takedown           = nv50_vram_fini;
 340                 engine->vram.get                = nvc0_vram_new;
 341                 engine->vram.put                = nv50_vram_del;
 342                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 343                 engine->pm.temp_get             = nv84_temp_get;
 344                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 345                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 346                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 347                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 348                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 349                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 350                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 351                 break;
 352         case 0xd0:
 353                 engine->instmem.init            = nvc0_instmem_init;
 354                 engine->instmem.takedown        = nvc0_instmem_takedown;
 355                 engine->instmem.suspend         = nvc0_instmem_suspend;
 356                 engine->instmem.resume          = nvc0_instmem_resume;
 357                 engine->instmem.get             = nv50_instmem_get;
 358                 engine->instmem.put             = nv50_instmem_put;
 359                 engine->instmem.map             = nv50_instmem_map;
 360                 engine->instmem.unmap           = nv50_instmem_unmap;
 361                 engine->instmem.flush           = nv84_instmem_flush;
 362                 engine->mc.init                 = nv50_mc_init;
 363                 engine->mc.takedown             = nv50_mc_takedown;
 364                 engine->timer.init              = nv04_timer_init;
 365                 engine->timer.read              = nv04_timer_read;
 366                 engine->timer.takedown          = nv04_timer_takedown;
 367                 engine->fb.init                 = nvc0_fb_init;
 368                 engine->fb.takedown             = nvc0_fb_takedown;
 369                 engine->display.early_init      = nouveau_stub_init;
 370                 engine->display.late_takedown   = nouveau_stub_takedown;
 371                 engine->display.create          = nvd0_display_create;
 372                 engine->display.destroy         = nvd0_display_destroy;
 373                 engine->display.init            = nvd0_display_init;
 374                 engine->display.fini            = nvd0_display_fini;
 375                 engine->gpio.init               = nv50_gpio_init;
 376                 engine->gpio.fini               = nv50_gpio_fini;
 377                 engine->gpio.drive              = nvd0_gpio_drive;
 378                 engine->gpio.sense              = nvd0_gpio_sense;
 379                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 380                 engine->vram.init               = nvc0_vram_init;
 381                 engine->vram.takedown           = nv50_vram_fini;
 382                 engine->vram.get                = nvc0_vram_new;
 383                 engine->vram.put                = nv50_vram_del;
 384                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 385                 engine->pm.temp_get             = nv84_temp_get;
 386                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 387                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 388                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 389                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 390                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 391                 break;
 392         case 0xe0:
 393                 engine->instmem.init            = nvc0_instmem_init;
 394                 engine->instmem.takedown        = nvc0_instmem_takedown;
 395                 engine->instmem.suspend         = nvc0_instmem_suspend;
 396                 engine->instmem.resume          = nvc0_instmem_resume;
 397                 engine->instmem.get             = nv50_instmem_get;
 398                 engine->instmem.put             = nv50_instmem_put;
 399                 engine->instmem.map             = nv50_instmem_map;
 400                 engine->instmem.unmap           = nv50_instmem_unmap;
 401                 engine->instmem.flush           = nv84_instmem_flush;
 402                 engine->mc.init                 = nv50_mc_init;
 403                 engine->mc.takedown             = nv50_mc_takedown;
 404                 engine->timer.init              = nv04_timer_init;
 405                 engine->timer.read              = nv04_timer_read;
 406                 engine->timer.takedown          = nv04_timer_takedown;
 407                 engine->fb.init                 = nvc0_fb_init;
 408                 engine->fb.takedown             = nvc0_fb_takedown;
 409                 engine->display.early_init      = nouveau_stub_init;
 410                 engine->display.late_takedown   = nouveau_stub_takedown;
 411                 engine->display.create          = nvd0_display_create;
 412                 engine->display.destroy         = nvd0_display_destroy;
 413                 engine->display.init            = nvd0_display_init;
 414                 engine->display.fini            = nvd0_display_fini;
 415                 engine->gpio.init               = nv50_gpio_init;
 416                 engine->gpio.fini               = nv50_gpio_fini;
 417                 engine->gpio.drive              = nvd0_gpio_drive;
 418                 engine->gpio.sense              = nvd0_gpio_sense;
 419                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 420                 engine->vram.init               = nvc0_vram_init;
 421                 engine->vram.takedown           = nv50_vram_fini;
 422                 engine->vram.get                = nvc0_vram_new;
 423                 engine->vram.put                = nv50_vram_del;
 424                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 425                 break;
 426         default:
 427                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 428                 return 1;
 429         }
 430
 431         /* headless mode */
 432         if (nouveau_modeset == 2) {
 433                 engine->display.early_init = nouveau_stub_init;
 434                 engine->display.late_takedown = nouveau_stub_takedown;
 435                 engine->display.create = nouveau_stub_init;
 436                 engine->display.init = nouveau_stub_init;
 437                 engine->display.destroy = nouveau_stub_takedown;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static unsigned int
 444 nouveau_vga_set_decode(void *priv, bool state)
 445 {
 446         struct drm_device *dev = priv;
 447         struct drm_nouveau_private *dev_priv = dev->dev_private;
 448
 449         if (dev_priv->chipset >= 0x40)
 450                 nv_wr32(dev, 0x88054, state);
 451         else
 452                 nv_wr32(dev, 0x1854, state);
 453
 454         if (state)
 455                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 456                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 457         else
 458                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 459 }
 460
 461 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 462                                          enum vga_switcheroo_state state)
 463 {
 464         struct drm_device *dev = pci_get_drvdata(pdev);
 465         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 466         if (state == VGA_SWITCHEROO_ON) {
 467                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 468                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 469                 nouveau_pci_resume(pdev);
 470                 drm_kms_helper_poll_enable(dev);
 471                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 472         } else {
 473                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 474                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 475                 drm_kms_helper_poll_disable(dev);
 476                 nouveau_switcheroo_optimus_dsm();
 477                 nouveau_pci_suspend(pdev, pmm);
 478                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 479         }
 480 }
 481
 482 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 483 {
 484         struct drm_device *dev = pci_get_drvdata(pdev);
 485         nouveau_fbcon_output_poll_changed(dev);
 486 }
 487
 488 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 489 {
 490         struct drm_device *dev = pci_get_drvdata(pdev);
 491         bool can_switch;
 492
 493         spin_lock(&dev->count_lock);
 494         can_switch = (dev->open_count == 0);
 495         spin_unlock(&dev->count_lock);
 496         return can_switch;
 497 }
 498
 499 static void
 500 nouveau_card_channel_fini(struct drm_device *dev)
 501 {
 502         struct drm_nouveau_private *dev_priv = dev->dev_private;
 503
 504         if (dev_priv->channel)
 505                 nouveau_channel_put_unlocked(&dev_priv->channel);
 506 }
 507
 508 static int
 509 nouveau_card_channel_init(struct drm_device *dev)
 510 {
 511         struct drm_nouveau_private *dev_priv = dev->dev_private;
 512         struct nouveau_channel *chan;
 513         int ret;
 514
 515         ret = nouveau_channel_alloc(dev, &chan, NULL, NvDmaFB, NvDmaTT);
 516         dev_priv->channel = chan;
 517         if (ret)
 518                 return ret;
 519         mutex_unlock(&dev_priv->channel->mutex);
 520
 521         nouveau_bo_move_init(chan);
 522         return 0;
 523 }
 524
 525 static const struct vga_switcheroo_client_ops nouveau_switcheroo_ops = {
 526         .set_gpu_state = nouveau_switcheroo_set_state,
 527         .reprobe = nouveau_switcheroo_reprobe,
 528         .can_switch = nouveau_switcheroo_can_switch,
 529 };
 530
 531 int
 532 nouveau_card_init(struct drm_device *dev)
 533 {
 534         struct drm_nouveau_private *dev_priv = dev->dev_private;
 535         struct nouveau_engine *engine;
 536         int ret, e = 0;
 537
 538         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 539         vga_switcheroo_register_client(dev->pdev, &nouveau_switcheroo_ops);
 540
 541         /* Initialise internal driver API hooks */
 542         ret = nouveau_init_engine_ptrs(dev);
 543         if (ret)
 544                 goto out;
 545         engine = &dev_priv->engine;
 546         spin_lock_init(&dev_priv->channels.lock);
 547         spin_lock_init(&dev_priv->tile.lock);
 548         spin_lock_init(&dev_priv->context_switch_lock);
 549         spin_lock_init(&dev_priv->vm_lock);
 550
 551         /* Make sure the AGP controller is in a consistent state */
 552         nouveau_agp_reset(dev);
 553
 554         /* Make the CRTCs and I2C buses accessible */
 555         ret = engine->display.early_init(dev);
 556         if (ret)
 557                 goto out;
 558
 559         /* Parse BIOS tables / Run init tables if card not POSTed */
 560         ret = nouveau_bios_init(dev);
 561         if (ret)
 562                 goto out_display_early;
 563
 564         /* workaround an odd issue on nvc1 by disabling the device's
 565          * nosnoop capability.  hopefully won't cause issues until a
 566          * better fix is found - assuming there is one...
 567          */
 568         if (dev_priv->chipset == 0xc1) {
 569                 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
 570         }
 571
 572         /* PMC */
 573         ret = engine->mc.init(dev);
 574         if (ret)
 575                 goto out_bios;
 576
 577         /* PTIMER */
 578         ret = engine->timer.init(dev);
 579         if (ret)
 580                 goto out_mc;
 581
 582         /* PFB */
 583         ret = engine->fb.init(dev);
 584         if (ret)
 585                 goto out_timer;
 586
 587         ret = engine->vram.init(dev);
 588         if (ret)
 589                 goto out_fb;
 590
 591         /* PGPIO */
 592         ret = nouveau_gpio_create(dev);
 593         if (ret)
 594                 goto out_vram;
 595
 596         ret = nouveau_gpuobj_init(dev);
 597         if (ret)
 598                 goto out_gpio;
 599
 600         ret = engine->instmem.init(dev);
 601         if (ret)
 602                 goto out_gpuobj;
 603
 604         ret = nouveau_mem_vram_init(dev);
 605         if (ret)
 606                 goto out_instmem;
 607
 608         ret = nouveau_mem_gart_init(dev);
 609         if (ret)
 610                 goto out_ttmvram;
 611
 612         if (!dev_priv->noaccel) {
 613                 switch (dev_priv->card_type) {
 614                 case NV_04:
 615                         nv04_fifo_create(dev);
 616                         break;
 617                 case NV_10:
 618                 case NV_20:
 619                 case NV_30:
 620                         if (dev_priv->chipset < 0x17)
 621                                 nv10_fifo_create(dev);
 622                         else
 623                                 nv17_fifo_create(dev);
 624                         break;
 625                 case NV_40:
 626                         nv40_fifo_create(dev);
 627                         break;
 628                 case NV_50:
 629                         if (dev_priv->chipset == 0x50)
 630                                 nv50_fifo_create(dev);
 631                         else
 632                                 nv84_fifo_create(dev);
 633                         break;
 634                 case NV_C0:
 635                 case NV_D0:
 636                         nvc0_fifo_create(dev);
 637                         break;
 638                 case NV_E0:
 639                         nve0_fifo_create(dev);
 640                         break;
 641                 default:
 642                         break;
 643                 }
 644
 645                 switch (dev_priv->card_type) {
 646                 case NV_04:
 647                         nv04_fence_create(dev);
 648                         break;
 649                 case NV_10:
 650                 case NV_20:
 651                 case NV_30:
 652                 case NV_40:
 653                 case NV_50:
 654                         if (dev_priv->chipset < 0x84)
 655                                 nv10_fence_create(dev);
 656                         else
 657                                 nv84_fence_create(dev);
 658                         break;
 659                 case NV_C0:
 660                 case NV_D0:
 661                 case NV_E0:
 662                         nvc0_fence_create(dev);
 663                         break;
 664                 default:
 665                         break;
 666                 }
 667
 668                 switch (dev_priv->card_type) {
 669                 case NV_04:
 670                 case NV_10:
 671                 case NV_20:
 672                 case NV_30:
 673                 case NV_40:
 674                         nv04_software_create(dev);
 675                         break;
 676                 case NV_50:
 677                         nv50_software_create(dev);
 678                         break;
 679                 case NV_C0:
 680                 case NV_D0:
 681                 case NV_E0:
 682                         nvc0_software_create(dev);
 683                         break;
 684                 default:
 685                         break;
 686                 }
 687
 688                 switch (dev_priv->card_type) {
 689                 case NV_04:
 690                         nv04_graph_create(dev);
 691                         break;
 692                 case NV_10:
 693                         nv10_graph_create(dev);
 694                         break;
 695                 case NV_20:
 696                 case NV_30:
 697                         nv20_graph_create(dev);
 698                         break;
 699                 case NV_40:
 700                         nv40_graph_create(dev);
 701                         break;
 702                 case NV_50:
 703                         nv50_graph_create(dev);
 704                         break;
 705                 case NV_C0:
 706                 case NV_D0:
 707                         nvc0_graph_create(dev);
 708                         break;
 709                 case NV_E0:
 710                         nve0_graph_create(dev);
 711                         break;
 712                 default:
 713                         break;
 714                 }
 715
 716                 switch (dev_priv->chipset) {
 717                 case 0x84:
 718                 case 0x86:
 719                 case 0x92:
 720                 case 0x94:
 721                 case 0x96:
 722                 case 0xa0:
 723                         nv84_crypt_create(dev);
 724                         break;
 725                 case 0x98:
 726                 case 0xaa:
 727                 case 0xac:
 728                         nv98_crypt_create(dev);
 729                         break;
 730                 }
 731
 732                 switch (dev_priv->card_type) {
 733                 case NV_50:
 734                         switch (dev_priv->chipset) {
 735                         case 0xa3:
 736                         case 0xa5:
 737                         case 0xa8:
 738                                 nva3_copy_create(dev);
 739                                 break;
 740                         }
 741                         break;
 742                 case NV_C0:
 743                         if (!(nv_rd32(dev, 0x022500) & 0x00000200))
 744                                 nvc0_copy_create(dev, 1);
 745                 case NV_D0:
 746                         if (!(nv_rd32(dev, 0x022500) & 0x00000100))
 747                                 nvc0_copy_create(dev, 0);
 748                         break;
 749                 default:
 750                         break;
 751                 }
 752
 753                 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
 754                         nv84_bsp_create(dev);
 755                         nv84_vp_create(dev);
 756                         nv98_ppp_create(dev);
 757                 } else
 758                 if (dev_priv->chipset >= 0x84) {
 759                         nv50_mpeg_create(dev);
 760                         nv84_bsp_create(dev);
 761                         nv84_vp_create(dev);
 762                 } else
 763                 if (dev_priv->chipset >= 0x50) {
 764                         nv50_mpeg_create(dev);
 765                 } else
 766                 if (dev_priv->card_type == NV_40 ||
 767                     dev_priv->chipset == 0x31 ||
 768                     dev_priv->chipset == 0x34 ||
 769                     dev_priv->chipset == 0x36) {
 770                         nv31_mpeg_create(dev);
 771                 }
 772
 773                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 774                         if (dev_priv->eng[e]) {
 775                                 ret = dev_priv->eng[e]->init(dev, e);
 776                                 if (ret)
 777                                         goto out_engine;
 778                         }
 779                 }
 780         }
 781
 782         ret = nouveau_irq_init(dev);
 783         if (ret)
 784                 goto out_engine;
 785
 786         ret = nouveau_display_create(dev);
 787         if (ret)
 788                 goto out_irq;
 789
 790         nouveau_backlight_init(dev);
 791         nouveau_pm_init(dev);
 792
 793         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 794                 ret = nouveau_card_channel_init(dev);
 795                 if (ret)
 796                         goto out_pm;
 797         }
 798
 799         if (dev->mode_config.num_crtc) {
 800                 ret = nouveau_display_init(dev);
 801                 if (ret)
 802                         goto out_chan;
 803
 804                 nouveau_fbcon_init(dev);
 805         }
 806
 807         return 0;
 808
 809 out_chan:
 810         nouveau_card_channel_fini(dev);
 811 out_pm:
 812         nouveau_pm_fini(dev);
 813         nouveau_backlight_exit(dev);
 814         nouveau_display_destroy(dev);
 815 out_irq:
 816         nouveau_irq_fini(dev);
 817 out_engine:
 818         if (!dev_priv->noaccel) {
 819                 for (e = e - 1; e >= 0; e--) {
 820                         if (!dev_priv->eng[e])
 821                                 continue;
 822                         dev_priv->eng[e]->fini(dev, e, false);
 823                         dev_priv->eng[e]->destroy(dev,e );
 824                 }
 825         }
 826         nouveau_mem_gart_fini(dev);
 827 out_ttmvram:
 828         nouveau_mem_vram_fini(dev);
 829 out_instmem:
 830         engine->instmem.takedown(dev);
 831 out_gpuobj:
 832         nouveau_gpuobj_takedown(dev);
 833 out_gpio:
 834         nouveau_gpio_destroy(dev);
 835 out_vram:
 836         engine->vram.takedown(dev);
 837 out_fb:
 838         engine->fb.takedown(dev);
 839 out_timer:
 840         engine->timer.takedown(dev);
 841 out_mc:
 842         engine->mc.takedown(dev);
 843 out_bios:
 844         nouveau_bios_takedown(dev);
 845 out_display_early:
 846         engine->display.late_takedown(dev);
 847 out:
 848         vga_switcheroo_unregister_client(dev->pdev);
 849         vga_client_register(dev->pdev, NULL, NULL, NULL);
 850         return ret;
 851 }
 852
 853 static void nouveau_card_takedown(struct drm_device *dev)
 854 {
 855         struct drm_nouveau_private *dev_priv = dev->dev_private;
 856         struct nouveau_engine *engine = &dev_priv->engine;
 857         int e;
 858
 859         if (dev->mode_config.num_crtc) {
 860                 nouveau_fbcon_fini(dev);
 861                 nouveau_display_fini(dev);
 862         }
 863
 864         nouveau_card_channel_fini(dev);
 865         nouveau_pm_fini(dev);
 866         nouveau_backlight_exit(dev);
 867         nouveau_display_destroy(dev);
 868
 869         if (!dev_priv->noaccel) {
 870                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
 871                         if (dev_priv->eng[e]) {
 872                                 dev_priv->eng[e]->fini(dev, e, false);
 873                                 dev_priv->eng[e]->destroy(dev,e );
 874                         }
 875                 }
 876         }
 877
 878         if (dev_priv->vga_ram) {
 879                 nouveau_bo_unpin(dev_priv->vga_ram);
 880                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 881         }
 882
 883         mutex_lock(&dev->struct_mutex);
 884         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 885         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 886         mutex_unlock(&dev->struct_mutex);
 887         nouveau_mem_gart_fini(dev);
 888         nouveau_mem_vram_fini(dev);
 889
 890         engine->instmem.takedown(dev);
 891         nouveau_gpuobj_takedown(dev);
 892
 893         nouveau_gpio_destroy(dev);
 894         engine->vram.takedown(dev);
 895         engine->fb.takedown(dev);
 896         engine->timer.takedown(dev);
 897         engine->mc.takedown(dev);
 898
 899         nouveau_bios_takedown(dev);
 900         engine->display.late_takedown(dev);
 901
 902         nouveau_irq_fini(dev);
 903
 904         vga_switcheroo_unregister_client(dev->pdev);
 905         vga_client_register(dev->pdev, NULL, NULL, NULL);
 906 }
 907
 908 int
 909 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
 910 {
 911         struct drm_nouveau_private *dev_priv = dev->dev_private;
 912         struct nouveau_fpriv *fpriv;
 913         int ret;
 914
 915         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 916         if (unlikely(!fpriv))
 917                 return -ENOMEM;
 918
 919         spin_lock_init(&fpriv->lock);
 920         INIT_LIST_HEAD(&fpriv->channels);
 921
 922         if (dev_priv->card_type == NV_50) {
 923                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
 924                                      &fpriv->vm);
 925                 if (ret) {
 926                         kfree(fpriv);
 927                         return ret;
 928                 }
 929         } else
 930         if (dev_priv->card_type >= NV_C0) {
 931                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
 932                                      &fpriv->vm);
 933                 if (ret) {
 934                         kfree(fpriv);
 935                         return ret;
 936                 }
 937         }
 938
 939         file_priv->driver_priv = fpriv;
 940         return 0;
 941 }
 942
 943 /* here a client dies, release the stuff that was allocated for its
 944  * file_priv */
 945 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 946 {
 947         nouveau_channel_cleanup(dev, file_priv);
 948 }
 949
 950 void
 951 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
 952 {
 953         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
 954         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
 955         kfree(fpriv);
 956 }
 957
 958 /* first module load, setup the mmio/fb mapping */
 959 /* KMS: we need mmio at load time, not when the first drm client opens. */
 960 int nouveau_firstopen(struct drm_device *dev)
 961 {
 962         return 0;
 963 }
 964
 965 /* if we have an OF card, copy vbios to RAMIN */
 966 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 967 {
 968 #if defined(__powerpc__)
 969         int size, i;
 970         const uint32_t *bios;
 971         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 972         if (!dn) {
 973                 NV_INFO(dev, "Unable to get the OF node\n");
 974                 return;
 975         }
 976
 977         bios = of_get_property(dn, "NVDA,BMP", &size);
 978         if (bios) {
 979                 for (i = 0; i < size; i += 4)
 980                         nv_wi32(dev, i, bios[i/4]);
 981                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 982         } else {
 983                 NV_INFO(dev, "Unable to get the OF bios\n");
 984         }
 985 #endif
 986 }
 987
 988 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 989 {
 990         struct pci_dev *pdev = dev->pdev;
 991         struct apertures_struct *aper = alloc_apertures(3);
 992         if (!aper)
 993                 return NULL;
 994
 995         aper->ranges[0].base = pci_resource_start(pdev, 1);
 996         aper->ranges[0].size = pci_resource_len(pdev, 1);
 997         aper->count = 1;
 998
 999         if (pci_resource_len(pdev, 2)) {
1000                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
1001                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
1002                 aper->count++;
1003         }
1004
1005         if (pci_resource_len(pdev, 3)) {
1006                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
1007                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
1008                 aper->count++;
1009         }
1010
1011         return aper;
1012 }
1013
1014 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
1015 {
1016         struct drm_nouveau_private *dev_priv = dev->dev_private;
1017         bool primary = false;
1018         dev_priv->apertures = nouveau_get_apertures(dev);
1019         if (!dev_priv->apertures)
1020                 return -ENOMEM;
1021
1022 #ifdef CONFIG_X86
1023         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1024 #endif
1025
1026         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
1027         return 0;
1028 }
1029
1030 void *
1031 nouveau_newpriv(struct drm_device *dev)
1032 {
1033         struct drm_nouveau_private *dev_priv = dev->dev_private;
1034         return dev_priv->newpriv;
1035 }
1036
1037 int nouveau_load(struct drm_device *dev, unsigned long flags)
1038 {
1039         struct drm_nouveau_private *dev_priv;
1040         uint32_t reg0 = ~0, strap;
1041         int ret;
1042
1043         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1044         if (!dev_priv) {
1045                 ret = -ENOMEM;
1046                 goto err_out;
1047         }
1048         dev_priv->newpriv = dev->dev_private;
1049         dev->dev_private = dev_priv;
1050         dev_priv->dev = dev;
1051
1052         dev_priv->flags = flags & NOUVEAU_FLAGS;
1053
1054         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1055                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
1056
1057         /* determine chipset and derive architecture from it */
1058         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1059         if ((reg0 & 0x0f000000) > 0) {
1060                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1061                 switch (dev_priv->chipset & 0xf0) {
1062                 case 0x10:
1063                 case 0x20:
1064                 case 0x30:
1065                         dev_priv->card_type = dev_priv->chipset & 0xf0;
1066                         break;
1067                 case 0x40:
1068                 case 0x60:
1069                         dev_priv->card_type = NV_40;
1070                         break;
1071                 case 0x50:
1072                 case 0x80:
1073                 case 0x90:
1074                 case 0xa0:
1075                         dev_priv->card_type = NV_50;
1076                         break;
1077                 case 0xc0:
1078                         dev_priv->card_type = NV_C0;
1079                         break;
1080                 case 0xd0:
1081                         dev_priv->card_type = NV_D0;
1082                         break;
1083                 case 0xe0:
1084                         dev_priv->card_type = NV_E0;
1085                         break;
1086                 default:
1087                         break;
1088                 }
1089         } else
1090         if ((reg0 & 0xff00fff0) == 0x20004000) {
1091                 if (reg0 & 0x00f00000)
1092                         dev_priv->chipset = 0x05;
1093                 else
1094                         dev_priv->chipset = 0x04;
1095                 dev_priv->card_type = NV_04;
1096         }
1097
1098         if (!dev_priv->card_type) {
1099                 NV_ERROR(dev, "unsupported chipset 0x%08x\n", reg0);
1100                 ret = -EINVAL;
1101                 goto err_priv;
1102         }
1103
1104         NV_INFO(dev, "Detected an NV%02x generation card (0x%08x)\n",
1105                      dev_priv->card_type, reg0);
1106
1107         /* determine frequency of timing crystal */
1108         strap = nv_rd32(dev, 0x101000);
1109         if ( dev_priv->chipset < 0x17 ||
1110             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1111                 strap &= 0x00000040;
1112         else
1113                 strap &= 0x00400040;
1114
1115         switch (strap) {
1116         case 0x00000000: dev_priv->crystal = 13500; break;
1117         case 0x00000040: dev_priv->crystal = 14318; break;
1118         case 0x00400000: dev_priv->crystal = 27000; break;
1119         case 0x00400040: dev_priv->crystal = 25000; break;
1120         }
1121
1122         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1123
1124         /* Determine whether we'll attempt acceleration or not, some
1125          * cards are disabled by default here due to them being known
1126          * non-functional, or never been tested due to lack of hw.
1127          */
1128         dev_priv->noaccel = !!nouveau_noaccel;
1129         if (nouveau_noaccel == -1) {
1130                 switch (dev_priv->chipset) {
1131                 case 0xd9: /* known broken */
1132                 case 0xe4: /* needs binary driver firmware */
1133                 case 0xe7: /* needs binary driver firmware */
1134                         NV_INFO(dev, "acceleration disabled by default, pass "
1135                                      "noaccel=0 to force enable\n");
1136                         dev_priv->noaccel = true;
1137                         break;
1138                 default:
1139                         dev_priv->noaccel = false;
1140                         break;
1141                 }
1142         }
1143
1144         ret = nouveau_remove_conflicting_drivers(dev);
1145         if (ret)
1146                 goto err_priv;
1147
1148         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1149         if (dev_priv->card_type >= NV_40) {
1150                 int ramin_bar = 2;
1151                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1152                         ramin_bar = 3;
1153
1154                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1155                 dev_priv->ramin =
1156                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1157                                 dev_priv->ramin_size);
1158                 if (!dev_priv->ramin) {
1159                         NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1160                         ret = -ENOMEM;
1161                         goto err_priv;
1162                 }
1163         } else {
1164                 dev_priv->ramin_size = 1 * 1024 * 1024;
1165                 dev_priv->ramin = ioremap(pci_resource_start(dev->pdev, 0),
1166                                           dev_priv->ramin_size);
1167                 if (!dev_priv->ramin) {
1168                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1169                         ret = -ENOMEM;
1170                         goto err_priv;
1171                 }
1172         }
1173
1174         nouveau_OF_copy_vbios_to_ramin(dev);
1175
1176         /* Special flags */
1177         if (dev->pci_device == 0x01a0)
1178                 dev_priv->flags |= NV_NFORCE;
1179         else if (dev->pci_device == 0x01f0)
1180                 dev_priv->flags |= NV_NFORCE2;
1181
1182         /* For kernel modesetting, init card now and bring up fbcon */
1183         ret = nouveau_card_init(dev);
1184         if (ret)
1185                 goto err_ramin;
1186
1187         return 0;
1188
1189 err_ramin:
1190         iounmap(dev_priv->ramin);
1191 err_priv:
1192         dev->dev_private = dev_priv->newpriv;
1193         kfree(dev_priv);
1194 err_out:
1195         return ret;
1196 }
1197
1198 void nouveau_lastclose(struct drm_device *dev)
1199 {
1200         vga_switcheroo_process_delayed_switch();
1201 }
1202
1203 int nouveau_unload(struct drm_device *dev)
1204 {
1205         struct drm_nouveau_private *dev_priv = dev->dev_private;
1206
1207         nouveau_card_takedown(dev);
1208
1209         iounmap(dev_priv->ramin);
1210
1211         dev->dev_private = dev_priv->newpriv;
1212         kfree(dev_priv);
1213         return 0;
1214 }
1215
1216 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1217 bool
1218 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1219                 uint32_t reg, uint32_t mask, uint32_t val)
1220 {
1221         struct drm_nouveau_private *dev_priv = dev->dev_private;
1222         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1223         uint64_t start = ptimer->read(dev);
1224
1225         do {
1226                 if ((nv_rd32(dev, reg) & mask) == val)
1227                         return true;
1228         } while (ptimer->read(dev) - start < timeout);
1229
1230         return false;
1231 }
1232
1233 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1234 bool
1235 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1236                 uint32_t reg, uint32_t mask, uint32_t val)
1237 {
1238         struct drm_nouveau_private *dev_priv = dev->dev_private;
1239         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1240         uint64_t start = ptimer->read(dev);
1241
1242         do {
1243                 if ((nv_rd32(dev, reg) & mask) != val)
1244                         return true;
1245         } while (ptimer->read(dev) - start < timeout);
1246
1247         return false;
1248 }
1249
1250 /* Wait until cond(data) == true, up until timeout has hit */
1251 bool
1252 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1253                 bool (*cond)(void *), void *data)
1254 {
1255         struct drm_nouveau_private *dev_priv = dev->dev_private;
1256         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1257         u64 start = ptimer->read(dev);
1258
1259         do {
1260                 if (cond(data) == true)
1261                         return true;
1262         } while (ptimer->read(dev) - start < timeout);
1263
1264         return false;
1265 }
1266
1267 /* Waits for PGRAPH to go completely idle */
1268 bool nouveau_wait_for_idle(struct drm_device *dev)
1269 {
1270         struct drm_nouveau_private *dev_priv = dev->dev_private;
1271         uint32_t mask = ~0;
1272
1273         if (dev_priv->card_type == NV_40)
1274                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1275
1276         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1277                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1278                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1279                 return false;
1280         }
1281
1282         return true;
1283 }
1284