2 * Copyright (C) 2008 Maarten Maathuis.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "drm_crtc_helper.h"
31 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
32 #include "nouveau_reg.h"
33 #include "nouveau_drv.h"
34 #include "nouveau_hw.h"
35 #include "nouveau_encoder.h"
36 #include "nouveau_crtc.h"
37 #include "nouveau_fb.h"
38 #include "nouveau_connector.h"
39 #include "nv50_display.h"
42 nv50_crtc_lut_load(struct drm_crtc *crtc)
44 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
45 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
48 NV_DEBUG_KMS(crtc->dev, "\n");
50 for (i = 0; i < 256; i++) {
51 writew(nv_crtc->lut.r[i] >> 2, lut + 8*i + 0);
52 writew(nv_crtc->lut.g[i] >> 2, lut + 8*i + 2);
53 writew(nv_crtc->lut.b[i] >> 2, lut + 8*i + 4);
56 if (nv_crtc->lut.depth == 30) {
57 writew(nv_crtc->lut.r[i - 1] >> 2, lut + 8*i + 0);
58 writew(nv_crtc->lut.g[i - 1] >> 2, lut + 8*i + 2);
59 writew(nv_crtc->lut.b[i - 1] >> 2, lut + 8*i + 4);
64 nv50_crtc_blank(struct nouveau_crtc *nv_crtc, bool blanked)
66 struct drm_device *dev = nv_crtc->base.dev;
67 struct drm_nouveau_private *dev_priv = dev->dev_private;
68 struct nouveau_channel *evo = nv50_display(dev)->master;
69 int index = nv_crtc->index, ret;
71 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
72 NV_DEBUG_KMS(dev, "%s\n", blanked ? "blanked" : "unblanked");
75 nv_crtc->cursor.hide(nv_crtc, false);
77 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 7 : 5);
79 NV_ERROR(dev, "no space while blanking crtc\n");
82 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
83 OUT_RING(evo, NV50_EVO_CRTC_CLUT_MODE_BLANK);
85 if (dev_priv->chipset != 0x50) {
86 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
87 OUT_RING(evo, NV84_EVO_CRTC_CLUT_DMA_HANDLE_NONE);
90 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
91 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
93 if (nv_crtc->cursor.visible)
94 nv_crtc->cursor.show(nv_crtc, false);
96 nv_crtc->cursor.hide(nv_crtc, false);
98 ret = RING_SPACE(evo, dev_priv->chipset != 0x50 ? 10 : 8);
100 NV_ERROR(dev, "no space while unblanking crtc\n");
103 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, CLUT_MODE), 2);
104 OUT_RING(evo, nv_crtc->lut.depth == 8 ?
105 NV50_EVO_CRTC_CLUT_MODE_OFF :
106 NV50_EVO_CRTC_CLUT_MODE_ON);
107 OUT_RING(evo, nv_crtc->lut.nvbo->bo.offset >> 8);
108 if (dev_priv->chipset != 0x50) {
109 BEGIN_RING(evo, 0, NV84_EVO_CRTC(index, CLUT_DMA), 1);
110 OUT_RING(evo, NvEvoVRAM);
113 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_OFFSET), 2);
114 OUT_RING(evo, nv_crtc->fb.offset >> 8);
116 BEGIN_RING(evo, 0, NV50_EVO_CRTC(index, FB_DMA), 1);
117 if (dev_priv->chipset != 0x50)
118 if (nv_crtc->fb.tile_flags == 0x7a00 ||
119 nv_crtc->fb.tile_flags == 0xfe00)
120 OUT_RING(evo, NvEvoFB32);
122 if (nv_crtc->fb.tile_flags == 0x7000)
123 OUT_RING(evo, NvEvoFB16);
125 OUT_RING(evo, NvEvoVRAM_LP);
127 OUT_RING(evo, NvEvoVRAM_LP);
130 nv_crtc->fb.blanked = blanked;
135 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
137 struct nouveau_channel *evo = nv50_display(nv_crtc->base.dev)->master;
138 struct nouveau_connector *nv_connector;
139 struct drm_connector *connector;
140 int head = nv_crtc->index, ret;
143 nv_connector = nouveau_crtc_connector_get(nv_crtc);
144 connector = &nv_connector->base;
145 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
146 if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3)
147 mode = DITHERING_MODE_DYNAMIC2X2;
149 mode = nv_connector->dithering_mode;
152 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
153 if (connector->display_info.bpc >= 8)
154 mode |= DITHERING_DEPTH_8BPC;
156 mode |= nv_connector->dithering_depth;
159 ret = RING_SPACE(evo, 2 + (update ? 2 : 0));
161 BEGIN_RING(evo, 0, NV50_EVO_CRTC(head, DITHER_CTRL), 1);
162 OUT_RING (evo, mode);
164 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
173 struct nouveau_connector *
174 nouveau_crtc_connector_get(struct nouveau_crtc *nv_crtc)
176 struct drm_device *dev = nv_crtc->base.dev;
177 struct drm_connector *connector;
178 struct drm_crtc *crtc = to_drm_crtc(nv_crtc);
180 /* The safest approach is to find an encoder with the right crtc, that
181 * is also linked to a connector. */
182 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
183 if (connector->encoder)
184 if (connector->encoder->crtc == crtc)
185 return nouveau_connector(connector);
192 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
194 struct nouveau_connector *nv_connector;
195 struct drm_crtc *crtc = &nv_crtc->base;
196 struct drm_device *dev = crtc->dev;
197 struct nouveau_channel *evo = nv50_display(dev)->master;
198 struct drm_display_mode *mode = &crtc->mode;
199 int scaling_mode, ret;
200 u32 ctrl = 0, oX, oY;
202 NV_DEBUG_KMS(dev, "\n");
204 nv_connector = nouveau_crtc_connector_get(nv_crtc);
205 if (!nv_connector || !nv_connector->native_mode) {
206 NV_ERROR(dev, "no native mode, forcing panel scaling\n");
207 scaling_mode = DRM_MODE_SCALE_NONE;
209 scaling_mode = nv_connector->scaling_mode;
212 /* start off at the resolution we programmed the crtc for, this
213 * effectively handles NONE/FULL scaling
215 if (scaling_mode != DRM_MODE_SCALE_NONE) {
216 oX = nv_connector->native_mode->hdisplay;
217 oY = nv_connector->native_mode->vdisplay;
223 /* add overscan compensation if necessary, will keep the aspect
224 * ratio the same as the backend mode unless overridden by the
225 * user setting both hborder and vborder properties.
227 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
228 (nv_connector->underscan == UNDERSCAN_AUTO &&
229 nv_connector->edid &&
230 drm_detect_hdmi_monitor(nv_connector->edid)))) {
231 u32 bX = nv_connector->underscan_hborder;
232 u32 bY = nv_connector->underscan_vborder;
233 u32 aspect = (oY << 19) / oX;
237 if (bY) oY -= (bY * 2);
238 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
240 oX -= (oX >> 4) + 32;
241 if (bY) oY -= (bY * 2);
242 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
246 /* handle CENTER/ASPECT scaling, taking into account the areas
247 * removed already for overscan compensation
249 switch (scaling_mode) {
250 case DRM_MODE_SCALE_CENTER:
251 oX = min((u32)mode->hdisplay, oX);
252 oY = min((u32)mode->vdisplay, oY);
254 case DRM_MODE_SCALE_ASPECT:
256 u32 aspect = (mode->hdisplay << 19) / mode->vdisplay;
257 oX = ((oY * aspect) + (aspect / 2)) >> 19;
259 u32 aspect = (mode->vdisplay << 19) / mode->hdisplay;
260 oY = ((oX * aspect) + (aspect / 2)) >> 19;
267 if (mode->hdisplay != oX || mode->vdisplay != oY ||
268 mode->flags & DRM_MODE_FLAG_INTERLACE ||
269 mode->flags & DRM_MODE_FLAG_DBLSCAN)
270 ctrl |= NV50_EVO_CRTC_SCALE_CTRL_ACTIVE;
272 ret = RING_SPACE(evo, 5);
276 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CTRL), 1);
277 OUT_RING (evo, ctrl);
278 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_RES1), 2);
279 OUT_RING (evo, oY << 16 | oX);
280 OUT_RING (evo, oY << 16 | oX);
283 nv50_display_flip_stop(crtc);
284 nv50_display_sync(dev);
285 nv50_display_flip_next(crtc, crtc->fb, NULL);
292 nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
294 struct drm_nouveau_private *dev_priv = dev->dev_private;
297 int ret, N1, M1, N2, M2, P;
299 ret = get_pll_limits(dev, PLL_VPLL0 + head, &pll);
303 if (pll.vco2.maxfreq) {
304 ret = nv50_calc_pll(dev, &pll, pclk, &N1, &M1, &N2, &M2, &P);
308 NV_DEBUG(dev, "pclk %d out %d NM1 %d %d NM2 %d %d P %d\n",
309 pclk, ret, N1, M1, N2, M2, P);
311 reg1 = nv_rd32(dev, pll.reg + 4) & 0xff00ff00;
312 reg2 = nv_rd32(dev, pll.reg + 8) & 0x8000ff00;
313 nv_wr32(dev, pll.reg + 0, 0x10000611);
314 nv_wr32(dev, pll.reg + 4, reg1 | (M1 << 16) | N1);
315 nv_wr32(dev, pll.reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
317 if (dev_priv->chipset < NV_C0) {
318 ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P);
322 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
323 pclk, ret, N1, N2, M1, P);
325 reg1 = nv_rd32(dev, pll.reg + 4) & 0xffc00000;
326 nv_wr32(dev, pll.reg + 0, 0x50000610);
327 nv_wr32(dev, pll.reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
328 nv_wr32(dev, pll.reg + 8, N2);
330 ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P);
334 NV_DEBUG(dev, "pclk %d out %d N %d fN 0x%04x M %d P %d\n",
335 pclk, ret, N1, N2, M1, P);
337 nv_mask(dev, pll.reg + 0x0c, 0x00000000, 0x00000100);
338 nv_wr32(dev, pll.reg + 0x04, (P << 16) | (N1 << 8) | M1);
339 nv_wr32(dev, pll.reg + 0x10, N2 << 16);
346 nv50_crtc_destroy(struct drm_crtc *crtc)
348 struct drm_device *dev;
349 struct nouveau_crtc *nv_crtc;
355 nv_crtc = nouveau_crtc(crtc);
357 NV_DEBUG_KMS(dev, "\n");
359 drm_crtc_cleanup(&nv_crtc->base);
361 nouveau_bo_unmap(nv_crtc->lut.nvbo);
362 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
363 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
364 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
365 kfree(nv_crtc->mode);
370 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
371 uint32_t buffer_handle, uint32_t width, uint32_t height)
373 struct drm_device *dev = crtc->dev;
374 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
375 struct nouveau_bo *cursor = NULL;
376 struct drm_gem_object *gem;
379 if (!buffer_handle) {
380 nv_crtc->cursor.hide(nv_crtc, true);
384 if (width != 64 || height != 64)
387 gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
390 cursor = nouveau_gem_object(gem);
392 ret = nouveau_bo_map(cursor);
396 /* The simple will do for now. */
397 for (i = 0; i < 64 * 64; i++)
398 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, nouveau_bo_rd32(cursor, i));
400 nouveau_bo_unmap(cursor);
402 nv_crtc->cursor.set_offset(nv_crtc, nv_crtc->cursor.nvbo->bo.offset);
403 nv_crtc->cursor.show(nv_crtc, true);
406 drm_gem_object_unreference_unlocked(gem);
411 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
413 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
415 nv_crtc->cursor.set_pos(nv_crtc, x, y);
420 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
421 uint32_t start, uint32_t size)
423 int end = (start + size > 256) ? 256 : start + size, i;
424 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
426 for (i = start; i < end; i++) {
427 nv_crtc->lut.r[i] = r[i];
428 nv_crtc->lut.g[i] = g[i];
429 nv_crtc->lut.b[i] = b[i];
432 /* We need to know the depth before we upload, but it's possible to
433 * get called before a framebuffer is bound. If this is the case,
434 * mark the lut values as dirty by setting depth==0, and it'll be
435 * uploaded on the first mode_set_base()
437 if (!nv_crtc->base.fb) {
438 nv_crtc->lut.depth = 0;
442 nv50_crtc_lut_load(crtc);
446 nv50_crtc_save(struct drm_crtc *crtc)
448 NV_ERROR(crtc->dev, "!!\n");
452 nv50_crtc_restore(struct drm_crtc *crtc)
454 NV_ERROR(crtc->dev, "!!\n");
457 static const struct drm_crtc_funcs nv50_crtc_funcs = {
458 .save = nv50_crtc_save,
459 .restore = nv50_crtc_restore,
460 .cursor_set = nv50_crtc_cursor_set,
461 .cursor_move = nv50_crtc_cursor_move,
462 .gamma_set = nv50_crtc_gamma_set,
463 .set_config = drm_crtc_helper_set_config,
464 .page_flip = nouveau_crtc_page_flip,
465 .destroy = nv50_crtc_destroy,
469 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
474 nv50_crtc_prepare(struct drm_crtc *crtc)
476 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
477 struct drm_device *dev = crtc->dev;
479 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
481 nv50_display_flip_stop(crtc);
482 drm_vblank_pre_modeset(dev, nv_crtc->index);
483 nv50_crtc_blank(nv_crtc, true);
487 nv50_crtc_commit(struct drm_crtc *crtc)
489 struct drm_device *dev = crtc->dev;
490 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
492 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
494 nv50_crtc_blank(nv_crtc, false);
495 drm_vblank_post_modeset(dev, nv_crtc->index);
496 nv50_display_sync(dev);
497 nv50_display_flip_next(crtc, crtc->fb, NULL);
501 nv50_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
502 struct drm_display_mode *adjusted_mode)
508 nv50_crtc_do_mode_set_base(struct drm_crtc *crtc,
509 struct drm_framebuffer *passed_fb,
510 int x, int y, bool atomic)
512 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
513 struct drm_device *dev = nv_crtc->base.dev;
514 struct drm_nouveau_private *dev_priv = dev->dev_private;
515 struct nouveau_channel *evo = nv50_display(dev)->master;
516 struct drm_framebuffer *drm_fb;
517 struct nouveau_framebuffer *fb;
520 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
523 if (!atomic && !crtc->fb) {
524 NV_DEBUG_KMS(dev, "No FB bound\n");
528 /* If atomic, we want to switch to the fb we were passed, so
529 * now we update pointers to do that. (We don't pin; just
530 * assume we're already pinned and update the base address.)
534 fb = nouveau_framebuffer(passed_fb);
537 fb = nouveau_framebuffer(crtc->fb);
538 /* If not atomic, we can go ahead and pin, and unpin the
539 * old fb we were passed.
541 ret = nouveau_bo_pin(fb->nvbo, TTM_PL_FLAG_VRAM);
546 struct nouveau_framebuffer *ofb = nouveau_framebuffer(passed_fb);
547 nouveau_bo_unpin(ofb->nvbo);
551 nv_crtc->fb.offset = fb->nvbo->bo.offset;
552 nv_crtc->fb.tile_flags = nouveau_bo_tile_layout(fb->nvbo);
553 nv_crtc->fb.cpp = drm_fb->bits_per_pixel / 8;
554 if (!nv_crtc->fb.blanked && dev_priv->chipset != 0x50) {
555 ret = RING_SPACE(evo, 2);
559 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_DMA), 1);
560 OUT_RING (evo, fb->r_dma);
563 ret = RING_SPACE(evo, 12);
567 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_OFFSET), 5);
568 OUT_RING (evo, nv_crtc->fb.offset >> 8);
570 OUT_RING (evo, (drm_fb->height << 16) | drm_fb->width);
571 OUT_RING (evo, fb->r_pitch);
572 OUT_RING (evo, fb->r_format);
574 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLUT_MODE), 1);
575 OUT_RING (evo, fb->base.depth == 8 ?
576 NV50_EVO_CRTC_CLUT_MODE_OFF : NV50_EVO_CRTC_CLUT_MODE_ON);
578 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, COLOR_CTRL), 1);
579 OUT_RING (evo, NV50_EVO_CRTC_COLOR_CTRL_COLOR);
580 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, FB_POS), 1);
581 OUT_RING (evo, (y << 16) | x);
583 if (nv_crtc->lut.depth != fb->base.depth) {
584 nv_crtc->lut.depth = fb->base.depth;
585 nv50_crtc_lut_load(crtc);
592 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
593 struct drm_display_mode *adjusted_mode, int x, int y,
594 struct drm_framebuffer *old_fb)
596 struct drm_device *dev = crtc->dev;
597 struct nouveau_channel *evo = nv50_display(dev)->master;
598 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
599 struct nouveau_connector *nv_connector = NULL;
600 uint32_t hsync_dur, vsync_dur, hsync_start_to_end, vsync_start_to_end;
601 uint32_t hunk1, vunk1, vunk2a, vunk2b;
604 /* Find the connector attached to this CRTC */
605 nv_connector = nouveau_crtc_connector_get(nv_crtc);
607 *nv_crtc->mode = *adjusted_mode;
609 NV_DEBUG_KMS(dev, "index %d\n", nv_crtc->index);
611 hsync_dur = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
612 vsync_dur = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
613 hsync_start_to_end = adjusted_mode->htotal - adjusted_mode->hsync_start;
614 vsync_start_to_end = adjusted_mode->vtotal - adjusted_mode->vsync_start;
615 /* I can't give this a proper name, anyone else can? */
616 hunk1 = adjusted_mode->htotal -
617 adjusted_mode->hsync_start + adjusted_mode->hdisplay;
618 vunk1 = adjusted_mode->vtotal -
619 adjusted_mode->vsync_start + adjusted_mode->vdisplay;
620 /* Another strange value, this time only for interlaced adjusted_modes. */
621 vunk2a = 2 * adjusted_mode->vtotal -
622 adjusted_mode->vsync_start + adjusted_mode->vdisplay;
623 vunk2b = adjusted_mode->vtotal -
624 adjusted_mode->vsync_start + adjusted_mode->vtotal;
626 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
628 vsync_start_to_end /= 2;
633 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
634 vsync_start_to_end -= 1;
641 ret = RING_SPACE(evo, 19);
645 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, CLOCK), 2);
646 OUT_RING(evo, adjusted_mode->clock | 0x800000);
647 OUT_RING(evo, (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 0);
649 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, DISPLAY_START), 5);
651 OUT_RING(evo, (adjusted_mode->vtotal << 16) | adjusted_mode->htotal);
652 OUT_RING(evo, (vsync_dur - 1) << 16 | (hsync_dur - 1));
653 OUT_RING(evo, (vsync_start_to_end - 1) << 16 |
654 (hsync_start_to_end - 1));
655 OUT_RING(evo, (vunk1 - 1) << 16 | (hunk1 - 1));
657 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
658 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK0824), 1);
659 OUT_RING(evo, (vunk2b - 1) << 16 | (vunk2a - 1));
665 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK082C), 1);
667 /* required to make display sync channel not hate life */
668 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, UNK900), 1);
669 OUT_RING (evo, 0x00000311);
671 /* This is the actual resolution of the mode. */
672 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, REAL_RES), 1);
673 OUT_RING(evo, (mode->vdisplay << 16) | mode->hdisplay);
674 BEGIN_RING(evo, 0, NV50_EVO_CRTC(nv_crtc->index, SCALE_CENTER_OFFSET), 1);
675 OUT_RING(evo, NV50_EVO_CRTC_SCALE_CENTER_OFFSET_VAL(0, 0));
677 nv_crtc->set_dither(nv_crtc, false);
678 nv_crtc->set_scale(nv_crtc, false);
680 return nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
684 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
685 struct drm_framebuffer *old_fb)
689 nv50_display_flip_stop(crtc);
690 ret = nv50_crtc_do_mode_set_base(crtc, old_fb, x, y, false);
694 ret = nv50_display_sync(crtc->dev);
698 return nv50_display_flip_next(crtc, crtc->fb, NULL);
702 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
703 struct drm_framebuffer *fb,
704 int x, int y, enum mode_set_atomic state)
708 nv50_display_flip_stop(crtc);
709 ret = nv50_crtc_do_mode_set_base(crtc, fb, x, y, true);
713 return nv50_display_sync(crtc->dev);
716 static const struct drm_crtc_helper_funcs nv50_crtc_helper_funcs = {
717 .dpms = nv50_crtc_dpms,
718 .prepare = nv50_crtc_prepare,
719 .commit = nv50_crtc_commit,
720 .mode_fixup = nv50_crtc_mode_fixup,
721 .mode_set = nv50_crtc_mode_set,
722 .mode_set_base = nv50_crtc_mode_set_base,
723 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
724 .load_lut = nv50_crtc_lut_load,
728 nv50_crtc_create(struct drm_device *dev, int index)
730 struct nouveau_crtc *nv_crtc = NULL;
733 NV_DEBUG_KMS(dev, "\n");
735 nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
739 nv_crtc->mode = kzalloc(sizeof(*nv_crtc->mode), GFP_KERNEL);
740 if (!nv_crtc->mode) {
745 /* Default CLUT parameters, will be activated on the hw upon
748 for (i = 0; i < 256; i++) {
749 nv_crtc->lut.r[i] = i << 8;
750 nv_crtc->lut.g[i] = i << 8;
751 nv_crtc->lut.b[i] = i << 8;
753 nv_crtc->lut.depth = 0;
755 ret = nouveau_bo_new(dev, 4096, 0x100, TTM_PL_FLAG_VRAM,
756 0, 0x0000, &nv_crtc->lut.nvbo);
758 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
760 ret = nouveau_bo_map(nv_crtc->lut.nvbo);
762 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
766 kfree(nv_crtc->mode);
771 nv_crtc->index = index;
773 /* set function pointers */
774 nv_crtc->set_dither = nv50_crtc_set_dither;
775 nv_crtc->set_scale = nv50_crtc_set_scale;
777 drm_crtc_init(dev, &nv_crtc->base, &nv50_crtc_funcs);
778 drm_crtc_helper_add(&nv_crtc->base, &nv50_crtc_helper_funcs);
779 drm_mode_crtc_set_gamma_size(&nv_crtc->base, 256);
781 ret = nouveau_bo_new(dev, 64*64*4, 0x100, TTM_PL_FLAG_VRAM,
782 0, 0x0000, &nv_crtc->cursor.nvbo);
784 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
786 ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
788 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
791 nv50_cursor_init(nv_crtc);