2 * Copyright 2011 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/dma-mapping.h>
28 #include <drm/drm_crtc_helper.h>
29 #include <drm/drm_dp_helper.h>
31 #include <nvif/class.h>
33 #include "nouveau_drm.h"
34 #include "nouveau_dma.h"
35 #include "nouveau_gem.h"
36 #include "nouveau_connector.h"
37 #include "nouveau_encoder.h"
38 #include "nouveau_crtc.h"
39 #include "nouveau_fence.h"
40 #include "nv50_display.h"
44 #define EVO_MASTER (0x00)
45 #define EVO_FLIP(c) (0x01 + (c))
46 #define EVO_OVLY(c) (0x05 + (c))
47 #define EVO_OIMM(c) (0x09 + (c))
48 #define EVO_CURS(c) (0x0d + (c))
50 /* offsets in shared sync bo of various structures */
51 #define EVO_SYNC(c, o) ((c) * 0x0100 + (o))
52 #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00)
53 #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00)
54 #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10)
56 /******************************************************************************
58 *****************************************************************************/
61 struct nvif_object user;
65 nv50_chan_create(struct nvif_object *disp, const u32 *oclass, u8 head,
66 void *data, u32 size, struct nv50_chan *chan)
69 int ret = nvif_object_init(disp, NULL, (oclass[0] << 16) | head,
70 oclass[0], data, size,
72 if (oclass++, ret == 0) {
73 nvif_object_map(&chan->user);
81 nv50_chan_destroy(struct nv50_chan *chan)
83 nvif_object_fini(&chan->user);
86 /******************************************************************************
88 *****************************************************************************/
91 struct nv50_chan base;
95 nv50_pioc_destroy(struct nv50_pioc *pioc)
97 nv50_chan_destroy(&pioc->base);
101 nv50_pioc_create(struct nvif_object *disp, const u32 *oclass, u8 head,
102 void *data, u32 size, struct nv50_pioc *pioc)
104 return nv50_chan_create(disp, oclass, head, data, size, &pioc->base);
107 /******************************************************************************
109 *****************************************************************************/
112 struct nv50_pioc base;
116 nv50_curs_create(struct nvif_object *disp, int head, struct nv50_curs *curs)
118 struct nv50_disp_cursor_v0 args = {
121 static const u32 oclass[] = {
130 return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
134 /******************************************************************************
136 *****************************************************************************/
139 struct nv50_pioc base;
143 nv50_oimm_create(struct nvif_object *disp, int head, struct nv50_oimm *oimm)
145 struct nv50_disp_cursor_v0 args = {
148 static const u32 oclass[] = {
157 return nv50_pioc_create(disp, oclass, head, &args, sizeof(args),
161 /******************************************************************************
163 *****************************************************************************/
166 struct nv50_chan base;
170 struct nvif_object sync;
171 struct nvif_object vram;
173 /* Protects against concurrent pushbuf access to this channel, lock is
174 * grabbed by evo_wait (if the pushbuf reservation is successful) and
175 * dropped again by evo_kick. */
180 nv50_dmac_destroy(struct nv50_dmac *dmac, struct nvif_object *disp)
182 nvif_object_fini(&dmac->vram);
183 nvif_object_fini(&dmac->sync);
185 nv50_chan_destroy(&dmac->base);
188 struct pci_dev *pdev = nvkm_device(nvif_device(disp))->pdev;
189 pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle);
194 nv50_dmac_create(struct nvif_object *disp, const u32 *oclass, u8 head,
195 void *data, u32 size, u64 syncbuf,
196 struct nv50_dmac *dmac)
198 struct nvif_device *device = nvif_device(disp);
199 struct nv50_disp_core_channel_dma_v0 *args = data;
200 struct nvif_object pushbuf;
203 mutex_init(&dmac->lock);
205 dmac->ptr = pci_alloc_consistent(nvkm_device(device)->pdev,
206 PAGE_SIZE, &dmac->handle);
210 ret = nvif_object_init(nvif_object(device), NULL,
211 args->pushbuf, NV_DMA_FROM_MEMORY,
212 &(struct nv_dma_v0) {
213 .target = NV_DMA_V0_TARGET_PCI_US,
214 .access = NV_DMA_V0_ACCESS_RD,
215 .start = dmac->handle + 0x0000,
216 .limit = dmac->handle + 0x0fff,
217 }, sizeof(struct nv_dma_v0), &pushbuf);
221 ret = nv50_chan_create(disp, oclass, head, data, size, &dmac->base);
222 nvif_object_fini(&pushbuf);
226 ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000000,
228 &(struct nv_dma_v0) {
229 .target = NV_DMA_V0_TARGET_VRAM,
230 .access = NV_DMA_V0_ACCESS_RDWR,
231 .start = syncbuf + 0x0000,
232 .limit = syncbuf + 0x0fff,
233 }, sizeof(struct nv_dma_v0),
238 ret = nvif_object_init(&dmac->base.user, NULL, 0xf0000001,
240 &(struct nv_dma_v0) {
241 .target = NV_DMA_V0_TARGET_VRAM,
242 .access = NV_DMA_V0_ACCESS_RDWR,
244 .limit = device->info.ram_user - 1,
245 }, sizeof(struct nv_dma_v0),
253 /******************************************************************************
255 *****************************************************************************/
258 struct nv50_dmac base;
262 nv50_core_create(struct nvif_object *disp, u64 syncbuf, struct nv50_mast *core)
264 struct nv50_disp_core_channel_dma_v0 args = {
265 .pushbuf = 0xb0007d00,
267 static const u32 oclass[] = {
268 GM107_DISP_CORE_CHANNEL_DMA,
269 GK110_DISP_CORE_CHANNEL_DMA,
270 GK104_DISP_CORE_CHANNEL_DMA,
271 GF110_DISP_CORE_CHANNEL_DMA,
272 GT214_DISP_CORE_CHANNEL_DMA,
273 GT206_DISP_CORE_CHANNEL_DMA,
274 GT200_DISP_CORE_CHANNEL_DMA,
275 G82_DISP_CORE_CHANNEL_DMA,
276 NV50_DISP_CORE_CHANNEL_DMA,
280 return nv50_dmac_create(disp, oclass, 0, &args, sizeof(args), syncbuf,
284 /******************************************************************************
286 *****************************************************************************/
289 struct nv50_dmac base;
295 nv50_base_create(struct nvif_object *disp, int head, u64 syncbuf,
296 struct nv50_sync *base)
298 struct nv50_disp_base_channel_dma_v0 args = {
299 .pushbuf = 0xb0007c00 | head,
302 static const u32 oclass[] = {
303 GK110_DISP_BASE_CHANNEL_DMA,
304 GK104_DISP_BASE_CHANNEL_DMA,
305 GF110_DISP_BASE_CHANNEL_DMA,
306 GT214_DISP_BASE_CHANNEL_DMA,
307 GT200_DISP_BASE_CHANNEL_DMA,
308 G82_DISP_BASE_CHANNEL_DMA,
309 NV50_DISP_BASE_CHANNEL_DMA,
313 return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
314 syncbuf, &base->base);
317 /******************************************************************************
319 *****************************************************************************/
322 struct nv50_dmac base;
326 nv50_ovly_create(struct nvif_object *disp, int head, u64 syncbuf,
327 struct nv50_ovly *ovly)
329 struct nv50_disp_overlay_channel_dma_v0 args = {
330 .pushbuf = 0xb0007e00 | head,
333 static const u32 oclass[] = {
334 GK104_DISP_OVERLAY_CONTROL_DMA,
335 GF110_DISP_OVERLAY_CONTROL_DMA,
336 GT214_DISP_OVERLAY_CHANNEL_DMA,
337 GT200_DISP_OVERLAY_CHANNEL_DMA,
338 G82_DISP_OVERLAY_CHANNEL_DMA,
339 NV50_DISP_OVERLAY_CHANNEL_DMA,
343 return nv50_dmac_create(disp, oclass, head, &args, sizeof(args),
344 syncbuf, &ovly->base);
348 struct nouveau_crtc base;
349 struct nouveau_bo *image;
350 struct nv50_curs curs;
351 struct nv50_sync sync;
352 struct nv50_ovly ovly;
353 struct nv50_oimm oimm;
356 #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c))
357 #define nv50_curs(c) (&nv50_head(c)->curs)
358 #define nv50_sync(c) (&nv50_head(c)->sync)
359 #define nv50_ovly(c) (&nv50_head(c)->ovly)
360 #define nv50_oimm(c) (&nv50_head(c)->oimm)
361 #define nv50_chan(c) (&(c)->base.base)
362 #define nv50_vers(c) nv50_chan(c)->user.oclass
365 struct list_head head;
366 struct nvif_object core;
367 struct nvif_object base[4];
371 struct nvif_object *disp;
372 struct nv50_mast mast;
374 struct list_head fbdma;
376 struct nouveau_bo *sync;
379 static struct nv50_disp *
380 nv50_disp(struct drm_device *dev)
382 return nouveau_display(dev)->priv;
385 #define nv50_mast(d) (&nv50_disp(d)->mast)
387 static struct drm_crtc *
388 nv50_display_crtc_get(struct drm_encoder *encoder)
390 return nouveau_encoder(encoder)->crtc;
393 /******************************************************************************
394 * EVO channel helpers
395 *****************************************************************************/
397 evo_wait(void *evoc, int nr)
399 struct nv50_dmac *dmac = evoc;
400 u32 put = nvif_rd32(&dmac->base.user, 0x0000) / 4;
402 mutex_lock(&dmac->lock);
403 if (put + nr >= (PAGE_SIZE / 4) - 8) {
404 dmac->ptr[put] = 0x20000000;
406 nvif_wr32(&dmac->base.user, 0x0000, 0x00000000);
407 if (!nvkm_wait(&dmac->base.user, 0x0004, ~0, 0x00000000)) {
408 mutex_unlock(&dmac->lock);
409 nv_error(nvkm_object(&dmac->base.user), "channel stalled\n");
416 return dmac->ptr + put;
420 evo_kick(u32 *push, void *evoc)
422 struct nv50_dmac *dmac = evoc;
423 nvif_wr32(&dmac->base.user, 0x0000, (push - dmac->ptr) << 2);
424 mutex_unlock(&dmac->lock);
427 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
428 #define evo_data(p,d) *((p)++) = (d)
431 evo_sync_wait(void *data)
433 if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000)
440 evo_sync(struct drm_device *dev)
442 struct nvif_device *device = &nouveau_drm(dev)->device;
443 struct nv50_disp *disp = nv50_disp(dev);
444 struct nv50_mast *mast = nv50_mast(dev);
445 u32 *push = evo_wait(mast, 8);
447 nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000);
448 evo_mthd(push, 0x0084, 1);
449 evo_data(push, 0x80000000 | EVO_MAST_NTFY);
450 evo_mthd(push, 0x0080, 2);
451 evo_data(push, 0x00000000);
452 evo_data(push, 0x00000000);
453 evo_kick(push, mast);
454 if (nv_wait_cb(nvkm_device(device), evo_sync_wait, disp->sync))
461 /******************************************************************************
462 * Page flipping channel
463 *****************************************************************************/
465 nv50_display_crtc_sema(struct drm_device *dev, int crtc)
467 return nv50_disp(dev)->sync;
470 struct nv50_display_flip {
471 struct nv50_disp *disp;
472 struct nv50_sync *chan;
476 nv50_display_flip_wait(void *data)
478 struct nv50_display_flip *flip = data;
479 if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) ==
487 nv50_display_flip_stop(struct drm_crtc *crtc)
489 struct nvif_device *device = &nouveau_drm(crtc->dev)->device;
490 struct nv50_display_flip flip = {
491 .disp = nv50_disp(crtc->dev),
492 .chan = nv50_sync(crtc),
496 push = evo_wait(flip.chan, 8);
498 evo_mthd(push, 0x0084, 1);
499 evo_data(push, 0x00000000);
500 evo_mthd(push, 0x0094, 1);
501 evo_data(push, 0x00000000);
502 evo_mthd(push, 0x00c0, 1);
503 evo_data(push, 0x00000000);
504 evo_mthd(push, 0x0080, 1);
505 evo_data(push, 0x00000000);
506 evo_kick(push, flip.chan);
509 nv_wait_cb(nvkm_device(device), nv50_display_flip_wait, &flip);
513 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
514 struct nouveau_channel *chan, u32 swap_interval)
516 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
517 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
518 struct nv50_head *head = nv50_head(crtc);
519 struct nv50_sync *sync = nv50_sync(crtc);
524 if (swap_interval == 0)
525 swap_interval |= 0x100;
529 push = evo_wait(sync, 128);
530 if (unlikely(push == NULL))
533 if (chan && chan->object->oclass < G82_CHANNEL_GPFIFO) {
534 ret = RING_SPACE(chan, 8);
538 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2);
539 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
540 OUT_RING (chan, sync->addr ^ 0x10);
541 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1);
542 OUT_RING (chan, sync->data + 1);
543 BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2);
544 OUT_RING (chan, sync->addr);
545 OUT_RING (chan, sync->data);
547 if (chan && chan->object->oclass < FERMI_CHANNEL_GPFIFO) {
548 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
549 ret = RING_SPACE(chan, 12);
553 BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1);
554 OUT_RING (chan, chan->vram.handle);
555 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
556 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
557 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
558 OUT_RING (chan, sync->data + 1);
559 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG);
560 BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
561 OUT_RING (chan, upper_32_bits(addr));
562 OUT_RING (chan, lower_32_bits(addr));
563 OUT_RING (chan, sync->data);
564 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
567 u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr;
568 ret = RING_SPACE(chan, 10);
572 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
573 OUT_RING (chan, upper_32_bits(addr ^ 0x10));
574 OUT_RING (chan, lower_32_bits(addr ^ 0x10));
575 OUT_RING (chan, sync->data + 1);
576 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG |
577 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
578 BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4);
579 OUT_RING (chan, upper_32_bits(addr));
580 OUT_RING (chan, lower_32_bits(addr));
581 OUT_RING (chan, sync->data);
582 OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL |
583 NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD);
593 evo_mthd(push, 0x0100, 1);
594 evo_data(push, 0xfffe0000);
595 evo_mthd(push, 0x0084, 1);
596 evo_data(push, swap_interval);
597 if (!(swap_interval & 0x00000100)) {
598 evo_mthd(push, 0x00e0, 1);
599 evo_data(push, 0x40000000);
601 evo_mthd(push, 0x0088, 4);
602 evo_data(push, sync->addr);
603 evo_data(push, sync->data++);
604 evo_data(push, sync->data);
605 evo_data(push, sync->base.sync.handle);
606 evo_mthd(push, 0x00a0, 2);
607 evo_data(push, 0x00000000);
608 evo_data(push, 0x00000000);
609 evo_mthd(push, 0x00c0, 1);
610 evo_data(push, nv_fb->r_handle);
611 evo_mthd(push, 0x0110, 2);
612 evo_data(push, 0x00000000);
613 evo_data(push, 0x00000000);
614 if (nv50_vers(sync) < GF110_DISP_BASE_CHANNEL_DMA) {
615 evo_mthd(push, 0x0800, 5);
616 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
618 evo_data(push, (fb->height << 16) | fb->width);
619 evo_data(push, nv_fb->r_pitch);
620 evo_data(push, nv_fb->r_format);
622 evo_mthd(push, 0x0400, 5);
623 evo_data(push, nv_fb->nvbo->bo.offset >> 8);
625 evo_data(push, (fb->height << 16) | fb->width);
626 evo_data(push, nv_fb->r_pitch);
627 evo_data(push, nv_fb->r_format);
629 evo_mthd(push, 0x0080, 1);
630 evo_data(push, 0x00000000);
631 evo_kick(push, sync);
633 nouveau_bo_ref(nv_fb->nvbo, &head->image);
637 /******************************************************************************
639 *****************************************************************************/
641 nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update)
643 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
644 struct nouveau_connector *nv_connector;
645 struct drm_connector *connector;
646 u32 *push, mode = 0x00;
648 nv_connector = nouveau_crtc_connector_get(nv_crtc);
649 connector = &nv_connector->base;
650 if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) {
651 if (nv_crtc->base.primary->fb->depth > connector->display_info.bpc * 3)
652 mode = DITHERING_MODE_DYNAMIC2X2;
654 mode = nv_connector->dithering_mode;
657 if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) {
658 if (connector->display_info.bpc >= 8)
659 mode |= DITHERING_DEPTH_8BPC;
661 mode |= nv_connector->dithering_depth;
664 push = evo_wait(mast, 4);
666 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
667 evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1);
668 evo_data(push, mode);
670 if (nv50_vers(mast) < GK104_DISP_CORE_CHANNEL_DMA) {
671 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1);
672 evo_data(push, mode);
674 evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1);
675 evo_data(push, mode);
679 evo_mthd(push, 0x0080, 1);
680 evo_data(push, 0x00000000);
682 evo_kick(push, mast);
689 nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update)
691 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
692 struct drm_display_mode *omode, *umode = &nv_crtc->base.mode;
693 struct drm_crtc *crtc = &nv_crtc->base;
694 struct nouveau_connector *nv_connector;
695 int mode = DRM_MODE_SCALE_NONE;
698 /* start off at the resolution we programmed the crtc for, this
699 * effectively handles NONE/FULL scaling
701 nv_connector = nouveau_crtc_connector_get(nv_crtc);
702 if (nv_connector && nv_connector->native_mode)
703 mode = nv_connector->scaling_mode;
705 if (mode != DRM_MODE_SCALE_NONE)
706 omode = nv_connector->native_mode;
710 oX = omode->hdisplay;
711 oY = omode->vdisplay;
712 if (omode->flags & DRM_MODE_FLAG_DBLSCAN)
715 /* add overscan compensation if necessary, will keep the aspect
716 * ratio the same as the backend mode unless overridden by the
717 * user setting both hborder and vborder properties.
719 if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON ||
720 (nv_connector->underscan == UNDERSCAN_AUTO &&
721 nv_connector->edid &&
722 drm_detect_hdmi_monitor(nv_connector->edid)))) {
723 u32 bX = nv_connector->underscan_hborder;
724 u32 bY = nv_connector->underscan_vborder;
725 u32 aspect = (oY << 19) / oX;
729 if (bY) oY -= (bY * 2);
730 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
732 oX -= (oX >> 4) + 32;
733 if (bY) oY -= (bY * 2);
734 else oY = ((oX * aspect) + (aspect / 2)) >> 19;
738 /* handle CENTER/ASPECT scaling, taking into account the areas
739 * removed already for overscan compensation
742 case DRM_MODE_SCALE_CENTER:
743 oX = min((u32)umode->hdisplay, oX);
744 oY = min((u32)umode->vdisplay, oY);
746 case DRM_MODE_SCALE_ASPECT:
748 u32 aspect = (umode->hdisplay << 19) / umode->vdisplay;
749 oX = ((oY * aspect) + (aspect / 2)) >> 19;
751 u32 aspect = (umode->vdisplay << 19) / umode->hdisplay;
752 oY = ((oX * aspect) + (aspect / 2)) >> 19;
759 push = evo_wait(mast, 8);
761 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
762 /*XXX: SCALE_CTRL_ACTIVE??? */
763 evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2);
764 evo_data(push, (oY << 16) | oX);
765 evo_data(push, (oY << 16) | oX);
766 evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1);
767 evo_data(push, 0x00000000);
768 evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1);
769 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
771 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
772 evo_data(push, (oY << 16) | oX);
773 evo_data(push, (oY << 16) | oX);
774 evo_data(push, (oY << 16) | oX);
775 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
776 evo_data(push, 0x00000000);
777 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
778 evo_data(push, umode->vdisplay << 16 | umode->hdisplay);
781 evo_kick(push, mast);
784 nv50_display_flip_stop(crtc);
785 nv50_display_flip_next(crtc, crtc->primary->fb,
794 nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update)
796 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
800 adj = (nv_crtc->color_vibrance > 0) ? 50 : 0;
801 vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff;
802 hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff;
804 push = evo_wait(mast, 16);
806 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
807 evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1);
808 evo_data(push, (hue << 20) | (vib << 8));
810 evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1);
811 evo_data(push, (hue << 20) | (vib << 8));
815 evo_mthd(push, 0x0080, 1);
816 evo_data(push, 0x00000000);
818 evo_kick(push, mast);
825 nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
826 int x, int y, bool update)
828 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
829 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
832 push = evo_wait(mast, 16);
834 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
835 evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1);
836 evo_data(push, nvfb->nvbo->bo.offset >> 8);
837 evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3);
838 evo_data(push, (fb->height << 16) | fb->width);
839 evo_data(push, nvfb->r_pitch);
840 evo_data(push, nvfb->r_format);
841 evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1);
842 evo_data(push, (y << 16) | x);
843 if (nv50_vers(mast) > NV50_DISP_CORE_CHANNEL_DMA) {
844 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
845 evo_data(push, nvfb->r_handle);
848 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
849 evo_data(push, nvfb->nvbo->bo.offset >> 8);
850 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
851 evo_data(push, (fb->height << 16) | fb->width);
852 evo_data(push, nvfb->r_pitch);
853 evo_data(push, nvfb->r_format);
854 evo_data(push, nvfb->r_handle);
855 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
856 evo_data(push, (y << 16) | x);
860 evo_mthd(push, 0x0080, 1);
861 evo_data(push, 0x00000000);
863 evo_kick(push, mast);
866 nv_crtc->fb.handle = nvfb->r_handle;
871 nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc)
873 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
874 u32 *push = evo_wait(mast, 16);
876 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
877 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
878 evo_data(push, 0x85000000);
879 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
881 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
882 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2);
883 evo_data(push, 0x85000000);
884 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
885 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
886 evo_data(push, mast->base.vram.handle);
888 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
889 evo_data(push, 0x85000000);
890 evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
891 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
892 evo_data(push, mast->base.vram.handle);
894 evo_kick(push, mast);
899 nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc)
901 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
902 u32 *push = evo_wait(mast, 16);
904 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
905 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
906 evo_data(push, 0x05000000);
908 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
909 evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1);
910 evo_data(push, 0x05000000);
911 evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1);
912 evo_data(push, 0x00000000);
914 evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
915 evo_data(push, 0x05000000);
916 evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
917 evo_data(push, 0x00000000);
919 evo_kick(push, mast);
924 nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update)
926 struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev);
929 nv50_crtc_cursor_show(nv_crtc);
931 nv50_crtc_cursor_hide(nv_crtc);
934 u32 *push = evo_wait(mast, 2);
936 evo_mthd(push, 0x0080, 1);
937 evo_data(push, 0x00000000);
938 evo_kick(push, mast);
944 nv50_crtc_dpms(struct drm_crtc *crtc, int mode)
949 nv50_crtc_prepare(struct drm_crtc *crtc)
951 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
952 struct nv50_mast *mast = nv50_mast(crtc->dev);
955 nv50_display_flip_stop(crtc);
957 push = evo_wait(mast, 6);
959 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
960 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
961 evo_data(push, 0x00000000);
962 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
963 evo_data(push, 0x40000000);
965 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
966 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
967 evo_data(push, 0x00000000);
968 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1);
969 evo_data(push, 0x40000000);
970 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
971 evo_data(push, 0x00000000);
973 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
974 evo_data(push, 0x00000000);
975 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
976 evo_data(push, 0x03000000);
977 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
978 evo_data(push, 0x00000000);
981 evo_kick(push, mast);
984 nv50_crtc_cursor_show_hide(nv_crtc, false, false);
988 nv50_crtc_commit(struct drm_crtc *crtc)
990 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
991 struct nv50_mast *mast = nv50_mast(crtc->dev);
994 push = evo_wait(mast, 32);
996 if (nv50_vers(mast) < G82_DISP_CORE_CHANNEL_DMA) {
997 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
998 evo_data(push, nv_crtc->fb.handle);
999 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1000 evo_data(push, 0xc0000000);
1001 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1003 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1004 evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1);
1005 evo_data(push, nv_crtc->fb.handle);
1006 evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2);
1007 evo_data(push, 0xc0000000);
1008 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1009 evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1);
1010 evo_data(push, mast->base.vram.handle);
1012 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
1013 evo_data(push, nv_crtc->fb.handle);
1014 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
1015 evo_data(push, 0x83000000);
1016 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
1017 evo_data(push, 0x00000000);
1018 evo_data(push, 0x00000000);
1019 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
1020 evo_data(push, mast->base.vram.handle);
1021 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
1022 evo_data(push, 0xffffff00);
1025 evo_kick(push, mast);
1028 nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true);
1029 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1033 nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode,
1034 struct drm_display_mode *adjusted_mode)
1036 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
1041 nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
1043 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb);
1044 struct nv50_head *head = nv50_head(crtc);
1047 ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
1050 nouveau_bo_unpin(head->image);
1051 nouveau_bo_ref(nvfb->nvbo, &head->image);
1058 nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
1059 struct drm_display_mode *mode, int x, int y,
1060 struct drm_framebuffer *old_fb)
1062 struct nv50_mast *mast = nv50_mast(crtc->dev);
1063 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1064 struct nouveau_connector *nv_connector;
1065 u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1;
1066 u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1;
1067 u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks;
1068 u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks;
1069 u32 vblan2e = 0, vblan2s = 1;
1073 hactive = mode->htotal;
1074 hsynce = mode->hsync_end - mode->hsync_start - 1;
1075 hbackp = mode->htotal - mode->hsync_end;
1076 hblanke = hsynce + hbackp;
1077 hfrontp = mode->hsync_start - mode->hdisplay;
1078 hblanks = mode->htotal - hfrontp - 1;
1080 vactive = mode->vtotal * vscan / ilace;
1081 vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1;
1082 vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace;
1083 vblanke = vsynce + vbackp;
1084 vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace;
1085 vblanks = vactive - vfrontp - 1;
1086 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1087 vblan2e = vactive + vsynce + vbackp;
1088 vblan2s = vblan2e + (mode->vdisplay * vscan / ilace);
1089 vactive = (vactive * 2) + 1;
1092 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1096 push = evo_wait(mast, 64);
1098 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1099 evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2);
1100 evo_data(push, 0x00800000 | mode->clock);
1101 evo_data(push, (ilace == 2) ? 2 : 0);
1102 evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6);
1103 evo_data(push, 0x00000000);
1104 evo_data(push, (vactive << 16) | hactive);
1105 evo_data(push, ( vsynce << 16) | hsynce);
1106 evo_data(push, (vblanke << 16) | hblanke);
1107 evo_data(push, (vblanks << 16) | hblanks);
1108 evo_data(push, (vblan2e << 16) | vblan2s);
1109 evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1);
1110 evo_data(push, 0x00000000);
1111 evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2);
1112 evo_data(push, 0x00000311);
1113 evo_data(push, 0x00000100);
1115 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6);
1116 evo_data(push, 0x00000000);
1117 evo_data(push, (vactive << 16) | hactive);
1118 evo_data(push, ( vsynce << 16) | hsynce);
1119 evo_data(push, (vblanke << 16) | hblanke);
1120 evo_data(push, (vblanks << 16) | hblanks);
1121 evo_data(push, (vblan2e << 16) | vblan2s);
1122 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
1123 evo_data(push, 0x00000000); /* ??? */
1124 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
1125 evo_data(push, mode->clock * 1000);
1126 evo_data(push, 0x00200000); /* ??? */
1127 evo_data(push, mode->clock * 1000);
1128 evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2);
1129 evo_data(push, 0x00000311);
1130 evo_data(push, 0x00000100);
1133 evo_kick(push, mast);
1136 nv_connector = nouveau_crtc_connector_get(nv_crtc);
1137 nv50_crtc_set_dither(nv_crtc, false);
1138 nv50_crtc_set_scale(nv_crtc, false);
1139 nv50_crtc_set_color_vibrance(nv_crtc, false);
1140 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, false);
1145 nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
1146 struct drm_framebuffer *old_fb)
1148 struct nouveau_drm *drm = nouveau_drm(crtc->dev);
1149 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1152 if (!crtc->primary->fb) {
1153 NV_DEBUG(drm, "No FB bound\n");
1157 ret = nv50_crtc_swap_fbs(crtc, old_fb);
1161 nv50_display_flip_stop(crtc);
1162 nv50_crtc_set_image(nv_crtc, crtc->primary->fb, x, y, true);
1163 nv50_display_flip_next(crtc, crtc->primary->fb, NULL, 1);
1168 nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
1169 struct drm_framebuffer *fb, int x, int y,
1170 enum mode_set_atomic state)
1172 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1173 nv50_display_flip_stop(crtc);
1174 nv50_crtc_set_image(nv_crtc, fb, x, y, true);
1179 nv50_crtc_lut_load(struct drm_crtc *crtc)
1181 struct nv50_disp *disp = nv50_disp(crtc->dev);
1182 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1183 void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
1186 for (i = 0; i < 256; i++) {
1187 u16 r = nv_crtc->lut.r[i] >> 2;
1188 u16 g = nv_crtc->lut.g[i] >> 2;
1189 u16 b = nv_crtc->lut.b[i] >> 2;
1191 if (disp->disp->oclass < GF110_DISP) {
1192 writew(r + 0x0000, lut + (i * 0x08) + 0);
1193 writew(g + 0x0000, lut + (i * 0x08) + 2);
1194 writew(b + 0x0000, lut + (i * 0x08) + 4);
1196 writew(r + 0x6000, lut + (i * 0x20) + 0);
1197 writew(g + 0x6000, lut + (i * 0x20) + 2);
1198 writew(b + 0x6000, lut + (i * 0x20) + 4);
1204 nv50_crtc_disable(struct drm_crtc *crtc)
1206 struct nv50_head *head = nv50_head(crtc);
1207 evo_sync(crtc->dev);
1209 nouveau_bo_unpin(head->image);
1210 nouveau_bo_ref(NULL, &head->image);
1214 nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
1215 uint32_t handle, uint32_t width, uint32_t height)
1217 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1218 struct drm_device *dev = crtc->dev;
1219 struct drm_gem_object *gem;
1220 struct nouveau_bo *nvbo;
1221 bool visible = (handle != 0);
1225 if (width != 64 || height != 64)
1228 gem = drm_gem_object_lookup(dev, file_priv, handle);
1231 nvbo = nouveau_gem_object(gem);
1233 ret = nouveau_bo_map(nvbo);
1235 for (i = 0; i < 64 * 64; i++) {
1236 u32 v = nouveau_bo_rd32(nvbo, i);
1237 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
1239 nouveau_bo_unmap(nvbo);
1242 drm_gem_object_unreference_unlocked(gem);
1245 if (visible != nv_crtc->cursor.visible) {
1246 nv50_crtc_cursor_show_hide(nv_crtc, visible, true);
1247 nv_crtc->cursor.visible = visible;
1254 nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1256 struct nv50_curs *curs = nv50_curs(crtc);
1257 struct nv50_chan *chan = nv50_chan(curs);
1258 nvif_wr32(&chan->user, 0x0084, (y << 16) | (x & 0xffff));
1259 nvif_wr32(&chan->user, 0x0080, 0x00000000);
1264 nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
1265 uint32_t start, uint32_t size)
1267 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1268 u32 end = min_t(u32, start + size, 256);
1271 for (i = start; i < end; i++) {
1272 nv_crtc->lut.r[i] = r[i];
1273 nv_crtc->lut.g[i] = g[i];
1274 nv_crtc->lut.b[i] = b[i];
1277 nv50_crtc_lut_load(crtc);
1281 nv50_crtc_destroy(struct drm_crtc *crtc)
1283 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
1284 struct nv50_disp *disp = nv50_disp(crtc->dev);
1285 struct nv50_head *head = nv50_head(crtc);
1286 struct nv50_fbdma *fbdma;
1288 list_for_each_entry(fbdma, &disp->fbdma, head) {
1289 nvif_object_fini(&fbdma->base[nv_crtc->index]);
1292 nv50_dmac_destroy(&head->ovly.base, disp->disp);
1293 nv50_pioc_destroy(&head->oimm.base);
1294 nv50_dmac_destroy(&head->sync.base, disp->disp);
1295 nv50_pioc_destroy(&head->curs.base);
1297 /*XXX: this shouldn't be necessary, but the core doesn't call
1298 * disconnect() during the cleanup paths
1301 nouveau_bo_unpin(head->image);
1302 nouveau_bo_ref(NULL, &head->image);
1304 nouveau_bo_unmap(nv_crtc->cursor.nvbo);
1305 if (nv_crtc->cursor.nvbo)
1306 nouveau_bo_unpin(nv_crtc->cursor.nvbo);
1307 nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
1309 nouveau_bo_unmap(nv_crtc->lut.nvbo);
1310 if (nv_crtc->lut.nvbo)
1311 nouveau_bo_unpin(nv_crtc->lut.nvbo);
1312 nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
1314 drm_crtc_cleanup(crtc);
1318 static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = {
1319 .dpms = nv50_crtc_dpms,
1320 .prepare = nv50_crtc_prepare,
1321 .commit = nv50_crtc_commit,
1322 .mode_fixup = nv50_crtc_mode_fixup,
1323 .mode_set = nv50_crtc_mode_set,
1324 .mode_set_base = nv50_crtc_mode_set_base,
1325 .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic,
1326 .load_lut = nv50_crtc_lut_load,
1327 .disable = nv50_crtc_disable,
1330 static const struct drm_crtc_funcs nv50_crtc_func = {
1331 .cursor_set = nv50_crtc_cursor_set,
1332 .cursor_move = nv50_crtc_cursor_move,
1333 .gamma_set = nv50_crtc_gamma_set,
1334 .set_config = nouveau_crtc_set_config,
1335 .destroy = nv50_crtc_destroy,
1336 .page_flip = nouveau_crtc_page_flip,
1340 nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y)
1345 nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset)
1350 nv50_crtc_create(struct drm_device *dev, int index)
1352 struct nv50_disp *disp = nv50_disp(dev);
1353 struct nv50_head *head;
1354 struct drm_crtc *crtc;
1357 head = kzalloc(sizeof(*head), GFP_KERNEL);
1361 head->base.index = index;
1362 head->base.set_dither = nv50_crtc_set_dither;
1363 head->base.set_scale = nv50_crtc_set_scale;
1364 head->base.set_color_vibrance = nv50_crtc_set_color_vibrance;
1365 head->base.color_vibrance = 50;
1366 head->base.vibrant_hue = 0;
1367 head->base.cursor.set_offset = nv50_cursor_set_offset;
1368 head->base.cursor.set_pos = nv50_cursor_set_pos;
1369 for (i = 0; i < 256; i++) {
1370 head->base.lut.r[i] = i << 8;
1371 head->base.lut.g[i] = i << 8;
1372 head->base.lut.b[i] = i << 8;
1375 crtc = &head->base.base;
1376 drm_crtc_init(dev, crtc, &nv50_crtc_func);
1377 drm_crtc_helper_add(crtc, &nv50_crtc_hfunc);
1378 drm_mode_crtc_set_gamma_size(crtc, 256);
1380 ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
1381 0, 0x0000, NULL, &head->base.lut.nvbo);
1383 ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM);
1385 ret = nouveau_bo_map(head->base.lut.nvbo);
1387 nouveau_bo_unpin(head->base.lut.nvbo);
1390 nouveau_bo_ref(NULL, &head->base.lut.nvbo);
1396 nv50_crtc_lut_load(crtc);
1398 /* allocate cursor resources */
1399 ret = nv50_curs_create(disp->disp, index, &head->curs);
1403 ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
1404 0, 0x0000, NULL, &head->base.cursor.nvbo);
1406 ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM);
1408 ret = nouveau_bo_map(head->base.cursor.nvbo);
1410 nouveau_bo_unpin(head->base.lut.nvbo);
1413 nouveau_bo_ref(NULL, &head->base.cursor.nvbo);
1419 /* allocate page flip / sync resources */
1420 ret = nv50_base_create(disp->disp, index, disp->sync->bo.offset,
1425 head->sync.addr = EVO_FLIP_SEM0(index);
1426 head->sync.data = 0x00000000;
1428 /* allocate overlay resources */
1429 ret = nv50_oimm_create(disp->disp, index, &head->oimm);
1433 ret = nv50_ovly_create(disp->disp, index, disp->sync->bo.offset,
1440 nv50_crtc_destroy(crtc);
1444 /******************************************************************************
1446 *****************************************************************************/
1448 nv50_dac_dpms(struct drm_encoder *encoder, int mode)
1450 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1451 struct nv50_disp *disp = nv50_disp(encoder->dev);
1453 struct nv50_disp_mthd_v1 base;
1454 struct nv50_disp_dac_pwr_v0 pwr;
1457 .base.method = NV50_DISP_MTHD_V1_DAC_PWR,
1458 .base.hasht = nv_encoder->dcb->hasht,
1459 .base.hashm = nv_encoder->dcb->hashm,
1462 .pwr.vsync = (mode != DRM_MODE_DPMS_SUSPEND &&
1463 mode != DRM_MODE_DPMS_OFF),
1464 .pwr.hsync = (mode != DRM_MODE_DPMS_STANDBY &&
1465 mode != DRM_MODE_DPMS_OFF),
1468 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1472 nv50_dac_mode_fixup(struct drm_encoder *encoder,
1473 const struct drm_display_mode *mode,
1474 struct drm_display_mode *adjusted_mode)
1476 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1477 struct nouveau_connector *nv_connector;
1479 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1480 if (nv_connector && nv_connector->native_mode) {
1481 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1482 int id = adjusted_mode->base.id;
1483 *adjusted_mode = *nv_connector->native_mode;
1484 adjusted_mode->base.id = id;
1492 nv50_dac_commit(struct drm_encoder *encoder)
1497 nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
1498 struct drm_display_mode *adjusted_mode)
1500 struct nv50_mast *mast = nv50_mast(encoder->dev);
1501 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1502 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1505 nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1507 push = evo_wait(mast, 8);
1509 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1510 u32 syncs = 0x00000000;
1512 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1513 syncs |= 0x00000001;
1514 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1515 syncs |= 0x00000002;
1517 evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2);
1518 evo_data(push, 1 << nv_crtc->index);
1519 evo_data(push, syncs);
1521 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1522 u32 syncs = 0x00000001;
1524 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1525 syncs |= 0x00000008;
1526 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1527 syncs |= 0x00000010;
1529 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1530 magic |= 0x00000001;
1532 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1533 evo_data(push, syncs);
1534 evo_data(push, magic);
1535 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1);
1536 evo_data(push, 1 << nv_crtc->index);
1539 evo_kick(push, mast);
1542 nv_encoder->crtc = encoder->crtc;
1546 nv50_dac_disconnect(struct drm_encoder *encoder)
1548 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1549 struct nv50_mast *mast = nv50_mast(encoder->dev);
1550 const int or = nv_encoder->or;
1553 if (nv_encoder->crtc) {
1554 nv50_crtc_prepare(nv_encoder->crtc);
1556 push = evo_wait(mast, 4);
1558 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1559 evo_mthd(push, 0x0400 + (or * 0x080), 1);
1560 evo_data(push, 0x00000000);
1562 evo_mthd(push, 0x0180 + (or * 0x020), 1);
1563 evo_data(push, 0x00000000);
1565 evo_kick(push, mast);
1569 nv_encoder->crtc = NULL;
1572 static enum drm_connector_status
1573 nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1575 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1576 struct nv50_disp *disp = nv50_disp(encoder->dev);
1578 struct nv50_disp_mthd_v1 base;
1579 struct nv50_disp_dac_load_v0 load;
1582 .base.method = NV50_DISP_MTHD_V1_DAC_LOAD,
1583 .base.hasht = nv_encoder->dcb->hasht,
1584 .base.hashm = nv_encoder->dcb->hashm,
1588 args.load.data = nouveau_drm(encoder->dev)->vbios.dactestval;
1589 if (args.load.data == 0)
1590 args.load.data = 340;
1592 ret = nvif_mthd(disp->disp, 0, &args, sizeof(args));
1593 if (ret || !args.load.load)
1594 return connector_status_disconnected;
1596 return connector_status_connected;
1600 nv50_dac_destroy(struct drm_encoder *encoder)
1602 drm_encoder_cleanup(encoder);
1606 static const struct drm_encoder_helper_funcs nv50_dac_hfunc = {
1607 .dpms = nv50_dac_dpms,
1608 .mode_fixup = nv50_dac_mode_fixup,
1609 .prepare = nv50_dac_disconnect,
1610 .commit = nv50_dac_commit,
1611 .mode_set = nv50_dac_mode_set,
1612 .disable = nv50_dac_disconnect,
1613 .get_crtc = nv50_display_crtc_get,
1614 .detect = nv50_dac_detect
1617 static const struct drm_encoder_funcs nv50_dac_func = {
1618 .destroy = nv50_dac_destroy,
1622 nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe)
1624 struct nouveau_drm *drm = nouveau_drm(connector->dev);
1625 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
1626 struct nouveau_encoder *nv_encoder;
1627 struct drm_encoder *encoder;
1628 int type = DRM_MODE_ENCODER_DAC;
1630 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
1633 nv_encoder->dcb = dcbe;
1634 nv_encoder->or = ffs(dcbe->or) - 1;
1635 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
1637 encoder = to_drm_encoder(nv_encoder);
1638 encoder->possible_crtcs = dcbe->heads;
1639 encoder->possible_clones = 0;
1640 drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type);
1641 drm_encoder_helper_add(encoder, &nv50_dac_hfunc);
1643 drm_mode_connector_attach_encoder(connector, encoder);
1647 /******************************************************************************
1649 *****************************************************************************/
1651 nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1653 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1654 struct nouveau_connector *nv_connector;
1655 struct nv50_disp *disp = nv50_disp(encoder->dev);
1657 struct nv50_disp_mthd_v1 base;
1658 struct nv50_disp_sor_hda_eld_v0 eld;
1659 u8 data[sizeof(nv_connector->base.eld)];
1662 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1663 .base.hasht = nv_encoder->dcb->hasht,
1664 .base.hashm = nv_encoder->dcb->hashm,
1667 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1668 if (!drm_detect_monitor_audio(nv_connector->edid))
1671 drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
1672 memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
1674 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1678 nv50_audio_disconnect(struct drm_encoder *encoder)
1680 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1681 struct nv50_disp *disp = nv50_disp(encoder->dev);
1683 struct nv50_disp_mthd_v1 base;
1684 struct nv50_disp_sor_hda_eld_v0 eld;
1687 .base.method = NV50_DISP_MTHD_V1_SOR_HDA_ELD,
1688 .base.hasht = nv_encoder->dcb->hasht,
1689 .base.hashm = nv_encoder->dcb->hashm,
1692 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1695 /******************************************************************************
1697 *****************************************************************************/
1699 nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
1701 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1702 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1703 struct nv50_disp *disp = nv50_disp(encoder->dev);
1705 struct nv50_disp_mthd_v1 base;
1706 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1709 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1710 .base.hasht = nv_encoder->dcb->hasht,
1711 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1712 (0x0100 << nv_crtc->index),
1714 .pwr.rekey = 56, /* binary driver, and tegra, constant */
1716 struct nouveau_connector *nv_connector;
1719 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1720 if (!drm_detect_hdmi_monitor(nv_connector->edid))
1723 max_ac_packet = mode->htotal - mode->hdisplay;
1724 max_ac_packet -= args.pwr.rekey;
1725 max_ac_packet -= 18; /* constant from tegra */
1726 args.pwr.max_ac_packet = max_ac_packet / 32;
1728 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1729 nv50_audio_mode_set(encoder, mode);
1733 nv50_hdmi_disconnect(struct drm_encoder *encoder, struct nouveau_crtc *nv_crtc)
1735 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1736 struct nv50_disp *disp = nv50_disp(encoder->dev);
1738 struct nv50_disp_mthd_v1 base;
1739 struct nv50_disp_sor_hdmi_pwr_v0 pwr;
1742 .base.method = NV50_DISP_MTHD_V1_SOR_HDMI_PWR,
1743 .base.hasht = nv_encoder->dcb->hasht,
1744 .base.hashm = (0xf0ff & nv_encoder->dcb->hashm) |
1745 (0x0100 << nv_crtc->index),
1748 nv50_audio_disconnect(encoder);
1750 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1753 /******************************************************************************
1755 *****************************************************************************/
1757 nv50_sor_dpms(struct drm_encoder *encoder, int mode)
1759 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1760 struct nv50_disp *disp = nv50_disp(encoder->dev);
1762 struct nv50_disp_mthd_v1 base;
1763 struct nv50_disp_sor_pwr_v0 pwr;
1766 .base.method = NV50_DISP_MTHD_V1_SOR_PWR,
1767 .base.hasht = nv_encoder->dcb->hasht,
1768 .base.hashm = nv_encoder->dcb->hashm,
1769 .pwr.state = mode == DRM_MODE_DPMS_ON,
1772 struct nv50_disp_mthd_v1 base;
1773 struct nv50_disp_sor_dp_pwr_v0 pwr;
1776 .base.method = NV50_DISP_MTHD_V1_SOR_DP_PWR,
1777 .base.hasht = nv_encoder->dcb->hasht,
1778 .base.hashm = nv_encoder->dcb->hashm,
1779 .pwr.state = mode == DRM_MODE_DPMS_ON,
1781 struct drm_device *dev = encoder->dev;
1782 struct drm_encoder *partner;
1784 nv_encoder->last_dpms = mode;
1786 list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
1787 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
1789 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
1792 if (nv_partner != nv_encoder &&
1793 nv_partner->dcb->or == nv_encoder->dcb->or) {
1794 if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
1800 if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
1802 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1803 nvif_mthd(disp->disp, 0, &link, sizeof(link));
1805 nvif_mthd(disp->disp, 0, &args, sizeof(args));
1810 nv50_sor_mode_fixup(struct drm_encoder *encoder,
1811 const struct drm_display_mode *mode,
1812 struct drm_display_mode *adjusted_mode)
1814 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1815 struct nouveau_connector *nv_connector;
1817 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1818 if (nv_connector && nv_connector->native_mode) {
1819 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
1820 int id = adjusted_mode->base.id;
1821 *adjusted_mode = *nv_connector->native_mode;
1822 adjusted_mode->base.id = id;
1830 nv50_sor_ctrl(struct nouveau_encoder *nv_encoder, u32 mask, u32 data)
1832 struct nv50_mast *mast = nv50_mast(nv_encoder->base.base.dev);
1833 u32 temp = (nv_encoder->ctrl & ~mask) | (data & mask), *push;
1834 if (temp != nv_encoder->ctrl && (push = evo_wait(mast, 2))) {
1835 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
1836 evo_mthd(push, 0x0600 + (nv_encoder->or * 0x40), 1);
1837 evo_data(push, (nv_encoder->ctrl = temp));
1839 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
1840 evo_data(push, (nv_encoder->ctrl = temp));
1842 evo_kick(push, mast);
1847 nv50_sor_disconnect(struct drm_encoder *encoder)
1849 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1850 struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
1852 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
1853 nv_encoder->crtc = NULL;
1856 nv50_crtc_prepare(&nv_crtc->base);
1857 nv50_sor_ctrl(nv_encoder, 1 << nv_crtc->index, 0);
1858 nv50_hdmi_disconnect(&nv_encoder->base.base, nv_crtc);
1863 nv50_sor_commit(struct drm_encoder *encoder)
1868 nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode,
1869 struct drm_display_mode *mode)
1871 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
1872 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
1874 struct nv50_disp_mthd_v1 base;
1875 struct nv50_disp_sor_lvds_script_v0 lvds;
1878 .base.method = NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT,
1879 .base.hasht = nv_encoder->dcb->hasht,
1880 .base.hashm = nv_encoder->dcb->hashm,
1882 struct nv50_disp *disp = nv50_disp(encoder->dev);
1883 struct nv50_mast *mast = nv50_mast(encoder->dev);
1884 struct drm_device *dev = encoder->dev;
1885 struct nouveau_drm *drm = nouveau_drm(dev);
1886 struct nouveau_connector *nv_connector;
1887 struct nvbios *bios = &drm->vbios;
1889 u8 owner = 1 << nv_crtc->index;
1893 nv_connector = nouveau_encoder_connector_get(nv_encoder);
1894 nv_encoder->crtc = encoder->crtc;
1896 switch (nv_encoder->dcb->type) {
1897 case DCB_OUTPUT_TMDS:
1898 if (nv_encoder->dcb->sorconf.link & 1) {
1899 if (mode->clock < 165000)
1907 nv50_hdmi_mode_set(&nv_encoder->base.base, mode);
1909 case DCB_OUTPUT_LVDS:
1912 if (bios->fp_no_ddc) {
1913 if (bios->fp.dual_link)
1914 lvds.lvds.script |= 0x0100;
1915 if (bios->fp.if_is_24bit)
1916 lvds.lvds.script |= 0x0200;
1918 if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) {
1919 if (((u8 *)nv_connector->edid)[121] == 2)
1920 lvds.lvds.script |= 0x0100;
1922 if (mode->clock >= bios->fp.duallink_transition_clk) {
1923 lvds.lvds.script |= 0x0100;
1926 if (lvds.lvds.script & 0x0100) {
1927 if (bios->fp.strapless_is_24bit & 2)
1928 lvds.lvds.script |= 0x0200;
1930 if (bios->fp.strapless_is_24bit & 1)
1931 lvds.lvds.script |= 0x0200;
1934 if (nv_connector->base.display_info.bpc == 8)
1935 lvds.lvds.script |= 0x0200;
1938 nvif_mthd(disp->disp, 0, &lvds, sizeof(lvds));
1941 if (nv_connector->base.display_info.bpc == 6) {
1942 nv_encoder->dp.datarate = mode->clock * 18 / 8;
1945 if (nv_connector->base.display_info.bpc == 8) {
1946 nv_encoder->dp.datarate = mode->clock * 24 / 8;
1949 nv_encoder->dp.datarate = mode->clock * 30 / 8;
1953 if (nv_encoder->dcb->sorconf.link & 1)
1963 nv50_sor_dpms(&nv_encoder->base.base, DRM_MODE_DPMS_ON);
1965 if (nv50_vers(mast) >= GF110_DISP) {
1966 u32 *push = evo_wait(mast, 3);
1968 u32 magic = 0x31ec6000 | (nv_crtc->index << 25);
1969 u32 syncs = 0x00000001;
1971 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1972 syncs |= 0x00000008;
1973 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1974 syncs |= 0x00000010;
1976 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1977 magic |= 0x00000001;
1979 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2);
1980 evo_data(push, syncs | (depth << 6));
1981 evo_data(push, magic);
1982 evo_kick(push, mast);
1988 ctrl = (depth << 16) | (proto << 8);
1989 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1991 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1996 nv50_sor_ctrl(nv_encoder, mask | owner, ctrl | owner);
2000 nv50_sor_destroy(struct drm_encoder *encoder)
2002 drm_encoder_cleanup(encoder);
2006 static const struct drm_encoder_helper_funcs nv50_sor_hfunc = {
2007 .dpms = nv50_sor_dpms,
2008 .mode_fixup = nv50_sor_mode_fixup,
2009 .prepare = nv50_sor_disconnect,
2010 .commit = nv50_sor_commit,
2011 .mode_set = nv50_sor_mode_set,
2012 .disable = nv50_sor_disconnect,
2013 .get_crtc = nv50_display_crtc_get,
2016 static const struct drm_encoder_funcs nv50_sor_func = {
2017 .destroy = nv50_sor_destroy,
2021 nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe)
2023 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2024 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
2025 struct nouveau_encoder *nv_encoder;
2026 struct drm_encoder *encoder;
2029 switch (dcbe->type) {
2030 case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break;
2031 case DCB_OUTPUT_TMDS:
2034 type = DRM_MODE_ENCODER_TMDS;
2038 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2041 nv_encoder->dcb = dcbe;
2042 nv_encoder->or = ffs(dcbe->or) - 1;
2043 nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index);
2044 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
2046 encoder = to_drm_encoder(nv_encoder);
2047 encoder->possible_crtcs = dcbe->heads;
2048 encoder->possible_clones = 0;
2049 drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type);
2050 drm_encoder_helper_add(encoder, &nv50_sor_hfunc);
2052 drm_mode_connector_attach_encoder(connector, encoder);
2056 /******************************************************************************
2058 *****************************************************************************/
2061 nv50_pior_dpms(struct drm_encoder *encoder, int mode)
2063 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2064 struct nv50_disp *disp = nv50_disp(encoder->dev);
2066 struct nv50_disp_mthd_v1 base;
2067 struct nv50_disp_pior_pwr_v0 pwr;
2070 .base.method = NV50_DISP_MTHD_V1_PIOR_PWR,
2071 .base.hasht = nv_encoder->dcb->hasht,
2072 .base.hashm = nv_encoder->dcb->hashm,
2073 .pwr.state = mode == DRM_MODE_DPMS_ON,
2074 .pwr.type = nv_encoder->dcb->type,
2077 nvif_mthd(disp->disp, 0, &args, sizeof(args));
2081 nv50_pior_mode_fixup(struct drm_encoder *encoder,
2082 const struct drm_display_mode *mode,
2083 struct drm_display_mode *adjusted_mode)
2085 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2086 struct nouveau_connector *nv_connector;
2088 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2089 if (nv_connector && nv_connector->native_mode) {
2090 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
2091 int id = adjusted_mode->base.id;
2092 *adjusted_mode = *nv_connector->native_mode;
2093 adjusted_mode->base.id = id;
2097 adjusted_mode->clock *= 2;
2102 nv50_pior_commit(struct drm_encoder *encoder)
2107 nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
2108 struct drm_display_mode *adjusted_mode)
2110 struct nv50_mast *mast = nv50_mast(encoder->dev);
2111 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2112 struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
2113 struct nouveau_connector *nv_connector;
2114 u8 owner = 1 << nv_crtc->index;
2118 nv_connector = nouveau_encoder_connector_get(nv_encoder);
2119 switch (nv_connector->base.display_info.bpc) {
2120 case 10: depth = 0x6; break;
2121 case 8: depth = 0x5; break;
2122 case 6: depth = 0x2; break;
2123 default: depth = 0x0; break;
2126 switch (nv_encoder->dcb->type) {
2127 case DCB_OUTPUT_TMDS:
2136 nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON);
2138 push = evo_wait(mast, 8);
2140 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2141 u32 ctrl = (depth << 16) | (proto << 8) | owner;
2142 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
2144 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
2146 evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1);
2147 evo_data(push, ctrl);
2150 evo_kick(push, mast);
2153 nv_encoder->crtc = encoder->crtc;
2157 nv50_pior_disconnect(struct drm_encoder *encoder)
2159 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
2160 struct nv50_mast *mast = nv50_mast(encoder->dev);
2161 const int or = nv_encoder->or;
2164 if (nv_encoder->crtc) {
2165 nv50_crtc_prepare(nv_encoder->crtc);
2167 push = evo_wait(mast, 4);
2169 if (nv50_vers(mast) < GF110_DISP_CORE_CHANNEL_DMA) {
2170 evo_mthd(push, 0x0700 + (or * 0x040), 1);
2171 evo_data(push, 0x00000000);
2173 evo_kick(push, mast);
2177 nv_encoder->crtc = NULL;
2181 nv50_pior_destroy(struct drm_encoder *encoder)
2183 drm_encoder_cleanup(encoder);
2187 static const struct drm_encoder_helper_funcs nv50_pior_hfunc = {
2188 .dpms = nv50_pior_dpms,
2189 .mode_fixup = nv50_pior_mode_fixup,
2190 .prepare = nv50_pior_disconnect,
2191 .commit = nv50_pior_commit,
2192 .mode_set = nv50_pior_mode_set,
2193 .disable = nv50_pior_disconnect,
2194 .get_crtc = nv50_display_crtc_get,
2197 static const struct drm_encoder_funcs nv50_pior_func = {
2198 .destroy = nv50_pior_destroy,
2202 nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe)
2204 struct nouveau_drm *drm = nouveau_drm(connector->dev);
2205 struct nouveau_i2c *i2c = nvkm_i2c(&drm->device);
2206 struct nouveau_i2c_port *ddc = NULL;
2207 struct nouveau_encoder *nv_encoder;
2208 struct drm_encoder *encoder;
2211 switch (dcbe->type) {
2212 case DCB_OUTPUT_TMDS:
2213 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev));
2214 type = DRM_MODE_ENCODER_TMDS;
2217 ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev));
2218 type = DRM_MODE_ENCODER_TMDS;
2224 nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
2227 nv_encoder->dcb = dcbe;
2228 nv_encoder->or = ffs(dcbe->or) - 1;
2229 nv_encoder->i2c = ddc;
2231 encoder = to_drm_encoder(nv_encoder);
2232 encoder->possible_crtcs = dcbe->heads;
2233 encoder->possible_clones = 0;
2234 drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type);
2235 drm_encoder_helper_add(encoder, &nv50_pior_hfunc);
2237 drm_mode_connector_attach_encoder(connector, encoder);
2241 /******************************************************************************
2243 *****************************************************************************/
2246 nv50_fbdma_fini(struct nv50_fbdma *fbdma)
2249 for (i = 0; i < ARRAY_SIZE(fbdma->base); i++)
2250 nvif_object_fini(&fbdma->base[i]);
2251 nvif_object_fini(&fbdma->core);
2252 list_del(&fbdma->head);
2257 nv50_fbdma_init(struct drm_device *dev, u32 name, u64 offset, u64 length, u8 kind)
2259 struct nouveau_drm *drm = nouveau_drm(dev);
2260 struct nv50_disp *disp = nv50_disp(dev);
2261 struct nv50_mast *mast = nv50_mast(dev);
2262 struct __attribute__ ((packed)) {
2263 struct nv_dma_v0 base;
2265 struct nv50_dma_v0 nv50;
2266 struct gf100_dma_v0 gf100;
2267 struct gf110_dma_v0 gf110;
2270 struct nv50_fbdma *fbdma;
2271 struct drm_crtc *crtc;
2272 u32 size = sizeof(args.base);
2275 list_for_each_entry(fbdma, &disp->fbdma, head) {
2276 if (fbdma->core.handle == name)
2280 fbdma = kzalloc(sizeof(*fbdma), GFP_KERNEL);
2283 list_add(&fbdma->head, &disp->fbdma);
2285 args.base.target = NV_DMA_V0_TARGET_VRAM;
2286 args.base.access = NV_DMA_V0_ACCESS_RDWR;
2287 args.base.start = offset;
2288 args.base.limit = offset + length - 1;
2290 if (drm->device.info.chipset < 0x80) {
2291 args.nv50.part = NV50_DMA_V0_PART_256;
2292 size += sizeof(args.nv50);
2294 if (drm->device.info.chipset < 0xc0) {
2295 args.nv50.part = NV50_DMA_V0_PART_256;
2296 args.nv50.kind = kind;
2297 size += sizeof(args.nv50);
2299 if (drm->device.info.chipset < 0xd0) {
2300 args.gf100.kind = kind;
2301 size += sizeof(args.gf100);
2303 args.gf110.page = GF110_DMA_V0_PAGE_LP;
2304 args.gf110.kind = kind;
2305 size += sizeof(args.gf110);
2308 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2309 struct nv50_head *head = nv50_head(crtc);
2310 int ret = nvif_object_init(&head->sync.base.base.user, NULL,
2311 name, NV_DMA_IN_MEMORY, &args, size,
2312 &fbdma->base[head->base.index]);
2314 nv50_fbdma_fini(fbdma);
2319 ret = nvif_object_init(&mast->base.base.user, NULL, name,
2320 NV_DMA_IN_MEMORY, &args, size,
2323 nv50_fbdma_fini(fbdma);
2331 nv50_fb_dtor(struct drm_framebuffer *fb)
2336 nv50_fb_ctor(struct drm_framebuffer *fb)
2338 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
2339 struct nouveau_drm *drm = nouveau_drm(fb->dev);
2340 struct nouveau_bo *nvbo = nv_fb->nvbo;
2341 struct nv50_disp *disp = nv50_disp(fb->dev);
2342 u8 kind = nouveau_bo_tile_layout(nvbo) >> 8;
2343 u8 tile = nvbo->tile_mode;
2345 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) {
2346 NV_ERROR(drm, "framebuffer requires contiguous bo\n");
2350 if (drm->device.info.chipset >= 0xc0)
2351 tile >>= 4; /* yep.. */
2353 switch (fb->depth) {
2354 case 8: nv_fb->r_format = 0x1e00; break;
2355 case 15: nv_fb->r_format = 0xe900; break;
2356 case 16: nv_fb->r_format = 0xe800; break;
2358 case 32: nv_fb->r_format = 0xcf00; break;
2359 case 30: nv_fb->r_format = 0xd100; break;
2361 NV_ERROR(drm, "unknown depth %d\n", fb->depth);
2365 if (disp->disp->oclass < G82_DISP) {
2366 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2367 (fb->pitches[0] | 0x00100000);
2368 nv_fb->r_format |= kind << 16;
2370 if (disp->disp->oclass < GF110_DISP) {
2371 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2372 (fb->pitches[0] | 0x00100000);
2374 nv_fb->r_pitch = kind ? (((fb->pitches[0] / 4) << 4) | tile) :
2375 (fb->pitches[0] | 0x01000000);
2377 nv_fb->r_handle = 0xffff0000 | kind;
2379 return nv50_fbdma_init(fb->dev, nv_fb->r_handle, 0,
2380 drm->device.info.ram_user, kind);
2383 /******************************************************************************
2385 *****************************************************************************/
2388 nv50_display_fini(struct drm_device *dev)
2393 nv50_display_init(struct drm_device *dev)
2395 struct nv50_disp *disp = nv50_disp(dev);
2396 struct drm_crtc *crtc;
2399 push = evo_wait(nv50_mast(dev), 32);
2403 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2404 struct nv50_sync *sync = nv50_sync(crtc);
2405 nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data);
2408 evo_mthd(push, 0x0088, 1);
2409 evo_data(push, nv50_mast(dev)->base.sync.handle);
2410 evo_kick(push, nv50_mast(dev));
2415 nv50_display_destroy(struct drm_device *dev)
2417 struct nv50_disp *disp = nv50_disp(dev);
2418 struct nv50_fbdma *fbdma, *fbtmp;
2420 list_for_each_entry_safe(fbdma, fbtmp, &disp->fbdma, head) {
2421 nv50_fbdma_fini(fbdma);
2424 nv50_dmac_destroy(&disp->mast.base, disp->disp);
2426 nouveau_bo_unmap(disp->sync);
2428 nouveau_bo_unpin(disp->sync);
2429 nouveau_bo_ref(NULL, &disp->sync);
2431 nouveau_display(dev)->priv = NULL;
2436 nv50_display_create(struct drm_device *dev)
2438 struct nvif_device *device = &nouveau_drm(dev)->device;
2439 struct nouveau_drm *drm = nouveau_drm(dev);
2440 struct dcb_table *dcb = &drm->vbios.dcb;
2441 struct drm_connector *connector, *tmp;
2442 struct nv50_disp *disp;
2443 struct dcb_output *dcbe;
2446 disp = kzalloc(sizeof(*disp), GFP_KERNEL);
2449 INIT_LIST_HEAD(&disp->fbdma);
2451 nouveau_display(dev)->priv = disp;
2452 nouveau_display(dev)->dtor = nv50_display_destroy;
2453 nouveau_display(dev)->init = nv50_display_init;
2454 nouveau_display(dev)->fini = nv50_display_fini;
2455 nouveau_display(dev)->fb_ctor = nv50_fb_ctor;
2456 nouveau_display(dev)->fb_dtor = nv50_fb_dtor;
2457 disp->disp = &nouveau_display(dev)->disp;
2459 /* small shared memory area we use for notifiers and semaphores */
2460 ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
2461 0, 0x0000, NULL, &disp->sync);
2463 ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM);
2465 ret = nouveau_bo_map(disp->sync);
2467 nouveau_bo_unpin(disp->sync);
2470 nouveau_bo_ref(NULL, &disp->sync);
2476 /* allocate master evo channel */
2477 ret = nv50_core_create(disp->disp, disp->sync->bo.offset,
2482 /* create crtc objects to represent the hw heads */
2483 if (disp->disp->oclass >= GF110_DISP)
2484 crtcs = nvif_rd32(device, 0x022448);
2488 for (i = 0; i < crtcs; i++) {
2489 ret = nv50_crtc_create(dev, i);
2494 /* create encoder/connector objects based on VBIOS DCB table */
2495 for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
2496 connector = nouveau_connector_create(dev, dcbe->connector);
2497 if (IS_ERR(connector))
2500 if (dcbe->location == DCB_LOC_ON_CHIP) {
2501 switch (dcbe->type) {
2502 case DCB_OUTPUT_TMDS:
2503 case DCB_OUTPUT_LVDS:
2505 ret = nv50_sor_create(connector, dcbe);
2507 case DCB_OUTPUT_ANALOG:
2508 ret = nv50_dac_create(connector, dcbe);
2515 ret = nv50_pior_create(connector, dcbe);
2519 NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n",
2520 dcbe->location, dcbe->type,
2521 ffs(dcbe->or) - 1, ret);
2526 /* cull any connectors we created that don't have an encoder */
2527 list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
2528 if (connector->encoder_ids[0])
2531 NV_WARN(drm, "%s has no encoders, removing\n",
2533 connector->funcs->destroy(connector);
2538 nv50_display_destroy(dev);