2 * Copyright (C) 2008 Maarten Maathuis.
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #define NOUVEAU_DMA_DEBUG (nouveau_reg_debug & NOUVEAU_REG_DEBUG_EVO)
28 #include "nv50_display.h"
29 #include "nouveau_crtc.h"
30 #include "nouveau_encoder.h"
31 #include "nouveau_connector.h"
32 #include "nouveau_fb.h"
33 #include "nouveau_fbcon.h"
34 #include "nouveau_ramht.h"
35 #include "drm_crtc_helper.h"
37 static void nv50_display_isr(struct drm_device *);
38 static void nv50_display_bh(unsigned long);
41 nv50_sor_nr(struct drm_device *dev)
43 struct drm_nouveau_private *dev_priv = dev->dev_private;
45 if (dev_priv->chipset < 0x90 ||
46 dev_priv->chipset == 0x92 ||
47 dev_priv->chipset == 0xa0)
54 nv50_display_early_init(struct drm_device *dev)
60 nv50_display_late_takedown(struct drm_device *dev)
65 nv50_display_init(struct drm_device *dev)
67 struct drm_nouveau_private *dev_priv = dev->dev_private;
68 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
69 struct drm_connector *connector;
70 struct nouveau_channel *evo;
74 NV_DEBUG_KMS(dev, "\n");
76 nv_wr32(dev, 0x00610184, nv_rd32(dev, 0x00614004));
79 * I think the 0x006101XX range is some kind of main control area
80 * that enables things.
83 for (i = 0; i < 2; i++) {
84 val = nv_rd32(dev, 0x00616100 + (i * 0x800));
85 nv_wr32(dev, 0x00610190 + (i * 0x10), val);
86 val = nv_rd32(dev, 0x00616104 + (i * 0x800));
87 nv_wr32(dev, 0x00610194 + (i * 0x10), val);
88 val = nv_rd32(dev, 0x00616108 + (i * 0x800));
89 nv_wr32(dev, 0x00610198 + (i * 0x10), val);
90 val = nv_rd32(dev, 0x0061610c + (i * 0x800));
91 nv_wr32(dev, 0x0061019c + (i * 0x10), val);
95 for (i = 0; i < 3; i++) {
96 val = nv_rd32(dev, 0x0061a000 + (i * 0x800));
97 nv_wr32(dev, 0x006101d0 + (i * 0x04), val);
101 for (i = 0; i < nv50_sor_nr(dev); i++) {
102 val = nv_rd32(dev, 0x0061c000 + (i * 0x800));
103 nv_wr32(dev, 0x006101e0 + (i * 0x04), val);
107 for (i = 0; i < 3; i++) {
108 val = nv_rd32(dev, 0x0061e000 + (i * 0x800));
109 nv_wr32(dev, 0x006101f0 + (i * 0x04), val);
112 for (i = 0; i < 3; i++) {
113 nv_wr32(dev, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
114 NV50_PDISPLAY_DAC_DPMS_CTRL_PENDING);
115 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
118 /* The precise purpose is unknown, i suspect it has something to do
121 if (nv_rd32(dev, NV50_PDISPLAY_INTR_1) & 0x100) {
122 nv_wr32(dev, NV50_PDISPLAY_INTR_1, 0x100);
123 nv_wr32(dev, 0x006194e8, nv_rd32(dev, 0x006194e8) & ~1);
124 if (!nv_wait(dev, 0x006194e8, 2, 0)) {
125 NV_ERROR(dev, "timeout: (0x6194e8 & 2) != 0\n");
126 NV_ERROR(dev, "0x6194e8 = 0x%08x\n",
127 nv_rd32(dev, 0x6194e8));
132 for (i = 0; i < 2; i++) {
133 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
134 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
135 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS, 0)) {
136 NV_ERROR(dev, "timeout: CURSOR_CTRL2_STATUS == 0\n");
137 NV_ERROR(dev, "CURSOR_CTRL2 = 0x%08x\n",
138 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
142 nv_wr32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
143 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_ON);
144 if (!nv_wait(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
145 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS,
146 NV50_PDISPLAY_CURSOR_CURSOR_CTRL2_STATUS_ACTIVE)) {
147 NV_ERROR(dev, "timeout: "
148 "CURSOR_CTRL2_STATUS_ACTIVE(%d)\n", i);
149 NV_ERROR(dev, "CURSOR_CTRL2(%d) = 0x%08x\n", i,
150 nv_rd32(dev, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i)));
155 nv_wr32(dev, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
156 nv_mask(dev, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
157 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
158 nv_mask(dev, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
159 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1,
160 NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
161 NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
162 NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
164 /* enable hotplug interrupts */
165 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
166 struct nouveau_connector *conn = nouveau_connector(connector);
168 if (conn->dcb->gpio_tag == 0xff)
171 pgpio->irq_enable(dev, conn->dcb->gpio_tag, true);
174 ret = nv50_evo_init(dev);
177 evo = nv50_display(dev)->master;
179 nv_wr32(dev, NV50_PDISPLAY_OBJECTS, (evo->ramin->vinst >> 8) | 9);
181 ret = RING_SPACE(evo, 15);
184 BEGIN_RING(evo, 0, NV50_EVO_UNK84, 2);
185 OUT_RING(evo, NV50_EVO_UNK84_NOTIFY_DISABLED);
186 OUT_RING(evo, NvEvoSync);
187 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, FB_DMA), 1);
188 OUT_RING(evo, NV50_EVO_CRTC_FB_DMA_HANDLE_NONE);
189 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK0800), 1);
191 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, DISPLAY_START), 1);
193 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK082C), 1);
195 /* required to make display sync channels not hate life */
196 BEGIN_RING(evo, 0, NV50_EVO_CRTC(0, UNK900), 1);
197 OUT_RING (evo, 0x00000311);
198 BEGIN_RING(evo, 0, NV50_EVO_CRTC(1, UNK900), 1);
199 OUT_RING (evo, 0x00000311);
201 if (!nv_wait(dev, 0x640004, 0xffffffff, evo->dma.put << 2))
202 NV_ERROR(dev, "evo pushbuf stalled\n");
208 static int nv50_display_disable(struct drm_device *dev)
210 struct drm_nouveau_private *dev_priv = dev->dev_private;
211 struct nv50_display *disp = nv50_display(dev);
212 struct nouveau_channel *evo = disp->master;
213 struct drm_crtc *drm_crtc;
216 NV_DEBUG_KMS(dev, "\n");
218 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
219 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
221 nv50_crtc_blank(crtc, true);
224 ret = RING_SPACE(evo, 2);
226 BEGIN_RING(evo, 0, NV50_EVO_UPDATE, 1);
231 /* Almost like ack'ing a vblank interrupt, maybe in the spirit of
234 list_for_each_entry(drm_crtc, &dev->mode_config.crtc_list, head) {
235 struct nouveau_crtc *crtc = nouveau_crtc(drm_crtc);
236 uint32_t mask = NV50_PDISPLAY_INTR_1_VBLANK_CRTC_(crtc->index);
238 if (!crtc->base.enabled)
241 nv_wr32(dev, NV50_PDISPLAY_INTR_1, mask);
242 if (!nv_wait(dev, NV50_PDISPLAY_INTR_1, mask, mask)) {
243 NV_ERROR(dev, "timeout: (0x610024 & 0x%08x) == "
244 "0x%08x\n", mask, mask);
245 NV_ERROR(dev, "0x610024 = 0x%08x\n",
246 nv_rd32(dev, NV50_PDISPLAY_INTR_1));
252 for (i = 0; i < 3; i++) {
253 if (!nv_wait(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i),
254 NV50_PDISPLAY_SOR_DPMS_STATE_WAIT, 0)) {
255 NV_ERROR(dev, "timeout: SOR_DPMS_STATE_WAIT(%d) == 0\n", i);
256 NV_ERROR(dev, "SOR_DPMS_STATE(%d) = 0x%08x\n", i,
257 nv_rd32(dev, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
261 /* disable interrupts. */
262 nv_wr32(dev, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
264 /* disable hotplug interrupts */
265 nv_wr32(dev, 0xe054, 0xffffffff);
266 nv_wr32(dev, 0xe050, 0x00000000);
267 if (dev_priv->chipset >= 0x90) {
268 nv_wr32(dev, 0xe074, 0xffffffff);
269 nv_wr32(dev, 0xe070, 0x00000000);
274 int nv50_display_create(struct drm_device *dev)
276 struct drm_nouveau_private *dev_priv = dev->dev_private;
277 struct dcb_table *dcb = &dev_priv->vbios.dcb;
278 struct drm_connector *connector, *ct;
279 struct nv50_display *priv;
282 NV_DEBUG_KMS(dev, "\n");
284 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
287 dev_priv->engine.display.priv = priv;
289 /* init basic kernel modesetting */
290 drm_mode_config_init(dev);
292 /* Initialise some optional connector properties. */
293 drm_mode_create_scaling_mode_property(dev);
294 drm_mode_create_dithering_property(dev);
296 dev->mode_config.min_width = 0;
297 dev->mode_config.min_height = 0;
299 dev->mode_config.funcs = (void *)&nouveau_mode_config_funcs;
301 dev->mode_config.max_width = 8192;
302 dev->mode_config.max_height = 8192;
304 dev->mode_config.fb_base = dev_priv->fb_phys;
306 /* Create CRTC objects */
307 for (i = 0; i < 2; i++)
308 nv50_crtc_create(dev, i);
310 /* We setup the encoders from the BIOS table */
311 for (i = 0 ; i < dcb->entries; i++) {
312 struct dcb_entry *entry = &dcb->entry[i];
314 if (entry->location != DCB_LOC_ON_CHIP) {
315 NV_WARN(dev, "Off-chip encoder %d/%d unsupported\n",
316 entry->type, ffs(entry->or) - 1);
320 connector = nouveau_connector_create(dev, entry->connector);
321 if (IS_ERR(connector))
324 switch (entry->type) {
328 nv50_sor_create(connector, entry);
331 nv50_dac_create(connector, entry);
334 NV_WARN(dev, "DCB encoder %d unknown\n", entry->type);
339 list_for_each_entry_safe(connector, ct,
340 &dev->mode_config.connector_list, head) {
341 if (!connector->encoder_ids[0]) {
342 NV_WARN(dev, "%s has no encoders, removing\n",
343 drm_get_connector_name(connector));
344 connector->funcs->destroy(connector);
348 tasklet_init(&priv->tasklet, nv50_display_bh, (unsigned long)dev);
349 nouveau_irq_register(dev, 26, nv50_display_isr);
351 ret = nv50_display_init(dev);
353 nv50_display_destroy(dev);
361 nv50_display_destroy(struct drm_device *dev)
363 struct nv50_display *disp = nv50_display(dev);
365 NV_DEBUG_KMS(dev, "\n");
367 drm_mode_config_cleanup(dev);
369 nv50_display_disable(dev);
370 nouveau_irq_unregister(dev, 26);
375 nv50_display_flip_stop(struct drm_crtc *crtc)
377 struct nv50_display *disp = nv50_display(crtc->dev);
378 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
379 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
380 struct nouveau_channel *evo = dispc->sync;
383 ret = RING_SPACE(evo, 8);
389 BEGIN_RING(evo, 0, 0x0084, 1);
390 OUT_RING (evo, 0x00000000);
391 BEGIN_RING(evo, 0, 0x0094, 1);
392 OUT_RING (evo, 0x00000000);
393 BEGIN_RING(evo, 0, 0x00c0, 1);
394 OUT_RING (evo, 0x00000000);
395 BEGIN_RING(evo, 0, 0x0080, 1);
396 OUT_RING (evo, 0x00000000);
401 nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb,
402 struct nouveau_channel *chan)
404 struct drm_nouveau_private *dev_priv = crtc->dev->dev_private;
405 struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb);
406 struct nv50_display *disp = nv50_display(crtc->dev);
407 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
408 struct nv50_display_crtc *dispc = &disp->crtc[nv_crtc->index];
409 struct nouveau_channel *evo = dispc->sync;
412 ret = RING_SPACE(evo, 24);
416 /* synchronise with the rendering channel, if necessary */
418 u64 offset = dispc->sem.bo->vma.offset + dispc->sem.offset;
420 ret = RING_SPACE(chan, 10);
426 if (dev_priv->chipset < 0xc0) {
427 BEGIN_RING(chan, NvSubSw, 0x0060, 2);
428 OUT_RING (chan, NvEvoSema0 + nv_crtc->index);
429 OUT_RING (chan, dispc->sem.offset);
430 BEGIN_RING(chan, NvSubSw, 0x006c, 1);
431 OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
432 BEGIN_RING(chan, NvSubSw, 0x0064, 2);
433 OUT_RING (chan, dispc->sem.offset ^ 0x10);
434 OUT_RING (chan, 0x74b1e000);
435 BEGIN_RING(chan, NvSubSw, 0x0060, 1);
436 if (dev_priv->chipset < 0x84)
437 OUT_RING (chan, NvSema);
439 OUT_RING (chan, chan->vram_handle);
441 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
442 OUT_RING (chan, upper_32_bits(offset));
443 OUT_RING (chan, lower_32_bits(offset));
444 OUT_RING (chan, 0xf00d0000 | dispc->sem.value);
445 OUT_RING (chan, 0x1002);
446 BEGIN_NVC0(chan, 2, NvSubM2MF, 0x0010, 4);
447 OUT_RING (chan, upper_32_bits(offset));
448 OUT_RING (chan, lower_32_bits(offset ^ 0x10));
449 OUT_RING (chan, 0x74b1e000);
450 OUT_RING (chan, 0x1001);
454 nouveau_bo_wr32(dispc->sem.bo, dispc->sem.offset / 4,
455 0xf00d0000 | dispc->sem.value);
458 /* queue the flip on the crtc's "display sync" channel */
459 BEGIN_RING(evo, 0, 0x0100, 1);
460 OUT_RING (evo, 0xfffe0000);
461 BEGIN_RING(evo, 0, 0x0084, 5);
462 OUT_RING (evo, chan ? 0x00000100 : 0x00000010);
463 OUT_RING (evo, dispc->sem.offset);
464 OUT_RING (evo, 0xf00d0000 | dispc->sem.value);
465 OUT_RING (evo, 0x74b1e000);
466 OUT_RING (evo, NvEvoSync);
467 BEGIN_RING(evo, 0, 0x00a0, 2);
468 OUT_RING (evo, 0x00000000);
469 OUT_RING (evo, 0x00000000);
470 BEGIN_RING(evo, 0, 0x00c0, 1);
471 OUT_RING (evo, nv_fb->r_dma);
472 BEGIN_RING(evo, 0, 0x0110, 2);
473 OUT_RING (evo, 0x00000000);
474 OUT_RING (evo, 0x00000000);
475 BEGIN_RING(evo, 0, 0x0800, 5);
476 OUT_RING (evo, (nv_fb->nvbo->bo.mem.start << PAGE_SHIFT) >> 8);
478 OUT_RING (evo, (fb->height << 16) | fb->width);
479 OUT_RING (evo, nv_fb->r_pitch);
480 OUT_RING (evo, nv_fb->r_format);
481 BEGIN_RING(evo, 0, 0x0080, 1);
482 OUT_RING (evo, 0x00000000);
485 dispc->sem.offset ^= 0x10;
491 nv50_display_script_select(struct drm_device *dev, struct dcb_entry *dcb,
494 struct drm_nouveau_private *dev_priv = dev->dev_private;
495 struct nouveau_connector *nv_connector = NULL;
496 struct drm_encoder *encoder;
497 struct nvbios *bios = &dev_priv->vbios;
500 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
501 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
503 if (nv_encoder->dcb != dcb)
506 nv_connector = nouveau_encoder_connector_get(nv_encoder);
510 or = ffs(dcb->or) - 1;
513 script = (mc >> 8) & 0xf;
514 if (bios->fp_no_ddc) {
515 if (bios->fp.dual_link)
517 if (bios->fp.if_is_24bit)
520 /* determine number of lvds links */
521 if (nv_connector && nv_connector->edid &&
522 nv_connector->dcb->type == DCB_CONNECTOR_LVDS_SPWG) {
523 /* http://www.spwg.org */
524 if (((u8 *)nv_connector->edid)[121] == 2)
527 if (pxclk >= bios->fp.duallink_transition_clk) {
531 /* determine panel depth */
532 if (script & 0x0100) {
533 if (bios->fp.strapless_is_24bit & 2)
536 if (bios->fp.strapless_is_24bit & 1)
540 if (nv_connector && nv_connector->edid &&
541 (nv_connector->edid->revision >= 4) &&
542 (nv_connector->edid->input & 0x70) >= 0x20)
546 if (nouveau_uscript_lvds >= 0) {
547 NV_INFO(dev, "override script 0x%04x with 0x%04x "
548 "for output LVDS-%d\n", script,
549 nouveau_uscript_lvds, or);
550 script = nouveau_uscript_lvds;
554 script = (mc >> 8) & 0xf;
558 if (nouveau_uscript_tmds >= 0) {
559 NV_INFO(dev, "override script 0x%04x with 0x%04x "
560 "for output TMDS-%d\n", script,
561 nouveau_uscript_tmds, or);
562 script = nouveau_uscript_tmds;
566 script = (mc >> 8) & 0xf;
572 NV_ERROR(dev, "modeset on unsupported output type!\n");
580 nv50_display_vblank_crtc_handler(struct drm_device *dev, int crtc)
582 struct drm_nouveau_private *dev_priv = dev->dev_private;
583 struct nouveau_channel *chan, *tmp;
585 list_for_each_entry_safe(chan, tmp, &dev_priv->vbl_waiting,
587 if (chan->nvsw.vblsem_head != crtc)
590 nouveau_bo_wr32(chan->notifier_bo, chan->nvsw.vblsem_offset,
591 chan->nvsw.vblsem_rval);
592 list_del(&chan->nvsw.vbl_wait);
593 drm_vblank_put(dev, crtc);
596 drm_handle_vblank(dev, crtc);
600 nv50_display_vblank_handler(struct drm_device *dev, uint32_t intr)
602 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_0)
603 nv50_display_vblank_crtc_handler(dev, 0);
605 if (intr & NV50_PDISPLAY_INTR_1_VBLANK_CRTC_1)
606 nv50_display_vblank_crtc_handler(dev, 1);
608 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_VBLANK_CRTC);
612 nv50_display_unk10_handler(struct drm_device *dev)
614 struct drm_nouveau_private *dev_priv = dev->dev_private;
615 struct nv50_display *disp = nv50_display(dev);
616 u32 unk30 = nv_rd32(dev, 0x610030), mc;
617 int i, crtc, or, type = OUTPUT_ANY;
619 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
620 disp->irq.dcb = NULL;
622 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) & ~8);
624 /* Determine which CRTC we're dealing with, only 1 ever will be
625 * signalled at the same time with the current nouveau code.
627 crtc = ffs((unk30 & 0x00000060) >> 5) - 1;
631 /* Nothing needs to be done for the encoder */
632 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
636 /* Find which encoder was connected to the CRTC */
637 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
638 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_C(i));
639 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
640 if (!(mc & (1 << crtc)))
643 switch ((mc & 0x00000f00) >> 8) {
644 case 0: type = OUTPUT_ANALOG; break;
645 case 1: type = OUTPUT_TV; break;
647 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
654 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
655 if (dev_priv->chipset < 0x90 ||
656 dev_priv->chipset == 0x92 ||
657 dev_priv->chipset == 0xa0)
658 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_C(i));
660 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_C(i));
662 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
663 if (!(mc & (1 << crtc)))
666 switch ((mc & 0x00000f00) >> 8) {
667 case 0: type = OUTPUT_LVDS; break;
668 case 1: type = OUTPUT_TMDS; break;
669 case 2: type = OUTPUT_TMDS; break;
670 case 5: type = OUTPUT_TMDS; break;
671 case 8: type = OUTPUT_DP; break;
672 case 9: type = OUTPUT_DP; break;
674 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
681 /* There was no encoder to disable */
682 if (type == OUTPUT_ANY)
685 /* Disable the encoder */
686 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
687 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
689 if (dcb->type == type && (dcb->or & (1 << or))) {
690 nouveau_bios_run_display_table(dev, dcb, 0, -1);
696 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
698 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK10);
699 nv_wr32(dev, 0x610030, 0x80000000);
703 nv50_display_unk20_dp_hack(struct drm_device *dev, struct dcb_entry *dcb)
705 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
706 struct drm_encoder *encoder;
707 uint32_t tmp, unk0 = 0, unk1 = 0;
709 if (dcb->type != OUTPUT_DP)
712 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
713 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
715 if (nv_encoder->dcb == dcb) {
716 unk0 = nv_encoder->dp.unk0;
717 unk1 = nv_encoder->dp.unk1;
723 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
725 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp | unk0);
727 tmp = nv_rd32(dev, NV50_SOR_DP_UNK128(or, link));
729 nv_wr32(dev, NV50_SOR_DP_UNK128(or, link), tmp | unk1);
734 nv50_display_unk20_handler(struct drm_device *dev)
736 struct drm_nouveau_private *dev_priv = dev->dev_private;
737 struct nv50_display *disp = nv50_display(dev);
738 u32 unk30 = nv_rd32(dev, 0x610030), tmp, pclk, script, mc = 0;
739 struct dcb_entry *dcb;
740 int i, crtc, or, type = OUTPUT_ANY;
742 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
745 nouveau_bios_run_display_table(dev, dcb, 0, -2);
746 disp->irq.dcb = NULL;
749 /* CRTC clock change requested? */
750 crtc = ffs((unk30 & 0x00000600) >> 9) - 1;
752 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK));
755 nv50_crtc_set_clock(dev, crtc, pclk);
757 tmp = nv_rd32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc));
759 nv_wr32(dev, NV50_PDISPLAY_CRTC_CLK_CTRL2(crtc), tmp);
762 /* Nothing needs to be done for the encoder */
763 crtc = ffs((unk30 & 0x00000180) >> 7) - 1;
766 pclk = nv_rd32(dev, NV50_PDISPLAY_CRTC_P(crtc, CLOCK)) & 0x003fffff;
768 /* Find which encoder is connected to the CRTC */
769 for (i = 0; type == OUTPUT_ANY && i < 3; i++) {
770 mc = nv_rd32(dev, NV50_PDISPLAY_DAC_MODE_CTRL_P(i));
771 NV_DEBUG_KMS(dev, "DAC-%d mc: 0x%08x\n", i, mc);
772 if (!(mc & (1 << crtc)))
775 switch ((mc & 0x00000f00) >> 8) {
776 case 0: type = OUTPUT_ANALOG; break;
777 case 1: type = OUTPUT_TV; break;
779 NV_ERROR(dev, "invalid mc, DAC-%d: 0x%08x\n", i, mc);
786 for (i = 0; type == OUTPUT_ANY && i < nv50_sor_nr(dev); i++) {
787 if (dev_priv->chipset < 0x90 ||
788 dev_priv->chipset == 0x92 ||
789 dev_priv->chipset == 0xa0)
790 mc = nv_rd32(dev, NV50_PDISPLAY_SOR_MODE_CTRL_P(i));
792 mc = nv_rd32(dev, NV90_PDISPLAY_SOR_MODE_CTRL_P(i));
794 NV_DEBUG_KMS(dev, "SOR-%d mc: 0x%08x\n", i, mc);
795 if (!(mc & (1 << crtc)))
798 switch ((mc & 0x00000f00) >> 8) {
799 case 0: type = OUTPUT_LVDS; break;
800 case 1: type = OUTPUT_TMDS; break;
801 case 2: type = OUTPUT_TMDS; break;
802 case 5: type = OUTPUT_TMDS; break;
803 case 8: type = OUTPUT_DP; break;
804 case 9: type = OUTPUT_DP; break;
806 NV_ERROR(dev, "invalid mc, SOR-%d: 0x%08x\n", i, mc);
813 if (type == OUTPUT_ANY)
816 /* Enable the encoder */
817 for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
818 dcb = &dev_priv->vbios.dcb.entry[i];
819 if (dcb->type == type && (dcb->or & (1 << or)))
823 if (i == dev_priv->vbios.dcb.entries) {
824 NV_ERROR(dev, "no dcb for %d %d 0x%08x\n", or, type, mc);
828 script = nv50_display_script_select(dev, dcb, mc, pclk);
829 nouveau_bios_run_display_table(dev, dcb, script, pclk);
831 nv50_display_unk20_dp_hack(dev, dcb);
833 if (dcb->type != OUTPUT_ANALOG) {
834 tmp = nv_rd32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or));
838 nv_wr32(dev, NV50_PDISPLAY_SOR_CLK_CTRL2(or), tmp);
840 nv_wr32(dev, NV50_PDISPLAY_DAC_CLK_CTRL2(or), 0);
844 disp->irq.pclk = pclk;
845 disp->irq.script = script;
848 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK20);
849 nv_wr32(dev, 0x610030, 0x80000000);
852 /* If programming a TMDS output on a SOR that can also be configured for
853 * DisplayPort, make sure NV50_SOR_DP_CTRL_ENABLE is forced off.
855 * It looks like the VBIOS TMDS scripts make an attempt at this, however,
856 * the VBIOS scripts on at least one board I have only switch it off on
857 * link 0, causing a blank display if the output has previously been
858 * programmed for DisplayPort.
861 nv50_display_unk40_dp_set_tmds(struct drm_device *dev, struct dcb_entry *dcb)
863 int or = ffs(dcb->or) - 1, link = !(dcb->dpconf.sor.link & 1);
864 struct drm_encoder *encoder;
867 if (dcb->type != OUTPUT_TMDS)
870 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
871 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
873 if (nv_encoder->dcb->type == OUTPUT_DP &&
874 nv_encoder->dcb->or & (1 << or)) {
875 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
876 tmp &= ~NV50_SOR_DP_CTRL_ENABLED;
877 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
884 nv50_display_unk40_handler(struct drm_device *dev)
886 struct nv50_display *disp = nv50_display(dev);
887 struct dcb_entry *dcb = disp->irq.dcb;
888 u16 script = disp->irq.script;
889 u32 unk30 = nv_rd32(dev, 0x610030), pclk = disp->irq.pclk;
891 NV_DEBUG_KMS(dev, "0x610030: 0x%08x\n", unk30);
892 disp->irq.dcb = NULL;
896 nouveau_bios_run_display_table(dev, dcb, script, -pclk);
897 nv50_display_unk40_dp_set_tmds(dev, dcb);
900 nv_wr32(dev, NV50_PDISPLAY_INTR_1, NV50_PDISPLAY_INTR_1_CLK_UNK40);
901 nv_wr32(dev, 0x610030, 0x80000000);
902 nv_wr32(dev, 0x619494, nv_rd32(dev, 0x619494) | 8);
906 nv50_display_bh(unsigned long data)
908 struct drm_device *dev = (struct drm_device *)data;
911 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
912 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
914 NV_DEBUG_KMS(dev, "PDISPLAY_INTR_BH 0x%08x 0x%08x\n", intr0, intr1);
916 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK10)
917 nv50_display_unk10_handler(dev);
919 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK20)
920 nv50_display_unk20_handler(dev);
922 if (intr1 & NV50_PDISPLAY_INTR_1_CLK_UNK40)
923 nv50_display_unk40_handler(dev);
928 nv_wr32(dev, NV03_PMC_INTR_EN_0, 1);
932 nv50_display_error_handler(struct drm_device *dev)
934 u32 channels = (nv_rd32(dev, NV50_PDISPLAY_INTR_0) & 0x001f0000) >> 16;
938 for (chid = 0; chid < 5; chid++) {
939 if (!(channels & (1 << chid)))
942 nv_wr32(dev, NV50_PDISPLAY_INTR_0, 0x00010000 << chid);
943 addr = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid));
944 data = nv_rd32(dev, NV50_PDISPLAY_TRAPPED_DATA(chid));
945 NV_ERROR(dev, "EvoCh %d Mthd 0x%04x Data 0x%08x "
946 "(0x%04x 0x%02x)\n", chid,
947 addr & 0xffc, data, addr >> 16, (addr >> 12) & 0xf);
949 nv_wr32(dev, NV50_PDISPLAY_TRAPPED_ADDR(chid), 0x90000000);
954 nv50_display_isr(struct drm_device *dev)
956 struct nv50_display *disp = nv50_display(dev);
957 uint32_t delayed = 0;
959 while (nv_rd32(dev, NV50_PMC_INTR_0) & NV50_PMC_INTR_0_DISPLAY) {
960 uint32_t intr0 = nv_rd32(dev, NV50_PDISPLAY_INTR_0);
961 uint32_t intr1 = nv_rd32(dev, NV50_PDISPLAY_INTR_1);
964 NV_DEBUG_KMS(dev, "PDISPLAY_INTR 0x%08x 0x%08x\n", intr0, intr1);
966 if (!intr0 && !(intr1 & ~delayed))
969 if (intr0 & 0x001f0000) {
970 nv50_display_error_handler(dev);
971 intr0 &= ~0x001f0000;
974 if (intr1 & NV50_PDISPLAY_INTR_1_VBLANK_CRTC) {
975 nv50_display_vblank_handler(dev, intr1);
976 intr1 &= ~NV50_PDISPLAY_INTR_1_VBLANK_CRTC;
979 clock = (intr1 & (NV50_PDISPLAY_INTR_1_CLK_UNK10 |
980 NV50_PDISPLAY_INTR_1_CLK_UNK20 |
981 NV50_PDISPLAY_INTR_1_CLK_UNK40));
983 nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
984 tasklet_schedule(&disp->tasklet);
990 NV_ERROR(dev, "unknown PDISPLAY_INTR_0: 0x%08x\n", intr0);
991 nv_wr32(dev, NV50_PDISPLAY_INTR_0, intr0);
996 "unknown PDISPLAY_INTR_1: 0x%08x\n", intr1);
997 nv_wr32(dev, NV50_PDISPLAY_INTR_1, intr1);