2 * Copyright 2010 Red Hat Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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26 #include "nouveau_drv.h"
27 #include "nouveau_bios.h"
28 #include "nouveau_pm.h"
30 struct nv50_pm_state {
31 struct nouveau_pm_level *perflvl;
38 nv50_pm_clock_get(struct drm_device *dev, u32 id)
44 ret = get_pll_limits(dev, id, &pll);
48 reg0 = nv_rd32(dev, pll.reg + 0);
49 reg1 = nv_rd32(dev, pll.reg + 4);
51 if ((reg0 & 0x80000000) == 0) {
52 if (id == PLL_SHADER) {
53 NV_DEBUG(dev, "Shader PLL is disabled. "
54 "Shader clock is twice the core\n");
55 ret = nv50_pm_clock_get(dev, PLL_CORE);
58 } else if (id == PLL_MEMORY) {
59 NV_DEBUG(dev, "Memory PLL is disabled. "
60 "Memory clock is equal to the ref_clk\n");
65 P = (reg0 & 0x00070000) >> 16;
66 N = (reg1 & 0x0000ff00) >> 8;
67 M = (reg1 & 0x000000ff);
69 return ((pll.refclk * N / M) >> P);
73 nv50_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
76 struct nv50_pm_state *state;
79 state = kzalloc(sizeof(*state), GFP_KERNEL);
81 return ERR_PTR(-ENOMEM);
83 state->perflvl = perflvl;
85 ret = get_pll_limits(dev, id, &state->pll);
88 return (ret == -ENOENT) ? NULL : ERR_PTR(ret);
91 ret = nv50_calc_pll(dev, &state->pll, khz, &state->N, &state->M,
92 &dummy, &dummy, &state->P);
102 nv50_pm_clock_set(struct drm_device *dev, void *pre_state)
104 struct nv50_pm_state *state = pre_state;
105 struct nouveau_pm_level *perflvl = state->perflvl;
106 u32 reg = state->pll.reg, tmp;
107 struct bit_entry BIT_M;
113 if (state->type == PLL_MEMORY && perflvl->memscript &&
114 bit_table(dev, 'M', &BIT_M) == 0 &&
115 BIT_M.version == 1 && BIT_M.length >= 0x0b) {
116 script = ROM16(BIT_M.data[0x05]);
118 nouveau_bios_run_init_table(dev, script, NULL, -1);
119 script = ROM16(BIT_M.data[0x07]);
121 nouveau_bios_run_init_table(dev, script, NULL, -1);
122 script = ROM16(BIT_M.data[0x09]);
124 nouveau_bios_run_init_table(dev, script, NULL, -1);
126 nouveau_bios_run_init_table(dev, perflvl->memscript, NULL, -1);
129 if (state->type == PLL_MEMORY) {
130 nv_wr32(dev, 0x100210, 0);
131 nv_wr32(dev, 0x1002dc, 1);
134 tmp = nv_rd32(dev, reg + 0) & 0xfff8ffff;
135 tmp |= 0x80000000 | (P << 16);
136 nv_wr32(dev, reg + 0, tmp);
137 nv_wr32(dev, reg + 4, (N << 8) | M);
139 if (state->type == PLL_MEMORY) {
140 nv_wr32(dev, 0x1002dc, 0);
141 nv_wr32(dev, 0x100210, 0x80000000);
148 pwm_info(struct drm_device *dev, struct dcb_gpio_entry *gpio,
149 int *ctrl, int *line, int *indx)
151 if (gpio->line == 0x04) {
156 if (gpio->line == 0x09) {
161 if (gpio->line == 0x10) {
166 NV_ERROR(dev, "unknown pwm ctrl for gpio %d\n", gpio->line);
174 nv50_pm_pwm_get(struct drm_device *dev, struct dcb_gpio_entry *gpio,
175 u32 *divs, u32 *duty)
177 int ctrl, line, id, ret = pwm_info(dev, gpio, &ctrl, &line, &id);
181 if (nv_rd32(dev, ctrl) & (1 << line)) {
182 *divs = nv_rd32(dev, 0x00e114 + (id * 8));
183 *duty = nv_rd32(dev, 0x00e118 + (id * 8));
191 nv50_pm_pwm_set(struct drm_device *dev, struct dcb_gpio_entry *gpio,
194 int ctrl, line, id, ret = pwm_info(dev, gpio, &ctrl, &line, &id);
198 nv_mask(dev, ctrl, 0x00010001 << line, 0x00000001 << line);
199 nv_wr32(dev, 0x00e114 + (id * 8), divs);
200 nv_wr32(dev, 0x00e118 + (id * 8), duty | 0x80000000);