2 * Copyright 2010 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <linux/firmware.h>
29 #include "nouveau_drv.h"
30 #include "nouveau_mm.h"
31 #include "nvc0_graph.h"
33 static void nvc0_graph_isr(struct drm_device *);
34 static int nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan);
37 nvc0_graph_fifo_access(struct drm_device *dev, bool enabled)
41 struct nouveau_channel *
42 nvc0_graph_channel(struct drm_device *dev)
48 nvc0_graph_construct_context(struct nouveau_channel *chan)
50 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
51 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
52 struct nvc0_graph_chan *grch = chan->pgraph_ctx;
53 struct drm_device *dev = chan->dev;
57 ctx = kmalloc(priv->grctx_size, GFP_KERNEL);
61 nvc0_graph_load_context(chan);
63 nv_wo32(grch->grctx, 0x1c, 1);
64 nv_wo32(grch->grctx, 0x20, 0);
65 nv_wo32(grch->grctx, 0x28, 0);
66 nv_wo32(grch->grctx, 0x2c, 0);
67 dev_priv->engine.instmem.flush(dev);
69 ret = nvc0_grctx_generate(chan);
75 ret = nvc0_graph_unload_context_to(dev, chan->ramin->vinst);
81 for (i = 0; i < priv->grctx_size; i += 4)
82 ctx[i / 4] = nv_ro32(grch->grctx, i);
84 priv->grctx_vals = ctx;
89 nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
91 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
92 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
93 struct nvc0_graph_chan *grch = chan->pgraph_ctx;
94 struct drm_device *dev = chan->dev;
95 int i = 0, gpc, tp, ret;
98 ret = nouveau_gpuobj_new(dev, NULL, 0x2000, 256, NVOBJ_FLAG_VM,
103 ret = nouveau_gpuobj_new(dev, NULL, 0x8000, 256, NVOBJ_FLAG_VM,
108 ret = nouveau_gpuobj_new(dev, NULL, 384 * 1024, 4096, NVOBJ_FLAG_VM,
113 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0, NVOBJ_FLAG_VM,
119 nv_wo32(grch->mmio, i++ * 4, 0x00408004);
120 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
121 nv_wo32(grch->mmio, i++ * 4, 0x00408008);
122 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
124 nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
125 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
126 nv_wo32(grch->mmio, i++ * 4, 0x00408010);
127 nv_wo32(grch->mmio, i++ * 4, 0x80000000);
129 nv_wo32(grch->mmio, i++ * 4, 0x00418810);
130 nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->vinst >> 12);
131 nv_wo32(grch->mmio, i++ * 4, 0x00419848);
132 nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->vinst >> 12);
134 nv_wo32(grch->mmio, i++ * 4, 0x00419004);
135 nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
136 nv_wo32(grch->mmio, i++ * 4, 0x00419008);
137 nv_wo32(grch->mmio, i++ * 4, 0x00000000);
139 nv_wo32(grch->mmio, i++ * 4, 0x00418808);
140 nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
141 nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
142 nv_wo32(grch->mmio, i++ * 4, 0x80000018);
145 nv_wo32(grch->mmio, i++ * 4, 0x00405830);
146 nv_wo32(grch->mmio, i++ * 4, magic);
147 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
148 for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x02fc) {
149 u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800);
150 nv_wo32(grch->mmio, i++ * 4, reg);
151 nv_wo32(grch->mmio, i++ * 4, magic);
155 grch->mmio_nr = i / 2;
160 nvc0_graph_create_context(struct nouveau_channel *chan)
162 struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
163 struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
164 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
165 struct nvc0_graph_priv *priv = pgraph->priv;
166 struct nvc0_graph_chan *grch;
167 struct drm_device *dev = chan->dev;
168 struct nouveau_gpuobj *grctx;
171 chan->pgraph_ctx = kzalloc(sizeof(*grch), GFP_KERNEL);
172 if (!chan->pgraph_ctx)
174 grch = chan->pgraph_ctx;
176 ret = nouveau_gpuobj_new(dev, NULL, priv->grctx_size, 256,
177 NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
181 chan->ramin_grctx = grch->grctx;
184 ret = nvc0_graph_create_context_mmio_list(chan);
188 nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->vinst) | 4);
189 nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->vinst));
190 pinstmem->flush(dev);
192 if (!priv->grctx_vals) {
193 ret = nvc0_graph_construct_context(chan);
198 for (i = 0; i < priv->grctx_size; i += 4)
199 nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
201 nv_wo32(grctx, 0xf4, 0);
202 nv_wo32(grctx, 0xf8, 0);
203 nv_wo32(grctx, 0x10, grch->mmio_nr);
204 nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst));
205 nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst));
206 nv_wo32(grctx, 0x1c, 1);
207 nv_wo32(grctx, 0x20, 0);
208 nv_wo32(grctx, 0x28, 0);
209 nv_wo32(grctx, 0x2c, 0);
210 pinstmem->flush(dev);
214 pgraph->destroy_context(chan);
219 nvc0_graph_destroy_context(struct nouveau_channel *chan)
221 struct nvc0_graph_chan *grch;
223 grch = chan->pgraph_ctx;
224 chan->pgraph_ctx = NULL;
228 nouveau_gpuobj_ref(NULL, &grch->mmio);
229 nouveau_gpuobj_ref(NULL, &grch->unk418810);
230 nouveau_gpuobj_ref(NULL, &grch->unk40800c);
231 nouveau_gpuobj_ref(NULL, &grch->unk408004);
232 nouveau_gpuobj_ref(NULL, &grch->grctx);
233 chan->ramin_grctx = NULL;
237 nvc0_graph_load_context(struct nouveau_channel *chan)
239 struct drm_device *dev = chan->dev;
241 nv_wr32(dev, 0x409840, 0x00000030);
242 nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
243 nv_wr32(dev, 0x409504, 0x00000003);
244 if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
245 NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
251 nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
253 nv_wr32(dev, 0x409840, 0x00000003);
254 nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
255 nv_wr32(dev, 0x409504, 0x00000009);
256 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
257 NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
265 nvc0_graph_unload_context(struct drm_device *dev)
267 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
268 return nvc0_graph_unload_context_to(dev, inst);
272 nvc0_graph_destroy(struct drm_device *dev)
274 struct drm_nouveau_private *dev_priv = dev->dev_private;
275 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
276 struct nvc0_graph_priv *priv;
282 nouveau_irq_unregister(dev, 12);
284 nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
285 nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
287 if (priv->grctx_vals)
288 kfree(priv->grctx_vals);
293 nvc0_graph_takedown(struct drm_device *dev)
295 nvc0_graph_destroy(dev);
299 nvc0_graph_create(struct drm_device *dev)
301 struct drm_nouveau_private *dev_priv = dev->dev_private;
302 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
303 struct nvc0_graph_priv *priv;
306 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
311 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
315 ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
319 for (i = 0; i < 0x1000; i += 4) {
320 nv_wo32(priv->unk4188b4, i, 0x00000010);
321 nv_wo32(priv->unk4188b8, i, 0x00000010);
324 priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f;
325 priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
326 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
327 priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
328 priv->tp_total += priv->tp_nr[gpc];
331 /*XXX: these need figuring out... */
332 switch (dev_priv->chipset) {
334 if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
335 priv->magic_not_rop_nr = 0x07;
336 /* filled values up to tp_total, the rest 0 */
337 priv->magicgpc980[0] = 0x22111000;
338 priv->magicgpc980[1] = 0x00000233;
339 priv->magicgpc980[2] = 0x00000000;
340 priv->magicgpc980[3] = 0x00000000;
341 priv->magicgpc918 = 0x000ba2e9;
343 if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
344 priv->magic_not_rop_nr = 0x05;
345 priv->magicgpc980[0] = 0x11110000;
346 priv->magicgpc980[1] = 0x00233222;
347 priv->magicgpc980[2] = 0x00000000;
348 priv->magicgpc980[3] = 0x00000000;
349 priv->magicgpc918 = 0x00092493;
351 if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
352 priv->magic_not_rop_nr = 0x06;
353 priv->magicgpc980[0] = 0x11110000;
354 priv->magicgpc980[1] = 0x03332222;
355 priv->magicgpc980[2] = 0x00000000;
356 priv->magicgpc980[3] = 0x00000000;
357 priv->magicgpc918 = 0x00088889;
360 case 0xc3: /* 450, 4/0/0/0, 2 */
361 priv->magic_not_rop_nr = 0x03;
362 priv->magicgpc980[0] = 0x00003210;
363 priv->magicgpc980[1] = 0x00000000;
364 priv->magicgpc980[2] = 0x00000000;
365 priv->magicgpc980[3] = 0x00000000;
366 priv->magicgpc918 = 0x00200000;
368 case 0xc4: /* 460, 3/4/0/0, 4 */
369 priv->magic_not_rop_nr = 0x01;
370 priv->magicgpc980[0] = 0x02321100;
371 priv->magicgpc980[1] = 0x00000000;
372 priv->magicgpc980[2] = 0x00000000;
373 priv->magicgpc980[3] = 0x00000000;
374 priv->magicgpc918 = 0x00124925;
378 if (!priv->magic_not_rop_nr) {
379 NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
380 priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
381 priv->tp_nr[3], priv->rop_nr);
382 /* use 0xc3's values... */
383 priv->magic_not_rop_nr = 0x03;
384 priv->magicgpc980[0] = 0x00003210;
385 priv->magicgpc980[1] = 0x00000000;
386 priv->magicgpc980[2] = 0x00000000;
387 priv->magicgpc980[3] = 0x00000000;
388 priv->magicgpc918 = 0x00200000;
391 nouveau_irq_register(dev, 12, nvc0_graph_isr);
392 NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
393 NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
394 NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
395 NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
399 nvc0_graph_destroy(dev);
404 nvc0_graph_init_obj418880(struct drm_device *dev)
406 struct drm_nouveau_private *dev_priv = dev->dev_private;
407 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
408 struct nvc0_graph_priv *priv = pgraph->priv;
411 nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
412 nv_wr32(dev, GPC_BCAST(0x08a4), 0x00000000);
413 for (i = 0; i < 4; i++)
414 nv_wr32(dev, GPC_BCAST(0x0888) + (i * 4), 0x00000000);
415 nv_wr32(dev, GPC_BCAST(0x08b4), priv->unk4188b4->vinst >> 8);
416 nv_wr32(dev, GPC_BCAST(0x08b8), priv->unk4188b8->vinst >> 8);
420 nvc0_graph_init_regs(struct drm_device *dev)
422 nv_wr32(dev, 0x400080, 0x003083c2);
423 nv_wr32(dev, 0x400088, 0x00006fe7);
424 nv_wr32(dev, 0x40008c, 0x00000000);
425 nv_wr32(dev, 0x400090, 0x00000030);
426 nv_wr32(dev, 0x40013c, 0x013901f7);
427 nv_wr32(dev, 0x400140, 0x00000100);
428 nv_wr32(dev, 0x400144, 0x00000000);
429 nv_wr32(dev, 0x400148, 0x00000110);
430 nv_wr32(dev, 0x400138, 0x00000000);
431 nv_wr32(dev, 0x400130, 0x00000000);
432 nv_wr32(dev, 0x400134, 0x00000000);
433 nv_wr32(dev, 0x400124, 0x00000002);
437 nvc0_graph_init_gpc_0(struct drm_device *dev)
439 struct drm_nouveau_private *dev_priv = dev->dev_private;
440 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
443 // TP ROP UNKVAL(magic_not_rop_nr)
451 // 450: 00200000 00000000001000000000000000000000
452 // 460: 00124925 00000000000100100100100100100101
453 // 465: 000ba2e9 00000000000010111010001011101001
454 // 470: 00092493 00000000000010010010010010010011
455 // 480: 00088889 00000000000010001000100010001001
457 /* filled values up to tp_total, remainder 0 */
458 // 450: 00003210 00000000 00000000 00000000
459 // 460: 02321100 00000000 00000000 00000000
460 // 465: 22111000 00000233 00000000 00000000
461 // 470: 11110000 00233222 00000000 00000000
462 // 480: 11110000 03332222 00000000 00000000
464 nv_wr32(dev, GPC_BCAST(0x0980), priv->magicgpc980[0]);
465 nv_wr32(dev, GPC_BCAST(0x0984), priv->magicgpc980[1]);
466 nv_wr32(dev, GPC_BCAST(0x0988), priv->magicgpc980[2]);
467 nv_wr32(dev, GPC_BCAST(0x098c), priv->magicgpc980[3]);
469 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
470 nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
472 nv_wr32(dev, GPC_UNIT(gpc, 0x0910), 0x00040000 | priv->tp_total);
473 nv_wr32(dev, GPC_UNIT(gpc, 0x0918), priv->magicgpc918);
476 nv_wr32(dev, GPC_BCAST(0x1bd4), priv->magicgpc918);
477 nv_wr32(dev, GPC_BCAST(0x08ac), priv->rop_nr);
481 nvc0_graph_init_units(struct drm_device *dev)
483 nv_wr32(dev, 0x409c24, 0x000f0000);
484 nv_wr32(dev, 0x404000, 0xc0000000); /* DISPATCH */
485 nv_wr32(dev, 0x404600, 0xc0000000); /* M2MF */
486 nv_wr32(dev, 0x408030, 0xc0000000);
487 nv_wr32(dev, 0x40601c, 0xc0000000);
488 nv_wr32(dev, 0x404490, 0xc0000000); /* MACRO */
489 nv_wr32(dev, 0x406018, 0xc0000000);
490 nv_wr32(dev, 0x405840, 0xc0000000);
491 nv_wr32(dev, 0x405844, 0x00ffffff);
492 nv_mask(dev, 0x419cc0, 0x00000008, 0x00000008);
493 nv_mask(dev, 0x419eb4, 0x00001000, 0x00001000);
497 nvc0_graph_init_gpc_1(struct drm_device *dev)
499 struct drm_nouveau_private *dev_priv = dev->dev_private;
500 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
503 for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
504 nv_wr32(dev, GPC_UNIT(gpc, 0x0420), 0xc0000000);
505 nv_wr32(dev, GPC_UNIT(gpc, 0x0900), 0xc0000000);
506 nv_wr32(dev, GPC_UNIT(gpc, 0x1028), 0xc0000000);
507 nv_wr32(dev, GPC_UNIT(gpc, 0x0824), 0xc0000000);
508 for (tp = 0; tp < priv->tp_nr[gpc]; tp++) {
509 nv_wr32(dev, TP_UNIT(gpc, tp, 0x508), 0xffffffff);
510 nv_wr32(dev, TP_UNIT(gpc, tp, 0x50c), 0xffffffff);
511 nv_wr32(dev, TP_UNIT(gpc, tp, 0x224), 0xc0000000);
512 nv_wr32(dev, TP_UNIT(gpc, tp, 0x48c), 0xc0000000);
513 nv_wr32(dev, TP_UNIT(gpc, tp, 0x084), 0xc0000000);
514 nv_wr32(dev, TP_UNIT(gpc, tp, 0xe44), 0x001ffffe);
515 nv_wr32(dev, TP_UNIT(gpc, tp, 0xe4c), 0x0000000f);
517 nv_wr32(dev, GPC_UNIT(gpc, 0x2c90), 0xffffffff);
518 nv_wr32(dev, GPC_UNIT(gpc, 0x2c94), 0xffffffff);
523 nvc0_graph_init_rop(struct drm_device *dev)
525 struct drm_nouveau_private *dev_priv = dev->dev_private;
526 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
529 for (rop = 0; rop < priv->rop_nr; rop++) {
530 nv_wr32(dev, ROP_UNIT(rop, 0x144), 0xc0000000);
531 nv_wr32(dev, ROP_UNIT(rop, 0x070), 0xc0000000);
532 nv_wr32(dev, ROP_UNIT(rop, 0x204), 0xffffffff);
533 nv_wr32(dev, ROP_UNIT(rop, 0x208), 0xffffffff);
538 nvc0_fuc_load_fw(struct drm_device *dev, u32 fuc_base,
539 const char *code_fw, const char *data_fw)
541 const struct firmware *fw;
545 snprintf(name, sizeof(name), "nouveau/%s", data_fw);
546 ret = request_firmware(&fw, name, &dev->pdev->dev);
548 NV_ERROR(dev, "failed to load %s\n", data_fw);
552 nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
553 for (i = 0; i < fw->size / 4; i++)
554 nv_wr32(dev, fuc_base + 0x01c4, ((u32 *)fw->data)[i]);
555 release_firmware(fw);
557 snprintf(name, sizeof(name), "nouveau/%s", code_fw);
558 ret = request_firmware(&fw, name, &dev->pdev->dev);
560 NV_ERROR(dev, "failed to load %s\n", code_fw);
564 nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
565 for (i = 0; i < fw->size / 4; i++) {
567 nv_wr32(dev, fuc_base + 0x0188, i >> 6);
568 nv_wr32(dev, fuc_base + 0x0184, ((u32 *)fw->data)[i]);
570 release_firmware(fw);
576 nvc0_graph_init_ctxctl(struct drm_device *dev)
578 struct drm_nouveau_private *dev_priv = dev->dev_private;
579 struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
583 /* load fuc microcode */
584 r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
585 ret = nvc0_fuc_load_fw(dev, 0x409000, "fuc409c", "fuc409d");
587 ret = nvc0_fuc_load_fw(dev, 0x41a000, "fuc41ac", "fuc41ad");
588 nv_wr32(dev, 0x000260, r000260);
593 /* start both of them running */
594 nv_wr32(dev, 0x409840, 0xffffffff);
595 nv_wr32(dev, 0x41a10c, 0x00000000);
596 nv_wr32(dev, 0x40910c, 0x00000000);
597 nv_wr32(dev, 0x41a100, 0x00000002);
598 nv_wr32(dev, 0x409100, 0x00000002);
599 if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000001))
600 NV_INFO(dev, "0x409800 wait failed\n");
602 nv_wr32(dev, 0x409840, 0xffffffff);
603 nv_wr32(dev, 0x409500, 0x7fffffff);
604 nv_wr32(dev, 0x409504, 0x00000021);
606 nv_wr32(dev, 0x409840, 0xffffffff);
607 nv_wr32(dev, 0x409500, 0x00000000);
608 nv_wr32(dev, 0x409504, 0x00000010);
609 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
610 NV_ERROR(dev, "fuc09 req 0x10 timeout\n");
613 priv->grctx_size = nv_rd32(dev, 0x409800);
615 nv_wr32(dev, 0x409840, 0xffffffff);
616 nv_wr32(dev, 0x409500, 0x00000000);
617 nv_wr32(dev, 0x409504, 0x00000016);
618 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
619 NV_ERROR(dev, "fuc09 req 0x16 timeout\n");
623 nv_wr32(dev, 0x409840, 0xffffffff);
624 nv_wr32(dev, 0x409500, 0x00000000);
625 nv_wr32(dev, 0x409504, 0x00000025);
626 if (!nv_wait_ne(dev, 0x409800, 0xffffffff, 0x00000000)) {
627 NV_ERROR(dev, "fuc09 req 0x25 timeout\n");
635 nvc0_graph_init(struct drm_device *dev)
637 struct drm_nouveau_private *dev_priv = dev->dev_private;
638 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
639 struct nvc0_graph_priv *priv;
642 dev_priv->engine.graph.accel_blocked = true;
644 switch (dev_priv->chipset) {
650 NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
651 if (nouveau_noaccel != 0)
656 nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
657 nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
660 ret = nvc0_graph_create(dev);
666 nvc0_graph_init_obj418880(dev);
667 nvc0_graph_init_regs(dev);
668 //nvc0_graph_init_unitplemented_magics(dev);
669 nvc0_graph_init_gpc_0(dev);
670 //nvc0_graph_init_unitplemented_c242(dev);
672 nv_wr32(dev, 0x400500, 0x00010001);
673 nv_wr32(dev, 0x400100, 0xffffffff);
674 nv_wr32(dev, 0x40013c, 0xffffffff);
676 nvc0_graph_init_units(dev);
677 nvc0_graph_init_gpc_1(dev);
678 nvc0_graph_init_rop(dev);
680 nv_wr32(dev, 0x400108, 0xffffffff);
681 nv_wr32(dev, 0x400138, 0xffffffff);
682 nv_wr32(dev, 0x400118, 0xffffffff);
683 nv_wr32(dev, 0x400130, 0xffffffff);
684 nv_wr32(dev, 0x40011c, 0xffffffff);
685 nv_wr32(dev, 0x400134, 0xffffffff);
686 nv_wr32(dev, 0x400054, 0x34ce3464);
688 ret = nvc0_graph_init_ctxctl(dev);
690 dev_priv->engine.graph.accel_blocked = false;
695 nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
697 struct drm_nouveau_private *dev_priv = dev->dev_private;
698 struct nouveau_channel *chan;
702 spin_lock_irqsave(&dev_priv->channels.lock, flags);
703 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
704 chan = dev_priv->channels.ptr[i];
705 if (!chan || !chan->ramin)
708 if (inst == chan->ramin->vinst)
711 spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
716 nvc0_graph_isr(struct drm_device *dev)
718 u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
719 u32 chid = nvc0_graph_isr_chid(dev, inst);
720 u32 stat = nv_rd32(dev, 0x400100);
721 u32 addr = nv_rd32(dev, 0x400704);
722 u32 mthd = (addr & 0x00003ffc);
723 u32 subc = (addr & 0x00070000) >> 16;
724 u32 data = nv_rd32(dev, 0x400708);
725 u32 code = nv_rd32(dev, 0x400110);
726 u32 class = nv_rd32(dev, 0x404200 + (subc * 4));
728 if (stat & 0x00000010) {
729 NV_INFO(dev, "PGRAPH: ILLEGAL_MTHD ch %d [0x%010llx] subc %d "
730 "class 0x%04x mthd 0x%04x data 0x%08x\n",
731 chid, inst, subc, class, mthd, data);
732 nv_wr32(dev, 0x400100, 0x00000010);
736 if (stat & 0x00000020) {
737 NV_INFO(dev, "PGRAPH: ILLEGAL_CLASS ch %d [0x%010llx] subc %d "
738 "class 0x%04x mthd 0x%04x data 0x%08x\n",
739 chid, inst, subc, class, mthd, data);
740 nv_wr32(dev, 0x400100, 0x00000020);
744 if (stat & 0x00100000) {
745 NV_INFO(dev, "PGRAPH: DATA_ERROR [");
746 nouveau_enum_print(nv50_data_error_names, code);
747 printk("] ch %d [0x%010llx] subc %d class 0x%04x "
748 "mthd 0x%04x data 0x%08x\n",
749 chid, inst, subc, class, mthd, data);
750 nv_wr32(dev, 0x400100, 0x00100000);
754 if (stat & 0x00200000) {
755 u32 trap = nv_rd32(dev, 0x400108);
756 NV_INFO(dev, "PGRAPH: TRAP ch %d status 0x%08x\n", chid, trap);
757 nv_wr32(dev, 0x400108, trap);
758 nv_wr32(dev, 0x400100, 0x00200000);
762 if (stat & 0x00080000) {
763 u32 ustat = nv_rd32(dev, 0x409c18);
765 NV_INFO(dev, "PGRAPH: CTXCTRL ustat 0x%08x\n", ustat);
767 nv_wr32(dev, 0x409c20, ustat);
768 nv_wr32(dev, 0x400100, 0x00080000);
773 NV_INFO(dev, "PGRAPH: unknown stat 0x%08x\n", stat);
774 nv_wr32(dev, 0x400100, stat);
777 nv_wr32(dev, 0x400500, 0x00010001);