drivers/gpu/drm/nouveau/nvd0_display.c

   1 /*
   2  * Copyright 2011 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24
  25 #include <linux/dma-mapping.h>
  26
  27 #include "drmP.h"
  28 #include "drm_crtc_helper.h"
  29
  30 #include "nouveau_drv.h"
  31 #include "nouveau_connector.h"
  32 #include "nouveau_encoder.h"
  33 #include "nouveau_crtc.h"
  34 #include "nouveau_fb.h"
  35 #include "nv50_display.h"
  36
  37 #define MEM_SYNC 0xe0000001
  38 #define MEM_VRAM 0xe0010000
  39 #include "nouveau_dma.h"
  40
  41 struct nvd0_display {
  42         struct nouveau_gpuobj *mem;
  43         struct {
  44                 dma_addr_t handle;
  45                 u32 *ptr;
  46         } evo[1];
  47         struct {
  48                 struct dcb_entry *dis;
  49                 struct dcb_entry *ena;
  50                 int crtc;
  51                 int pclk;
  52                 u16 cfg;
  53         } irq;
  54 };
  55
  56 static struct nvd0_display *
  57 nvd0_display(struct drm_device *dev)
  58 {
  59         struct drm_nouveau_private *dev_priv = dev->dev_private;
  60         return dev_priv->engine.display.priv;
  61 }
  62
  63 static int
  64 evo_icmd(struct drm_device *dev, int id, u32 mthd, u32 data)
  65 {
  66         int ret = 0;
  67         nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000001);
  68         nv_wr32(dev, 0x610704 + (id * 0x10), data);
  69         nv_mask(dev, 0x610704 + (id * 0x10), 0x80000ffc, 0x80000000 | mthd);
  70         if (!nv_wait(dev, 0x610704 + (id * 0x10), 0x80000000, 0x00000000))
  71                 ret = -EBUSY;
  72         nv_mask(dev, 0x610700 + (id * 0x10), 0x00000001, 0x00000000);
  73         return ret;
  74 }
  75
  76 static u32 *
  77 evo_wait(struct drm_device *dev, int id, int nr)
  78 {
  79         struct nvd0_display *disp = nvd0_display(dev);
  80         u32 put = nv_rd32(dev, 0x640000 + (id * 0x1000)) / 4;
  81
  82         if (put + nr >= (PAGE_SIZE / 4)) {
  83                 disp->evo[id].ptr[put] = 0x20000000;
  84
  85                 nv_wr32(dev, 0x640000 + (id * 0x1000), 0x00000000);
  86                 if (!nv_wait(dev, 0x640004 + (id * 0x1000), ~0, 0x00000000)) {
  87                         NV_ERROR(dev, "evo %d dma stalled\n", id);
  88                         return NULL;
  89                 }
  90
  91                 put = 0;
  92         }
  93
  94         return disp->evo[id].ptr + put;
  95 }
  96
  97 static void
  98 evo_kick(u32 *push, struct drm_device *dev, int id)
  99 {
 100         struct nvd0_display *disp = nvd0_display(dev);
 101         nv_wr32(dev, 0x640000 + (id * 0x1000), (push - disp->evo[id].ptr) << 2);
 102 }
 103
 104 #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m))
 105 #define evo_data(p,d)   *((p)++) = (d)
 106
 107 static struct drm_crtc *
 108 nvd0_display_crtc_get(struct drm_encoder *encoder)
 109 {
 110         return nouveau_encoder(encoder)->crtc;
 111 }
 112
 113 /******************************************************************************
 114  * CRTC
 115  *****************************************************************************/
 116 static int
 117 nvd0_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool on, bool update)
 118 {
 119         struct drm_device *dev = nv_crtc->base.dev;
 120         u32 *push, mode;
 121
 122         mode = 0x00000000;
 123         if (on) {
 124                 /* 0x11: 6bpc dynamic 2x2
 125                  * 0x13: 8bpc dynamic 2x2
 126                  * 0x19: 6bpc static 2x2
 127                  * 0x1b: 8bpc static 2x2
 128                  * 0x21: 6bpc temporal
 129                  * 0x23: 8bpc temporal
 130                  */
 131                 mode = 0x00000011;
 132         }
 133
 134         push = evo_wait(dev, 0, 4);
 135         if (push) {
 136                 evo_mthd(push, 0x0490 + (nv_crtc->index * 0x300), 1);
 137                 evo_data(push, mode);
 138                 if (update) {
 139                         evo_mthd(push, 0x0080, 1);
 140                         evo_data(push, 0x00000000);
 141                 }
 142                 evo_kick(push, dev, 0);
 143         }
 144
 145         return 0;
 146 }
 147
 148 static int
 149 nvd0_crtc_set_scale(struct nouveau_crtc *nv_crtc, int type, bool update)
 150 {
 151         struct drm_display_mode *mode = &nv_crtc->base.mode;
 152         struct drm_device *dev = nv_crtc->base.dev;
 153         struct nouveau_connector *nv_connector;
 154         u32 *push, outX, outY;
 155
 156         outX = mode->hdisplay;
 157         outY = mode->vdisplay;
 158
 159         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 160         if (nv_connector && nv_connector->native_mode) {
 161                 struct drm_display_mode *native = nv_connector->native_mode;
 162                 u32 xratio = (native->hdisplay << 19) / mode->hdisplay;
 163                 u32 yratio = (native->vdisplay << 19) / mode->vdisplay;
 164
 165                 switch (type) {
 166                 case DRM_MODE_SCALE_ASPECT:
 167                         if (xratio > yratio) {
 168                                 outX = (mode->hdisplay * yratio) >> 19;
 169                                 outY = (mode->vdisplay * yratio) >> 19;
 170                         } else {
 171                                 outX = (mode->hdisplay * xratio) >> 19;
 172                                 outY = (mode->vdisplay * xratio) >> 19;
 173                         }
 174                         break;
 175                 case DRM_MODE_SCALE_FULLSCREEN:
 176                         outX = native->hdisplay;
 177                         outY = native->vdisplay;
 178                         break;
 179                 default:
 180                         break;
 181                 }
 182         }
 183
 184         push = evo_wait(dev, 0, 16);
 185         if (push) {
 186                 evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3);
 187                 evo_data(push, (outY << 16) | outX);
 188                 evo_data(push, (outY << 16) | outX);
 189                 evo_data(push, (outY << 16) | outX);
 190                 evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1);
 191                 evo_data(push, 0x00000000);
 192                 evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1);
 193                 evo_data(push, 0x00000000);
 194                 evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1);
 195                 evo_data(push, (mode->vdisplay << 16) | mode->hdisplay);
 196                 if (update) {
 197                         evo_mthd(push, 0x0080, 1);
 198                         evo_data(push, 0x00000000);
 199                 }
 200                 evo_kick(push, dev, 0);
 201         }
 202
 203         return 0;
 204 }
 205
 206 static int
 207 nvd0_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb,
 208                     int x, int y, bool update)
 209 {
 210         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb);
 211         u32 *push;
 212
 213         push = evo_wait(fb->dev, 0, 16);
 214         if (push) {
 215                 evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1);
 216                 evo_data(push, nvfb->nvbo->bo.offset >> 8);
 217                 evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4);
 218                 evo_data(push, (fb->height << 16) | fb->width);
 219                 evo_data(push, nvfb->r_pitch);
 220                 evo_data(push, nvfb->r_format);
 221                 evo_data(push, nvfb->r_dma);
 222                 if (update) {
 223                         evo_mthd(push, 0x0080, 1);
 224                         evo_data(push, 0x00000000);
 225                 }
 226                 evo_kick(push, fb->dev, 0);
 227         }
 228
 229         nv_crtc->fb.tile_flags = nvfb->r_dma;
 230         return 0;
 231 }
 232
 233 static void
 234 nvd0_crtc_cursor_show(struct nouveau_crtc *nv_crtc, bool show, bool update)
 235 {
 236         struct drm_device *dev = nv_crtc->base.dev;
 237         u32 *push = evo_wait(dev, 0, 16);
 238         if (push) {
 239                 if (show) {
 240                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2);
 241                         evo_data(push, 0x85000000);
 242                         evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8);
 243                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 244                         evo_data(push, MEM_VRAM);
 245                 } else {
 246                         evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1);
 247                         evo_data(push, 0x05000000);
 248                         evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1);
 249                         evo_data(push, 0x00000000);
 250                 }
 251
 252                 if (update) {
 253                         evo_mthd(push, 0x0080, 1);
 254                         evo_data(push, 0x00000000);
 255                 }
 256
 257                 evo_kick(push, dev, 0);
 258         }
 259 }
 260
 261 static void
 262 nvd0_crtc_dpms(struct drm_crtc *crtc, int mode)
 263 {
 264 }
 265
 266 static void
 267 nvd0_crtc_prepare(struct drm_crtc *crtc)
 268 {
 269         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 270         u32 *push;
 271
 272         push = evo_wait(crtc->dev, 0, 2);
 273         if (push) {
 274                 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 275                 evo_data(push, 0x00000000);
 276                 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1);
 277                 evo_data(push, 0x03000000);
 278                 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 279                 evo_data(push, 0x00000000);
 280                 evo_kick(push, crtc->dev, 0);
 281         }
 282
 283         nvd0_crtc_cursor_show(nv_crtc, false, false);
 284 }
 285
 286 static void
 287 nvd0_crtc_commit(struct drm_crtc *crtc)
 288 {
 289         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 290         u32 *push;
 291
 292         push = evo_wait(crtc->dev, 0, 32);
 293         if (push) {
 294                 evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1);
 295                 evo_data(push, nv_crtc->fb.tile_flags);
 296                 evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4);
 297                 evo_data(push, 0x83000000);
 298                 evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8);
 299                 evo_data(push, 0x00000000);
 300                 evo_data(push, 0x00000000);
 301                 evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1);
 302                 evo_data(push, MEM_VRAM);
 303                 evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1);
 304                 evo_data(push, 0xffffff00);
 305                 evo_kick(push, crtc->dev, 0);
 306         }
 307
 308         nvd0_crtc_cursor_show(nv_crtc, nv_crtc->cursor.visible, true);
 309 }
 310
 311 static bool
 312 nvd0_crtc_mode_fixup(struct drm_crtc *crtc, struct drm_display_mode *mode,
 313                      struct drm_display_mode *adjusted_mode)
 314 {
 315         return true;
 316 }
 317
 318 static int
 319 nvd0_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb)
 320 {
 321         struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb);
 322         int ret;
 323
 324         ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM);
 325         if (ret)
 326                 return ret;
 327
 328         if (old_fb) {
 329                 nvfb = nouveau_framebuffer(old_fb);
 330                 nouveau_bo_unpin(nvfb->nvbo);
 331         }
 332
 333         return 0;
 334 }
 335
 336 static int
 337 nvd0_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode,
 338                    struct drm_display_mode *mode, int x, int y,
 339                    struct drm_framebuffer *old_fb)
 340 {
 341         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 342         struct nouveau_connector *nv_connector;
 343         u32 htotal = mode->htotal;
 344         u32 vtotal = mode->vtotal;
 345         u32 hsyncw = mode->hsync_end - mode->hsync_start - 1;
 346         u32 vsyncw = mode->vsync_end - mode->vsync_start - 1;
 347         u32 hfrntp = mode->hsync_start - mode->hdisplay;
 348         u32 vfrntp = mode->vsync_start - mode->vdisplay;
 349         u32 hbackp = mode->htotal - mode->hsync_end;
 350         u32 vbackp = mode->vtotal - mode->vsync_end;
 351         u32 hss2be = hsyncw + hbackp;
 352         u32 vss2be = vsyncw + vbackp;
 353         u32 hss2de = htotal - hfrntp;
 354         u32 vss2de = vtotal - vfrntp;
 355         u32 syncs, *push;
 356         int ret;
 357
 358         syncs = 0x00000001;
 359         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 360                 syncs |= 0x00000008;
 361         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 362                 syncs |= 0x00000010;
 363
 364         ret = nvd0_crtc_swap_fbs(crtc, old_fb);
 365         if (ret)
 366                 return ret;
 367
 368         push = evo_wait(crtc->dev, 0, 64);
 369         if (push) {
 370                 evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 5);
 371                 evo_data(push, 0x00000000);
 372                 evo_data(push, (vtotal << 16) | htotal);
 373                 evo_data(push, (vsyncw << 16) | hsyncw);
 374                 evo_data(push, (vss2be << 16) | hss2be);
 375                 evo_data(push, (vss2de << 16) | hss2de);
 376                 evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1);
 377                 evo_data(push, 0x00000000); /* ??? */
 378                 evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3);
 379                 evo_data(push, mode->clock * 1000);
 380                 evo_data(push, 0x00200000); /* ??? */
 381                 evo_data(push, mode->clock * 1000);
 382                 evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 1);
 383                 evo_data(push, syncs);
 384                 evo_kick(push, crtc->dev, 0);
 385         }
 386
 387         nv_connector = nouveau_crtc_connector_get(nv_crtc);
 388         nvd0_crtc_set_dither(nv_crtc, nv_connector->use_dithering, false);
 389         nvd0_crtc_set_scale(nv_crtc, nv_connector->scaling_mode, false);
 390         nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, false);
 391         return 0;
 392 }
 393
 394 static int
 395 nvd0_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 396                         struct drm_framebuffer *old_fb)
 397 {
 398         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 399         int ret;
 400
 401         ret = nvd0_crtc_swap_fbs(crtc, old_fb);
 402         if (ret)
 403                 return ret;
 404
 405         nvd0_crtc_set_image(nv_crtc, crtc->fb, x, y, true);
 406         return 0;
 407 }
 408
 409 static int
 410 nvd0_crtc_mode_set_base_atomic(struct drm_crtc *crtc,
 411                                struct drm_framebuffer *fb, int x, int y,
 412                                enum mode_set_atomic state)
 413 {
 414         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 415         nvd0_crtc_set_image(nv_crtc, fb, x, y, true);
 416         return 0;
 417 }
 418
 419 static void
 420 nvd0_crtc_lut_load(struct drm_crtc *crtc)
 421 {
 422         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 423         void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo);
 424         int i;
 425
 426         for (i = 0; i < 256; i++) {
 427                 writew(0x6000 + (nv_crtc->lut.r[i] >> 2), lut + (i * 0x20) + 0);
 428                 writew(0x6000 + (nv_crtc->lut.g[i] >> 2), lut + (i * 0x20) + 2);
 429                 writew(0x6000 + (nv_crtc->lut.b[i] >> 2), lut + (i * 0x20) + 4);
 430         }
 431 }
 432
 433 static int
 434 nvd0_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv,
 435                      uint32_t handle, uint32_t width, uint32_t height)
 436 {
 437         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 438         struct drm_device *dev = crtc->dev;
 439         struct drm_gem_object *gem;
 440         struct nouveau_bo *nvbo;
 441         bool visible = (handle != 0);
 442         int i, ret = 0;
 443
 444         if (visible) {
 445                 if (width != 64 || height != 64)
 446                         return -EINVAL;
 447
 448                 gem = drm_gem_object_lookup(dev, file_priv, handle);
 449                 if (unlikely(!gem))
 450                         return -ENOENT;
 451                 nvbo = nouveau_gem_object(gem);
 452
 453                 ret = nouveau_bo_map(nvbo);
 454                 if (ret == 0) {
 455                         for (i = 0; i < 64 * 64; i++) {
 456                                 u32 v = nouveau_bo_rd32(nvbo, i);
 457                                 nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v);
 458                         }
 459                         nouveau_bo_unmap(nvbo);
 460                 }
 461
 462                 drm_gem_object_unreference_unlocked(gem);
 463         }
 464
 465         if (visible != nv_crtc->cursor.visible) {
 466                 nvd0_crtc_cursor_show(nv_crtc, visible, true);
 467                 nv_crtc->cursor.visible = visible;
 468         }
 469
 470         return ret;
 471 }
 472
 473 static int
 474 nvd0_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 475 {
 476         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 477         const u32 data = (y << 16) | x;
 478
 479         nv_wr32(crtc->dev, 0x64d084 + (nv_crtc->index * 0x1000), data);
 480         nv_wr32(crtc->dev, 0x64d080 + (nv_crtc->index * 0x1000), 0x00000000);
 481         return 0;
 482 }
 483
 484 static void
 485 nvd0_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
 486                     uint32_t start, uint32_t size)
 487 {
 488         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 489         u32 end = max(start + size, (u32)256);
 490         u32 i;
 491
 492         for (i = start; i < end; i++) {
 493                 nv_crtc->lut.r[i] = r[i];
 494                 nv_crtc->lut.g[i] = g[i];
 495                 nv_crtc->lut.b[i] = b[i];
 496         }
 497
 498         nvd0_crtc_lut_load(crtc);
 499 }
 500
 501 static void
 502 nvd0_crtc_destroy(struct drm_crtc *crtc)
 503 {
 504         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
 505         nouveau_bo_unmap(nv_crtc->cursor.nvbo);
 506         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 507         nouveau_bo_unmap(nv_crtc->lut.nvbo);
 508         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 509         drm_crtc_cleanup(crtc);
 510         kfree(crtc);
 511 }
 512
 513 static const struct drm_crtc_helper_funcs nvd0_crtc_hfunc = {
 514         .dpms = nvd0_crtc_dpms,
 515         .prepare = nvd0_crtc_prepare,
 516         .commit = nvd0_crtc_commit,
 517         .mode_fixup = nvd0_crtc_mode_fixup,
 518         .mode_set = nvd0_crtc_mode_set,
 519         .mode_set_base = nvd0_crtc_mode_set_base,
 520         .mode_set_base_atomic = nvd0_crtc_mode_set_base_atomic,
 521         .load_lut = nvd0_crtc_lut_load,
 522 };
 523
 524 static const struct drm_crtc_funcs nvd0_crtc_func = {
 525         .cursor_set = nvd0_crtc_cursor_set,
 526         .cursor_move = nvd0_crtc_cursor_move,
 527         .gamma_set = nvd0_crtc_gamma_set,
 528         .set_config = drm_crtc_helper_set_config,
 529         .destroy = nvd0_crtc_destroy,
 530 };
 531
 532 static int
 533 nvd0_crtc_create(struct drm_device *dev, int index)
 534 {
 535         struct nouveau_crtc *nv_crtc;
 536         struct drm_crtc *crtc;
 537         int ret, i;
 538
 539         nv_crtc = kzalloc(sizeof(*nv_crtc), GFP_KERNEL);
 540         if (!nv_crtc)
 541                 return -ENOMEM;
 542
 543         nv_crtc->index = index;
 544         nv_crtc->set_dither = nvd0_crtc_set_dither;
 545         nv_crtc->set_scale = nvd0_crtc_set_scale;
 546         for (i = 0; i < 256; i++) {
 547                 nv_crtc->lut.r[i] = i << 8;
 548                 nv_crtc->lut.g[i] = i << 8;
 549                 nv_crtc->lut.b[i] = i << 8;
 550         }
 551
 552         crtc = &nv_crtc->base;
 553         drm_crtc_init(dev, crtc, &nvd0_crtc_func);
 554         drm_crtc_helper_add(crtc, &nvd0_crtc_hfunc);
 555         drm_mode_crtc_set_gamma_size(crtc, 256);
 556
 557         ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM,
 558                              0, 0x0000, &nv_crtc->cursor.nvbo);
 559         if (!ret) {
 560                 ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
 561                 if (!ret)
 562                         ret = nouveau_bo_map(nv_crtc->cursor.nvbo);
 563                 if (ret)
 564                         nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo);
 565         }
 566
 567         if (ret)
 568                 goto out;
 569
 570         ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM,
 571                              0, 0x0000, &nv_crtc->lut.nvbo);
 572         if (!ret) {
 573                 ret = nouveau_bo_pin(nv_crtc->lut.nvbo, TTM_PL_FLAG_VRAM);
 574                 if (!ret)
 575                         ret = nouveau_bo_map(nv_crtc->lut.nvbo);
 576                 if (ret)
 577                         nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo);
 578         }
 579
 580         if (ret)
 581                 goto out;
 582
 583         nvd0_crtc_lut_load(crtc);
 584
 585 out:
 586         if (ret)
 587                 nvd0_crtc_destroy(crtc);
 588         return ret;
 589 }
 590
 591 /******************************************************************************
 592  * DAC
 593  *****************************************************************************/
 594 static void
 595 nvd0_dac_dpms(struct drm_encoder *encoder, int mode)
 596 {
 597         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 598         struct drm_device *dev = encoder->dev;
 599         int or = nv_encoder->or;
 600         u32 dpms_ctrl;
 601
 602         dpms_ctrl = 0x80000000;
 603         if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF)
 604                 dpms_ctrl |= 0x00000001;
 605         if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF)
 606                 dpms_ctrl |= 0x00000004;
 607
 608         nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
 609         nv_mask(dev, 0x61a004 + (or * 0x0800), 0xc000007f, dpms_ctrl);
 610         nv_wait(dev, 0x61a004 + (or * 0x0800), 0x80000000, 0x00000000);
 611 }
 612
 613 static bool
 614 nvd0_dac_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 615                     struct drm_display_mode *adjusted_mode)
 616 {
 617         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 618         struct nouveau_connector *nv_connector;
 619
 620         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 621         if (nv_connector && nv_connector->native_mode) {
 622                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 623                         int id = adjusted_mode->base.id;
 624                         *adjusted_mode = *nv_connector->native_mode;
 625                         adjusted_mode->base.id = id;
 626                 }
 627         }
 628
 629         return true;
 630 }
 631
 632 static void
 633 nvd0_dac_prepare(struct drm_encoder *encoder)
 634 {
 635 }
 636
 637 static void
 638 nvd0_dac_commit(struct drm_encoder *encoder)
 639 {
 640 }
 641
 642 static void
 643 nvd0_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 644                   struct drm_display_mode *adjusted_mode)
 645 {
 646         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 647         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 648         u32 *push;
 649
 650         nvd0_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 651
 652         push = evo_wait(encoder->dev, 0, 4);
 653         if (push) {
 654                 evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 2);
 655                 evo_data(push, 1 << nv_crtc->index);
 656                 evo_data(push, 0x00ff);
 657                 evo_kick(push, encoder->dev, 0);
 658         }
 659
 660         nv_encoder->crtc = encoder->crtc;
 661 }
 662
 663 static void
 664 nvd0_dac_disconnect(struct drm_encoder *encoder)
 665 {
 666         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 667         struct drm_device *dev = encoder->dev;
 668         u32 *push;
 669
 670         if (nv_encoder->crtc) {
 671                 nvd0_crtc_prepare(nv_encoder->crtc);
 672
 673                 push = evo_wait(dev, 0, 4);
 674                 if (push) {
 675                         evo_mthd(push, 0x0180 + (nv_encoder->or * 0x20), 1);
 676                         evo_data(push, 0x00000000);
 677                         evo_mthd(push, 0x0080, 1);
 678                         evo_data(push, 0x00000000);
 679                         evo_kick(push, dev, 0);
 680                 }
 681
 682                 nv_encoder->crtc = NULL;
 683         }
 684 }
 685
 686 static enum drm_connector_status
 687 nvd0_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 688 {
 689         enum drm_connector_status status = connector_status_disconnected;
 690         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 691         struct drm_device *dev = encoder->dev;
 692         int or = nv_encoder->or;
 693         u32 load;
 694
 695         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00100000);
 696         udelay(9500);
 697         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x80000000);
 698
 699         load = nv_rd32(dev, 0x61a00c + (or * 0x800));
 700         if ((load & 0x38000000) == 0x38000000)
 701                 status = connector_status_connected;
 702
 703         nv_wr32(dev, 0x61a00c + (or * 0x800), 0x00000000);
 704         return status;
 705 }
 706
 707 static void
 708 nvd0_dac_destroy(struct drm_encoder *encoder)
 709 {
 710         drm_encoder_cleanup(encoder);
 711         kfree(encoder);
 712 }
 713
 714 static const struct drm_encoder_helper_funcs nvd0_dac_hfunc = {
 715         .dpms = nvd0_dac_dpms,
 716         .mode_fixup = nvd0_dac_mode_fixup,
 717         .prepare = nvd0_dac_prepare,
 718         .commit = nvd0_dac_commit,
 719         .mode_set = nvd0_dac_mode_set,
 720         .disable = nvd0_dac_disconnect,
 721         .get_crtc = nvd0_display_crtc_get,
 722         .detect = nvd0_dac_detect
 723 };
 724
 725 static const struct drm_encoder_funcs nvd0_dac_func = {
 726         .destroy = nvd0_dac_destroy,
 727 };
 728
 729 static int
 730 nvd0_dac_create(struct drm_connector *connector, struct dcb_entry *dcbe)
 731 {
 732         struct drm_device *dev = connector->dev;
 733         struct nouveau_encoder *nv_encoder;
 734         struct drm_encoder *encoder;
 735
 736         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 737         if (!nv_encoder)
 738                 return -ENOMEM;
 739         nv_encoder->dcb = dcbe;
 740         nv_encoder->or = ffs(dcbe->or) - 1;
 741
 742         encoder = to_drm_encoder(nv_encoder);
 743         encoder->possible_crtcs = dcbe->heads;
 744         encoder->possible_clones = 0;
 745         drm_encoder_init(dev, encoder, &nvd0_dac_func, DRM_MODE_ENCODER_DAC);
 746         drm_encoder_helper_add(encoder, &nvd0_dac_hfunc);
 747
 748         drm_mode_connector_attach_encoder(connector, encoder);
 749         return 0;
 750 }
 751
 752 /******************************************************************************
 753  * SOR
 754  *****************************************************************************/
 755 static void
 756 nvd0_sor_dpms(struct drm_encoder *encoder, int mode)
 757 {
 758         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 759         struct drm_device *dev = encoder->dev;
 760         struct drm_encoder *partner;
 761         int or = nv_encoder->or;
 762         u32 dpms_ctrl;
 763
 764         nv_encoder->last_dpms = mode;
 765
 766         list_for_each_entry(partner, &dev->mode_config.encoder_list, head) {
 767                 struct nouveau_encoder *nv_partner = nouveau_encoder(partner);
 768
 769                 if (partner->encoder_type != DRM_MODE_ENCODER_TMDS)
 770                         continue;
 771
 772                 if (nv_partner != nv_encoder &&
 773                     nv_partner->dcb->or == nv_encoder->or) {
 774                         if (nv_partner->last_dpms == DRM_MODE_DPMS_ON)
 775                                 return;
 776                         break;
 777                 }
 778         }
 779
 780         dpms_ctrl  = (mode == DRM_MODE_DPMS_ON);
 781         dpms_ctrl |= 0x80000000;
 782
 783         nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
 784         nv_mask(dev, 0x61c004 + (or * 0x0800), 0x80000001, dpms_ctrl);
 785         nv_wait(dev, 0x61c004 + (or * 0x0800), 0x80000000, 0x00000000);
 786         nv_wait(dev, 0x61c030 + (or * 0x0800), 0x10000000, 0x00000000);
 787 }
 788
 789 static bool
 790 nvd0_sor_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
 791                     struct drm_display_mode *adjusted_mode)
 792 {
 793         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 794         struct nouveau_connector *nv_connector;
 795
 796         nv_connector = nouveau_encoder_connector_get(nv_encoder);
 797         if (nv_connector && nv_connector->native_mode) {
 798                 if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) {
 799                         int id = adjusted_mode->base.id;
 800                         *adjusted_mode = *nv_connector->native_mode;
 801                         adjusted_mode->base.id = id;
 802                 }
 803         }
 804
 805         return true;
 806 }
 807
 808 static void
 809 nvd0_sor_prepare(struct drm_encoder *encoder)
 810 {
 811 }
 812
 813 static void
 814 nvd0_sor_commit(struct drm_encoder *encoder)
 815 {
 816 }
 817
 818 static void
 819 nvd0_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 820                   struct drm_display_mode *adjusted_mode)
 821 {
 822         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 823         struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
 824         u32 mode_ctrl = (1 << nv_crtc->index);
 825         u32 *push, or_config;
 826
 827         if (nv_encoder->dcb->sorconf.link & 1) {
 828                 if (adjusted_mode->clock < 165000)
 829                         mode_ctrl |= 0x00000100;
 830                 else
 831                         mode_ctrl |= 0x00000500;
 832         } else {
 833                 mode_ctrl |= 0x00000200;
 834         }
 835
 836         or_config = (mode_ctrl & 0x00000f00) >> 8;
 837         if (adjusted_mode->clock >= 165000)
 838                 or_config |= 0x0100;
 839
 840         nvd0_sor_dpms(encoder, DRM_MODE_DPMS_ON);
 841
 842         push = evo_wait(encoder->dev, 0, 4);
 843         if (push) {
 844                 evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 2);
 845                 evo_data(push, mode_ctrl);
 846                 evo_data(push, or_config);
 847                 evo_kick(push, encoder->dev, 0);
 848         }
 849
 850         nv_encoder->crtc = encoder->crtc;
 851 }
 852
 853 static void
 854 nvd0_sor_disconnect(struct drm_encoder *encoder)
 855 {
 856         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
 857         struct drm_device *dev = encoder->dev;
 858         u32 *push;
 859
 860         if (nv_encoder->crtc) {
 861                 nvd0_crtc_prepare(nv_encoder->crtc);
 862
 863                 push = evo_wait(dev, 0, 4);
 864                 if (push) {
 865                         evo_mthd(push, 0x0200 + (nv_encoder->or * 0x20), 1);
 866                         evo_data(push, 0x00000000);
 867                         evo_mthd(push, 0x0080, 1);
 868                         evo_data(push, 0x00000000);
 869                         evo_kick(push, dev, 0);
 870                 }
 871
 872                 nv_encoder->crtc = NULL;
 873                 nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
 874         }
 875 }
 876
 877 static void
 878 nvd0_sor_destroy(struct drm_encoder *encoder)
 879 {
 880         drm_encoder_cleanup(encoder);
 881         kfree(encoder);
 882 }
 883
 884 static const struct drm_encoder_helper_funcs nvd0_sor_hfunc = {
 885         .dpms = nvd0_sor_dpms,
 886         .mode_fixup = nvd0_sor_mode_fixup,
 887         .prepare = nvd0_sor_prepare,
 888         .commit = nvd0_sor_commit,
 889         .mode_set = nvd0_sor_mode_set,
 890         .disable = nvd0_sor_disconnect,
 891         .get_crtc = nvd0_display_crtc_get,
 892 };
 893
 894 static const struct drm_encoder_funcs nvd0_sor_func = {
 895         .destroy = nvd0_sor_destroy,
 896 };
 897
 898 static int
 899 nvd0_sor_create(struct drm_connector *connector, struct dcb_entry *dcbe)
 900 {
 901         struct drm_device *dev = connector->dev;
 902         struct nouveau_encoder *nv_encoder;
 903         struct drm_encoder *encoder;
 904
 905         nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL);
 906         if (!nv_encoder)
 907                 return -ENOMEM;
 908         nv_encoder->dcb = dcbe;
 909         nv_encoder->or = ffs(dcbe->or) - 1;
 910         nv_encoder->last_dpms = DRM_MODE_DPMS_OFF;
 911
 912         encoder = to_drm_encoder(nv_encoder);
 913         encoder->possible_crtcs = dcbe->heads;
 914         encoder->possible_clones = 0;
 915         drm_encoder_init(dev, encoder, &nvd0_sor_func, DRM_MODE_ENCODER_TMDS);
 916         drm_encoder_helper_add(encoder, &nvd0_sor_hfunc);
 917
 918         drm_mode_connector_attach_encoder(connector, encoder);
 919         return 0;
 920 }
 921
 922 /******************************************************************************
 923  * IRQ
 924  *****************************************************************************/
 925 static struct dcb_entry *
 926 lookup_dcb(struct drm_device *dev, int id, u32 mc)
 927 {
 928         struct drm_nouveau_private *dev_priv = dev->dev_private;
 929         int type, or, i;
 930
 931         if (id < 4) {
 932                 type = OUTPUT_ANALOG;
 933                 or   = id;
 934         } else {
 935                 type = OUTPUT_TMDS;
 936                 or   = id - 4;
 937         }
 938
 939         for (i = 0; i < dev_priv->vbios.dcb.entries; i++) {
 940                 struct dcb_entry *dcb = &dev_priv->vbios.dcb.entry[i];
 941                 if (dcb->type == type && (dcb->or & (1 << or)))
 942                         return dcb;
 943         }
 944
 945         NV_INFO(dev, "PDISP: DCB for %d/0x%08x not found\n", id, mc);
 946         return NULL;
 947 }
 948
 949 static void
 950 nvd0_display_unk1_handler(struct drm_device *dev)
 951 {
 952         struct nvd0_display *disp = nvd0_display(dev);
 953         struct dcb_entry *dcb;
 954         u32 unkn, crtc = 0;
 955         int i;
 956
 957         NV_INFO(dev, "PDISP: 1 0x%08x 0x%08x 0x%08x\n", nv_rd32(dev, 0x6101d0),
 958                 nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
 959
 960         unkn = nv_rd32(dev, 0x6101d4);
 961         if (!unkn) {
 962                 unkn = nv_rd32(dev, 0x6109d4);
 963                 crtc = 1;
 964         }
 965
 966         disp->irq.ena = NULL;
 967         disp->irq.dis = NULL;
 968         disp->irq.crtc = crtc;
 969         disp->irq.pclk = nv_rd32(dev, 0x660450 + (disp->irq.crtc * 0x300));
 970         disp->irq.pclk /= 1000;
 971
 972         for (i = 0; i < 8; i++) {
 973                 u32 mcc = nv_rd32(dev, 0x640180 + (i * 0x20));
 974                 u32 mcp = nv_rd32(dev, 0x660180 + (i * 0x20));
 975
 976                 if (mcc & (1 << crtc))
 977                         disp->irq.dis = lookup_dcb(dev, i, mcc);
 978
 979                 if (mcp & (1 << crtc)) {
 980                         disp->irq.cfg = nv_rd32(dev, 0x660184 + (i * 0x20));
 981                         disp->irq.ena = lookup_dcb(dev, i, mcp);
 982                 }
 983         }
 984
 985         dcb = disp->irq.dis;
 986         if (dcb)
 987                 nouveau_bios_run_display_table(dev, 0x0000, -1, dcb, crtc);
 988
 989         nv_wr32(dev, 0x6101d4, 0x00000000);
 990         nv_wr32(dev, 0x6109d4, 0x00000000);
 991         nv_wr32(dev, 0x6101d0, 0x80000000);
 992 }
 993
 994 static void
 995 nvd0_display_unk2_handler(struct drm_device *dev)
 996 {
 997         struct nvd0_display *disp = nvd0_display(dev);
 998         struct dcb_entry *dcb;
 999         int crtc = disp->irq.crtc;
1000         int pclk = disp->irq.pclk;
1001         int or;
1002         u32 tmp;
1003
1004         NV_INFO(dev, "PDISP: 2 0x%08x 0x%08x 0x%08x\n", nv_rd32(dev, 0x6101d0),
1005                 nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
1006
1007         dcb = disp->irq.dis;
1008         disp->irq.dis = NULL;
1009         if (dcb)
1010                 nouveau_bios_run_display_table(dev, 0x0000, -2, dcb, crtc);
1011
1012         nv50_crtc_set_clock(dev, crtc, pclk);
1013
1014         dcb = disp->irq.ena;
1015         if (!dcb)
1016                 goto ack;
1017         or = ffs(dcb->or) - 1;
1018
1019         nouveau_bios_run_display_table(dev, disp->irq.cfg, pclk, dcb, crtc);
1020
1021         nv_wr32(dev, 0x612200 + (crtc * 0x800), 0x00000000);
1022         switch (dcb->type) {
1023         case OUTPUT_ANALOG:
1024                 nv_wr32(dev, 0x612280 + (or * 0x800), 0x00000000);
1025                 break;
1026         case OUTPUT_TMDS:
1027                 if (disp->irq.pclk >= 165000)
1028                         tmp = 0x00000101;
1029                 else
1030                         tmp = 0x00000000;
1031
1032                 nv_mask(dev, 0x612300 + (or * 0x800), 0x00000707, tmp);
1033                 break;
1034         default:
1035                 break;
1036         }
1037
1038 ack:
1039         nv_wr32(dev, 0x6101d4, 0x00000000);
1040         nv_wr32(dev, 0x6109d4, 0x00000000);
1041         nv_wr32(dev, 0x6101d0, 0x80000000);
1042 }
1043
1044 static void
1045 nvd0_display_unk4_handler(struct drm_device *dev)
1046 {
1047         struct nvd0_display *disp = nvd0_display(dev);
1048         struct dcb_entry *dcb;
1049         int crtc = disp->irq.crtc;
1050         int pclk = disp->irq.pclk;
1051
1052         NV_INFO(dev, "PDISP: 4 0x%08x 0x%08x 0x%08x\n", nv_rd32(dev, 0x6101d0),
1053                 nv_rd32(dev, 0x6101d4), nv_rd32(dev, 0x6109d4));
1054
1055         dcb = disp->irq.ena;
1056         disp->irq.ena = NULL;
1057         if (!dcb)
1058                 goto ack;
1059
1060         nouveau_bios_run_display_table(dev, disp->irq.cfg, pclk, dcb, crtc);
1061
1062 ack:
1063         nv_wr32(dev, 0x6101d4, 0x00000000);
1064         nv_wr32(dev, 0x6109d4, 0x00000000);
1065         nv_wr32(dev, 0x6101d0, 0x80000000);
1066 }
1067
1068 static void
1069 nvd0_display_intr(struct drm_device *dev)
1070 {
1071         u32 intr = nv_rd32(dev, 0x610088);
1072
1073         if (intr & 0x00000002) {
1074                 u32 stat = nv_rd32(dev, 0x61009c);
1075                 int chid = ffs(stat) - 1;
1076                 if (chid >= 0) {
1077                         u32 mthd = nv_rd32(dev, 0x6101f0 + (chid * 12));
1078                         u32 data = nv_rd32(dev, 0x6101f4 + (chid * 12));
1079                         u32 unkn = nv_rd32(dev, 0x6101f8 + (chid * 12));
1080
1081                         NV_INFO(dev, "EvoCh: chid %d mthd 0x%04x data 0x%08x "
1082                                      "0x%08x 0x%08x\n",
1083                                 chid, (mthd & 0x0000ffc), data, mthd, unkn);
1084                         nv_wr32(dev, 0x61009c, (1 << chid));
1085                         nv_wr32(dev, 0x6101f0 + (chid * 12), 0x90000000);
1086                 }
1087
1088                 intr &= ~0x00000002;
1089         }
1090
1091         if (intr & 0x00100000) {
1092                 u32 stat = nv_rd32(dev, 0x6100ac);
1093
1094                 if (stat & 0x00000007) {
1095                         nv_wr32(dev, 0x6100ac, (stat & 0x00000007));
1096
1097                         if (stat & 0x00000001)
1098                                 nvd0_display_unk1_handler(dev);
1099                         if (stat & 0x00000002)
1100                                 nvd0_display_unk2_handler(dev);
1101                         if (stat & 0x00000004)
1102                                 nvd0_display_unk4_handler(dev);
1103                         stat &= ~0x00000007;
1104                 }
1105
1106                 if (stat) {
1107                         NV_INFO(dev, "PDISP: unknown intr24 0x%08x\n", stat);
1108                         nv_wr32(dev, 0x6100ac, stat);
1109                 }
1110
1111                 intr &= ~0x00100000;
1112         }
1113
1114         if (intr & 0x01000000) {
1115                 u32 stat = nv_rd32(dev, 0x6100bc);
1116                 nv_wr32(dev, 0x6100bc, stat);
1117                 intr &= ~0x01000000;
1118         }
1119
1120         if (intr & 0x02000000) {
1121                 u32 stat = nv_rd32(dev, 0x6108bc);
1122                 nv_wr32(dev, 0x6108bc, stat);
1123                 intr &= ~0x02000000;
1124         }
1125
1126         if (intr)
1127                 NV_INFO(dev, "PDISP: unknown intr 0x%08x\n", intr);
1128 }
1129
1130 /******************************************************************************
1131  * Init
1132  *****************************************************************************/
1133 static void
1134 nvd0_display_fini(struct drm_device *dev)
1135 {
1136         int i;
1137
1138         /* fini cursors */
1139         for (i = 14; i >= 13; i--) {
1140                 if (!(nv_rd32(dev, 0x610490 + (i * 0x10)) & 0x00000001))
1141                         continue;
1142
1143                 nv_mask(dev, 0x610490 + (i * 0x10), 0x00000001, 0x00000000);
1144                 nv_wait(dev, 0x610490 + (i * 0x10), 0x00010000, 0x00000000);
1145                 nv_mask(dev, 0x610090, 1 << i, 0x00000000);
1146                 nv_mask(dev, 0x6100a0, 1 << i, 0x00000000);
1147         }
1148
1149         /* fini master */
1150         if (nv_rd32(dev, 0x610490) & 0x00000010) {
1151                 nv_mask(dev, 0x610490, 0x00000010, 0x00000000);
1152                 nv_mask(dev, 0x610490, 0x00000003, 0x00000000);
1153                 nv_wait(dev, 0x610490, 0x80000000, 0x00000000);
1154                 nv_mask(dev, 0x610090, 0x00000001, 0x00000000);
1155                 nv_mask(dev, 0x6100a0, 0x00000001, 0x00000000);
1156         }
1157 }
1158
1159 int
1160 nvd0_display_init(struct drm_device *dev)
1161 {
1162         struct nvd0_display *disp = nvd0_display(dev);
1163         u32 *push;
1164         int i;
1165
1166         if (nv_rd32(dev, 0x6100ac) & 0x00000100) {
1167                 nv_wr32(dev, 0x6100ac, 0x00000100);
1168                 nv_mask(dev, 0x6194e8, 0x00000001, 0x00000000);
1169                 if (!nv_wait(dev, 0x6194e8, 0x00000002, 0x00000000)) {
1170                         NV_ERROR(dev, "PDISP: 0x6194e8 0x%08x\n",
1171                                  nv_rd32(dev, 0x6194e8));
1172                         return -EBUSY;
1173                 }
1174         }
1175
1176         /* nfi what these are exactly, i do know that SOR_MODE_CTRL won't
1177          * work at all unless you do the SOR part below.
1178          */
1179         for (i = 0; i < 3; i++) {
1180                 u32 dac = nv_rd32(dev, 0x61a000 + (i * 0x800));
1181                 nv_wr32(dev, 0x6101c0 + (i * 0x800), dac);
1182         }
1183
1184         for (i = 0; i < 4; i++) {
1185                 u32 sor = nv_rd32(dev, 0x61c000 + (i * 0x800));
1186                 nv_wr32(dev, 0x6301c4 + (i * 0x800), sor);
1187         }
1188
1189         for (i = 0; i < 2; i++) {
1190                 u32 crtc0 = nv_rd32(dev, 0x616104 + (i * 0x800));
1191                 u32 crtc1 = nv_rd32(dev, 0x616108 + (i * 0x800));
1192                 u32 crtc2 = nv_rd32(dev, 0x61610c + (i * 0x800));
1193                 nv_wr32(dev, 0x6101b4 + (i * 0x800), crtc0);
1194                 nv_wr32(dev, 0x6101b8 + (i * 0x800), crtc1);
1195                 nv_wr32(dev, 0x6101bc + (i * 0x800), crtc2);
1196         }
1197
1198         /* point at our hash table / objects, enable interrupts */
1199         nv_wr32(dev, 0x610010, (disp->mem->vinst >> 8) | 9);
1200         nv_mask(dev, 0x6100b0, 0x00000307, 0x00000307);
1201
1202         /* init master */
1203         nv_wr32(dev, 0x610494, (disp->evo[0].handle >> 8) | 3);
1204         nv_wr32(dev, 0x610498, 0x00010000);
1205         nv_wr32(dev, 0x61049c, 0x00000001);
1206         nv_mask(dev, 0x610490, 0x00000010, 0x00000010);
1207         nv_wr32(dev, 0x640000, 0x00000000);
1208         nv_wr32(dev, 0x610490, 0x01000013);
1209         if (!nv_wait(dev, 0x610490, 0x80000000, 0x00000000)) {
1210                 NV_ERROR(dev, "PDISP: master 0x%08x\n",
1211                          nv_rd32(dev, 0x610490));
1212                 return -EBUSY;
1213         }
1214         nv_mask(dev, 0x610090, 0x00000001, 0x00000001);
1215         nv_mask(dev, 0x6100a0, 0x00000001, 0x00000001);
1216
1217         /* init cursors */
1218         for (i = 13; i <= 14; i++) {
1219                 nv_wr32(dev, 0x610490 + (i * 0x10), 0x00000001);
1220                 if (!nv_wait(dev, 0x610490 + (i * 0x10), 0x00010000, 0x00010000)) {
1221                         NV_ERROR(dev, "PDISP: curs%d 0x%08x\n", i,
1222                                  nv_rd32(dev, 0x610490 + (i * 0x10)));
1223                         return -EBUSY;
1224                 }
1225
1226                 nv_mask(dev, 0x610090, 1 << i, 1 << i);
1227                 nv_mask(dev, 0x6100a0, 1 << i, 1 << i);
1228         }
1229
1230         push = evo_wait(dev, 0, 32);
1231         if (!push)
1232                 return -EBUSY;
1233         evo_mthd(push, 0x0088, 1);
1234         evo_data(push, MEM_SYNC);
1235         evo_mthd(push, 0x0084, 1);
1236         evo_data(push, 0x00000000);
1237         evo_mthd(push, 0x0084, 1);
1238         evo_data(push, 0x80000000);
1239         evo_mthd(push, 0x008c, 1);
1240         evo_data(push, 0x00000000);
1241         evo_kick(push, dev, 0);
1242
1243         return 0;
1244 }
1245
1246 void
1247 nvd0_display_destroy(struct drm_device *dev)
1248 {
1249         struct drm_nouveau_private *dev_priv = dev->dev_private;
1250         struct nvd0_display *disp = nvd0_display(dev);
1251         struct pci_dev *pdev = dev->pdev;
1252
1253         nvd0_display_fini(dev);
1254
1255         pci_free_consistent(pdev, PAGE_SIZE, disp->evo[0].ptr, disp->evo[0].handle);
1256         nouveau_gpuobj_ref(NULL, &disp->mem);
1257         nouveau_irq_unregister(dev, 26);
1258
1259         dev_priv->engine.display.priv = NULL;
1260         kfree(disp);
1261 }
1262
1263 int
1264 nvd0_display_create(struct drm_device *dev)
1265 {
1266         struct drm_nouveau_private *dev_priv = dev->dev_private;
1267         struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
1268         struct dcb_table *dcb = &dev_priv->vbios.dcb;
1269         struct drm_connector *connector, *tmp;
1270         struct pci_dev *pdev = dev->pdev;
1271         struct nvd0_display *disp;
1272         struct dcb_entry *dcbe;
1273         int ret, i;
1274
1275         disp = kzalloc(sizeof(*disp), GFP_KERNEL);
1276         if (!disp)
1277                 return -ENOMEM;
1278         dev_priv->engine.display.priv = disp;
1279
1280         /* create crtc objects to represent the hw heads */
1281         for (i = 0; i < 2; i++) {
1282                 ret = nvd0_crtc_create(dev, i);
1283                 if (ret)
1284                         goto out;
1285         }
1286
1287         /* create encoder/connector objects based on VBIOS DCB table */
1288         for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) {
1289                 connector = nouveau_connector_create(dev, dcbe->connector);
1290                 if (IS_ERR(connector))
1291                         continue;
1292
1293                 if (dcbe->location != DCB_LOC_ON_CHIP) {
1294                         NV_WARN(dev, "skipping off-chip encoder %d/%d\n",
1295                                 dcbe->type, ffs(dcbe->or) - 1);
1296                         continue;
1297                 }
1298
1299                 switch (dcbe->type) {
1300                 case OUTPUT_TMDS:
1301                         nvd0_sor_create(connector, dcbe);
1302                         break;
1303                 case OUTPUT_ANALOG:
1304                         nvd0_dac_create(connector, dcbe);
1305                         break;
1306                 default:
1307                         NV_WARN(dev, "skipping unsupported encoder %d/%d\n",
1308                                 dcbe->type, ffs(dcbe->or) - 1);
1309                         continue;
1310                 }
1311         }
1312
1313         /* cull any connectors we created that don't have an encoder */
1314         list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) {
1315                 if (connector->encoder_ids[0])
1316                         continue;
1317
1318                 NV_WARN(dev, "%s has no encoders, removing\n",
1319                         drm_get_connector_name(connector));
1320                 connector->funcs->destroy(connector);
1321         }
1322
1323         /* setup interrupt handling */
1324         nouveau_irq_register(dev, 26, nvd0_display_intr);
1325
1326         /* hash table and dma objects for the memory areas we care about */
1327         ret = nouveau_gpuobj_new(dev, NULL, 0x4000, 0x10000,
1328                                  NVOBJ_FLAG_ZERO_ALLOC, &disp->mem);
1329         if (ret)
1330                 goto out;
1331
1332         nv_wo32(disp->mem, 0x1000, 0x00000049);
1333         nv_wo32(disp->mem, 0x1004, (disp->mem->vinst + 0x2000) >> 8);
1334         nv_wo32(disp->mem, 0x1008, (disp->mem->vinst + 0x2fff) >> 8);
1335         nv_wo32(disp->mem, 0x100c, 0x00000000);
1336         nv_wo32(disp->mem, 0x1010, 0x00000000);
1337         nv_wo32(disp->mem, 0x1014, 0x00000000);
1338         nv_wo32(disp->mem, 0x0000, MEM_SYNC);
1339         nv_wo32(disp->mem, 0x0004, (0x1000 << 9) | 0x00000001);
1340
1341         nv_wo32(disp->mem, 0x1020, 0x00000049);
1342         nv_wo32(disp->mem, 0x1024, 0x00000000);
1343         nv_wo32(disp->mem, 0x1028, (dev_priv->vram_size - 1) >> 8);
1344         nv_wo32(disp->mem, 0x102c, 0x00000000);
1345         nv_wo32(disp->mem, 0x1030, 0x00000000);
1346         nv_wo32(disp->mem, 0x1034, 0x00000000);
1347         nv_wo32(disp->mem, 0x0008, MEM_VRAM);
1348         nv_wo32(disp->mem, 0x000c, (0x1020 << 9) | 0x00000001);
1349
1350         nv_wo32(disp->mem, 0x1040, 0x00000009);
1351         nv_wo32(disp->mem, 0x1044, 0x00000000);
1352         nv_wo32(disp->mem, 0x1048, (dev_priv->vram_size - 1) >> 8);
1353         nv_wo32(disp->mem, 0x104c, 0x00000000);
1354         nv_wo32(disp->mem, 0x1050, 0x00000000);
1355         nv_wo32(disp->mem, 0x1054, 0x00000000);
1356         nv_wo32(disp->mem, 0x0010, NvEvoVRAM_LP);
1357         nv_wo32(disp->mem, 0x0014, (0x1040 << 9) | 0x00000001);
1358
1359         nv_wo32(disp->mem, 0x1060, 0x0fe00009);
1360         nv_wo32(disp->mem, 0x1064, 0x00000000);
1361         nv_wo32(disp->mem, 0x1068, (dev_priv->vram_size - 1) >> 8);
1362         nv_wo32(disp->mem, 0x106c, 0x00000000);
1363         nv_wo32(disp->mem, 0x1070, 0x00000000);
1364         nv_wo32(disp->mem, 0x1074, 0x00000000);
1365         nv_wo32(disp->mem, 0x0018, NvEvoFB32);
1366         nv_wo32(disp->mem, 0x001c, (0x1060 << 9) | 0x00000001);
1367
1368         pinstmem->flush(dev);
1369
1370         /* push buffers for evo channels */
1371         disp->evo[0].ptr =
1372                 pci_alloc_consistent(pdev, PAGE_SIZE, &disp->evo[0].handle);
1373         if (!disp->evo[0].ptr) {
1374                 ret = -ENOMEM;
1375                 goto out;
1376         }
1377
1378         ret = nvd0_display_init(dev);
1379         if (ret)
1380                 goto out;
1381
1382 out:
1383         if (ret)
1384                 nvd0_display_destroy(dev);
1385         return ret;
1386 }