1 #ifndef __NVIF_CLASS_H__
2 #define __NVIF_CLASS_H__
4 /*******************************************************************************
6 ******************************************************************************/
8 /* the below match nvidia-assigned (either in hw, or sw) class numbers */
9 #define NV_DEVICE 0x00000080
11 #define NV_DMA_FROM_MEMORY 0x00000002
12 #define NV_DMA_TO_MEMORY 0x00000003
13 #define NV_DMA_IN_MEMORY 0x0000003d
15 #define NV04_DISP 0x00000046
17 #define NV03_CHANNEL_DMA 0x0000006b
18 #define NV10_CHANNEL_DMA 0x0000006e
19 #define NV17_CHANNEL_DMA 0x0000176e
20 #define NV40_CHANNEL_DMA 0x0000406e
21 #define NV50_CHANNEL_DMA 0x0000506e
22 #define G82_CHANNEL_DMA 0x0000826e
24 #define NV50_CHANNEL_GPFIFO 0x0000506f
25 #define G82_CHANNEL_GPFIFO 0x0000826f
26 #define FERMI_CHANNEL_GPFIFO 0x0000906f
27 #define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f
29 #define NV50_DISP 0x00005070
30 #define G82_DISP 0x00008270
31 #define GT200_DISP 0x00008370
32 #define GT214_DISP 0x00008570
33 #define GT206_DISP 0x00008870
34 #define GF110_DISP 0x00009070
35 #define GK104_DISP 0x00009170
36 #define GK110_DISP 0x00009270
37 #define GM107_DISP 0x00009470
39 #define NV50_DISP_CURSOR 0x0000507a
40 #define G82_DISP_CURSOR 0x0000827a
41 #define GT214_DISP_CURSOR 0x0000857a
42 #define GF110_DISP_CURSOR 0x0000907a
43 #define GK104_DISP_CURSOR 0x0000917a
45 #define NV50_DISP_OVERLAY 0x0000507b
46 #define G82_DISP_OVERLAY 0x0000827b
47 #define GT214_DISP_OVERLAY 0x0000857b
48 #define GF110_DISP_OVERLAY 0x0000907b
49 #define GK104_DISP_OVERLAY 0x0000917b
51 #define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c
52 #define G82_DISP_BASE_CHANNEL_DMA 0x0000827c
53 #define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c
54 #define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c
55 #define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c
56 #define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c
57 #define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c
59 #define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d
60 #define G82_DISP_CORE_CHANNEL_DMA 0x0000827d
61 #define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d
62 #define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d
63 #define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d
64 #define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d
65 #define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d
66 #define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d
67 #define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d
69 #define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e
70 #define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e
71 #define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e
72 #define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e
73 #define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e
74 #define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e
76 #define FERMI_A 0x00009097
77 #define FERMI_B 0x00009197
78 #define FERMI_C 0x00009297
80 #define KEPLER_A 0x0000a097
81 #define KEPLER_B 0x0000a197
82 #define KEPLER_C 0x0000a297
84 #define MAXWELL_A 0x0000b097
86 #define FERMI_COMPUTE_A 0x000090c0
87 #define FERMI_COMPUTE_B 0x000091c0
89 #define KEPLER_COMPUTE_A 0x0000a0c0
90 #define KEPLER_COMPUTE_B 0x0000a1c0
92 #define MAXWELL_COMPUTE_A 0x0000b0c0
95 /*******************************************************************************
97 ******************************************************************************/
99 #define NV_CLIENT_DEVLIST 0x00
101 struct nv_client_devlist_v0 {
109 /*******************************************************************************
111 ******************************************************************************/
113 struct nv_device_v0 {
116 __u64 device; /* device identifier, ~0 for client default */
117 #define NV_DEVICE_V0_DISABLE_IDENTIFY 0x0000000000000001ULL
118 #define NV_DEVICE_V0_DISABLE_MMIO 0x0000000000000002ULL
119 #define NV_DEVICE_V0_DISABLE_VBIOS 0x0000000000000004ULL
120 #define NV_DEVICE_V0_DISABLE_CORE 0x0000000000000008ULL
121 #define NV_DEVICE_V0_DISABLE_DISP 0x0000000000010000ULL
122 #define NV_DEVICE_V0_DISABLE_FIFO 0x0000000000020000ULL
123 #define NV_DEVICE_V0_DISABLE_GRAPH 0x0000000100000000ULL
124 #define NV_DEVICE_V0_DISABLE_MPEG 0x0000000200000000ULL
125 #define NV_DEVICE_V0_DISABLE_ME 0x0000000400000000ULL
126 #define NV_DEVICE_V0_DISABLE_VP 0x0000000800000000ULL
127 #define NV_DEVICE_V0_DISABLE_CRYPT 0x0000001000000000ULL
128 #define NV_DEVICE_V0_DISABLE_BSP 0x0000002000000000ULL
129 #define NV_DEVICE_V0_DISABLE_PPP 0x0000004000000000ULL
130 #define NV_DEVICE_V0_DISABLE_COPY0 0x0000008000000000ULL
131 #define NV_DEVICE_V0_DISABLE_COPY1 0x0000010000000000ULL
132 #define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
133 #define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL
134 __u64 disable; /* disable particular subsystems */
135 __u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */
138 #define NV_DEVICE_V0_INFO 0x00
140 struct nv_device_info_v0 {
142 #define NV_DEVICE_INFO_V0_IGP 0x00
143 #define NV_DEVICE_INFO_V0_PCI 0x01
144 #define NV_DEVICE_INFO_V0_AGP 0x02
145 #define NV_DEVICE_INFO_V0_PCIE 0x03
146 #define NV_DEVICE_INFO_V0_SOC 0x04
148 __u16 chipset; /* from NV_PMC_BOOT_0 */
149 __u8 revision; /* from NV_PMC_BOOT_0 */
150 #define NV_DEVICE_INFO_V0_TNT 0x01
151 #define NV_DEVICE_INFO_V0_CELSIUS 0x02
152 #define NV_DEVICE_INFO_V0_KELVIN 0x03
153 #define NV_DEVICE_INFO_V0_RANKINE 0x04
154 #define NV_DEVICE_INFO_V0_CURIE 0x05
155 #define NV_DEVICE_INFO_V0_TESLA 0x06
156 #define NV_DEVICE_INFO_V0_FERMI 0x07
157 #define NV_DEVICE_INFO_V0_KEPLER 0x08
158 #define NV_DEVICE_INFO_V0_MAXWELL 0x09
166 /*******************************************************************************
168 ******************************************************************************/
172 #define NV_DMA_V0_TARGET_VM 0x00
173 #define NV_DMA_V0_TARGET_VRAM 0x01
174 #define NV_DMA_V0_TARGET_PCI 0x02
175 #define NV_DMA_V0_TARGET_PCI_US 0x03
176 #define NV_DMA_V0_TARGET_AGP 0x04
178 #define NV_DMA_V0_ACCESS_VM 0x00
179 #define NV_DMA_V0_ACCESS_RD 0x01
180 #define NV_DMA_V0_ACCESS_WR 0x02
181 #define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
186 /* ... chipset-specific class data */
191 #define NV50_DMA_V0_PRIV_VM 0x00
192 #define NV50_DMA_V0_PRIV_US 0x01
193 #define NV50_DMA_V0_PRIV__S 0x02
195 #define NV50_DMA_V0_PART_VM 0x00
196 #define NV50_DMA_V0_PART_256 0x01
197 #define NV50_DMA_V0_PART_1KB 0x02
199 #define NV50_DMA_V0_COMP_NONE 0x00
200 #define NV50_DMA_V0_COMP_1 0x01
201 #define NV50_DMA_V0_COMP_2 0x02
202 #define NV50_DMA_V0_COMP_VM 0x03
204 #define NV50_DMA_V0_KIND_PITCH 0x00
205 #define NV50_DMA_V0_KIND_VM 0x7f
210 struct gf100_dma_v0 {
212 #define GF100_DMA_V0_PRIV_VM 0x00
213 #define GF100_DMA_V0_PRIV_US 0x01
214 #define GF100_DMA_V0_PRIV__S 0x02
216 #define GF100_DMA_V0_KIND_PITCH 0x00
217 #define GF100_DMA_V0_KIND_VM 0xff
222 struct gf110_dma_v0 {
224 #define GF110_DMA_V0_PAGE_LP 0x00
225 #define GF110_DMA_V0_PAGE_SP 0x01
227 #define GF110_DMA_V0_KIND_PITCH 0x00
228 #define GF110_DMA_V0_KIND_VM 0xff
234 /*******************************************************************************
236 ******************************************************************************/
238 struct nvif_perfctr_v0 {
246 #define NVIF_PERFCTR_V0_QUERY 0x00
247 #define NVIF_PERFCTR_V0_SAMPLE 0x01
248 #define NVIF_PERFCTR_V0_READ 0x02
250 struct nvif_perfctr_query_v0 {
257 struct nvif_perfctr_sample {
260 struct nvif_perfctr_read_v0 {
268 /*******************************************************************************
270 ******************************************************************************/
272 #define NVIF_CONTROL_PSTATE_INFO 0x00
273 #define NVIF_CONTROL_PSTATE_ATTR 0x01
274 #define NVIF_CONTROL_PSTATE_USER 0x02
276 struct nvif_control_pstate_info_v0 {
278 __u8 count; /* out: number of power states */
279 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1)
280 #define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2)
281 __s8 ustate_ac; /* out: target pstate index */
282 __s8 ustate_dc; /* out: target pstate index */
283 __s8 pwrsrc; /* out: current power source */
284 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1)
285 #define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2)
286 __s8 pstate; /* out: current pstate index */
290 struct nvif_control_pstate_attr_v0 {
292 #define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1)
293 __s8 state; /* in: index of pstate to query
294 * out: pstate identifier
296 __u8 index; /* in: index of attribute to query
297 * out: index of next attribute, or 0 if no more
306 struct nvif_control_pstate_user_v0 {
308 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1)
309 #define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2)
310 __s8 ustate; /* in: pstate identifier */
311 __s8 pwrsrc; /* in: target power source */
316 /*******************************************************************************
318 ******************************************************************************/
320 struct nv03_channel_dma_v0 {
328 #define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
330 /*******************************************************************************
332 ******************************************************************************/
334 struct nv50_channel_gpfifo_v0 {
343 struct kepler_channel_gpfifo_a_v0 {
345 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
346 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02
347 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP 0x04
348 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_BSP 0x08
349 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
350 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20
351 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40
360 /*******************************************************************************
362 ******************************************************************************/
364 #define NV04_DISP_NTFY_VBLANK 0x00
365 #define NV04_DISP_NTFY_CONN 0x01
367 struct nv04_disp_mthd_v0 {
369 #define NV04_DISP_SCANOUTPOS 0x00
375 struct nv04_disp_scanoutpos_v0 {
389 /*******************************************************************************
391 ******************************************************************************/
393 #define NV50_DISP_MTHD 0x00
395 struct nv50_disp_mthd_v0 {
397 #define NV50_DISP_SCANOUTPOS 0x00
403 struct nv50_disp_mthd_v1 {
405 #define NV50_DISP_MTHD_V1_DAC_PWR 0x10
406 #define NV50_DISP_MTHD_V1_DAC_LOAD 0x11
407 #define NV50_DISP_MTHD_V1_SOR_PWR 0x20
408 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21
409 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22
410 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23
411 #define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24
412 #define NV50_DISP_MTHD_V1_PIOR_PWR 0x30
419 struct nv50_disp_dac_pwr_v0 {
428 struct nv50_disp_dac_load_v0 {
435 struct nv50_disp_sor_pwr_v0 {
441 struct nv50_disp_sor_hda_eld_v0 {
447 struct nv50_disp_sor_hdmi_pwr_v0 {
455 struct nv50_disp_sor_lvds_script_v0 {
462 struct nv50_disp_sor_dp_pwr_v0 {
468 struct nv50_disp_pior_pwr_v0 {
476 struct nv50_disp_core_channel_dma_v0 {
482 #define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
484 /* cursor immediate */
485 struct nv50_disp_cursor_v0 {
491 #define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00
494 struct nv50_disp_base_channel_dma_v0 {
501 #define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
504 struct nv50_disp_overlay_channel_dma_v0 {
511 #define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
513 /* overlay immediate */
514 struct nv50_disp_overlay_v0 {
520 #define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00
522 /*******************************************************************************
524 ******************************************************************************/
526 #define FERMI_A_ZBC_COLOR 0x00
527 #define FERMI_A_ZBC_DEPTH 0x01
529 struct fermi_a_zbc_color_v0 {
531 #define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01
532 #define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02
533 #define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04
534 #define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08
535 #define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c
536 #define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10
537 #define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14
538 #define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16
539 #define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18
540 #define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c
541 #define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20
542 #define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24
543 #define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28
544 #define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c
545 #define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30
546 #define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34
547 #define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38
548 #define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c
549 #define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40
557 struct fermi_a_zbc_depth_v0 {
559 #define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01