drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "priv.h"
  25
  26 int
  27 gm100_identify(struct nvkm_device *device)
  28 {
  29         switch (device->chipset) {
  30         case 0x117:
  31                 device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
  32                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
  33                 device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
  34                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
  35                 device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;
  36                 device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;
  37
  38 #if 0
  39                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
  40 #endif
  41                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
  42                 device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;
  43                 device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
  44                 device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;
  45                 device->oclass[NVDEV_ENGINE_DISP   ] =  gm107_disp_oclass;
  46                 device->oclass[NVDEV_ENGINE_CE0    ] = &gk104_ce0_oclass;
  47 #if 0
  48                 device->oclass[NVDEV_ENGINE_CE1    ] = &gk104_ce1_oclass;
  49 #endif
  50                 device->oclass[NVDEV_ENGINE_CE2    ] = &gk104_ce2_oclass;
  51 #if 0
  52                 device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;
  53                 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
  54                 device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
  55 #endif
  56                 break;
  57         case 0x124:
  58 #if 0
  59                 /* looks to be some non-trivial changes */
  60                 /* priv ring says no to 0x10eb14 writes */
  61                 device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
  62 #endif
  63                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
  64                 device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
  65                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
  66                 device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;
  67                 device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;
  68 #if 0
  69                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
  70 #endif
  71                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
  72                 device->oclass[NVDEV_ENGINE_FIFO   ] =  gm204_fifo_oclass;
  73                 device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
  74                 device->oclass[NVDEV_ENGINE_GR     ] =  gm204_gr_oclass;
  75                 device->oclass[NVDEV_ENGINE_DISP   ] =  gm204_disp_oclass;
  76                 device->oclass[NVDEV_ENGINE_CE0    ] = &gm204_ce0_oclass;
  77                 device->oclass[NVDEV_ENGINE_CE1    ] = &gm204_ce1_oclass;
  78                 device->oclass[NVDEV_ENGINE_CE2    ] = &gm204_ce2_oclass;
  79 #if 0
  80                 device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;
  81                 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
  82                 device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
  83 #endif
  84                 break;
  85         case 0x126:
  86 #if 0
  87                 /* looks to be some non-trivial changes */
  88                 /* priv ring says no to 0x10eb14 writes */
  89                 device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;
  90 #endif
  91                 device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;
  92                 device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
  93                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
  94                 device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;
  95                 device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;
  96 #if 0
  97                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
  98 #endif
  99                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 100                 device->oclass[NVDEV_ENGINE_FIFO   ] =  gm204_fifo_oclass;
 101                 device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 102                 device->oclass[NVDEV_ENGINE_GR     ] =  gm206_gr_oclass;
 103                 device->oclass[NVDEV_ENGINE_DISP   ] =  gm204_disp_oclass;
 104                 device->oclass[NVDEV_ENGINE_CE0    ] = &gm204_ce0_oclass;
 105                 device->oclass[NVDEV_ENGINE_CE1    ] = &gm204_ce1_oclass;
 106                 device->oclass[NVDEV_ENGINE_CE2    ] = &gm204_ce2_oclass;
 107 #if 0
 108                 device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;
 109                 device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;
 110                 device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;
 111 #endif
 112                 break;
 113         case 0x12b:
 114
 115                 device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;
 116                 device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;
 117                 device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;
 118                 device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;
 119                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
 120                 device->oclass[NVDEV_ENGINE_FIFO   ] =  gm20b_fifo_oclass;
 121                 device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;
 122                 device->oclass[NVDEV_ENGINE_GR     ] =  gm20b_gr_oclass;
 123                 device->oclass[NVDEV_ENGINE_CE2    ] = &gm204_ce2_oclass;
 124                 break;
 125         default:
 126                 return -EINVAL;
 127         }
 128
 129         return 0;
 130 }