drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "priv.h"
  25
  26 int
  27 nv10_identify(struct nvkm_device *device)
  28 {
  29         switch (device->chipset) {
  30         case 0x10:
  31                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
  32                 device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
  33                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  34                 break;
  35         case 0x15:
  36                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
  37                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
  38                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  39                 device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
  40                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  41                 break;
  42         case 0x16:
  43                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
  44                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
  45                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  46                 device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
  47                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  48                 break;
  49         case 0x1a:
  50                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
  51                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
  52                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  53                 device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
  54                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  55                 break;
  56         case 0x11:
  57                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
  58                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv10_fifo_oclass;
  59                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  60                 device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
  61                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  62                 break;
  63         case 0x17:
  64                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
  65                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
  66                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  67                 device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
  68                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  69                 break;
  70         case 0x1f:
  71                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
  72                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
  73                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  74                 device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
  75                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  76                 break;
  77         case 0x18:
  78                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv04_dmaeng_oclass;
  79                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv17_fifo_oclass;
  80                 device->oclass[NVDEV_ENGINE_SW     ] =  nv10_sw_oclass;
  81                 device->oclass[NVDEV_ENGINE_GR     ] = &nv10_gr_oclass;
  82                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv04_disp_oclass;
  83                 break;
  84         default:
  85                 return -EINVAL;
  86         }
  87
  88         return 0;
  89 }