drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "priv.h"
  25
  26 int
  27 nv50_identify(struct nvkm_device *device)
  28 {
  29         switch (device->chipset) {
  30         case 0x50:
  31                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
  32                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
  33                 device->oclass[NVDEV_ENGINE_FIFO   ] =  nv50_fifo_oclass;
  34                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
  35                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
  36                 device->oclass[NVDEV_ENGINE_MPEG   ] = &nv50_mpeg_oclass;
  37                 device->oclass[NVDEV_ENGINE_DISP   ] =  nv50_disp_oclass;
  38                 device->oclass[NVDEV_ENGINE_PM     ] =  nv50_pm_oclass;
  39                 break;
  40         case 0x84:
  41                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
  42                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
  43                 device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
  44                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
  45                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
  46                 device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
  47                 device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
  48                 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
  49                 device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
  50                 device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
  51                 device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
  52                 break;
  53         case 0x86:
  54                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
  55                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
  56                 device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
  57                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
  58                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
  59                 device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
  60                 device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
  61                 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
  62                 device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
  63                 device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
  64                 device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
  65                 break;
  66         case 0x92:
  67                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
  68                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
  69                 device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
  70                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
  71                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
  72                 device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
  73                 device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
  74                 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
  75                 device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
  76                 device->oclass[NVDEV_ENGINE_DISP   ] =  g84_disp_oclass;
  77                 device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
  78                 break;
  79         case 0x94:
  80                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
  81                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
  82                 device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
  83                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
  84                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
  85                 device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
  86                 device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
  87                 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
  88                 device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
  89                 device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
  90                 device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
  91                 break;
  92         case 0x96:
  93                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
  94                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
  95                 device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
  96                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
  97                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
  98                 device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
  99                 device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
 100                 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
 101                 device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
 102                 device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
 103                 device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
 104                 break;
 105         case 0x98:
 106                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 107                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 108                 device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
 109                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
 110                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 111                 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 112                 device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;
 113                 device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
 114                 device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 115                 device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
 116                 device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
 117                 break;
 118         case 0xa0:
 119                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 120                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 121                 device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
 122                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
 123                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 124                 device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
 125                 device->oclass[NVDEV_ENGINE_VP     ] = &g84_vp_oclass;
 126                 device->oclass[NVDEV_ENGINE_CIPHER ] = &g84_cipher_oclass;
 127                 device->oclass[NVDEV_ENGINE_BSP    ] = &g84_bsp_oclass;
 128                 device->oclass[NVDEV_ENGINE_DISP   ] =  gt200_disp_oclass;
 129                 device->oclass[NVDEV_ENGINE_PM     ] =  gt200_pm_oclass;
 130                 break;
 131         case 0xaa:
 132                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 133                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 134                 device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
 135                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
 136                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 137                 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 138                 device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;
 139                 device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
 140                 device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 141                 device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
 142                 device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
 143                 break;
 144         case 0xac:
 145                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 146                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 147                 device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
 148                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
 149                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 150                 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 151                 device->oclass[NVDEV_ENGINE_SEC    ] = &g98_sec_oclass;
 152                 device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
 153                 device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 154                 device->oclass[NVDEV_ENGINE_DISP   ] =  g94_disp_oclass;
 155                 device->oclass[NVDEV_ENGINE_PM     ] =  g84_pm_oclass;
 156                 break;
 157         case 0xa3:
 158                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 159                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 160                 device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
 161                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
 162                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 163                 device->oclass[NVDEV_ENGINE_MPEG   ] = &g84_mpeg_oclass;
 164                 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 165                 device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
 166                 device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 167                 device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
 168                 device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 169                 device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
 170                 break;
 171         case 0xa5:
 172                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 173                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 174                 device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
 175                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
 176                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 177                 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 178                 device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
 179                 device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 180                 device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
 181                 device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 182                 device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
 183                 break;
 184         case 0xa8:
 185                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 186                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 187                 device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
 188                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
 189                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 190                 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 191                 device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
 192                 device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 193                 device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
 194                 device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 195                 device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
 196                 break;
 197         case 0xaf:
 198                 device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;
 199                 device->oclass[NVDEV_ENGINE_DMAOBJ ] =  nv50_dmaeng_oclass;
 200                 device->oclass[NVDEV_ENGINE_FIFO   ] =  g84_fifo_oclass;
 201                 device->oclass[NVDEV_ENGINE_SW     ] =  nv50_sw_oclass;
 202                 device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
 203                 device->oclass[NVDEV_ENGINE_MSPDEC ] = &g98_mspdec_oclass;
 204                 device->oclass[NVDEV_ENGINE_MSVLD  ] = &g98_msvld_oclass;
 205                 device->oclass[NVDEV_ENGINE_MSPPP  ] = &g98_msppp_oclass;
 206                 device->oclass[NVDEV_ENGINE_CE0    ] = &gt215_ce_oclass;
 207                 device->oclass[NVDEV_ENGINE_DISP   ] =  gt215_disp_oclass;
 208                 device->oclass[NVDEV_ENGINE_PM     ] =  gt215_pm_oclass;
 209                 break;
 210         default:
 211                 return -EINVAL;
 212         }
 213
 214         return 0;
 215 }