2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #include <nvif/class.h>
28 /*******************************************************************************
29 * EVO master channel object
30 ******************************************************************************/
32 static const struct nv50_disp_mthd_list
33 gk104_disp_core_mthd_head = {
100 { 0x052c, 0x66052c },
101 { 0x0530, 0x660530 },
102 { 0x054c, 0x66054c },
103 { 0x0550, 0x660550 },
104 { 0x0554, 0x660554 },
105 { 0x0558, 0x660558 },
106 { 0x055c, 0x66055c },
111 const struct nv50_disp_mthd_chan
112 gk104_disp_core_mthd_chan = {
116 { "Global", 1, &gf110_disp_core_mthd_base },
117 { "DAC", 3, &gf110_disp_core_mthd_dac },
118 { "SOR", 8, &gf110_disp_core_mthd_sor },
119 { "PIOR", 4, &gf110_disp_core_mthd_pior },
120 { "HEAD", 4, &gk104_disp_core_mthd_head },
125 /*******************************************************************************
126 * EVO overlay channel objects
127 ******************************************************************************/
129 static const struct nv50_disp_mthd_list
130 gk104_disp_ovly_mthd_base = {
133 { 0x0080, 0x665080 },
134 { 0x0084, 0x665084 },
135 { 0x0088, 0x665088 },
136 { 0x008c, 0x66508c },
137 { 0x0090, 0x665090 },
138 { 0x0094, 0x665094 },
139 { 0x00a0, 0x6650a0 },
140 { 0x00a4, 0x6650a4 },
141 { 0x00b0, 0x6650b0 },
142 { 0x00b4, 0x6650b4 },
143 { 0x00b8, 0x6650b8 },
144 { 0x00c0, 0x6650c0 },
145 { 0x00c4, 0x6650c4 },
146 { 0x00e0, 0x6650e0 },
147 { 0x00e4, 0x6650e4 },
148 { 0x00e8, 0x6650e8 },
149 { 0x0100, 0x665100 },
150 { 0x0104, 0x665104 },
151 { 0x0108, 0x665108 },
152 { 0x010c, 0x66510c },
153 { 0x0110, 0x665110 },
154 { 0x0118, 0x665118 },
155 { 0x011c, 0x66511c },
156 { 0x0120, 0x665120 },
157 { 0x0124, 0x665124 },
158 { 0x0130, 0x665130 },
159 { 0x0134, 0x665134 },
160 { 0x0138, 0x665138 },
161 { 0x013c, 0x66513c },
162 { 0x0140, 0x665140 },
163 { 0x0144, 0x665144 },
164 { 0x0148, 0x665148 },
165 { 0x014c, 0x66514c },
166 { 0x0150, 0x665150 },
167 { 0x0154, 0x665154 },
168 { 0x0158, 0x665158 },
169 { 0x015c, 0x66515c },
170 { 0x0160, 0x665160 },
171 { 0x0164, 0x665164 },
172 { 0x0168, 0x665168 },
173 { 0x016c, 0x66516c },
174 { 0x0400, 0x665400 },
175 { 0x0404, 0x665404 },
176 { 0x0408, 0x665408 },
177 { 0x040c, 0x66540c },
178 { 0x0410, 0x665410 },
183 const struct nv50_disp_mthd_chan
184 gk104_disp_ovly_mthd_chan = {
188 { "Global", 1, &gk104_disp_ovly_mthd_base },
193 /*******************************************************************************
194 * Base display object
195 ******************************************************************************/
197 static struct nvkm_oclass
198 gk104_disp_sclass[] = {
199 { GK104_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
200 { GK104_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
201 { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
202 { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
203 { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
207 static struct nvkm_oclass
208 gk104_disp_main_oclass[] = {
209 { GK104_DISP, &gf110_disp_main_ofuncs },
213 /*******************************************************************************
214 * Display engine implementation
215 ******************************************************************************/
218 gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
219 struct nvkm_oclass *oclass, void *data, u32 size,
220 struct nvkm_object **pobject)
222 struct nvkm_device *device = (void *)parent;
223 struct nv50_disp *disp;
224 int heads = nvkm_rd32(device, 0x022448);
227 ret = nvkm_disp_create(parent, engine, oclass, heads,
228 "PDISP", "display", &disp);
229 *pobject = nv_object(disp);
233 ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &disp->uevent);
237 nv_engine(disp)->sclass = gk104_disp_main_oclass;
238 nv_engine(disp)->cclass = &nv50_disp_cclass;
239 nv_subdev(disp)->intr = gf110_disp_intr;
240 INIT_WORK(&disp->supervisor, gf110_disp_intr_supervisor);
241 disp->sclass = gk104_disp_sclass;
242 disp->head.nr = heads;
245 disp->dac.power = nv50_dac_power;
246 disp->dac.sense = nv50_dac_sense;
247 disp->sor.power = nv50_sor_power;
248 disp->sor.hda_eld = gf110_hda_eld;
249 disp->sor.hdmi = gk104_hdmi_ctrl;
254 gk104_disp_oclass = &(struct nv50_disp_impl) {
255 .base.base.handle = NV_ENGINE(DISP, 0x91),
256 .base.base.ofuncs = &(struct nvkm_ofuncs) {
257 .ctor = gk104_disp_ctor,
258 .dtor = _nvkm_disp_dtor,
259 .init = _nvkm_disp_init,
260 .fini = _nvkm_disp_fini,
262 .base.vblank = &gf110_disp_vblank_func,
263 .base.outp = gf110_disp_outp_sclass,
264 .mthd.core = &gk104_disp_core_mthd_chan,
265 .mthd.base = &gf110_disp_base_mthd_chan,
266 .mthd.ovly = &gk104_disp_ovly_mthd_chan,
267 .mthd.prev = -0x020000,
268 .head.scanoutpos = gf110_disp_main_scanoutpos,