drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv50.h"
  25 #include "nv04.h"
  26
  27 #include <core/client.h>
  28 #include <core/engctx.h>
  29 #include <core/ramht.h>
  30 #include <subdev/bar.h>
  31 #include <subdev/mmu.h>
  32 #include <subdev/timer.h>
  33
  34 #include <nvif/class.h>
  35 #include <nvif/unpack.h>
  36
  37 /*******************************************************************************
  38  * FIFO channel objects
  39  ******************************************************************************/
  40
  41 static int
  42 g84_fifo_context_attach(struct nvkm_object *parent, struct nvkm_object *object)
  43 {
  44         struct nvkm_bar *bar = nvkm_bar(parent);
  45         struct nv50_fifo_base *base = (void *)parent->parent;
  46         struct nvkm_gpuobj *ectx = (void *)object;
  47         u64 limit = ectx->addr + ectx->size - 1;
  48         u64 start = ectx->addr;
  49         u32 addr;
  50
  51         switch (nv_engidx(object->engine)) {
  52         case NVDEV_ENGINE_SW    : return 0;
  53         case NVDEV_ENGINE_GR    : addr = 0x0020; break;
  54         case NVDEV_ENGINE_VP    :
  55         case NVDEV_ENGINE_MSPDEC: addr = 0x0040; break;
  56         case NVDEV_ENGINE_MSPPP :
  57         case NVDEV_ENGINE_MPEG  : addr = 0x0060; break;
  58         case NVDEV_ENGINE_BSP   :
  59         case NVDEV_ENGINE_MSVLD : addr = 0x0080; break;
  60         case NVDEV_ENGINE_CIPHER:
  61         case NVDEV_ENGINE_SEC   : addr = 0x00a0; break;
  62         case NVDEV_ENGINE_CE0   : addr = 0x00c0; break;
  63         default:
  64                 return -EINVAL;
  65         }
  66
  67         nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
  68         nv_wo32(base->eng, addr + 0x00, 0x00190000);
  69         nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));
  70         nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));
  71         nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |
  72                                         upper_32_bits(start));
  73         nv_wo32(base->eng, addr + 0x10, 0x00000000);
  74         nv_wo32(base->eng, addr + 0x14, 0x00000000);
  75         bar->flush(bar);
  76         return 0;
  77 }
  78
  79 static int
  80 g84_fifo_context_detach(struct nvkm_object *parent, bool suspend,
  81                         struct nvkm_object *object)
  82 {
  83         struct nv50_fifo *fifo = (void *)parent->engine;
  84         struct nv50_fifo_base *base = (void *)parent->parent;
  85         struct nv50_fifo_chan *chan = (void *)parent;
  86         struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
  87         struct nvkm_device *device = subdev->device;
  88         struct nvkm_bar *bar = device->bar;
  89         u32 addr, save, engn;
  90         bool done;
  91
  92         switch (nv_engidx(object->engine)) {
  93         case NVDEV_ENGINE_SW    : return 0;
  94         case NVDEV_ENGINE_GR    : engn = 0; addr = 0x0020; break;
  95         case NVDEV_ENGINE_VP    :
  96         case NVDEV_ENGINE_MSPDEC: engn = 3; addr = 0x0040; break;
  97         case NVDEV_ENGINE_MSPPP :
  98         case NVDEV_ENGINE_MPEG  : engn = 1; addr = 0x0060; break;
  99         case NVDEV_ENGINE_BSP   :
 100         case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break;
 101         case NVDEV_ENGINE_CIPHER:
 102         case NVDEV_ENGINE_SEC   : engn = 4; addr = 0x00a0; break;
 103         case NVDEV_ENGINE_CE0   : engn = 2; addr = 0x00c0; break;
 104         default:
 105                 return -EINVAL;
 106         }
 107
 108         save = nvkm_mask(device, 0x002520, 0x0000003f, 1 << engn);
 109         nvkm_wr32(device, 0x0032fc, nv_gpuobj(base)->addr >> 12);
 110         done = nvkm_msec(device, 2000,
 111                 if (nvkm_rd32(device, 0x0032fc) != 0xffffffff)
 112                         break;
 113         ) >= 0;
 114         nvkm_wr32(device, 0x002520, save);
 115         if (!done) {
 116                 nvkm_error(subdev, "channel %d [%s] unload timeout\n",
 117                            chan->base.chid, nvkm_client_name(chan));
 118                 if (suspend)
 119                         return -EBUSY;
 120         }
 121
 122         nv_wo32(base->eng, addr + 0x00, 0x00000000);
 123         nv_wo32(base->eng, addr + 0x04, 0x00000000);
 124         nv_wo32(base->eng, addr + 0x08, 0x00000000);
 125         nv_wo32(base->eng, addr + 0x0c, 0x00000000);
 126         nv_wo32(base->eng, addr + 0x10, 0x00000000);
 127         nv_wo32(base->eng, addr + 0x14, 0x00000000);
 128         bar->flush(bar);
 129         return 0;
 130 }
 131
 132 static int
 133 g84_fifo_object_attach(struct nvkm_object *parent,
 134                        struct nvkm_object *object, u32 handle)
 135 {
 136         struct nv50_fifo_chan *chan = (void *)parent;
 137         u32 context;
 138
 139         if (nv_iclass(object, NV_GPUOBJ_CLASS))
 140                 context = nv_gpuobj(object)->node->offset >> 4;
 141         else
 142                 context = 0x00000004; /* just non-zero */
 143
 144         switch (nv_engidx(object->engine)) {
 145         case NVDEV_ENGINE_DMAOBJ:
 146         case NVDEV_ENGINE_SW    : context |= 0x00000000; break;
 147         case NVDEV_ENGINE_GR    : context |= 0x00100000; break;
 148         case NVDEV_ENGINE_MPEG  :
 149         case NVDEV_ENGINE_MSPPP : context |= 0x00200000; break;
 150         case NVDEV_ENGINE_ME    :
 151         case NVDEV_ENGINE_CE0   : context |= 0x00300000; break;
 152         case NVDEV_ENGINE_VP    :
 153         case NVDEV_ENGINE_MSPDEC: context |= 0x00400000; break;
 154         case NVDEV_ENGINE_CIPHER:
 155         case NVDEV_ENGINE_SEC   :
 156         case NVDEV_ENGINE_VIC   : context |= 0x00500000; break;
 157         case NVDEV_ENGINE_BSP   :
 158         case NVDEV_ENGINE_MSVLD : context |= 0x00600000; break;
 159         default:
 160                 return -EINVAL;
 161         }
 162
 163         return nvkm_ramht_insert(chan->ramht, 0, handle, context);
 164 }
 165
 166 static int
 167 g84_fifo_chan_ctor_dma(struct nvkm_object *parent, struct nvkm_object *engine,
 168                        struct nvkm_oclass *oclass, void *data, u32 size,
 169                        struct nvkm_object **pobject)
 170 {
 171         union {
 172                 struct nv03_channel_dma_v0 v0;
 173         } *args = data;
 174         struct nvkm_bar *bar = nvkm_bar(parent);
 175         struct nv50_fifo_base *base = (void *)parent;
 176         struct nv50_fifo_chan *chan;
 177         int ret;
 178
 179         nv_ioctl(parent, "create channel dma size %d\n", size);
 180         if (nvif_unpack(args->v0, 0, 0, false)) {
 181                 nv_ioctl(parent, "create channel dma vers %d pushbuf %08x "
 182                                  "offset %016llx\n", args->v0.version,
 183                          args->v0.pushbuf, args->v0.offset);
 184         } else
 185                 return ret;
 186
 187         ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 188                                        0x2000, args->v0.pushbuf,
 189                                        (1ULL << NVDEV_ENGINE_DMAOBJ) |
 190                                        (1ULL << NVDEV_ENGINE_SW) |
 191                                        (1ULL << NVDEV_ENGINE_GR) |
 192                                        (1ULL << NVDEV_ENGINE_MPEG) |
 193                                        (1ULL << NVDEV_ENGINE_ME) |
 194                                        (1ULL << NVDEV_ENGINE_VP) |
 195                                        (1ULL << NVDEV_ENGINE_CIPHER) |
 196                                        (1ULL << NVDEV_ENGINE_SEC) |
 197                                        (1ULL << NVDEV_ENGINE_BSP) |
 198                                        (1ULL << NVDEV_ENGINE_MSVLD) |
 199                                        (1ULL << NVDEV_ENGINE_MSPDEC) |
 200                                        (1ULL << NVDEV_ENGINE_MSPPP) |
 201                                        (1ULL << NVDEV_ENGINE_CE0) |
 202                                        (1ULL << NVDEV_ENGINE_VIC), &chan);
 203         *pobject = nv_object(chan);
 204         if (ret)
 205                 return ret;
 206
 207         args->v0.chid = chan->base.chid;
 208
 209         ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
 210                              &chan->ramht);
 211         if (ret)
 212                 return ret;
 213
 214         nv_parent(chan)->context_attach = g84_fifo_context_attach;
 215         nv_parent(chan)->context_detach = g84_fifo_context_detach;
 216         nv_parent(chan)->object_attach = g84_fifo_object_attach;
 217         nv_parent(chan)->object_detach = nv50_fifo_object_detach;
 218
 219         nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset));
 220         nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset));
 221         nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset));
 222         nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset));
 223         nv_wo32(base->ramfc, 0x3c, 0x003f6078);
 224         nv_wo32(base->ramfc, 0x44, 0x01003fff);
 225         nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
 226         nv_wo32(base->ramfc, 0x4c, 0xffffffff);
 227         nv_wo32(base->ramfc, 0x60, 0x7fffffff);
 228         nv_wo32(base->ramfc, 0x78, 0x00000000);
 229         nv_wo32(base->ramfc, 0x7c, 0x30000001);
 230         nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 231                                    (4 << 24) /* SEARCH_FULL */ |
 232                                    (chan->ramht->gpuobj.node->offset >> 4));
 233         nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
 234         nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
 235         bar->flush(bar);
 236         return 0;
 237 }
 238
 239 static int
 240 g84_fifo_chan_ctor_ind(struct nvkm_object *parent, struct nvkm_object *engine,
 241                        struct nvkm_oclass *oclass, void *data, u32 size,
 242                        struct nvkm_object **pobject)
 243 {
 244         union {
 245                 struct nv50_channel_gpfifo_v0 v0;
 246         } *args = data;
 247         struct nvkm_bar *bar = nvkm_bar(parent);
 248         struct nv50_fifo_base *base = (void *)parent;
 249         struct nv50_fifo_chan *chan;
 250         u64 ioffset, ilength;
 251         int ret;
 252
 253         nv_ioctl(parent, "create channel gpfifo size %d\n", size);
 254         if (nvif_unpack(args->v0, 0, 0, false)) {
 255                 nv_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x "
 256                                  "ioffset %016llx ilength %08x\n",
 257                          args->v0.version, args->v0.pushbuf, args->v0.ioffset,
 258                          args->v0.ilength);
 259         } else
 260                 return ret;
 261
 262         ret = nvkm_fifo_channel_create(parent, engine, oclass, 0, 0xc00000,
 263                                        0x2000, args->v0.pushbuf,
 264                                        (1ULL << NVDEV_ENGINE_DMAOBJ) |
 265                                        (1ULL << NVDEV_ENGINE_SW) |
 266                                        (1ULL << NVDEV_ENGINE_GR) |
 267                                        (1ULL << NVDEV_ENGINE_MPEG) |
 268                                        (1ULL << NVDEV_ENGINE_ME) |
 269                                        (1ULL << NVDEV_ENGINE_VP) |
 270                                        (1ULL << NVDEV_ENGINE_CIPHER) |
 271                                        (1ULL << NVDEV_ENGINE_SEC) |
 272                                        (1ULL << NVDEV_ENGINE_BSP) |
 273                                        (1ULL << NVDEV_ENGINE_MSVLD) |
 274                                        (1ULL << NVDEV_ENGINE_MSPDEC) |
 275                                        (1ULL << NVDEV_ENGINE_MSPPP) |
 276                                        (1ULL << NVDEV_ENGINE_CE0) |
 277                                        (1ULL << NVDEV_ENGINE_VIC), &chan);
 278         *pobject = nv_object(chan);
 279         if (ret)
 280                 return ret;
 281
 282         args->v0.chid = chan->base.chid;
 283
 284         ret = nvkm_ramht_new(nv_object(chan), nv_object(chan), 0x8000, 16,
 285                              &chan->ramht);
 286         if (ret)
 287                 return ret;
 288
 289         nv_parent(chan)->context_attach = g84_fifo_context_attach;
 290         nv_parent(chan)->context_detach = g84_fifo_context_detach;
 291         nv_parent(chan)->object_attach = g84_fifo_object_attach;
 292         nv_parent(chan)->object_detach = nv50_fifo_object_detach;
 293
 294         ioffset = args->v0.ioffset;
 295         ilength = order_base_2(args->v0.ilength / 8);
 296
 297         nv_wo32(base->ramfc, 0x3c, 0x403f6078);
 298         nv_wo32(base->ramfc, 0x44, 0x01003fff);
 299         nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);
 300         nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));
 301         nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));
 302         nv_wo32(base->ramfc, 0x60, 0x7fffffff);
 303         nv_wo32(base->ramfc, 0x78, 0x00000000);
 304         nv_wo32(base->ramfc, 0x7c, 0x30000001);
 305         nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |
 306                                    (4 << 24) /* SEARCH_FULL */ |
 307                                    (chan->ramht->gpuobj.node->offset >> 4));
 308         nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);
 309         nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);
 310         bar->flush(bar);
 311         return 0;
 312 }
 313
 314 static int
 315 g84_fifo_chan_init(struct nvkm_object *object)
 316 {
 317         struct nv50_fifo *fifo = (void *)object->engine;
 318         struct nv50_fifo_base *base = (void *)object->parent;
 319         struct nv50_fifo_chan *chan = (void *)object;
 320         struct nvkm_gpuobj *ramfc = base->ramfc;
 321         struct nvkm_device *device = fifo->base.engine.subdev.device;
 322         u32 chid = chan->base.chid;
 323         int ret;
 324
 325         ret = nvkm_fifo_channel_init(&chan->base);
 326         if (ret)
 327                 return ret;
 328
 329         nvkm_wr32(device, 0x002600 + (chid * 4), 0x80000000 | ramfc->addr >> 8);
 330         nv50_fifo_playlist_update(fifo);
 331         return 0;
 332 }
 333
 334 static struct nvkm_ofuncs
 335 g84_fifo_ofuncs_dma = {
 336         .ctor = g84_fifo_chan_ctor_dma,
 337         .dtor = nv50_fifo_chan_dtor,
 338         .init = g84_fifo_chan_init,
 339         .fini = nv50_fifo_chan_fini,
 340         .map  = _nvkm_fifo_channel_map,
 341         .rd32 = _nvkm_fifo_channel_rd32,
 342         .wr32 = _nvkm_fifo_channel_wr32,
 343         .ntfy = _nvkm_fifo_channel_ntfy
 344 };
 345
 346 static struct nvkm_ofuncs
 347 g84_fifo_ofuncs_ind = {
 348         .ctor = g84_fifo_chan_ctor_ind,
 349         .dtor = nv50_fifo_chan_dtor,
 350         .init = g84_fifo_chan_init,
 351         .fini = nv50_fifo_chan_fini,
 352         .map  = _nvkm_fifo_channel_map,
 353         .rd32 = _nvkm_fifo_channel_rd32,
 354         .wr32 = _nvkm_fifo_channel_wr32,
 355         .ntfy = _nvkm_fifo_channel_ntfy
 356 };
 357
 358 static struct nvkm_oclass
 359 g84_fifo_sclass[] = {
 360         { G82_CHANNEL_DMA, &g84_fifo_ofuncs_dma },
 361         { G82_CHANNEL_GPFIFO, &g84_fifo_ofuncs_ind },
 362         {}
 363 };
 364
 365 /*******************************************************************************
 366  * FIFO context - basically just the instmem reserved for the channel
 367  ******************************************************************************/
 368
 369 static int
 370 g84_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 371                       struct nvkm_oclass *oclass, void *data, u32 size,
 372                       struct nvkm_object **pobject)
 373 {
 374         struct nv50_fifo_base *base;
 375         int ret;
 376
 377         ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x10000,
 378                                        0x1000, NVOBJ_FLAG_HEAP, &base);
 379         *pobject = nv_object(base);
 380         if (ret)
 381                 return ret;
 382
 383         ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0,
 384                               NVOBJ_FLAG_ZERO_ALLOC, &base->eng);
 385         if (ret)
 386                 return ret;
 387
 388         ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0,
 389                               0, &base->pgd);
 390         if (ret)
 391                 return ret;
 392
 393         ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);
 394         if (ret)
 395                 return ret;
 396
 397         ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x1000,
 398                               0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache);
 399         if (ret)
 400                 return ret;
 401
 402         ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0100,
 403                               0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);
 404         if (ret)
 405                 return ret;
 406
 407         return 0;
 408 }
 409
 410 static struct nvkm_oclass
 411 g84_fifo_cclass = {
 412         .handle = NV_ENGCTX(FIFO, 0x84),
 413         .ofuncs = &(struct nvkm_ofuncs) {
 414                 .ctor = g84_fifo_context_ctor,
 415                 .dtor = nv50_fifo_context_dtor,
 416                 .init = _nvkm_fifo_context_init,
 417                 .fini = _nvkm_fifo_context_fini,
 418                 .rd32 = _nvkm_fifo_context_rd32,
 419                 .wr32 = _nvkm_fifo_context_wr32,
 420         },
 421 };
 422
 423 /*******************************************************************************
 424  * PFIFO engine
 425  ******************************************************************************/
 426
 427 static void
 428 g84_fifo_uevent_init(struct nvkm_event *event, int type, int index)
 429 {
 430         struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
 431         struct nvkm_device *device = fifo->engine.subdev.device;
 432         nvkm_mask(device, 0x002140, 0x40000000, 0x40000000);
 433 }
 434
 435 static void
 436 g84_fifo_uevent_fini(struct nvkm_event *event, int type, int index)
 437 {
 438         struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent);
 439         struct nvkm_device *device = fifo->engine.subdev.device;
 440         nvkm_mask(device, 0x002140, 0x40000000, 0x00000000);
 441 }
 442
 443 static const struct nvkm_event_func
 444 g84_fifo_uevent_func = {
 445         .ctor = nvkm_fifo_uevent_ctor,
 446         .init = g84_fifo_uevent_init,
 447         .fini = g84_fifo_uevent_fini,
 448 };
 449
 450 static int
 451 g84_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 452               struct nvkm_oclass *oclass, void *data, u32 size,
 453               struct nvkm_object **pobject)
 454 {
 455         struct nv50_fifo *fifo;
 456         int ret;
 457
 458         ret = nvkm_fifo_create(parent, engine, oclass, 1, 127, &fifo);
 459         *pobject = nv_object(fifo);
 460         if (ret)
 461                 return ret;
 462
 463         ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 4, 0x1000, 0,
 464                               &fifo->playlist[0]);
 465         if (ret)
 466                 return ret;
 467
 468         ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 4, 0x1000, 0,
 469                               &fifo->playlist[1]);
 470         if (ret)
 471                 return ret;
 472
 473         ret = nvkm_event_init(&g84_fifo_uevent_func, 1, 1, &fifo->base.uevent);
 474         if (ret)
 475                 return ret;
 476
 477         nv_subdev(fifo)->unit = 0x00000100;
 478         nv_subdev(fifo)->intr = nv04_fifo_intr;
 479         nv_engine(fifo)->cclass = &g84_fifo_cclass;
 480         nv_engine(fifo)->sclass = g84_fifo_sclass;
 481         fifo->base.pause = nv04_fifo_pause;
 482         fifo->base.start = nv04_fifo_start;
 483         return 0;
 484 }
 485
 486 struct nvkm_oclass *
 487 g84_fifo_oclass = &(struct nvkm_oclass) {
 488         .handle = NV_ENGINE(FIFO, 0x84),
 489         .ofuncs = &(struct nvkm_ofuncs) {
 490                 .ctor = g84_fifo_ctor,
 491                 .dtor = nv50_fifo_dtor,
 492                 .init = nv50_fifo_init,
 493                 .fini = _nvkm_fifo_fini,
 494         },
 495 };