drm/nouveau/clk: rename from clock (no binary change)
[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / nouveau / nvkm / subdev / clk / base.c
1 /*
2  * Copyright 2013 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24
25 #include <core/option.h>
26
27 #include <subdev/clk.h>
28 #include <subdev/therm.h>
29 #include <subdev/volt.h>
30 #include <subdev/fb.h>
31
32 #include <subdev/bios.h>
33 #include <subdev/bios/boost.h>
34 #include <subdev/bios/cstep.h>
35 #include <subdev/bios/perf.h>
36
37 /******************************************************************************
38  * misc
39  *****************************************************************************/
40 static u32
41 nouveau_clk_adjust(struct nouveau_clk *clk, bool adjust,
42                      u8 pstate, u8 domain, u32 input)
43 {
44         struct nouveau_bios *bios = nouveau_bios(clk);
45         struct nvbios_boostE boostE;
46         u8  ver, hdr, cnt, len;
47         u16 data;
48
49         data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
50         if (data) {
51                 struct nvbios_boostS boostS;
52                 u8  idx = 0, sver, shdr;
53                 u16 subd;
54
55                 input = max(boostE.min, input);
56                 input = min(boostE.max, input);
57                 do {
58                         sver = ver;
59                         shdr = hdr;
60                         subd = nvbios_boostSp(bios, idx++, data, &sver, &shdr,
61                                               cnt, len, &boostS);
62                         if (subd && boostS.domain == domain) {
63                                 if (adjust)
64                                         input = input * boostS.percent / 100;
65                                 input = max(boostS.min, input);
66                                 input = min(boostS.max, input);
67                                 break;
68                         }
69                 } while (subd);
70         }
71
72         return input;
73 }
74
75 /******************************************************************************
76  * C-States
77  *****************************************************************************/
78 static int
79 nouveau_cstate_prog(struct nouveau_clk *clk,
80                     struct nouveau_pstate *pstate, int cstatei)
81 {
82         struct nouveau_therm *ptherm = nouveau_therm(clk);
83         struct nouveau_volt *volt = nouveau_volt(clk);
84         struct nouveau_cstate *cstate;
85         int ret;
86
87         if (!list_empty(&pstate->list)) {
88                 cstate = list_entry(pstate->list.prev, typeof(*cstate), head);
89         } else {
90                 cstate = &pstate->base;
91         }
92
93         if (ptherm) {
94                 ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, +1);
95                 if (ret && ret != -ENODEV) {
96                         nv_error(clk, "failed to raise fan speed: %d\n", ret);
97                         return ret;
98                 }
99         }
100
101         if (volt) {
102                 ret = volt->set_id(volt, cstate->voltage, +1);
103                 if (ret && ret != -ENODEV) {
104                         nv_error(clk, "failed to raise voltage: %d\n", ret);
105                         return ret;
106                 }
107         }
108
109         ret = clk->calc(clk, cstate);
110         if (ret == 0) {
111                 ret = clk->prog(clk);
112                 clk->tidy(clk);
113         }
114
115         if (volt) {
116                 ret = volt->set_id(volt, cstate->voltage, -1);
117                 if (ret && ret != -ENODEV)
118                         nv_error(clk, "failed to lower voltage: %d\n", ret);
119         }
120
121         if (ptherm) {
122                 ret = nouveau_therm_cstate(ptherm, pstate->fanspeed, -1);
123                 if (ret && ret != -ENODEV)
124                         nv_error(clk, "failed to lower fan speed: %d\n", ret);
125         }
126
127         return 0;
128 }
129
130 static void
131 nouveau_cstate_del(struct nouveau_cstate *cstate)
132 {
133         list_del(&cstate->head);
134         kfree(cstate);
135 }
136
137 static int
138 nouveau_cstate_new(struct nouveau_clk *clk, int idx,
139                    struct nouveau_pstate *pstate)
140 {
141         struct nouveau_bios *bios = nouveau_bios(clk);
142         struct nouveau_domain *domain = clk->domains;
143         struct nouveau_cstate *cstate = NULL;
144         struct nvbios_cstepX cstepX;
145         u8  ver, hdr;
146         u16 data;
147
148         data = nvbios_cstepXp(bios, idx, &ver, &hdr, &cstepX);
149         if (!data)
150                 return -ENOENT;
151
152         cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
153         if (!cstate)
154                 return -ENOMEM;
155
156         *cstate = pstate->base;
157         cstate->voltage = cstepX.voltage;
158
159         while (domain && domain->name != nv_clk_src_max) {
160                 if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
161                         u32 freq = nouveau_clk_adjust(clk, true,
162                                                         pstate->pstate,
163                                                         domain->bios,
164                                                         cstepX.freq);
165                         cstate->domain[domain->name] = freq;
166                 }
167                 domain++;
168         }
169
170         list_add(&cstate->head, &pstate->list);
171         return 0;
172 }
173
174 /******************************************************************************
175  * P-States
176  *****************************************************************************/
177 static int
178 nouveau_pstate_prog(struct nouveau_clk *clk, int pstatei)
179 {
180         struct nouveau_fb *pfb = nouveau_fb(clk);
181         struct nouveau_pstate *pstate;
182         int ret, idx = 0;
183
184         list_for_each_entry(pstate, &clk->states, head) {
185                 if (idx++ == pstatei)
186                         break;
187         }
188
189         nv_debug(clk, "setting performance state %d\n", pstatei);
190         clk->pstate = pstatei;
191
192         if (pfb->ram->calc) {
193                 int khz = pstate->base.domain[nv_clk_src_mem];
194                 do {
195                         ret = pfb->ram->calc(pfb, khz);
196                         if (ret == 0)
197                                 ret = pfb->ram->prog(pfb);
198                 } while (ret > 0);
199                 pfb->ram->tidy(pfb);
200         }
201
202         return nouveau_cstate_prog(clk, pstate, 0);
203 }
204
205 static void
206 nouveau_pstate_work(struct work_struct *work)
207 {
208         struct nouveau_clk *clk = container_of(work, typeof(*clk), work);
209         int pstate;
210
211         if (!atomic_xchg(&clk->waiting, 0))
212                 return;
213         clk->pwrsrc = power_supply_is_system_supplied();
214
215         nv_trace(clk, "P %d PWR %d U(AC) %d U(DC) %d A %d T %d D %d\n",
216                  clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
217                  clk->astate, clk->tstate, clk->dstate);
218
219         pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc;
220         if (clk->state_nr && pstate != -1) {
221                 pstate = (pstate < 0) ? clk->astate : pstate;
222                 pstate = min(pstate, clk->state_nr - 1 - clk->tstate);
223                 pstate = max(pstate, clk->dstate);
224         } else {
225                 pstate = clk->pstate = -1;
226         }
227
228         nv_trace(clk, "-> %d\n", pstate);
229         if (pstate != clk->pstate) {
230                 int ret = nouveau_pstate_prog(clk, pstate);
231                 if (ret) {
232                         nv_error(clk, "error setting pstate %d: %d\n",
233                                  pstate, ret);
234                 }
235         }
236
237         wake_up_all(&clk->wait);
238         nvkm_notify_get(&clk->pwrsrc_ntfy);
239 }
240
241 static int
242 nouveau_pstate_calc(struct nouveau_clk *clk, bool wait)
243 {
244         atomic_set(&clk->waiting, 1);
245         schedule_work(&clk->work);
246         if (wait)
247                 wait_event(clk->wait, !atomic_read(&clk->waiting));
248         return 0;
249 }
250
251 static void
252 nouveau_pstate_info(struct nouveau_clk *clk, struct nouveau_pstate *pstate)
253 {
254         struct nouveau_domain *clock = clk->domains - 1;
255         struct nouveau_cstate *cstate;
256         char info[3][32] = { "", "", "" };
257         char name[4] = "--";
258         int i = -1;
259
260         if (pstate->pstate != 0xff)
261                 snprintf(name, sizeof(name), "%02x", pstate->pstate);
262
263         while ((++clock)->name != nv_clk_src_max) {
264                 u32 lo = pstate->base.domain[clock->name];
265                 u32 hi = lo;
266                 if (hi == 0)
267                         continue;
268
269                 nv_debug(clk, "%02x: %10d KHz\n", clock->name, lo);
270                 list_for_each_entry(cstate, &pstate->list, head) {
271                         u32 freq = cstate->domain[clock->name];
272                         lo = min(lo, freq);
273                         hi = max(hi, freq);
274                         nv_debug(clk, "%10d KHz\n", freq);
275                 }
276
277                 if (clock->mname && ++i < ARRAY_SIZE(info)) {
278                         lo /= clock->mdiv;
279                         hi /= clock->mdiv;
280                         if (lo == hi) {
281                                 snprintf(info[i], sizeof(info[i]), "%s %d MHz",
282                                          clock->mname, lo);
283                         } else {
284                                 snprintf(info[i], sizeof(info[i]),
285                                          "%s %d-%d MHz", clock->mname, lo, hi);
286                         }
287                 }
288         }
289
290         nv_info(clk, "%s: %s %s %s\n", name, info[0], info[1], info[2]);
291 }
292
293 static void
294 nouveau_pstate_del(struct nouveau_pstate *pstate)
295 {
296         struct nouveau_cstate *cstate, *temp;
297
298         list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
299                 nouveau_cstate_del(cstate);
300         }
301
302         list_del(&pstate->head);
303         kfree(pstate);
304 }
305
306 static int
307 nouveau_pstate_new(struct nouveau_clk *clk, int idx)
308 {
309         struct nouveau_bios *bios = nouveau_bios(clk);
310         struct nouveau_domain *domain = clk->domains - 1;
311         struct nouveau_pstate *pstate;
312         struct nouveau_cstate *cstate;
313         struct nvbios_cstepE cstepE;
314         struct nvbios_perfE perfE;
315         u8  ver, hdr, cnt, len;
316         u16 data;
317
318         data = nvbios_perfEp(bios, idx, &ver, &hdr, &cnt, &len, &perfE);
319         if (!data)
320                 return -EINVAL;
321         if (perfE.pstate == 0xff)
322                 return 0;
323
324         pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
325         cstate = &pstate->base;
326         if (!pstate)
327                 return -ENOMEM;
328
329         INIT_LIST_HEAD(&pstate->list);
330
331         pstate->pstate = perfE.pstate;
332         pstate->fanspeed = perfE.fanspeed;
333         cstate->voltage = perfE.voltage;
334         cstate->domain[nv_clk_src_core] = perfE.core;
335         cstate->domain[nv_clk_src_shader] = perfE.shader;
336         cstate->domain[nv_clk_src_mem] = perfE.memory;
337         cstate->domain[nv_clk_src_vdec] = perfE.vdec;
338         cstate->domain[nv_clk_src_dom6] = perfE.disp;
339
340         while (ver >= 0x40 && (++domain)->name != nv_clk_src_max) {
341                 struct nvbios_perfS perfS;
342                 u8  sver = ver, shdr = hdr;
343                 u32 perfSe = nvbios_perfSp(bios, data, domain->bios,
344                                           &sver, &shdr, cnt, len, &perfS);
345                 if (perfSe == 0 || sver != 0x40)
346                         continue;
347
348                 if (domain->flags & NVKM_CLK_DOM_FLAG_CORE) {
349                         perfS.v40.freq = nouveau_clk_adjust(clk, false,
350                                                               pstate->pstate,
351                                                               domain->bios,
352                                                               perfS.v40.freq);
353                 }
354
355                 cstate->domain[domain->name] = perfS.v40.freq;
356         }
357
358         data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);
359         if (data) {
360                 int idx = cstepE.index;
361                 do {
362                         nouveau_cstate_new(clk, idx, pstate);
363                 } while(idx--);
364         }
365
366         nouveau_pstate_info(clk, pstate);
367         list_add_tail(&pstate->head, &clk->states);
368         clk->state_nr++;
369         return 0;
370 }
371
372 /******************************************************************************
373  * Adjustment triggers
374  *****************************************************************************/
375 static int
376 nouveau_clk_ustate_update(struct nouveau_clk *clk, int req)
377 {
378         struct nouveau_pstate *pstate;
379         int i = 0;
380
381         if (!clk->allow_reclock)
382                 return -ENOSYS;
383
384         if (req != -1 && req != -2) {
385                 list_for_each_entry(pstate, &clk->states, head) {
386                         if (pstate->pstate == req)
387                                 break;
388                         i++;
389                 }
390
391                 if (pstate->pstate != req)
392                         return -EINVAL;
393                 req = i;
394         }
395
396         return req + 2;
397 }
398
399 static int
400 nouveau_clk_nstate(struct nouveau_clk *clk, const char *mode, int arglen)
401 {
402         int ret = 1;
403
404         if (clk->allow_reclock && !strncasecmpz(mode, "auto", arglen))
405                 return -2;
406
407         if (strncasecmpz(mode, "disabled", arglen)) {
408                 char save = mode[arglen];
409                 long v;
410
411                 ((char *)mode)[arglen] = '\0';
412                 if (!kstrtol(mode, 0, &v)) {
413                         ret = nouveau_clk_ustate_update(clk, v);
414                         if (ret < 0)
415                                 ret = 1;
416                 }
417                 ((char *)mode)[arglen] = save;
418         }
419
420         return ret - 2;
421 }
422
423 int
424 nouveau_clk_ustate(struct nouveau_clk *clk, int req, int pwr)
425 {
426         int ret = nouveau_clk_ustate_update(clk, req);
427         if (ret >= 0) {
428                 if (ret -= 2, pwr) clk->ustate_ac = ret;
429                 else               clk->ustate_dc = ret;
430                 return nouveau_pstate_calc(clk, true);
431         }
432         return ret;
433 }
434
435 int
436 nouveau_clk_astate(struct nouveau_clk *clk, int req, int rel, bool wait)
437 {
438         if (!rel) clk->astate  = req;
439         if ( rel) clk->astate += rel;
440         clk->astate = min(clk->astate, clk->state_nr - 1);
441         clk->astate = max(clk->astate, 0);
442         return nouveau_pstate_calc(clk, wait);
443 }
444
445 int
446 nouveau_clk_tstate(struct nouveau_clk *clk, int req, int rel)
447 {
448         if (!rel) clk->tstate  = req;
449         if ( rel) clk->tstate += rel;
450         clk->tstate = min(clk->tstate, 0);
451         clk->tstate = max(clk->tstate, -(clk->state_nr - 1));
452         return nouveau_pstate_calc(clk, true);
453 }
454
455 int
456 nouveau_clk_dstate(struct nouveau_clk *clk, int req, int rel)
457 {
458         if (!rel) clk->dstate  = req;
459         if ( rel) clk->dstate += rel;
460         clk->dstate = min(clk->dstate, clk->state_nr - 1);
461         clk->dstate = max(clk->dstate, 0);
462         return nouveau_pstate_calc(clk, true);
463 }
464
465 static int
466 nouveau_clk_pwrsrc(struct nvkm_notify *notify)
467 {
468         struct nouveau_clk *clk =
469                 container_of(notify, typeof(*clk), pwrsrc_ntfy);
470         nouveau_pstate_calc(clk, false);
471         return NVKM_NOTIFY_DROP;
472 }
473
474 /******************************************************************************
475  * subdev base class implementation
476  *****************************************************************************/
477
478 int
479 _nouveau_clk_fini(struct nouveau_object *object, bool suspend)
480 {
481         struct nouveau_clk *clk = (void *)object;
482         nvkm_notify_put(&clk->pwrsrc_ntfy);
483         return nouveau_subdev_fini(&clk->base, suspend);
484 }
485
486 int
487 _nouveau_clk_init(struct nouveau_object *object)
488 {
489         struct nouveau_clk *clk = (void *)object;
490         struct nouveau_domain *clock = clk->domains;
491         int ret;
492
493         ret = nouveau_subdev_init(&clk->base);
494         if (ret)
495                 return ret;
496
497         memset(&clk->bstate, 0x00, sizeof(clk->bstate));
498         INIT_LIST_HEAD(&clk->bstate.list);
499         clk->bstate.pstate = 0xff;
500
501         while (clock->name != nv_clk_src_max) {
502                 ret = clk->read(clk, clock->name);
503                 if (ret < 0) {
504                         nv_error(clk, "%02x freq unknown\n", clock->name);
505                         return ret;
506                 }
507                 clk->bstate.base.domain[clock->name] = ret;
508                 clock++;
509         }
510
511         nouveau_pstate_info(clk, &clk->bstate);
512
513         clk->astate = clk->state_nr - 1;
514         clk->tstate = 0;
515         clk->dstate = 0;
516         clk->pstate = -1;
517         nouveau_pstate_calc(clk, true);
518         return 0;
519 }
520
521 void
522 _nouveau_clk_dtor(struct nouveau_object *object)
523 {
524         struct nouveau_clk *clk = (void *)object;
525         struct nouveau_pstate *pstate, *temp;
526
527         nvkm_notify_fini(&clk->pwrsrc_ntfy);
528
529         list_for_each_entry_safe(pstate, temp, &clk->states, head) {
530                 nouveau_pstate_del(pstate);
531         }
532
533         nouveau_subdev_destroy(&clk->base);
534 }
535
536 int
537 nouveau_clk_create_(struct nouveau_object *parent,
538                       struct nouveau_object *engine,
539                       struct nouveau_oclass *oclass,
540                       struct nouveau_domain *clocks,
541                       struct nouveau_pstate *pstates, int nb_pstates,
542                       bool allow_reclock,
543                       int length, void **object)
544 {
545         struct nouveau_device *device = nv_device(parent);
546         struct nouveau_clk *clk;
547         int ret, idx, arglen;
548         const char *mode;
549
550         ret = nouveau_subdev_create_(parent, engine, oclass, 0, "CLK",
551                                      "clock", length, object);
552         clk = *object;
553         if (ret)
554                 return ret;
555
556         INIT_LIST_HEAD(&clk->states);
557         clk->domains = clocks;
558         clk->ustate_ac = -1;
559         clk->ustate_dc = -1;
560
561         INIT_WORK(&clk->work, nouveau_pstate_work);
562         init_waitqueue_head(&clk->wait);
563         atomic_set(&clk->waiting, 0);
564
565         /* If no pstates are provided, try and fetch them from the BIOS */
566         if (!pstates) {
567                 idx = 0;
568                 do {
569                         ret = nouveau_pstate_new(clk, idx++);
570                 } while (ret == 0);
571         } else {
572                 for (idx = 0; idx < nb_pstates; idx++)
573                         list_add_tail(&pstates[idx].head, &clk->states);
574                 clk->state_nr = nb_pstates;
575         }
576
577         clk->allow_reclock = allow_reclock;
578
579         ret = nvkm_notify_init(NULL, &device->event, nouveau_clk_pwrsrc, true,
580                                NULL, 0, 0, &clk->pwrsrc_ntfy);
581         if (ret)
582                 return ret;
583
584         mode = nouveau_stropt(device->cfgopt, "NvClkMode", &arglen);
585         if (mode) {
586                 clk->ustate_ac = nouveau_clk_nstate(clk, mode, arglen);
587                 clk->ustate_dc = nouveau_clk_nstate(clk, mode, arglen);
588         }
589
590         mode = nouveau_stropt(device->cfgopt, "NvClkModeAC", &arglen);
591         if (mode)
592                 clk->ustate_ac = nouveau_clk_nstate(clk, mode, arglen);
593
594         mode = nouveau_stropt(device->cfgopt, "NvClkModeDC", &arglen);
595         if (mode)
596                 clk->ustate_dc = nouveau_clk_nstate(clk, mode, arglen);
597
598
599         return 0;
600 }