2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
25 #include <subdev/bios.h>
26 #include <subdev/bios/pll.h>
33 read_div(struct nv50_clock_priv *priv)
35 switch (nv_device(priv)->chipset) {
36 case 0x50: /* it exists, but only has bit 31, not the dividers.. */
41 return nv_rd32(priv, 0x004700);
45 return nv_rd32(priv, 0x004800);
52 read_pll_src(struct nv50_clock_priv *priv, u32 base)
54 struct nouveau_clock *clk = &priv->base;
55 u32 coef, ref = clk->read(clk, nv_clk_src_crystal);
56 u32 rsel = nv_rd32(priv, 0x00e18c);
59 switch (nv_device(priv)->chipset) {
64 case 0x4028: id = !!(rsel & 0x00000004); break;
65 case 0x4008: id = !!(rsel & 0x00000008); break;
66 case 0x4030: id = 0; break;
68 nv_error(priv, "ref: bad pll 0x%06x\n", base);
72 coef = nv_rd32(priv, 0x00e81c + (id * 0x0c));
73 ref *= (coef & 0x01000000) ? 2 : 4;
74 P = (coef & 0x00070000) >> 16;
75 N = ((coef & 0x0000ff00) >> 8) + 1;
76 M = ((coef & 0x000000ff) >> 0) + 1;
81 coef = nv_rd32(priv, 0x00e81c);
82 P = (coef & 0x00070000) >> 16;
83 N = (coef & 0x0000ff00) >> 8;
84 M = (coef & 0x000000ff) >> 0;
89 rsel = nv_rd32(priv, 0x00c050);
91 case 0x4020: rsel = (rsel & 0x00000003) >> 0; break;
92 case 0x4008: rsel = (rsel & 0x0000000c) >> 2; break;
93 case 0x4028: rsel = (rsel & 0x00001800) >> 11; break;
94 case 0x4030: rsel = 3; break;
96 nv_error(priv, "ref: bad pll 0x%06x\n", base);
101 case 0: id = 1; break;
102 case 1: return clk->read(clk, nv_clk_src_crystal);
103 case 2: return clk->read(clk, nv_clk_src_href);
104 case 3: id = 0; break;
107 coef = nv_rd32(priv, 0x00e81c + (id * 0x28));
108 P = (nv_rd32(priv, 0x00e824 + (id * 0x28)) >> 16) & 7;
109 P += (coef & 0x00070000) >> 16;
110 N = (coef & 0x0000ff00) >> 8;
111 M = (coef & 0x000000ff) >> 0;
118 return (ref * N / M) >> P;
123 read_pll_ref(struct nv50_clock_priv *priv, u32 base)
125 struct nouveau_clock *clk = &priv->base;
126 u32 src, mast = nv_rd32(priv, 0x00c040);
130 src = !!(mast & 0x00200000);
133 src = !!(mast & 0x00400000);
136 src = !!(mast & 0x00010000);
139 src = !!(mast & 0x02000000);
142 return clk->read(clk, nv_clk_src_crystal);
144 nv_error(priv, "bad pll 0x%06x\n", base);
149 return clk->read(clk, nv_clk_src_href);
150 return read_pll_src(priv, base);
154 read_pll(struct nv50_clock_priv *priv, u32 base)
156 struct nouveau_clock *clk = &priv->base;
157 u32 mast = nv_rd32(priv, 0x00c040);
158 u32 ctrl = nv_rd32(priv, base + 0);
159 u32 coef = nv_rd32(priv, base + 4);
160 u32 ref = read_pll_ref(priv, base);
164 if (base == 0x004028 && (mast & 0x00100000)) {
165 /* wtf, appears to only disable post-divider on nva0 */
166 if (nv_device(priv)->chipset != 0xa0)
167 return clk->read(clk, nv_clk_src_dom6);
170 N2 = (coef & 0xff000000) >> 24;
171 M2 = (coef & 0x00ff0000) >> 16;
172 N1 = (coef & 0x0000ff00) >> 8;
173 M1 = (coef & 0x000000ff);
174 if ((ctrl & 0x80000000) && M1) {
175 freq = ref * N1 / M1;
176 if ((ctrl & 0x40000100) == 0x40000000) {
178 freq = freq * N2 / M2;
188 nv50_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
190 struct nv50_clock_priv *priv = (void *)clk;
191 u32 mast = nv_rd32(priv, 0x00c040);
195 case nv_clk_src_crystal:
196 return nv_device(priv)->crystal;
197 case nv_clk_src_href:
198 return 100000; /* PCIE reference clock */
199 case nv_clk_src_hclk:
200 return div_u64((u64)clk->read(clk, nv_clk_src_href) * 27778, 10000);
201 case nv_clk_src_hclkm3:
202 return clk->read(clk, nv_clk_src_hclk) * 3;
203 case nv_clk_src_hclkm3d2:
204 return clk->read(clk, nv_clk_src_hclk) * 3 / 2;
205 case nv_clk_src_host:
206 switch (mast & 0x30000000) {
207 case 0x00000000: return clk->read(clk, nv_clk_src_href);
208 case 0x10000000: break;
209 case 0x20000000: /* !0x50 */
210 case 0x30000000: return clk->read(clk, nv_clk_src_hclk);
213 case nv_clk_src_core:
214 if (!(mast & 0x00100000))
215 P = (nv_rd32(priv, 0x004028) & 0x00070000) >> 16;
216 switch (mast & 0x00000003) {
217 case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P;
218 case 0x00000001: return clk->read(clk, nv_clk_src_dom6);
219 case 0x00000002: return read_pll(priv, 0x004020) >> P;
220 case 0x00000003: return read_pll(priv, 0x004028) >> P;
223 case nv_clk_src_shader:
224 P = (nv_rd32(priv, 0x004020) & 0x00070000) >> 16;
225 switch (mast & 0x00000030) {
227 if (mast & 0x00000080)
228 return clk->read(clk, nv_clk_src_host) >> P;
229 return clk->read(clk, nv_clk_src_crystal) >> P;
230 case 0x00000010: break;
231 case 0x00000020: return read_pll(priv, 0x004028) >> P;
232 case 0x00000030: return read_pll(priv, 0x004020) >> P;
236 P = (nv_rd32(priv, 0x004008) & 0x00070000) >> 16;
237 if (nv_rd32(priv, 0x004008) & 0x00000200) {
238 switch (mast & 0x0000c000) {
240 return clk->read(clk, nv_clk_src_crystal) >> P;
243 return clk->read(clk, nv_clk_src_href) >> P;
246 return read_pll(priv, 0x004008) >> P;
249 case nv_clk_src_vdec:
250 P = (read_div(priv) & 0x00000700) >> 8;
251 switch (nv_device(priv)->chipset) {
258 switch (mast & 0x00000c00) {
260 if (nv_device(priv)->chipset == 0xa0) /* wtf?? */
261 return clk->read(clk, nv_clk_src_core) >> P;
262 return clk->read(clk, nv_clk_src_crystal) >> P;
266 if (mast & 0x01000000)
267 return read_pll(priv, 0x004028) >> P;
268 return read_pll(priv, 0x004030) >> P;
270 return clk->read(clk, nv_clk_src_core) >> P;
274 switch (mast & 0x00000c00) {
276 return clk->read(clk, nv_clk_src_core) >> P;
280 return clk->read(clk, nv_clk_src_hclkm3d2) >> P;
282 return clk->read(clk, nv_clk_src_mem) >> P;
287 case nv_clk_src_dom6:
288 switch (nv_device(priv)->chipset) {
291 return read_pll(priv, 0x00e810) >> 2;
298 P = (read_div(priv) & 0x00000007) >> 0;
299 switch (mast & 0x0c000000) {
300 case 0x00000000: return clk->read(clk, nv_clk_src_href);
301 case 0x04000000: break;
302 case 0x08000000: return clk->read(clk, nv_clk_src_hclk);
304 return clk->read(clk, nv_clk_src_hclkm3) >> P;
314 nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast);
319 calc_pll(struct nv50_clock_priv *priv, u32 reg, u32 clk, int *N, int *M, int *P)
321 struct nouveau_bios *bios = nouveau_bios(priv);
322 struct nvbios_pll pll;
325 ret = nvbios_pll_parse(bios, reg, &pll);
329 pll.vco2.max_freq = 0;
330 pll.refclk = read_pll_ref(priv, reg);
334 return nv04_pll_calc(nv_subdev(priv), &pll, clk, N, M, NULL, NULL, P);
338 calc_div(u32 src, u32 target, int *div)
340 u32 clk0 = src, clk1 = src;
341 for (*div = 0; *div <= 7; (*div)++) {
342 if (clk0 <= target) {
343 clk1 = clk0 << (*div ? 1 : 0);
349 if (target - clk0 <= clk1 - target)
356 clk_same(u32 a, u32 b)
358 return ((a / 1000) == (b / 1000));
362 nv50_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
364 struct nv50_clock_priv *priv = (void *)clk;
365 struct nv50_clock_hwsq *hwsq = &priv->hwsq;
366 const int shader = cstate->domain[nv_clk_src_shader];
367 const int core = cstate->domain[nv_clk_src_core];
368 const int vdec = cstate->domain[nv_clk_src_vdec];
369 const int dom6 = cstate->domain[nv_clk_src_dom6];
370 u32 mastm = 0, mastv = 0;
371 u32 divsm = 0, divsv = 0;
375 /* prepare a hwsq script from which we'll perform the reclock */
376 out = clk_init(hwsq, nv_subdev(clk));
380 clk_wr32(hwsq, fifo, 0x00000001); /* block fifo */
381 clk_nsec(hwsq, 8000);
382 clk_setf(hwsq, 0x10, 0x00); /* disable fb */
383 clk_wait(hwsq, 0x00, 0x01); /* wait for fb disabled */
385 /* vdec: avoid modifying xpll until we know exactly how the other
386 * clock domains work, i suspect at least some of them can also be
390 /* see how close we can get using nvclk as a source */
391 freq = calc_div(core, vdec, &P1);
393 /* see how close we can get using xpll/hclk as a source */
394 if (nv_device(priv)->chipset != 0x98)
395 out = read_pll(priv, 0x004030);
397 out = clk->read(clk, nv_clk_src_hclkm3d2);
398 out = calc_div(out, vdec, &P2);
400 /* select whichever gets us closest */
401 if (abs(vdec - freq) <= abs(vdec - out)) {
402 if (nv_device(priv)->chipset != 0x98)
414 /* dom6: nfi what this is, but we're limited to various combinations
415 * of the host clock frequency
418 if (clk_same(dom6, clk->read(clk, nv_clk_src_href))) {
421 if (clk_same(dom6, clk->read(clk, nv_clk_src_hclk))) {
424 freq = clk->read(clk, nv_clk_src_hclk) * 3;
425 freq = calc_div(freq, dom6, &P1);
435 /* vdec/dom6: switch to "safe" clocks temporarily, update dividers
436 * and then switch to target clocks
438 clk_mask(hwsq, mast, mastm, 0x00000000);
439 clk_mask(hwsq, divs, divsm, divsv);
440 clk_mask(hwsq, mast, mastm, mastv);
442 /* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6,
443 * sclk to hclk) before reprogramming
445 if (nv_device(priv)->chipset < 0x92)
446 clk_mask(hwsq, mast, 0x001000b0, 0x00100080);
448 clk_mask(hwsq, mast, 0x000000b3, 0x00000081);
450 /* core: for the moment at least, always use nvpll */
451 freq = calc_pll(priv, 0x4028, core, &N, &M, &P1);
455 clk_mask(hwsq, nvpll[0], 0xc03f0100,
456 0x80000000 | (P1 << 19) | (P1 << 16));
457 clk_mask(hwsq, nvpll[1], 0x0000ffff, (N << 8) | M);
459 /* shader: tie to nvclk if possible, otherwise use spll. have to be
460 * very careful that the shader clock is at least twice the core, or
461 * some chipsets will be very unhappy. i expect most or all of these
462 * cases will be handled by tying to nvclk, but it's possible there's
465 if (P1-- && shader == (core << 1)) {
466 clk_mask(hwsq, spll[0], 0xc03f0100, (P1 << 19) | (P1 << 16));
467 clk_mask(hwsq, mast, 0x00100033, 0x00000023);
469 freq = calc_pll(priv, 0x4020, shader, &N, &M, &P1);
473 clk_mask(hwsq, spll[0], 0xc03f0100,
474 0x80000000 | (P1 << 19) | (P1 << 16));
475 clk_mask(hwsq, spll[1], 0x0000ffff, (N << 8) | M);
476 clk_mask(hwsq, mast, 0x00100033, 0x00000033);
479 /* restore normal operation */
480 clk_setf(hwsq, 0x10, 0x01); /* enable fb */
481 clk_wait(hwsq, 0x00, 0x00); /* wait for fb enabled */
482 clk_wr32(hwsq, fifo, 0x00000000); /* un-block fifo */
487 nv50_clock_prog(struct nouveau_clock *clk)
489 struct nv50_clock_priv *priv = (void *)clk;
490 return clk_exec(&priv->hwsq, true);
494 nv50_clock_tidy(struct nouveau_clock *clk)
496 struct nv50_clock_priv *priv = (void *)clk;
497 clk_exec(&priv->hwsq, false);
501 nv50_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
502 struct nouveau_oclass *oclass, void *data, u32 size,
503 struct nouveau_object **pobject)
505 struct nv50_clock_oclass *pclass = (void *)oclass;
506 struct nv50_clock_priv *priv;
509 ret = nouveau_clock_create(parent, engine, oclass, pclass->domains,
510 NULL, 0, false, &priv);
511 *pobject = nv_object(priv);
515 priv->hwsq.r_fifo = hwsq_reg(0x002504);
516 priv->hwsq.r_spll[0] = hwsq_reg(0x004020);
517 priv->hwsq.r_spll[1] = hwsq_reg(0x004024);
518 priv->hwsq.r_nvpll[0] = hwsq_reg(0x004028);
519 priv->hwsq.r_nvpll[1] = hwsq_reg(0x00402c);
520 switch (nv_device(priv)->chipset) {
524 priv->hwsq.r_divs = hwsq_reg(0x004800);
527 priv->hwsq.r_divs = hwsq_reg(0x004700);
530 priv->hwsq.r_mast = hwsq_reg(0x00c040);
532 priv->base.read = nv50_clock_read;
533 priv->base.calc = nv50_clock_calc;
534 priv->base.prog = nv50_clock_prog;
535 priv->base.tidy = nv50_clock_tidy;
539 static struct nouveau_clocks
541 { nv_clk_src_crystal, 0xff },
542 { nv_clk_src_href , 0xff },
543 { nv_clk_src_core , 0xff, 0, "core", 1000 },
544 { nv_clk_src_shader , 0xff, 0, "shader", 1000 },
545 { nv_clk_src_mem , 0xff, 0, "memory", 1000 },
549 struct nouveau_oclass *
550 nv50_clock_oclass = &(struct nv50_clock_oclass) {
551 .base.handle = NV_SUBDEV(CLOCK, 0x50),
552 .base.ofuncs = &(struct nouveau_ofuncs) {
553 .ctor = nv50_clock_ctor,
554 .dtor = _nouveau_clock_dtor,
555 .init = _nouveau_clock_init,
556 .fini = _nouveau_clock_fini,
558 .domains = nv50_domains,