2 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
23 #include <subdev/fb.h>
25 #include <core/device.h>
28 #include <linux/dma-attrs.h>
33 struct gk20a_instobj_priv {
34 struct nvkm_instobj base;
35 /* Must be second member here - see nouveau_gpuobj_map_vm() */
41 struct nvkm_mm_node r;
44 struct gk20a_instmem_priv {
45 struct nvkm_instmem base;
48 struct dma_attrs attrs;
52 gk20a_instobj_rd32(struct nvkm_object *object, u64 offset)
54 struct gk20a_instmem_priv *priv = (void *)nvkm_instmem(object);
55 struct gk20a_instobj_priv *node = (void *)object;
57 u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
58 u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
61 spin_lock_irqsave(&priv->lock, flags);
62 if (unlikely(priv->addr != base)) {
63 nv_wr32(priv, 0x001700, base >> 16);
66 data = nv_rd32(priv, 0x700000 + addr);
67 spin_unlock_irqrestore(&priv->lock, flags);
72 gk20a_instobj_wr32(struct nvkm_object *object, u64 offset, u32 data)
74 struct gk20a_instmem_priv *priv = (void *)nvkm_instmem(object);
75 struct gk20a_instobj_priv *node = (void *)object;
77 u64 base = (node->mem->offset + offset) & 0xffffff00000ULL;
78 u64 addr = (node->mem->offset + offset) & 0x000000fffffULL;
80 spin_lock_irqsave(&priv->lock, flags);
81 if (unlikely(priv->addr != base)) {
82 nv_wr32(priv, 0x001700, base >> 16);
85 nv_wr32(priv, 0x700000 + addr, data);
86 spin_unlock_irqrestore(&priv->lock, flags);
90 gk20a_instobj_dtor(struct nvkm_object *object)
92 struct gk20a_instobj_priv *node = (void *)object;
93 struct gk20a_instmem_priv *priv = (void *)nvkm_instmem(node);
94 struct device *dev = nv_device_base(nv_device(priv));
96 if (unlikely(!node->handle))
99 dma_free_attrs(dev, node->mem->size << PAGE_SHIFT, node->cpuaddr,
100 node->handle, &priv->attrs);
102 nvkm_instobj_destroy(&node->base);
106 gk20a_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
107 struct nvkm_oclass *oclass, void *data, u32 _size,
108 struct nvkm_object **pobject)
110 struct nvkm_instobj_args *args = data;
111 struct gk20a_instmem_priv *priv = (void *)nvkm_instmem(parent);
112 struct device *dev = nv_device_base(nv_device(priv));
113 struct gk20a_instobj_priv *node;
118 nv_debug(parent, "%s: size: %x align: %x\n", __func__,
119 args->size, args->align);
121 size = max((args->size + 4095) & ~4095, (u32)4096);
122 align = max((args->align + 4095) & ~4095, (u32)4096);
124 npages = size >> PAGE_SHIFT;
126 ret = nvkm_instobj_create_(parent, engine, oclass, sizeof(*node),
128 *pobject = nv_object(node);
132 node->mem = &node->_mem;
134 node->cpuaddr = dma_alloc_attrs(dev, npages << PAGE_SHIFT,
135 &node->handle, GFP_KERNEL,
137 if (!node->cpuaddr) {
138 nv_error(priv, "cannot allocate DMA memory\n");
142 /* alignment check */
143 if (unlikely(node->handle & (align - 1)))
144 nv_warn(priv, "memory not aligned as requested: %pad (0x%x)\n",
145 &node->handle, align);
147 node->mem->offset = node->handle;
148 node->mem->size = size >> 12;
149 node->mem->memtype = 0;
150 node->mem->page_shift = 12;
151 INIT_LIST_HEAD(&node->mem->regions);
154 node->r.offset = node->handle >> 12;
155 node->r.length = npages;
156 list_add_tail(&node->r.rl_entry, &node->mem->regions);
158 node->base.addr = node->mem->offset;
159 node->base.size = size;
161 nv_debug(parent, "alloc size: 0x%x, align: 0x%x, gaddr: 0x%llx\n",
162 size, align, node->mem->offset);
167 static struct nvkm_instobj_impl
168 gk20a_instobj_oclass = {
169 .base.ofuncs = &(struct nvkm_ofuncs) {
170 .ctor = gk20a_instobj_ctor,
171 .dtor = gk20a_instobj_dtor,
172 .init = _nvkm_instobj_init,
173 .fini = _nvkm_instobj_fini,
174 .rd32 = gk20a_instobj_rd32,
175 .wr32 = gk20a_instobj_wr32,
182 gk20a_instmem_fini(struct nvkm_object *object, bool suspend)
184 struct gk20a_instmem_priv *priv = (void *)object;
186 return nvkm_instmem_fini(&priv->base, suspend);
190 gk20a_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
191 struct nvkm_oclass *oclass, void *data, u32 size,
192 struct nvkm_object **pobject)
194 struct gk20a_instmem_priv *priv;
197 ret = nvkm_instmem_create(parent, engine, oclass, &priv);
198 *pobject = nv_object(priv);
202 spin_lock_init(&priv->lock);
204 init_dma_attrs(&priv->attrs);
206 * We will access instmem through PRAMIN and thus do not need a
207 * consistent CPU pointer or kernel mapping
209 dma_set_attr(DMA_ATTR_NON_CONSISTENT, &priv->attrs);
210 dma_set_attr(DMA_ATTR_WEAK_ORDERING, &priv->attrs);
211 dma_set_attr(DMA_ATTR_WRITE_COMBINE, &priv->attrs);
212 dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &priv->attrs);
218 gk20a_instmem_oclass = &(struct nvkm_instmem_impl) {
219 .base.handle = NV_SUBDEV(INSTMEM, 0xea),
220 .base.ofuncs = &(struct nvkm_ofuncs) {
221 .ctor = gk20a_instmem_ctor,
222 .dtor = _nvkm_instmem_dtor,
223 .init = _nvkm_instmem_init,
224 .fini = gk20a_instmem_fini,
226 .instobj = &gk20a_instobj_oclass.base,