drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv04.h"
  25
  26 #include <core/ramht.h>
  27
  28 /******************************************************************************
  29  * instmem object implementation
  30  *****************************************************************************/
  31
  32 static u32
  33 nv04_instobj_rd32(struct nvkm_object *object, u64 addr)
  34 {
  35         struct nv04_instmem *imem = (void *)nvkm_instmem(object);
  36         struct nv04_instobj *node = (void *)object;
  37         return nv_ro32(imem, node->mem->offset + addr);
  38 }
  39
  40 static void
  41 nv04_instobj_wr32(struct nvkm_object *object, u64 addr, u32 data)
  42 {
  43         struct nv04_instmem *imem = (void *)nvkm_instmem(object);
  44         struct nv04_instobj *node = (void *)object;
  45         nv_wo32(imem, node->mem->offset + addr, data);
  46 }
  47
  48 static void
  49 nv04_instobj_dtor(struct nvkm_object *object)
  50 {
  51         struct nv04_instmem *imem = (void *)nvkm_instmem(object);
  52         struct nv04_instobj *node = (void *)object;
  53         mutex_lock(&imem->base.subdev.mutex);
  54         nvkm_mm_free(&imem->heap, &node->mem);
  55         mutex_unlock(&imem->base.subdev.mutex);
  56         nvkm_instobj_destroy(&node->base);
  57 }
  58
  59 static int
  60 nv04_instobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  61                   struct nvkm_oclass *oclass, void *data, u32 size,
  62                   struct nvkm_object **pobject)
  63 {
  64         struct nv04_instmem *imem = (void *)nvkm_instmem(parent);
  65         struct nv04_instobj *node;
  66         struct nvkm_instobj_args *args = data;
  67         int ret;
  68
  69         if (!args->align)
  70                 args->align = 1;
  71
  72         ret = nvkm_instobj_create(parent, engine, oclass, &node);
  73         *pobject = nv_object(node);
  74         if (ret)
  75                 return ret;
  76
  77         mutex_lock(&imem->base.subdev.mutex);
  78         ret = nvkm_mm_head(&imem->heap, 0, 1, args->size, args->size,
  79                            args->align, &node->mem);
  80         mutex_unlock(&imem->base.subdev.mutex);
  81         if (ret)
  82                 return ret;
  83
  84         node->base.addr = node->mem->offset;
  85         node->base.size = node->mem->length;
  86         return 0;
  87 }
  88
  89 struct nvkm_instobj_impl
  90 nv04_instobj_oclass = {
  91         .base.ofuncs = &(struct nvkm_ofuncs) {
  92                 .ctor = nv04_instobj_ctor,
  93                 .dtor = nv04_instobj_dtor,
  94                 .init = _nvkm_instobj_init,
  95                 .fini = _nvkm_instobj_fini,
  96                 .rd32 = nv04_instobj_rd32,
  97                 .wr32 = nv04_instobj_wr32,
  98         },
  99 };
 100
 101 /******************************************************************************
 102  * instmem subdev implementation
 103  *****************************************************************************/
 104
 105 static u32
 106 nv04_instmem_rd32(struct nvkm_object *object, u64 addr)
 107 {
 108         return nv_rd32(object, 0x700000 + addr);
 109 }
 110
 111 static void
 112 nv04_instmem_wr32(struct nvkm_object *object, u64 addr, u32 data)
 113 {
 114         return nv_wr32(object, 0x700000 + addr, data);
 115 }
 116
 117 void
 118 nv04_instmem_dtor(struct nvkm_object *object)
 119 {
 120         struct nv04_instmem *imem = (void *)object;
 121         nvkm_gpuobj_ref(NULL, &imem->ramfc);
 122         nvkm_gpuobj_ref(NULL, &imem->ramro);
 123         nvkm_ramht_ref(NULL, &imem->ramht);
 124         nvkm_gpuobj_ref(NULL, &imem->vbios);
 125         nvkm_mm_fini(&imem->heap);
 126         if (imem->iomem)
 127                 iounmap(imem->iomem);
 128         nvkm_instmem_destroy(&imem->base);
 129 }
 130
 131 static int
 132 nv04_instmem_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 133                   struct nvkm_oclass *oclass, void *data, u32 size,
 134                   struct nvkm_object **pobject)
 135 {
 136         struct nv04_instmem *imem;
 137         int ret;
 138
 139         ret = nvkm_instmem_create(parent, engine, oclass, &imem);
 140         *pobject = nv_object(imem);
 141         if (ret)
 142                 return ret;
 143
 144         /* PRAMIN aperture maps over the end of VRAM, reserve it */
 145         imem->base.reserved = 512 * 1024;
 146
 147         ret = nvkm_mm_init(&imem->heap, 0, imem->base.reserved, 1);
 148         if (ret)
 149                 return ret;
 150
 151         /* 0x00000-0x10000: reserve for probable vbios image */
 152         ret = nvkm_gpuobj_new(nv_object(imem), NULL, 0x10000, 0, 0,
 153                               &imem->vbios);
 154         if (ret)
 155                 return ret;
 156
 157         /* 0x10000-0x18000: reserve for RAMHT */
 158         ret = nvkm_ramht_new(nv_object(imem), NULL, 0x08000, 0, &imem->ramht);
 159         if (ret)
 160                 return ret;
 161
 162         /* 0x18000-0x18800: reserve for RAMFC (enough for 32 nv30 channels) */
 163         ret = nvkm_gpuobj_new(nv_object(imem), NULL, 0x00800, 0,
 164                               NVOBJ_FLAG_ZERO_ALLOC, &imem->ramfc);
 165         if (ret)
 166                 return ret;
 167
 168         /* 0x18800-0x18a00: reserve for RAMRO */
 169         ret = nvkm_gpuobj_new(nv_object(imem), NULL, 0x00200, 0, 0,
 170                               &imem->ramro);
 171         if (ret)
 172                 return ret;
 173
 174         return 0;
 175 }
 176
 177 struct nvkm_oclass *
 178 nv04_instmem_oclass = &(struct nvkm_instmem_impl) {
 179         .base.handle = NV_SUBDEV(INSTMEM, 0x04),
 180         .base.ofuncs = &(struct nvkm_ofuncs) {
 181                 .ctor = nv04_instmem_ctor,
 182                 .dtor = nv04_instmem_dtor,
 183                 .init = _nvkm_instmem_init,
 184                 .fini = _nvkm_instmem_fini,
 185                 .rd32 = nv04_instmem_rd32,
 186                 .wr32 = nv04_instmem_wr32,
 187         },
 188         .instobj = &nv04_instobj_oclass.base,
 189 }.base;