drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Ben Skeggs
  23  */
  24 #include "nv04.h"
  25
  26 #include <core/gpuobj.h>
  27 #include <core/option.h>
  28 #include <subdev/timer.h>
  29
  30 #define NV41_GART_SIZE (512 * 1024 * 1024)
  31 #define NV41_GART_PAGE (  4 * 1024)
  32
  33 /*******************************************************************************
  34  * VM map/unmap callbacks
  35  ******************************************************************************/
  36
  37 static void
  38 nv41_vm_map_sg(struct nvkm_vma *vma, struct nvkm_gpuobj *pgt,
  39                struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)
  40 {
  41         pte = pte * 4;
  42         while (cnt) {
  43                 u32 page = PAGE_SIZE / NV41_GART_PAGE;
  44                 u64 phys = (u64)*list++;
  45                 while (cnt && page--) {
  46                         nv_wo32(pgt, pte, (phys >> 7) | 1);
  47                         phys += NV41_GART_PAGE;
  48                         pte += 4;
  49                         cnt -= 1;
  50                 }
  51         }
  52 }
  53
  54 static void
  55 nv41_vm_unmap(struct nvkm_gpuobj *pgt, u32 pte, u32 cnt)
  56 {
  57         pte = pte * 4;
  58         while (cnt--) {
  59                 nv_wo32(pgt, pte, 0x00000000);
  60                 pte += 4;
  61         }
  62 }
  63
  64 static void
  65 nv41_vm_flush(struct nvkm_vm *vm)
  66 {
  67         struct nv04_mmu_priv *priv = (void *)vm->mmu;
  68
  69         mutex_lock(&nv_subdev(priv)->mutex);
  70         nv_wr32(priv, 0x100810, 0x00000022);
  71         if (!nv_wait(priv, 0x100810, 0x00000020, 0x00000020)) {
  72                 nv_warn(priv, "flush timeout, 0x%08x\n",
  73                         nv_rd32(priv, 0x100810));
  74         }
  75         nv_wr32(priv, 0x100810, 0x00000000);
  76         mutex_unlock(&nv_subdev(priv)->mutex);
  77 }
  78
  79 /*******************************************************************************
  80  * MMU subdev
  81  ******************************************************************************/
  82
  83 static int
  84 nv41_mmu_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
  85               struct nvkm_oclass *oclass, void *data, u32 size,
  86               struct nvkm_object **pobject)
  87 {
  88         struct nvkm_device *device = nv_device(parent);
  89         struct nv04_mmu_priv *priv;
  90         int ret;
  91
  92         if (pci_find_capability(device->pdev, PCI_CAP_ID_AGP) ||
  93             !nvkm_boolopt(device->cfgopt, "NvPCIE", true)) {
  94                 return nvkm_object_ctor(parent, engine, &nv04_mmu_oclass,
  95                                         data, size, pobject);
  96         }
  97
  98         ret = nvkm_mmu_create(parent, engine, oclass, "PCIEGART",
  99                               "pciegart", &priv);
 100         *pobject = nv_object(priv);
 101         if (ret)
 102                 return ret;
 103
 104         priv->base.create = nv04_vm_create;
 105         priv->base.limit = NV41_GART_SIZE;
 106         priv->base.dma_bits = 39;
 107         priv->base.pgt_bits = 32 - 12;
 108         priv->base.spg_shift = 12;
 109         priv->base.lpg_shift = 12;
 110         priv->base.map_sg = nv41_vm_map_sg;
 111         priv->base.unmap = nv41_vm_unmap;
 112         priv->base.flush = nv41_vm_flush;
 113
 114         ret = nvkm_vm_create(&priv->base, 0, NV41_GART_SIZE, 0, 4096,
 115                              &priv->vm);
 116         if (ret)
 117                 return ret;
 118
 119         ret = nvkm_gpuobj_new(nv_object(priv), NULL,
 120                               (NV41_GART_SIZE / NV41_GART_PAGE) * 4, 16,
 121                               NVOBJ_FLAG_ZERO_ALLOC,
 122                               &priv->vm->pgt[0].obj[0]);
 123         priv->vm->pgt[0].refcount[0] = 1;
 124         if (ret)
 125                 return ret;
 126
 127         return 0;
 128 }
 129
 130 static int
 131 nv41_mmu_init(struct nvkm_object *object)
 132 {
 133         struct nv04_mmu_priv *priv = (void *)object;
 134         struct nvkm_gpuobj *dma = priv->vm->pgt[0].obj[0];
 135         int ret;
 136
 137         ret = nvkm_mmu_init(&priv->base);
 138         if (ret)
 139                 return ret;
 140
 141         nv_wr32(priv, 0x100800, dma->addr | 0x00000002);
 142         nv_mask(priv, 0x10008c, 0x00000100, 0x00000100);
 143         nv_wr32(priv, 0x100820, 0x00000000);
 144         return 0;
 145 }
 146
 147 struct nvkm_oclass
 148 nv41_mmu_oclass = {
 149         .handle = NV_SUBDEV(MMU, 0x41),
 150         .ofuncs = &(struct nvkm_ofuncs) {
 151                 .ctor = nv41_mmu_ctor,
 152                 .dtor = nv04_mmu_dtor,
 153                 .init = nv41_mmu_init,
 154                 .fini = _nvkm_mmu_fini,
 155         },
 156 };