2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
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8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 * DEALINGS IN THE SOFTWARE.
24 #include <subdev/clk.h>
25 #include <subdev/timer.h>
26 #include <subdev/volt.h>
31 struct gk20a_pwr_dvfs_data {
35 unsigned int avg_load;
38 struct gk20a_pwr_priv {
39 struct nouveau_pwr base;
40 struct nouveau_alarm alarm;
41 struct gk20a_pwr_dvfs_data *data;
44 struct gk20a_pwr_dvfs_dev_status {
51 gk20a_pwr_dvfs_target(struct gk20a_pwr_priv *priv, int *state)
53 struct nouveau_clk *clk = nouveau_clk(priv);
55 return nouveau_clk_astate(clk, *state, 0, false);
59 gk20a_pwr_dvfs_get_cur_state(struct gk20a_pwr_priv *priv, int *state)
61 struct nouveau_clk *clk = nouveau_clk(priv);
68 gk20a_pwr_dvfs_get_target_state(struct gk20a_pwr_priv *priv,
71 struct gk20a_pwr_dvfs_data *data = priv->data;
72 struct nouveau_clk *clk = nouveau_clk(priv);
75 /* For GK20A, the performance level is directly mapped to pstate */
76 level = cur_level = clk->pstate;
78 if (load > data->p_load_max) {
79 level = min(clk->state_nr - 1, level + (clk->state_nr / 3));
81 level += ((load - data->p_load_target) * 10 /
82 data->p_load_target) / 2;
83 level = max(0, level);
84 level = min(clk->state_nr - 1, level);
87 nv_trace(priv, "cur level = %d, new level = %d\n", cur_level, level);
91 if (level == cur_level)
98 gk20a_pwr_dvfs_get_dev_status(struct gk20a_pwr_priv *priv,
99 struct gk20a_pwr_dvfs_dev_status *status)
101 status->busy = nv_rd32(priv, 0x10a508 + (BUSY_SLOT * 0x10));
102 status->total= nv_rd32(priv, 0x10a508 + (CLK_SLOT * 0x10));
107 gk20a_pwr_dvfs_reset_dev_status(struct gk20a_pwr_priv *priv)
109 nv_wr32(priv, 0x10a508 + (BUSY_SLOT * 0x10), 0x80000000);
110 nv_wr32(priv, 0x10a508 + (CLK_SLOT * 0x10), 0x80000000);
114 gk20a_pwr_dvfs_work(struct nouveau_alarm *alarm)
116 struct gk20a_pwr_priv *priv = container_of(alarm,
117 struct gk20a_pwr_priv, alarm);
118 struct gk20a_pwr_dvfs_data *data = priv->data;
119 struct gk20a_pwr_dvfs_dev_status status;
120 struct nouveau_clk *clk = nouveau_clk(priv);
121 struct nouveau_volt *volt = nouveau_volt(priv);
126 * The PWR is initialized before CLK and VOLT, so we have to make sure the
127 * CLK and VOLT are ready here.
132 ret = gk20a_pwr_dvfs_get_dev_status(priv, &status);
134 nv_warn(priv, "failed to get device status\n");
139 utilization = div_u64((u64)status.busy * 100, status.total);
141 data->avg_load = (data->p_smooth * data->avg_load) + utilization;
142 data->avg_load /= data->p_smooth + 1;
143 nv_trace(priv, "utilization = %d %%, avg_load = %d %%\n",
144 utilization, data->avg_load);
146 ret = gk20a_pwr_dvfs_get_cur_state(priv, &state);
148 nv_warn(priv, "failed to get current state\n");
152 if (gk20a_pwr_dvfs_get_target_state(priv, &state, data->avg_load)) {
153 nv_trace(priv, "set new state to %d\n", state);
154 gk20a_pwr_dvfs_target(priv, &state);
158 gk20a_pwr_dvfs_reset_dev_status(priv);
159 nouveau_timer_alarm(priv, 100000000, alarm);
163 gk20a_pwr_fini(struct nouveau_object *object, bool suspend)
165 struct nouveau_pwr *ppwr = (void *)object;
166 struct gk20a_pwr_priv *priv = (void *)ppwr;
168 nouveau_timer_alarm_cancel(priv, &priv->alarm);
170 return nouveau_subdev_fini(&ppwr->base, suspend);
174 gk20a_pwr_init(struct nouveau_object *object)
176 struct nouveau_pwr *ppwr = (void *)object;
177 struct gk20a_pwr_priv *priv = (void *)ppwr;
180 ret = nouveau_subdev_init(&ppwr->base);
184 ppwr->pgob = nouveau_pwr_pgob;
186 /* init pwr perf counter */
187 nv_wr32(ppwr, 0x10a504 + (BUSY_SLOT * 0x10), 0x00200001);
188 nv_wr32(ppwr, 0x10a50c + (BUSY_SLOT * 0x10), 0x00000002);
189 nv_wr32(ppwr, 0x10a50c + (CLK_SLOT * 0x10), 0x00000003);
191 nouveau_timer_alarm(ppwr, 2000000000, &priv->alarm);
196 struct gk20a_pwr_dvfs_data gk20a_dvfs_data= {
203 gk20a_pwr_ctor(struct nouveau_object *parent,
204 struct nouveau_object *engine,
205 struct nouveau_oclass *oclass, void *data, u32 size,
206 struct nouveau_object **pobject)
208 struct gk20a_pwr_priv *priv;
211 ret = nouveau_pwr_create(parent, engine, oclass, &priv);
212 *pobject = nv_object(priv);
216 priv->data = &gk20a_dvfs_data;
218 nouveau_alarm_init(&priv->alarm, gk20a_pwr_dvfs_work);
223 struct nouveau_oclass *
224 gk20a_pwr_oclass = &(struct nvkm_pwr_impl) {
225 .base.handle = NV_SUBDEV(PWR, 0xea),
226 .base.ofuncs = &(struct nouveau_ofuncs) {
227 .ctor = gk20a_pwr_ctor,
228 .dtor = _nouveau_pwr_dtor,
229 .init = gk20a_pwr_init,
230 .fini = gk20a_pwr_fini,