2 * Copyright 2012 Red Hat Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include <core/device.h>
29 struct nv40_therm_priv {
30 struct nvkm_therm_priv base;
33 enum nv40_sensor_style { INVALID_STYLE = -1, OLD_STYLE = 0, NEW_STYLE = 1 };
35 static enum nv40_sensor_style
36 nv40_sensor_style(struct nvkm_therm *therm)
38 struct nvkm_device *device = nv_device(therm);
40 switch (device->chipset) {
62 nv40_sensor_setup(struct nvkm_therm *therm)
64 enum nv40_sensor_style style = nv40_sensor_style(therm);
66 /* enable ADC readout and disable the ALARM threshold */
67 if (style == NEW_STYLE) {
68 nv_mask(therm, 0x15b8, 0x80000000, 0);
69 nv_wr32(therm, 0x15b0, 0x80003fff);
70 mdelay(20); /* wait for the temperature to stabilize */
71 return nv_rd32(therm, 0x15b4) & 0x3fff;
72 } else if (style == OLD_STYLE) {
73 nv_wr32(therm, 0x15b0, 0xff);
74 mdelay(20); /* wait for the temperature to stabilize */
75 return nv_rd32(therm, 0x15b4) & 0xff;
81 nv40_temp_get(struct nvkm_therm *therm)
83 struct nvkm_therm_priv *priv = (void *)therm;
84 struct nvbios_therm_sensor *sensor = &priv->bios_sensor;
85 enum nv40_sensor_style style = nv40_sensor_style(therm);
88 if (style == NEW_STYLE) {
89 nv_wr32(therm, 0x15b0, 0x80003fff);
90 core_temp = nv_rd32(therm, 0x15b4) & 0x3fff;
91 } else if (style == OLD_STYLE) {
92 nv_wr32(therm, 0x15b0, 0xff);
93 core_temp = nv_rd32(therm, 0x15b4) & 0xff;
97 /* if the slope or the offset is unset, do no use the sensor */
98 if (!sensor->slope_div || !sensor->slope_mult ||
99 !sensor->offset_num || !sensor->offset_den)
102 core_temp = core_temp * sensor->slope_mult / sensor->slope_div;
103 core_temp = core_temp + sensor->offset_num / sensor->offset_den;
104 core_temp = core_temp + sensor->offset_constant - 8;
106 /* reserve negative temperatures for errors */
114 nv40_fan_pwm_ctrl(struct nvkm_therm *therm, int line, bool enable)
116 u32 mask = enable ? 0x80000000 : 0x0000000;
117 if (line == 2) nv_mask(therm, 0x0010f0, 0x80000000, mask);
118 else if (line == 9) nv_mask(therm, 0x0015f4, 0x80000000, mask);
120 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
127 nv40_fan_pwm_get(struct nvkm_therm *therm, int line, u32 *divs, u32 *duty)
130 u32 reg = nv_rd32(therm, 0x0010f0);
131 if (reg & 0x80000000) {
132 *duty = (reg & 0x7fff0000) >> 16;
133 *divs = (reg & 0x00007fff);
138 u32 reg = nv_rd32(therm, 0x0015f4);
139 if (reg & 0x80000000) {
140 *divs = nv_rd32(therm, 0x0015f8);
141 *duty = (reg & 0x7fffffff);
145 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
153 nv40_fan_pwm_set(struct nvkm_therm *therm, int line, u32 divs, u32 duty)
156 nv_mask(therm, 0x0010f0, 0x7fff7fff, (duty << 16) | divs);
159 nv_wr32(therm, 0x0015f8, divs);
160 nv_mask(therm, 0x0015f4, 0x7fffffff, duty);
162 nv_error(therm, "unknown pwm ctrl for gpio %d\n", line);
170 nv40_therm_intr(struct nvkm_subdev *subdev)
172 struct nvkm_therm *therm = nvkm_therm(subdev);
173 uint32_t stat = nv_rd32(therm, 0x1100);
178 nv_wr32(therm, 0x1100, 0x70000);
180 nv_error(therm, "THERM received an IRQ: stat = %x\n", stat);
184 nv40_therm_ctor(struct nvkm_object *parent,
185 struct nvkm_object *engine,
186 struct nvkm_oclass *oclass, void *data, u32 size,
187 struct nvkm_object **pobject)
189 struct nv40_therm_priv *priv;
192 ret = nvkm_therm_create(parent, engine, oclass, &priv);
193 *pobject = nv_object(priv);
197 priv->base.base.pwm_ctrl = nv40_fan_pwm_ctrl;
198 priv->base.base.pwm_get = nv40_fan_pwm_get;
199 priv->base.base.pwm_set = nv40_fan_pwm_set;
200 priv->base.base.temp_get = nv40_temp_get;
201 priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling;
202 nv_subdev(priv)->intr = nv40_therm_intr;
203 return nvkm_therm_preinit(&priv->base.base);
207 nv40_therm_init(struct nvkm_object *object)
209 struct nvkm_therm *therm = (void *)object;
211 nv40_sensor_setup(therm);
213 return _nvkm_therm_init(object);
217 nv40_therm_oclass = {
218 .handle = NV_SUBDEV(THERM, 0x40),
219 .ofuncs = &(struct nvkm_ofuncs) {
220 .ctor = nv40_therm_ctor,
221 .dtor = _nvkm_therm_dtor,
222 .init = nv40_therm_init,
223 .fini = _nvkm_therm_fini,