2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
36 #include <video/display_timing.h>
37 #include <video/mipi_display.h>
38 #include <video/of_display_timing.h>
39 #include <video/videomode.h>
42 u8 dtype; /* data type */
44 u8 dlen; /* payload len */
48 struct dsi_ctrl_hdr dchdr;
52 struct dsi_panel_cmds {
55 struct dsi_cmd_desc *cmds;
60 const struct drm_display_mode *modes;
61 unsigned int num_modes;
62 const struct display_timing *timings;
63 unsigned int num_timings;
73 * @reset: the time (in milliseconds) indicates the delay time
74 * after the panel to operate reset gpio
75 * @init: the time (in milliseconds) that it takes for the panel to
76 * power on and dsi host can send command to panel
77 * @prepare: the time (in milliseconds) that it takes for the panel to
78 * become ready and start receiving video data
79 * @enable: the time (in milliseconds) that it takes for the panel to
80 * display the first valid frame after starting to receive
82 * @disable: the time (in milliseconds) that it takes for the panel to
83 * turn the display off (no content is visible)
84 * @unprepare: the time (in milliseconds) that it takes for the panel
85 * to power itself down completely
93 unsigned int unprepare;
100 struct drm_panel base;
101 struct mipi_dsi_device *dsi;
106 const struct panel_desc *desc;
108 struct backlight_device *backlight;
109 struct regulator *supply;
110 struct i2c_adapter *ddc;
112 struct gpio_desc *enable_gpio;
113 struct gpio_desc *reset_gpio;
115 struct dsi_panel_cmds *on_cmds;
116 struct dsi_panel_cmds *off_cmds;
119 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
121 return container_of(panel, struct panel_simple, base);
124 static void panel_simple_dsi_cmds_cleanup(struct panel_simple *p)
127 kfree(p->on_cmds->buf);
128 kfree(p->on_cmds->cmds);
132 kfree(p->off_cmds->buf);
133 kfree(p->off_cmds->cmds);
137 static int panel_simple_dsi_parse_dcs_cmds(struct device *dev,
138 const u8 *data, int blen,
139 struct dsi_panel_cmds *pcmds)
143 struct dsi_ctrl_hdr *dchdr;
149 buf = kmemdup(data, blen, GFP_KERNEL);
153 /* scan dcs commands */
157 while (len > sizeof(*dchdr)) {
158 dchdr = (struct dsi_ctrl_hdr *)bp;
160 if (dchdr->dlen > len) {
161 dev_err(dev, "%s: error, len=%d", __func__,
166 bp += sizeof(*dchdr);
167 len -= sizeof(*dchdr);
174 dev_err(dev, "%s: dcs_cmd=%x len=%d error!",
175 __func__, buf[0], blen);
180 pcmds->cmds = kcalloc(cnt, sizeof(struct dsi_cmd_desc), GFP_KERNEL);
186 pcmds->cmd_cnt = cnt;
192 for (i = 0; i < cnt; i++) {
193 dchdr = (struct dsi_ctrl_hdr *)bp;
194 len -= sizeof(*dchdr);
195 bp += sizeof(*dchdr);
196 pcmds->cmds[i].dchdr = *dchdr;
197 pcmds->cmds[i].payload = bp;
202 dev_info(dev, "%s: dcs_cmd=%x len=%d, cmd_cnt=%d\n", __func__,
203 pcmds->buf[0], pcmds->blen, pcmds->cmd_cnt);
207 static int panel_simple_dsi_send_cmds(struct panel_simple *panel,
208 struct dsi_panel_cmds *cmds)
210 struct mipi_dsi_device *dsi = panel->dsi;
216 for (i = 0; i < cmds->cmd_cnt; i++) {
217 struct dsi_cmd_desc *cmd = &cmds->cmds[i];
219 switch (cmd->dchdr.dtype) {
220 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
221 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
222 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
223 case MIPI_DSI_GENERIC_LONG_WRITE:
224 err = mipi_dsi_generic_write(dsi, cmd->payload,
227 case MIPI_DSI_DCS_SHORT_WRITE:
228 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
229 case MIPI_DSI_DCS_LONG_WRITE:
230 err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
238 dev_err(panel->dev, "failed to write dcs cmd: %d\n",
242 msleep(cmd->dchdr.wait);
248 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
250 struct drm_connector *connector = panel->base.connector;
251 struct drm_device *drm = panel->base.drm;
252 struct drm_display_mode *mode;
253 unsigned int i, num = 0;
258 for (i = 0; i < panel->desc->num_timings; i++) {
259 const struct display_timing *dt = &panel->desc->timings[i];
262 videomode_from_timing(dt, &vm);
263 mode = drm_mode_create(drm);
265 dev_err(drm->dev, "failed to add mode %ux%u\n",
266 dt->hactive.typ, dt->vactive.typ);
270 drm_display_mode_from_videomode(&vm, mode);
271 drm_mode_set_name(mode);
273 drm_mode_probed_add(connector, mode);
277 for (i = 0; i < panel->desc->num_modes; i++) {
278 const struct drm_display_mode *m = &panel->desc->modes[i];
280 mode = drm_mode_duplicate(drm, m);
282 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
283 m->hdisplay, m->vdisplay, m->vrefresh);
287 drm_mode_set_name(mode);
289 drm_mode_probed_add(connector, mode);
293 connector->display_info.bpc = panel->desc->bpc;
294 connector->display_info.width_mm = panel->desc->size.width;
295 connector->display_info.height_mm = panel->desc->size.height;
296 if (panel->desc->bus_format)
297 drm_display_info_set_bus_formats(&connector->display_info,
298 &panel->desc->bus_format, 1);
303 static int panel_simple_of_get_native_mode(struct panel_simple *panel)
305 struct drm_connector *connector = panel->base.connector;
306 struct drm_device *drm = panel->base.drm;
307 struct drm_display_mode *mode;
308 struct device_node *timings_np;
311 timings_np = of_get_child_by_name(panel->dev->of_node,
314 dev_dbg(panel->dev, "failed to find display-timings node\n");
318 of_node_put(timings_np);
319 mode = drm_mode_create(drm);
323 ret = of_get_drm_display_mode(panel->dev->of_node, mode,
326 dev_dbg(panel->dev, "failed to find dts display timings\n");
327 drm_mode_destroy(drm, mode);
331 drm_mode_set_name(mode);
332 mode->type |= DRM_MODE_TYPE_PREFERRED;
333 drm_mode_probed_add(connector, mode);
338 static int panel_simple_loader_protect(struct drm_panel *panel, bool on)
340 struct panel_simple *p = to_panel_simple(panel);
344 err = regulator_enable(p->supply);
346 dev_err(panel->dev, "failed to enable supply: %d\n",
351 regulator_disable(p->supply);
357 static int panel_simple_disable(struct drm_panel *panel)
359 struct panel_simple *p = to_panel_simple(panel);
365 p->backlight->props.power = FB_BLANK_POWERDOWN;
366 backlight_update_status(p->backlight);
369 if (p->desc && p->desc->delay.disable)
370 msleep(p->desc->delay.disable);
377 static int panel_simple_unprepare(struct drm_panel *panel)
379 struct panel_simple *p = to_panel_simple(panel);
386 err = panel_simple_dsi_send_cmds(p, p->off_cmds);
388 dev_err(p->dev, "failed to send off cmds\n");
392 gpiod_direction_output(p->reset_gpio, 1);
395 gpiod_direction_output(p->enable_gpio, 0);
397 regulator_disable(p->supply);
399 if (p->desc && p->desc->delay.unprepare)
400 msleep(p->desc->delay.unprepare);
407 static int panel_simple_prepare(struct drm_panel *panel)
409 struct panel_simple *p = to_panel_simple(panel);
415 err = regulator_enable(p->supply);
417 dev_err(panel->dev, "failed to enable supply: %d\n", err);
422 gpiod_direction_output(p->enable_gpio, 1);
424 if (p->desc && p->desc->delay.prepare)
425 msleep(p->desc->delay.prepare);
428 gpiod_direction_output(p->reset_gpio, 1);
430 if (p->desc && p->desc->delay.reset)
431 msleep(p->desc->delay.reset);
434 gpiod_direction_output(p->reset_gpio, 0);
436 if (p->desc && p->desc->delay.init)
437 msleep(p->desc->delay.init);
440 err = panel_simple_dsi_send_cmds(p, p->on_cmds);
442 dev_err(p->dev, "failed to send on cmds\n");
450 static int panel_simple_enable(struct drm_panel *panel)
452 struct panel_simple *p = to_panel_simple(panel);
457 if (p->desc && p->desc->delay.enable)
458 msleep(p->desc->delay.enable);
461 p->backlight->props.power = FB_BLANK_UNBLANK;
462 backlight_update_status(p->backlight);
470 static int panel_simple_get_modes(struct drm_panel *panel)
472 struct panel_simple *p = to_panel_simple(panel);
475 /* add device node plane modes */
476 num += panel_simple_of_get_native_mode(p);
478 /* add hard-coded panel modes */
479 num += panel_simple_get_fixed_modes(p);
481 /* probe EDID if a DDC bus is available */
483 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
484 drm_mode_connector_update_edid_property(panel->connector, edid);
486 num += drm_add_edid_modes(panel->connector, edid);
494 static int panel_simple_get_timings(struct drm_panel *panel,
495 unsigned int num_timings,
496 struct display_timing *timings)
498 struct panel_simple *p = to_panel_simple(panel);
504 if (p->desc->num_timings < num_timings)
505 num_timings = p->desc->num_timings;
508 for (i = 0; i < num_timings; i++)
509 timings[i] = p->desc->timings[i];
511 return p->desc->num_timings;
514 static const struct drm_panel_funcs panel_simple_funcs = {
515 .loader_protect = panel_simple_loader_protect,
516 .disable = panel_simple_disable,
517 .unprepare = panel_simple_unprepare,
518 .prepare = panel_simple_prepare,
519 .enable = panel_simple_enable,
520 .get_modes = panel_simple_get_modes,
521 .get_timings = panel_simple_get_timings,
524 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
526 struct device_node *backlight, *ddc;
527 struct panel_simple *panel;
528 struct panel_desc *of_desc;
532 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
537 of_desc = devm_kzalloc(dev, sizeof(*of_desc), GFP_KERNEL);
539 of_desc = devm_kmemdup(dev, desc, sizeof(*of_desc), GFP_KERNEL);
541 if (!of_property_read_u32(dev->of_node, "bus-format", &val))
542 of_desc->bus_format = val;
543 if (!of_property_read_u32(dev->of_node, "prepare-delay-ms", &val))
544 of_desc->delay.prepare = val;
545 if (!of_property_read_u32(dev->of_node, "enable-delay-ms", &val))
546 of_desc->delay.enable = val;
547 if (!of_property_read_u32(dev->of_node, "disable-delay-ms", &val))
548 of_desc->delay.disable = val;
549 if (!of_property_read_u32(dev->of_node, "unprepare-delay-ms", &val))
550 of_desc->delay.unprepare = val;
551 if (!of_property_read_u32(dev->of_node, "reset-delay-ms", &val))
552 of_desc->delay.reset = val;
553 if (!of_property_read_u32(dev->of_node, "init-delay-ms", &val))
554 of_desc->delay.init = val;
556 panel->enabled = false;
557 panel->prepared = false;
558 panel->desc = of_desc;
561 panel->supply = devm_regulator_get(dev, "power");
562 if (IS_ERR(panel->supply))
563 return PTR_ERR(panel->supply);
565 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 0);
566 if (IS_ERR(panel->enable_gpio)) {
567 err = PTR_ERR(panel->enable_gpio);
568 dev_err(dev, "failed to request enable GPIO: %d\n", err);
572 panel->reset_gpio = devm_gpiod_get_optional(dev, "reset", 0);
573 if (IS_ERR(panel->reset_gpio)) {
574 err = PTR_ERR(panel->reset_gpio);
575 dev_err(dev, "failed to request reset GPIO: %d\n", err);
579 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
581 panel->backlight = of_find_backlight_by_node(backlight);
582 of_node_put(backlight);
584 if (!panel->backlight)
585 return -EPROBE_DEFER;
588 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
590 panel->ddc = of_find_i2c_adapter_by_node(ddc);
599 drm_panel_init(&panel->base);
600 panel->base.dev = dev;
601 panel->base.funcs = &panel_simple_funcs;
603 err = drm_panel_add(&panel->base);
607 dev_set_drvdata(dev, panel);
613 put_device(&panel->ddc->dev);
615 if (panel->backlight)
616 put_device(&panel->backlight->dev);
621 static int panel_simple_remove(struct device *dev)
623 struct panel_simple *panel = dev_get_drvdata(dev);
625 drm_panel_detach(&panel->base);
626 drm_panel_remove(&panel->base);
628 panel_simple_disable(&panel->base);
631 put_device(&panel->ddc->dev);
633 if (panel->backlight)
634 put_device(&panel->backlight->dev);
636 panel_simple_dsi_cmds_cleanup(panel);
641 static void panel_simple_shutdown(struct device *dev)
643 struct panel_simple *panel = dev_get_drvdata(dev);
645 panel_simple_disable(&panel->base);
648 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
651 .hsync_start = 800 + 0,
652 .hsync_end = 800 + 0 + 255,
653 .htotal = 800 + 0 + 255 + 0,
655 .vsync_start = 480 + 2,
656 .vsync_end = 480 + 2 + 45,
657 .vtotal = 480 + 2 + 45 + 0,
659 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
662 static const struct panel_desc ampire_am800480r3tmqwa1h = {
663 .modes = &ire_am800480r3tmqwa1h_mode,
670 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
673 static const struct drm_display_mode auo_b101aw03_mode = {
676 .hsync_start = 1024 + 156,
677 .hsync_end = 1024 + 156 + 8,
678 .htotal = 1024 + 156 + 8 + 156,
680 .vsync_start = 600 + 16,
681 .vsync_end = 600 + 16 + 6,
682 .vtotal = 600 + 16 + 6 + 16,
686 static const struct panel_desc auo_b101aw03 = {
687 .modes = &auo_b101aw03_mode,
696 static const struct drm_display_mode auo_b101ean01_mode = {
699 .hsync_start = 1280 + 119,
700 .hsync_end = 1280 + 119 + 32,
701 .htotal = 1280 + 119 + 32 + 21,
703 .vsync_start = 800 + 4,
704 .vsync_end = 800 + 4 + 20,
705 .vtotal = 800 + 4 + 20 + 8,
709 static const struct panel_desc auo_b101ean01 = {
710 .modes = &auo_b101ean01_mode,
719 static const struct drm_display_mode auo_b101ew05_mode = {
722 .hsync_start = 1280 + 18,
723 .hsync_end = 1280 + 18 + 100,
724 .htotal = 1280 + 18 + 100 + 10,
726 .vsync_start = 800 + 6,
727 .vsync_end = 800 + 6 + 8,
728 .vtotal = 800 + 6 + 8 + 2,
732 static const struct panel_desc auo_b101ew05 = {
733 .modes = &auo_b101ew05_mode,
742 static const struct drm_display_mode auo_b101xtn01_mode = {
745 .hsync_start = 1366 + 20,
746 .hsync_end = 1366 + 20 + 70,
747 .htotal = 1366 + 20 + 70,
749 .vsync_start = 768 + 14,
750 .vsync_end = 768 + 14 + 42,
751 .vtotal = 768 + 14 + 42,
753 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
756 static const struct panel_desc auo_b101xtn01 = {
757 .modes = &auo_b101xtn01_mode,
766 static const struct drm_display_mode auo_b116xw03_mode = {
769 .hsync_start = 1366 + 40,
770 .hsync_end = 1366 + 40 + 40,
771 .htotal = 1366 + 40 + 40 + 32,
773 .vsync_start = 768 + 10,
774 .vsync_end = 768 + 10 + 12,
775 .vtotal = 768 + 10 + 12 + 6,
779 static const struct panel_desc auo_b116xw03 = {
780 .modes = &auo_b116xw03_mode,
789 static const struct drm_display_mode auo_b125han03_mode = {
792 .hsync_start = 1920 + 48,
793 .hsync_end = 1920 + 48 + 32,
794 .htotal = 1920 + 48 + 32 + 140,
796 .vsync_start = 1080 + 2,
797 .vsync_end = 1080 + 2 + 5,
798 .vtotal = 1080 + 2 + 5 + 57,
800 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
803 static const struct panel_desc auo_b125han03 = {
804 .modes = &auo_b125han03_mode,
811 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
814 static const struct drm_display_mode auo_b133xtn01_mode = {
817 .hsync_start = 1366 + 48,
818 .hsync_end = 1366 + 48 + 32,
819 .htotal = 1366 + 48 + 32 + 20,
821 .vsync_start = 768 + 3,
822 .vsync_end = 768 + 3 + 6,
823 .vtotal = 768 + 3 + 6 + 13,
827 static const struct panel_desc auo_b133xtn01 = {
828 .modes = &auo_b133xtn01_mode,
837 static const struct drm_display_mode auo_b133htn01_mode = {
840 .hsync_start = 1920 + 172,
841 .hsync_end = 1920 + 172 + 80,
842 .htotal = 1920 + 172 + 80 + 60,
844 .vsync_start = 1080 + 25,
845 .vsync_end = 1080 + 25 + 10,
846 .vtotal = 1080 + 25 + 10 + 10,
850 static const struct panel_desc auo_b133htn01 = {
851 .modes = &auo_b133htn01_mode,
865 static const struct drm_display_mode avic_tm070ddh03_mode = {
868 .hsync_start = 1024 + 160,
869 .hsync_end = 1024 + 160 + 4,
870 .htotal = 1024 + 160 + 4 + 156,
872 .vsync_start = 600 + 17,
873 .vsync_end = 600 + 17 + 1,
874 .vtotal = 600 + 17 + 1 + 17,
878 static const struct panel_desc avic_tm070ddh03 = {
879 .modes = &avic_tm070ddh03_mode,
893 static const struct drm_display_mode boe_nv125fhm_n73_mode = {
896 .hsync_start = 1366 + 80,
897 .hsync_end = 1366 + 80 + 20,
898 .htotal = 1366 + 80 + 20 + 60,
900 .vsync_start = 768 + 12,
901 .vsync_end = 768 + 12 + 2,
902 .vtotal = 768 + 12 + 2 + 8,
904 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
907 static const struct panel_desc boe_nv125fhm_n73 = {
908 .modes = &boe_nv125fhm_n73_mode,
918 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
921 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
924 .hsync_start = 800 + 24,
925 .hsync_end = 800 + 24 + 16,
926 .htotal = 800 + 24 + 16 + 24,
928 .vsync_start = 1280 + 2,
929 .vsync_end = 1280 + 2 + 2,
930 .vtotal = 1280 + 2 + 2 + 4,
934 static const struct panel_desc chunghwa_claa070wp03xg = {
935 .modes = &chunghwa_claa070wp03xg_mode,
944 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
947 .hsync_start = 1366 + 58,
948 .hsync_end = 1366 + 58 + 58,
949 .htotal = 1366 + 58 + 58 + 58,
951 .vsync_start = 768 + 4,
952 .vsync_end = 768 + 4 + 4,
953 .vtotal = 768 + 4 + 4 + 4,
957 static const struct panel_desc chunghwa_claa101wa01a = {
958 .modes = &chunghwa_claa101wa01a_mode,
967 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
970 .hsync_start = 1366 + 48,
971 .hsync_end = 1366 + 48 + 32,
972 .htotal = 1366 + 48 + 32 + 20,
974 .vsync_start = 768 + 16,
975 .vsync_end = 768 + 16 + 8,
976 .vtotal = 768 + 16 + 8 + 16,
980 static const struct panel_desc chunghwa_claa101wb01 = {
981 .modes = &chunghwa_claa101wb01_mode,
990 static const struct drm_display_mode edt_et057090dhu_mode = {
993 .hsync_start = 640 + 16,
994 .hsync_end = 640 + 16 + 30,
995 .htotal = 640 + 16 + 30 + 114,
997 .vsync_start = 480 + 10,
998 .vsync_end = 480 + 10 + 3,
999 .vtotal = 480 + 10 + 3 + 32,
1001 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1004 static const struct panel_desc edt_et057090dhu = {
1005 .modes = &edt_et057090dhu_mode,
1014 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1017 .hsync_start = 800 + 40,
1018 .hsync_end = 800 + 40 + 128,
1019 .htotal = 800 + 40 + 128 + 88,
1021 .vsync_start = 480 + 10,
1022 .vsync_end = 480 + 10 + 2,
1023 .vtotal = 480 + 10 + 2 + 33,
1025 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1028 static const struct panel_desc edt_etm0700g0dh6 = {
1029 .modes = &edt_etm0700g0dh6_mode,
1038 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1041 .hsync_start = 800 + 168,
1042 .hsync_end = 800 + 168 + 64,
1043 .htotal = 800 + 168 + 64 + 88,
1045 .vsync_start = 480 + 37,
1046 .vsync_end = 480 + 37 + 2,
1047 .vtotal = 480 + 37 + 2 + 8,
1051 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1052 .modes = &foxlink_fl500wvr00_a0t_mode,
1059 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1062 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1065 .hsync_start = 480 + 5,
1066 .hsync_end = 480 + 5 + 1,
1067 .htotal = 480 + 5 + 1 + 40,
1069 .vsync_start = 272 + 8,
1070 .vsync_end = 272 + 8 + 1,
1071 .vtotal = 272 + 8 + 1 + 8,
1075 static const struct panel_desc giantplus_gpg482739qs5 = {
1076 .modes = &giantplus_gpg482739qs5_mode,
1083 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1086 static const struct display_timing hannstar_hsd070pww1_timing = {
1087 .pixelclock = { 64300000, 71100000, 82000000 },
1088 .hactive = { 1280, 1280, 1280 },
1089 .hfront_porch = { 1, 1, 10 },
1090 .hback_porch = { 1, 1, 10 },
1092 * According to the data sheet, the minimum horizontal blanking interval
1093 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1094 * minimum working horizontal blanking interval to be 60 clocks.
1096 .hsync_len = { 58, 158, 661 },
1097 .vactive = { 800, 800, 800 },
1098 .vfront_porch = { 1, 1, 10 },
1099 .vback_porch = { 1, 1, 10 },
1100 .vsync_len = { 1, 21, 203 },
1101 .flags = DISPLAY_FLAGS_DE_HIGH,
1104 static const struct panel_desc hannstar_hsd070pww1 = {
1105 .timings = &hannstar_hsd070pww1_timing,
1112 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1115 static const struct display_timing hannstar_hsd100pxn1_timing = {
1116 .pixelclock = { 55000000, 65000000, 75000000 },
1117 .hactive = { 1024, 1024, 1024 },
1118 .hfront_porch = { 40, 40, 40 },
1119 .hback_porch = { 220, 220, 220 },
1120 .hsync_len = { 20, 60, 100 },
1121 .vactive = { 768, 768, 768 },
1122 .vfront_porch = { 7, 7, 7 },
1123 .vback_porch = { 21, 21, 21 },
1124 .vsync_len = { 10, 10, 10 },
1125 .flags = DISPLAY_FLAGS_DE_HIGH,
1128 static const struct panel_desc hannstar_hsd100pxn1 = {
1129 .timings = &hannstar_hsd100pxn1_timing,
1136 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1139 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1142 .hsync_start = 800 + 85,
1143 .hsync_end = 800 + 85 + 86,
1144 .htotal = 800 + 85 + 86 + 85,
1146 .vsync_start = 480 + 16,
1147 .vsync_end = 480 + 16 + 13,
1148 .vtotal = 480 + 16 + 13 + 16,
1152 static const struct panel_desc hitachi_tx23d38vm0caa = {
1153 .modes = &hitachi_tx23d38vm0caa_mode,
1162 static const struct drm_display_mode innolux_at043tn24_mode = {
1165 .hsync_start = 480 + 2,
1166 .hsync_end = 480 + 2 + 41,
1167 .htotal = 480 + 2 + 41 + 2,
1169 .vsync_start = 272 + 2,
1170 .vsync_end = 272 + 2 + 11,
1171 .vtotal = 272 + 2 + 11 + 2,
1173 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1176 static const struct panel_desc innolux_at043tn24 = {
1177 .modes = &innolux_at043tn24_mode,
1184 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1187 static const struct drm_display_mode innolux_g121i1_l01_mode = {
1190 .hsync_start = 1280 + 64,
1191 .hsync_end = 1280 + 64 + 32,
1192 .htotal = 1280 + 64 + 32 + 64,
1194 .vsync_start = 800 + 9,
1195 .vsync_end = 800 + 9 + 6,
1196 .vtotal = 800 + 9 + 6 + 9,
1200 static const struct panel_desc innolux_g121i1_l01 = {
1201 .modes = &innolux_g121i1_l01_mode,
1210 static const struct drm_display_mode innolux_n116bge_mode = {
1213 .hsync_start = 1366 + 136,
1214 .hsync_end = 1366 + 136 + 30,
1215 .htotal = 1366 + 136 + 30 + 60,
1217 .vsync_start = 768 + 8,
1218 .vsync_end = 768 + 8 + 12,
1219 .vtotal = 768 + 8 + 12 + 12,
1221 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1224 static const struct panel_desc innolux_n116bge = {
1225 .modes = &innolux_n116bge_mode,
1234 static const struct drm_display_mode innolux_n125hce_mode = {
1237 .hsync_start = 1920 + 80,
1238 .hsync_end = 1920 + 80 + 30,
1239 .htotal = 1920 + 80 + 30 + 50,
1241 .vsync_start = 1080 + 12,
1242 .vsync_end = 1080 + 12 + 4,
1243 .vtotal = 1080 + 12 + 4 + 16,
1245 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1248 static const struct panel_desc innolux_n125hce = {
1249 .modes = &innolux_n125hce_mode,
1260 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1263 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1266 .hsync_start = 1366 + 16,
1267 .hsync_end = 1366 + 16 + 34,
1268 .htotal = 1366 + 16 + 34 + 50,
1270 .vsync_start = 768 + 2,
1271 .vsync_end = 768 + 2 + 6,
1272 .vtotal = 768 + 2 + 6 + 12,
1276 static const struct panel_desc innolux_n156bge_l21 = {
1277 .modes = &innolux_n156bge_l21_mode,
1286 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1289 .hsync_start = 1024 + 128,
1290 .hsync_end = 1024 + 128 + 64,
1291 .htotal = 1024 + 128 + 64 + 128,
1293 .vsync_start = 600 + 16,
1294 .vsync_end = 600 + 16 + 4,
1295 .vtotal = 600 + 16 + 4 + 16,
1299 static const struct panel_desc innolux_zj070na_01p = {
1300 .modes = &innolux_zj070na_01p_mode,
1309 static const struct drm_display_mode lg_lb070wv8_mode = {
1312 .hsync_start = 800 + 88,
1313 .hsync_end = 800 + 88 + 80,
1314 .htotal = 800 + 88 + 80 + 88,
1316 .vsync_start = 480 + 10,
1317 .vsync_end = 480 + 10 + 25,
1318 .vtotal = 480 + 10 + 25 + 10,
1322 static const struct panel_desc lg_lb070wv8 = {
1323 .modes = &lg_lb070wv8_mode,
1330 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1333 static const struct drm_display_mode sharp_lcd_f402_mode = {
1336 .hsync_start = 1536 + 12,
1337 .hsync_end = 1536 + 12 + 48,
1338 .htotal = 1536 + 12 + 48 + 16,
1340 .vsync_start = 2048 + 8,
1341 .vsync_end = 2048 + 8 + 8,
1342 .vtotal = 2048 + 8 + 8 + 4,
1344 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1347 static const struct panel_desc sharp_lcd_f402 = {
1348 .modes = &sharp_lcd_f402_mode,
1355 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1358 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1361 .hsync_start = 1536 + 12,
1362 .hsync_end = 1536 + 12 + 16,
1363 .htotal = 1536 + 12 + 16 + 48,
1365 .vsync_start = 2048 + 8,
1366 .vsync_end = 2048 + 8 + 4,
1367 .vtotal = 2048 + 8 + 4 + 8,
1369 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1372 static const struct panel_desc lg_lp079qx1_sp0v = {
1373 .modes = &lg_lp079qx1_sp0v_mode,
1379 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1382 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1385 .hsync_start = 2048 + 150,
1386 .hsync_end = 2048 + 150 + 5,
1387 .htotal = 2048 + 150 + 5 + 5,
1389 .vsync_start = 1536 + 3,
1390 .vsync_end = 1536 + 3 + 1,
1391 .vtotal = 1536 + 3 + 1 + 9,
1395 static const struct panel_desc lg_lp097qx1_spa1 = {
1396 .modes = &lg_lp097qx1_spa1_mode,
1404 static const struct drm_display_mode lg_lp129qe_mode = {
1407 .hsync_start = 2560 + 48,
1408 .hsync_end = 2560 + 48 + 32,
1409 .htotal = 2560 + 48 + 32 + 80,
1411 .vsync_start = 1700 + 3,
1412 .vsync_end = 1700 + 3 + 10,
1413 .vtotal = 1700 + 3 + 10 + 36,
1417 static const struct panel_desc lg_lp129qe = {
1418 .modes = &lg_lp129qe_mode,
1427 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1430 .hsync_start = 480 + 2,
1431 .hsync_end = 480 + 2 + 41,
1432 .htotal = 480 + 2 + 41 + 2,
1434 .vsync_start = 272 + 2,
1435 .vsync_end = 272 + 2 + 4,
1436 .vtotal = 272 + 2 + 4 + 2,
1440 static const struct panel_desc nec_nl4827hc19_05b = {
1441 .modes = &nec_nl4827hc19_05b_mode,
1448 .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1451 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1452 .pixelclock = { 30000000, 30000000, 40000000 },
1453 .hactive = { 800, 800, 800 },
1454 .hfront_porch = { 40, 40, 40 },
1455 .hback_porch = { 40, 40, 40 },
1456 .hsync_len = { 1, 48, 48 },
1457 .vactive = { 480, 480, 480 },
1458 .vfront_porch = { 13, 13, 13 },
1459 .vback_porch = { 29, 29, 29 },
1460 .vsync_len = { 3, 3, 3 },
1461 .flags = DISPLAY_FLAGS_DE_HIGH,
1464 static const struct panel_desc okaya_rs800480t_7x0gp = {
1465 .timings = &okaya_rs800480t_7x0gp_timing,
1478 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1481 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1484 .hsync_start = 480 + 10,
1485 .hsync_end = 480 + 10 + 10,
1486 .htotal = 480 + 10 + 10 + 15,
1488 .vsync_start = 800 + 3,
1489 .vsync_end = 800 + 3 + 3,
1490 .vtotal = 800 + 3 + 3 + 3,
1494 static const struct panel_desc ortustech_com43h4m85ulc = {
1495 .modes = &ortustech_com43h4m85ulc_mode,
1502 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1505 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1508 .hsync_start = 2560 + 48,
1509 .hsync_end = 2560 + 48 + 32,
1510 .htotal = 2560 + 48 + 32 + 80,
1512 .vsync_start = 1600 + 2,
1513 .vsync_end = 1600 + 2 + 5,
1514 .vtotal = 1600 + 2 + 5 + 57,
1518 static const struct panel_desc samsung_lsn122dl01_c01 = {
1519 .modes = &samsung_lsn122dl01_c01_mode,
1527 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1530 .hsync_start = 1024 + 24,
1531 .hsync_end = 1024 + 24 + 136,
1532 .htotal = 1024 + 24 + 136 + 160,
1534 .vsync_start = 600 + 3,
1535 .vsync_end = 600 + 3 + 6,
1536 .vtotal = 600 + 3 + 6 + 61,
1540 static const struct panel_desc samsung_ltn101nt05 = {
1541 .modes = &samsung_ltn101nt05_mode,
1550 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1553 .hsync_start = 1366 + 64,
1554 .hsync_end = 1366 + 64 + 48,
1555 .htotal = 1366 + 64 + 48 + 128,
1557 .vsync_start = 768 + 2,
1558 .vsync_end = 768 + 2 + 5,
1559 .vtotal = 768 + 2 + 5 + 17,
1563 static const struct panel_desc samsung_ltn140at29_301 = {
1564 .modes = &samsung_ltn140at29_301_mode,
1573 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1576 .hsync_start = 800 + 1,
1577 .hsync_end = 800 + 1 + 64,
1578 .htotal = 800 + 1 + 64 + 64,
1580 .vsync_start = 480 + 1,
1581 .vsync_end = 480 + 1 + 23,
1582 .vtotal = 480 + 1 + 23 + 22,
1586 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1587 .modes = &shelly_sca07010_bfn_lnn_mode,
1593 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1596 static const struct of_device_id platform_of_match[] = {
1598 .compatible = "simple-panel",
1601 .compatible = "ampire,am800480r3tmqwa1h",
1602 .data = &ire_am800480r3tmqwa1h,
1604 .compatible = "auo,b101aw03",
1605 .data = &auo_b101aw03,
1607 .compatible = "auo,b101ean01",
1608 .data = &auo_b101ean01,
1610 .compatible = "auo,b101ew05",
1611 .data = &auo_b101ew05,
1613 .compatible = "auo,b101xtn01",
1614 .data = &auo_b101xtn01,
1616 .compatible = "auo,b116xw03",
1617 .data = &auo_b116xw03,
1619 .compatible = "auo,b125han03",
1620 .data = &auo_b125han03,
1622 .compatible = "auo,b133htn01",
1623 .data = &auo_b133htn01,
1625 .compatible = "auo,b133xtn01",
1626 .data = &auo_b133xtn01,
1628 .compatible = "avic,tm070ddh03",
1629 .data = &avic_tm070ddh03,
1631 .compatible = "boe,nv125fhm-n73",
1632 .data = &boe_nv125fhm_n73,
1634 .compatible = "chunghwa,claa070wp03xg",
1635 .data = &chunghwa_claa070wp03xg,
1637 .compatible = "chunghwa,claa101wa01a",
1638 .data = &chunghwa_claa101wa01a
1640 .compatible = "chunghwa,claa101wb01",
1641 .data = &chunghwa_claa101wb01
1643 .compatible = "edt,et057090dhu",
1644 .data = &edt_et057090dhu,
1646 .compatible = "edt,et070080dh6",
1647 .data = &edt_etm0700g0dh6,
1649 .compatible = "edt,etm0700g0dh6",
1650 .data = &edt_etm0700g0dh6,
1652 .compatible = "foxlink,fl500wvr00-a0t",
1653 .data = &foxlink_fl500wvr00_a0t,
1655 .compatible = "giantplus,gpg482739qs5",
1656 .data = &giantplus_gpg482739qs5
1658 .compatible = "hannstar,hsd070pww1",
1659 .data = &hannstar_hsd070pww1,
1661 .compatible = "hannstar,hsd100pxn1",
1662 .data = &hannstar_hsd100pxn1,
1664 .compatible = "hit,tx23d38vm0caa",
1665 .data = &hitachi_tx23d38vm0caa
1667 .compatible = "innolux,at043tn24",
1668 .data = &innolux_at043tn24,
1670 .compatible ="innolux,g121i1-l01",
1671 .data = &innolux_g121i1_l01
1673 .compatible = "innolux,n116bge",
1674 .data = &innolux_n116bge,
1676 .compatible = "innolux,n125hce",
1677 .data = &innolux_n125hce,
1679 .compatible = "innolux,n156bge-l21",
1680 .data = &innolux_n156bge_l21,
1682 .compatible = "innolux,zj070na-01p",
1683 .data = &innolux_zj070na_01p,
1685 .compatible = "lg,lb070wv8",
1686 .data = &lg_lb070wv8,
1688 .compatible = "lg,lp079qx1-sp0v",
1689 .data = &lg_lp079qx1_sp0v,
1691 .compatible = "sharp,lcd-f402",
1692 .data = &sharp_lcd_f402,
1694 .compatible = "lg,lp097qx1-spa1",
1695 .data = &lg_lp097qx1_spa1,
1697 .compatible = "lg,lp129qe",
1698 .data = &lg_lp129qe,
1700 .compatible = "nec,nl4827hc19-05b",
1701 .data = &nec_nl4827hc19_05b,
1703 .compatible = "okaya,rs800480t-7x0gp",
1704 .data = &okaya_rs800480t_7x0gp,
1706 .compatible = "ortustech,com43h4m85ulc",
1707 .data = &ortustech_com43h4m85ulc,
1709 .compatible = "samsung,lsn122dl01-c01",
1710 .data = &samsung_lsn122dl01_c01,
1712 .compatible = "samsung,ltn101nt05",
1713 .data = &samsung_ltn101nt05,
1715 .compatible = "samsung,ltn140at29-301",
1716 .data = &samsung_ltn140at29_301,
1718 .compatible = "sharp,lcd-f402",
1719 .data = &sharp_lcd_f402,
1721 .compatible = "shelly,sca07010-bfn-lnn",
1722 .data = &shelly_sca07010_bfn_lnn,
1727 MODULE_DEVICE_TABLE(of, platform_of_match);
1729 static int panel_simple_platform_probe(struct platform_device *pdev)
1731 const struct of_device_id *id;
1733 id = of_match_node(platform_of_match, pdev->dev.of_node);
1737 return panel_simple_probe(&pdev->dev, id->data);
1740 static int panel_simple_platform_remove(struct platform_device *pdev)
1742 return panel_simple_remove(&pdev->dev);
1745 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1747 panel_simple_shutdown(&pdev->dev);
1750 static struct platform_driver panel_simple_platform_driver = {
1752 .name = "panel-simple",
1753 .of_match_table = platform_of_match,
1755 .probe = panel_simple_platform_probe,
1756 .remove = panel_simple_platform_remove,
1757 .shutdown = panel_simple_platform_shutdown,
1760 struct panel_desc_dsi {
1761 struct panel_desc desc;
1763 unsigned long flags;
1764 enum mipi_dsi_pixel_format format;
1768 static const struct drm_display_mode auo_b080uan01_mode = {
1771 .hsync_start = 1200 + 62,
1772 .hsync_end = 1200 + 62 + 4,
1773 .htotal = 1200 + 62 + 4 + 62,
1775 .vsync_start = 1920 + 9,
1776 .vsync_end = 1920 + 9 + 2,
1777 .vtotal = 1920 + 9 + 2 + 8,
1781 static const struct panel_desc_dsi auo_b080uan01 = {
1783 .modes = &auo_b080uan01_mode,
1791 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1792 .format = MIPI_DSI_FMT_RGB888,
1796 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1799 .hsync_start = 1200 + 120,
1800 .hsync_end = 1200 + 120 + 20,
1801 .htotal = 1200 + 120 + 20 + 21,
1803 .vsync_start = 1920 + 21,
1804 .vsync_end = 1920 + 21 + 3,
1805 .vtotal = 1920 + 21 + 3 + 18,
1807 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1810 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1812 .modes = &boe_tv080wum_nl0_mode,
1819 .flags = MIPI_DSI_MODE_VIDEO |
1820 MIPI_DSI_MODE_VIDEO_BURST |
1821 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1822 .format = MIPI_DSI_FMT_RGB888,
1826 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1829 .hsync_start = 800 + 32,
1830 .hsync_end = 800 + 32 + 1,
1831 .htotal = 800 + 32 + 1 + 57,
1833 .vsync_start = 1280 + 28,
1834 .vsync_end = 1280 + 28 + 1,
1835 .vtotal = 1280 + 28 + 1 + 14,
1839 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1841 .modes = &lg_ld070wx3_sl01_mode,
1849 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1850 .format = MIPI_DSI_FMT_RGB888,
1854 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1857 .hsync_start = 720 + 12,
1858 .hsync_end = 720 + 12 + 4,
1859 .htotal = 720 + 12 + 4 + 112,
1861 .vsync_start = 1280 + 8,
1862 .vsync_end = 1280 + 8 + 4,
1863 .vtotal = 1280 + 8 + 4 + 12,
1867 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1869 .modes = &lg_lh500wx1_sd03_mode,
1877 .flags = MIPI_DSI_MODE_VIDEO,
1878 .format = MIPI_DSI_FMT_RGB888,
1882 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1885 .hsync_start = 1920 + 154,
1886 .hsync_end = 1920 + 154 + 16,
1887 .htotal = 1920 + 154 + 16 + 32,
1889 .vsync_start = 1200 + 17,
1890 .vsync_end = 1200 + 17 + 2,
1891 .vtotal = 1200 + 17 + 2 + 16,
1895 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1897 .modes = &panasonic_vvx10f004b00_mode,
1905 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1906 MIPI_DSI_CLOCK_NON_CONTINUOUS,
1907 .format = MIPI_DSI_FMT_RGB888,
1912 static const struct of_device_id dsi_of_match[] = {
1914 .compatible = "simple-panel-dsi",
1917 .compatible = "auo,b080uan01",
1918 .data = &auo_b080uan01
1920 .compatible = "boe,tv080wum-nl0",
1921 .data = &boe_tv080wum_nl0
1923 .compatible = "lg,ld070wx3-sl01",
1924 .data = &lg_ld070wx3_sl01
1926 .compatible = "lg,lh500wx1-sd03",
1927 .data = &lg_lh500wx1_sd03
1929 .compatible = "panasonic,vvx10f004b00",
1930 .data = &panasonic_vvx10f004b00
1935 MODULE_DEVICE_TABLE(of, dsi_of_match);
1937 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1939 struct panel_simple *panel;
1940 const struct panel_desc_dsi *desc;
1941 const struct of_device_id *id;
1942 const struct panel_desc *pdesc;
1948 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1955 dsi->mode_flags = desc->flags;
1956 dsi->format = desc->format;
1957 dsi->lanes = desc->lanes;
1958 pdesc = &desc->desc;
1963 err = panel_simple_probe(&dsi->dev, pdesc);
1967 panel = dev_get_drvdata(&dsi->dev);
1970 if (!of_property_read_u32(dsi->dev.of_node, "dsi,flags", &val))
1971 dsi->mode_flags = val;
1973 if (!of_property_read_u32(dsi->dev.of_node, "dsi,format", &val))
1976 if (!of_property_read_u32(dsi->dev.of_node, "dsi,lanes", &val))
1979 data = of_get_property(dsi->dev.of_node, "panel-init-sequence", &len);
1981 panel->on_cmds = devm_kzalloc(&dsi->dev,
1982 sizeof(*panel->on_cmds),
1984 if (!panel->on_cmds)
1987 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
1990 dev_err(&dsi->dev, "failed to parse panel init sequence\n");
1995 data = of_get_property(dsi->dev.of_node, "panel-exit-sequence", &len);
1997 panel->off_cmds = devm_kzalloc(&dsi->dev,
1998 sizeof(*panel->off_cmds),
2000 if (!panel->off_cmds)
2003 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
2006 dev_err(&dsi->dev, "failed to parse panel exit sequence\n");
2011 return mipi_dsi_attach(dsi);
2014 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2018 err = mipi_dsi_detach(dsi);
2020 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2022 return panel_simple_remove(&dsi->dev);
2025 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2027 panel_simple_shutdown(&dsi->dev);
2030 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2032 .name = "panel-simple-dsi",
2033 .of_match_table = dsi_of_match,
2035 .probe = panel_simple_dsi_probe,
2036 .remove = panel_simple_dsi_remove,
2037 .shutdown = panel_simple_dsi_shutdown,
2040 static int __init panel_simple_init(void)
2044 err = platform_driver_register(&panel_simple_platform_driver);
2048 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2049 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2056 module_init(panel_simple_init);
2058 static void __exit panel_simple_exit(void)
2060 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2061 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2063 platform_driver_unregister(&panel_simple_platform_driver);
2065 module_exit(panel_simple_exit);
2067 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2068 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2069 MODULE_LICENSE("GPL and additional rights");