drivers/gpu/drm/panel/panel-simple.c

   1 /*
   2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/backlight.h>
  25 #include <linux/gpio/consumer.h>
  26 #include <linux/module.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_mipi_dsi.h>
  34 #include <drm/drm_panel.h>
  35
  36 #include <video/display_timing.h>
  37 #include <video/mipi_display.h>
  38 #include <video/of_display_timing.h>
  39 #include <video/videomode.h>
  40
  41 struct dsi_ctrl_hdr {
  42         u8 dtype;       /* data type */
  43         u8 wait;        /* ms */
  44         u8 dlen;        /* payload len */
  45 } __packed;
  46
  47 struct dsi_cmd_desc {
  48         struct dsi_ctrl_hdr dchdr;
  49         u8 *payload;
  50 };
  51
  52 struct dsi_panel_cmds {
  53         u8 *buf;
  54         int blen;
  55         struct dsi_cmd_desc *cmds;
  56         int cmd_cnt;
  57 };
  58
  59 struct panel_desc {
  60         const struct drm_display_mode *modes;
  61         unsigned int num_modes;
  62         const struct display_timing *timings;
  63         unsigned int num_timings;
  64
  65         unsigned int bpc;
  66
  67         struct {
  68                 unsigned int width;
  69                 unsigned int height;
  70         } size;
  71
  72         /**
  73          * @prepare: the time (in milliseconds) that it takes for the panel to
  74          *           become ready and start receiving video data
  75          * @enable: the time (in milliseconds) that it takes for the panel to
  76          *          display the first valid frame after starting to receive
  77          *          video data
  78          * @disable: the time (in milliseconds) that it takes for the panel to
  79          *           turn the display off (no content is visible)
  80          * @unprepare: the time (in milliseconds) that it takes for the panel
  81          *             to power itself down completely
  82          */
  83         struct {
  84                 unsigned int prepare;
  85                 unsigned int enable;
  86                 unsigned int disable;
  87                 unsigned int unprepare;
  88         } delay;
  89
  90         u32 bus_format;
  91 };
  92
  93 struct panel_simple {
  94         struct drm_panel base;
  95         struct mipi_dsi_device *dsi;
  96         bool prepared;
  97         bool enabled;
  98
  99         struct device *dev;
 100         const struct panel_desc *desc;
 101
 102         struct backlight_device *backlight;
 103         struct regulator *supply;
 104         struct i2c_adapter *ddc;
 105
 106         struct gpio_desc *enable_gpio;
 107         struct gpio_desc *reset_gpio;
 108         unsigned int reset_delay;
 109
 110         struct dsi_panel_cmds *on_cmds;
 111         struct dsi_panel_cmds *off_cmds;
 112 };
 113
 114 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
 115 {
 116         return container_of(panel, struct panel_simple, base);
 117 }
 118
 119 static void panel_simple_dsi_cmds_cleanup(struct panel_simple *p)
 120 {
 121         if (p->on_cmds) {
 122                 kfree(p->on_cmds->buf);
 123                 kfree(p->on_cmds->cmds);
 124         }
 125
 126         if (p->off_cmds) {
 127                 kfree(p->off_cmds->buf);
 128                 kfree(p->off_cmds->cmds);
 129         }
 130 }
 131
 132 static int panel_simple_dsi_parse_dcs_cmds(struct device *dev,
 133                                            const u8 *data, int blen,
 134                                            struct dsi_panel_cmds *pcmds)
 135 {
 136         int len;
 137         char *buf, *bp;
 138         struct dsi_ctrl_hdr *dchdr;
 139         int i, cnt;
 140
 141         if (!pcmds)
 142                 return -EINVAL;
 143
 144         buf = kmemdup(data, blen, GFP_KERNEL);
 145         if (!buf)
 146                 return -ENOMEM;
 147
 148         /* scan dcs commands */
 149         bp = buf;
 150         len = blen;
 151         cnt = 0;
 152         while (len > sizeof(*dchdr)) {
 153                 dchdr = (struct dsi_ctrl_hdr *)bp;
 154
 155                 if (dchdr->dlen > len) {
 156                         dev_err(dev, "%s: error, len=%d", __func__,
 157                                 dchdr->dlen);
 158                         return -EINVAL;
 159                 }
 160
 161                 bp += sizeof(*dchdr);
 162                 len -= sizeof(*dchdr);
 163                 bp += dchdr->dlen;
 164                 len -= dchdr->dlen;
 165                 cnt++;
 166         }
 167
 168         if (len != 0) {
 169                 dev_err(dev, "%s: dcs_cmd=%x len=%d error!",
 170                         __func__, buf[0], blen);
 171                 kfree(buf);
 172                 return -EINVAL;
 173         }
 174
 175         pcmds->cmds = kcalloc(cnt, sizeof(struct dsi_cmd_desc), GFP_KERNEL);
 176         if (!pcmds->cmds) {
 177                 kfree(buf);
 178                 return -ENOMEM;
 179         }
 180
 181         pcmds->cmd_cnt = cnt;
 182         pcmds->buf = buf;
 183         pcmds->blen = blen;
 184
 185         bp = buf;
 186         len = blen;
 187         for (i = 0; i < cnt; i++) {
 188                 dchdr = (struct dsi_ctrl_hdr *)bp;
 189                 len -= sizeof(*dchdr);
 190                 bp += sizeof(*dchdr);
 191                 pcmds->cmds[i].dchdr = *dchdr;
 192                 pcmds->cmds[i].payload = bp;
 193                 bp += dchdr->dlen;
 194                 len -= dchdr->dlen;
 195         }
 196
 197         dev_info(dev, "%s: dcs_cmd=%x len=%d, cmd_cnt=%d\n", __func__,
 198                  pcmds->buf[0], pcmds->blen, pcmds->cmd_cnt);
 199         return 0;
 200 }
 201
 202 static int panel_simple_dsi_send_cmds(struct panel_simple *panel,
 203                                       struct dsi_panel_cmds *cmds)
 204 {
 205         struct mipi_dsi_device *dsi = panel->dsi;
 206         int i, err;
 207
 208         if (!cmds)
 209                 return -EINVAL;
 210
 211         for (i = 0; i < cmds->cmd_cnt; i++) {
 212                 struct dsi_cmd_desc *cmd = &cmds->cmds[i];
 213
 214                 switch (cmd->dchdr.dtype) {
 215                 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 216                 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 217                 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 218                 case MIPI_DSI_GENERIC_LONG_WRITE:
 219                         err = mipi_dsi_generic_write(dsi, cmd->payload,
 220                                                      cmd->dchdr.dlen);
 221                         break;
 222                 case MIPI_DSI_DCS_SHORT_WRITE:
 223                 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 224                 case MIPI_DSI_DCS_LONG_WRITE:
 225                         err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
 226                                                         cmd->dchdr.dlen);
 227                         break;
 228                 default:
 229                         return -EINVAL;
 230                 }
 231
 232                 if (err < 0)
 233                         dev_err(panel->dev, "failed to write dcs cmd: %d\n",
 234                                 err);
 235
 236                 if (cmd->dchdr.wait)
 237                         msleep(cmd->dchdr.wait);
 238         }
 239
 240         return 0;
 241 }
 242
 243 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
 244 {
 245         struct drm_connector *connector = panel->base.connector;
 246         struct drm_device *drm = panel->base.drm;
 247         struct drm_display_mode *mode;
 248         unsigned int i, num = 0;
 249
 250         if (!panel->desc)
 251                 return 0;
 252
 253         for (i = 0; i < panel->desc->num_timings; i++) {
 254                 const struct display_timing *dt = &panel->desc->timings[i];
 255                 struct videomode vm;
 256
 257                 videomode_from_timing(dt, &vm);
 258                 mode = drm_mode_create(drm);
 259                 if (!mode) {
 260                         dev_err(drm->dev, "failed to add mode %ux%u\n",
 261                                 dt->hactive.typ, dt->vactive.typ);
 262                         continue;
 263                 }
 264
 265                 drm_display_mode_from_videomode(&vm, mode);
 266                 drm_mode_set_name(mode);
 267
 268                 drm_mode_probed_add(connector, mode);
 269                 num++;
 270         }
 271
 272         for (i = 0; i < panel->desc->num_modes; i++) {
 273                 const struct drm_display_mode *m = &panel->desc->modes[i];
 274
 275                 mode = drm_mode_duplicate(drm, m);
 276                 if (!mode) {
 277                         dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
 278                                 m->hdisplay, m->vdisplay, m->vrefresh);
 279                         continue;
 280                 }
 281
 282                 drm_mode_set_name(mode);
 283
 284                 drm_mode_probed_add(connector, mode);
 285                 num++;
 286         }
 287
 288         connector->display_info.bpc = panel->desc->bpc;
 289         connector->display_info.width_mm = panel->desc->size.width;
 290         connector->display_info.height_mm = panel->desc->size.height;
 291         if (panel->desc->bus_format)
 292                 drm_display_info_set_bus_formats(&connector->display_info,
 293                                                  &panel->desc->bus_format, 1);
 294
 295         return num;
 296 }
 297
 298 static int panel_simple_of_get_native_mode(struct panel_simple *panel)
 299 {
 300         struct drm_connector *connector = panel->base.connector;
 301         struct drm_device *drm = panel->base.drm;
 302         struct drm_display_mode *mode;
 303         struct device_node *timings_np;
 304         int ret;
 305
 306         timings_np = of_get_child_by_name(panel->dev->of_node,
 307                                           "display-timings");
 308         if (!timings_np) {
 309                 dev_dbg(panel->dev, "failed to find display-timings node\n");
 310                 return 0;
 311         }
 312
 313         of_node_put(timings_np);
 314         mode = drm_mode_create(drm);
 315         if (!mode)
 316                 return 0;
 317
 318         ret = of_get_drm_display_mode(panel->dev->of_node, mode,
 319                                       OF_USE_NATIVE_MODE);
 320         if (ret) {
 321                 dev_dbg(panel->dev, "failed to find dts display timings\n");
 322                 drm_mode_destroy(drm, mode);
 323                 return 0;
 324         }
 325
 326         drm_mode_set_name(mode);
 327         mode->type |= DRM_MODE_TYPE_PREFERRED;
 328         drm_mode_probed_add(connector, mode);
 329
 330         return 1;
 331 }
 332
 333 static int panel_simple_loader_protect(struct drm_panel *panel, bool on)
 334 {
 335         struct panel_simple *p = to_panel_simple(panel);
 336         int err;
 337
 338         if (on) {
 339                 err = regulator_enable(p->supply);
 340                 if (err < 0) {
 341                         dev_err(panel->dev, "failed to enable supply: %d\n",
 342                                 err);
 343                         return err;
 344                 }
 345         } else {
 346                 regulator_disable(p->supply);
 347         }
 348
 349         return 0;
 350 }
 351
 352 static int panel_simple_disable(struct drm_panel *panel)
 353 {
 354         struct panel_simple *p = to_panel_simple(panel);
 355
 356         if (!p->enabled)
 357                 return 0;
 358
 359         if (p->backlight) {
 360                 p->backlight->props.power = FB_BLANK_POWERDOWN;
 361                 backlight_update_status(p->backlight);
 362         }
 363
 364         if (p->desc && p->desc->delay.disable)
 365                 msleep(p->desc->delay.disable);
 366
 367         p->enabled = false;
 368
 369         return 0;
 370 }
 371
 372 static int panel_simple_unprepare(struct drm_panel *panel)
 373 {
 374         struct panel_simple *p = to_panel_simple(panel);
 375         int err;
 376
 377         if (!p->prepared)
 378                 return 0;
 379
 380         if (p->off_cmds) {
 381                 err = panel_simple_dsi_send_cmds(p, p->off_cmds);
 382                 if (err)
 383                         dev_err(p->dev, "failed to send off cmds\n");
 384         }
 385
 386         if (p->reset_gpio)
 387                 gpiod_direction_output(p->reset_gpio, 1);
 388
 389         if (p->enable_gpio)
 390                 gpiod_direction_output(p->enable_gpio, 0);
 391
 392         regulator_disable(p->supply);
 393
 394         if (p->desc && p->desc->delay.unprepare)
 395                 msleep(p->desc->delay.unprepare);
 396
 397         p->prepared = false;
 398
 399         return 0;
 400 }
 401
 402 static int panel_simple_prepare(struct drm_panel *panel)
 403 {
 404         struct panel_simple *p = to_panel_simple(panel);
 405         int err;
 406
 407         if (p->prepared)
 408                 return 0;
 409
 410         err = regulator_enable(p->supply);
 411         if (err < 0) {
 412                 dev_err(panel->dev, "failed to enable supply: %d\n", err);
 413                 return err;
 414         }
 415
 416         if (p->enable_gpio)
 417                 gpiod_direction_output(p->enable_gpio, 1);
 418
 419         if (p->desc && p->desc->delay.prepare)
 420                 msleep(p->desc->delay.prepare);
 421
 422         if (p->reset_gpio)
 423                 gpiod_direction_output(p->reset_gpio, 1);
 424
 425         if (p->reset_delay)
 426                 msleep(p->reset_delay);
 427
 428         if (p->reset_gpio)
 429                 gpiod_direction_output(p->reset_gpio, 0);
 430
 431         if (p->on_cmds) {
 432                 err = panel_simple_dsi_send_cmds(p, p->on_cmds);
 433                 if (err)
 434                         dev_err(p->dev, "failed to send on cmds\n");
 435         }
 436
 437         p->prepared = true;
 438
 439         return 0;
 440 }
 441
 442 static int panel_simple_enable(struct drm_panel *panel)
 443 {
 444         struct panel_simple *p = to_panel_simple(panel);
 445
 446         if (p->enabled)
 447                 return 0;
 448
 449         if (p->desc && p->desc->delay.enable)
 450                 msleep(p->desc->delay.enable);
 451
 452         if (p->backlight) {
 453                 p->backlight->props.power = FB_BLANK_UNBLANK;
 454                 backlight_update_status(p->backlight);
 455         }
 456
 457         p->enabled = true;
 458
 459         return 0;
 460 }
 461
 462 static int panel_simple_get_modes(struct drm_panel *panel)
 463 {
 464         struct panel_simple *p = to_panel_simple(panel);
 465         int num = 0;
 466
 467         /* add device node plane modes */
 468         num += panel_simple_of_get_native_mode(p);
 469
 470         /* add hard-coded panel modes */
 471         num += panel_simple_get_fixed_modes(p);
 472
 473         /* probe EDID if a DDC bus is available */
 474         if (p->ddc) {
 475                 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
 476                 drm_mode_connector_update_edid_property(panel->connector, edid);
 477                 if (edid) {
 478                         num += drm_add_edid_modes(panel->connector, edid);
 479                         kfree(edid);
 480                 }
 481         }
 482
 483         return num;
 484 }
 485
 486 static int panel_simple_get_timings(struct drm_panel *panel,
 487                                     unsigned int num_timings,
 488                                     struct display_timing *timings)
 489 {
 490         struct panel_simple *p = to_panel_simple(panel);
 491         unsigned int i;
 492
 493         if (!p->desc)
 494                 return 0;
 495
 496         if (p->desc->num_timings < num_timings)
 497                 num_timings = p->desc->num_timings;
 498
 499         if (timings)
 500                 for (i = 0; i < num_timings; i++)
 501                         timings[i] = p->desc->timings[i];
 502
 503         return p->desc->num_timings;
 504 }
 505
 506 static const struct drm_panel_funcs panel_simple_funcs = {
 507         .loader_protect = panel_simple_loader_protect,
 508         .disable = panel_simple_disable,
 509         .unprepare = panel_simple_unprepare,
 510         .prepare = panel_simple_prepare,
 511         .enable = panel_simple_enable,
 512         .get_modes = panel_simple_get_modes,
 513         .get_timings = panel_simple_get_timings,
 514 };
 515
 516 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 517 {
 518         struct device_node *backlight, *ddc;
 519         struct panel_simple *panel;
 520         struct panel_desc *of_desc;
 521         u32 val;
 522         int err;
 523
 524         panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
 525         if (!panel)
 526                 return -ENOMEM;
 527
 528         if (!desc)
 529                 of_desc = devm_kzalloc(dev, sizeof(*of_desc), GFP_KERNEL);
 530         else
 531                 of_desc = devm_kmemdup(dev, desc, sizeof(*of_desc), GFP_KERNEL);
 532
 533         if (!of_property_read_u32(dev->of_node, "bus-format", &val))
 534                 of_desc->bus_format = val;
 535         if (!of_property_read_u32(dev->of_node, "delay,prepare", &val))
 536                 of_desc->delay.prepare = val;
 537         if (!of_property_read_u32(dev->of_node, "delay,enable", &val))
 538                 of_desc->delay.enable = val;
 539         if (!of_property_read_u32(dev->of_node, "delay,disable", &val))
 540                 of_desc->delay.disable = val;
 541         if (!of_property_read_u32(dev->of_node, "delay,unprepare", &val))
 542                 of_desc->delay.unprepare = val;
 543
 544         panel->enabled = false;
 545         panel->prepared = false;
 546         panel->desc = of_desc;
 547         panel->dev = dev;
 548
 549         panel->supply = devm_regulator_get(dev, "power");
 550         if (IS_ERR(panel->supply))
 551                 return PTR_ERR(panel->supply);
 552
 553         panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 0);
 554         if (IS_ERR(panel->enable_gpio)) {
 555                 err = PTR_ERR(panel->enable_gpio);
 556                 dev_err(dev, "failed to request enable GPIO: %d\n", err);
 557                 return err;
 558         }
 559
 560         panel->reset_gpio = devm_gpiod_get_optional(dev, "reset", 0);
 561         if (IS_ERR(panel->reset_gpio)) {
 562                 err = PTR_ERR(panel->reset_gpio);
 563                 dev_err(dev, "failed to request reset GPIO: %d\n", err);
 564                 return err;
 565         }
 566
 567         backlight = of_parse_phandle(dev->of_node, "backlight", 0);
 568         if (backlight) {
 569                 panel->backlight = of_find_backlight_by_node(backlight);
 570                 of_node_put(backlight);
 571
 572                 if (!panel->backlight)
 573                         return -EPROBE_DEFER;
 574         }
 575
 576         ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
 577         if (ddc) {
 578                 panel->ddc = of_find_i2c_adapter_by_node(ddc);
 579                 of_node_put(ddc);
 580
 581                 if (!panel->ddc) {
 582                         err = -EPROBE_DEFER;
 583                         goto free_backlight;
 584                 }
 585         }
 586
 587         drm_panel_init(&panel->base);
 588         panel->base.dev = dev;
 589         panel->base.funcs = &panel_simple_funcs;
 590
 591         err = drm_panel_add(&panel->base);
 592         if (err < 0)
 593                 goto free_ddc;
 594
 595         dev_set_drvdata(dev, panel);
 596
 597         return 0;
 598
 599 free_ddc:
 600         if (panel->ddc)
 601                 put_device(&panel->ddc->dev);
 602 free_backlight:
 603         if (panel->backlight)
 604                 put_device(&panel->backlight->dev);
 605
 606         return err;
 607 }
 608
 609 static int panel_simple_remove(struct device *dev)
 610 {
 611         struct panel_simple *panel = dev_get_drvdata(dev);
 612
 613         drm_panel_detach(&panel->base);
 614         drm_panel_remove(&panel->base);
 615
 616         panel_simple_disable(&panel->base);
 617
 618         if (panel->ddc)
 619                 put_device(&panel->ddc->dev);
 620
 621         if (panel->backlight)
 622                 put_device(&panel->backlight->dev);
 623
 624         panel_simple_dsi_cmds_cleanup(panel);
 625
 626         return 0;
 627 }
 628
 629 static void panel_simple_shutdown(struct device *dev)
 630 {
 631         struct panel_simple *panel = dev_get_drvdata(dev);
 632
 633         panel_simple_disable(&panel->base);
 634 }
 635
 636 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
 637         .clock = 33333,
 638         .hdisplay = 800,
 639         .hsync_start = 800 + 0,
 640         .hsync_end = 800 + 0 + 255,
 641         .htotal = 800 + 0 + 255 + 0,
 642         .vdisplay = 480,
 643         .vsync_start = 480 + 2,
 644         .vsync_end = 480 + 2 + 45,
 645         .vtotal = 480 + 2 + 45 + 0,
 646         .vrefresh = 60,
 647         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 648 };
 649
 650 static const struct panel_desc ampire_am800480r3tmqwa1h = {
 651         .modes = &ampire_am800480r3tmqwa1h_mode,
 652         .num_modes = 1,
 653         .bpc = 6,
 654         .size = {
 655                 .width = 152,
 656                 .height = 91,
 657         },
 658         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 659 };
 660
 661 static const struct drm_display_mode auo_b101aw03_mode = {
 662         .clock = 51450,
 663         .hdisplay = 1024,
 664         .hsync_start = 1024 + 156,
 665         .hsync_end = 1024 + 156 + 8,
 666         .htotal = 1024 + 156 + 8 + 156,
 667         .vdisplay = 600,
 668         .vsync_start = 600 + 16,
 669         .vsync_end = 600 + 16 + 6,
 670         .vtotal = 600 + 16 + 6 + 16,
 671         .vrefresh = 60,
 672 };
 673
 674 static const struct panel_desc auo_b101aw03 = {
 675         .modes = &auo_b101aw03_mode,
 676         .num_modes = 1,
 677         .bpc = 6,
 678         .size = {
 679                 .width = 223,
 680                 .height = 125,
 681         },
 682 };
 683
 684 static const struct drm_display_mode auo_b101ean01_mode = {
 685         .clock = 72500,
 686         .hdisplay = 1280,
 687         .hsync_start = 1280 + 119,
 688         .hsync_end = 1280 + 119 + 32,
 689         .htotal = 1280 + 119 + 32 + 21,
 690         .vdisplay = 800,
 691         .vsync_start = 800 + 4,
 692         .vsync_end = 800 + 4 + 20,
 693         .vtotal = 800 + 4 + 20 + 8,
 694         .vrefresh = 60,
 695 };
 696
 697 static const struct panel_desc auo_b101ean01 = {
 698         .modes = &auo_b101ean01_mode,
 699         .num_modes = 1,
 700         .bpc = 6,
 701         .size = {
 702                 .width = 217,
 703                 .height = 136,
 704         },
 705 };
 706
 707 static const struct drm_display_mode auo_b101ew05_mode = {
 708         .clock = 71000,
 709         .hdisplay = 1280,
 710         .hsync_start = 1280 + 18,
 711         .hsync_end = 1280 + 18 + 10,
 712         .htotal = 1280 + 18 + 10 + 100,
 713         .vdisplay = 800,
 714         .vsync_start = 800 + 6,
 715         .vsync_end = 800 + 6 + 2,
 716         .vtotal = 800 + 6 + 2 + 8,
 717         .vrefresh = 60,
 718 };
 719
 720 static const struct panel_desc auo_b101ew05 = {
 721         .modes = &auo_b101ew05_mode,
 722         .num_modes = 1,
 723         .bpc = 6,
 724         .size = {
 725                 .width = 217,
 726                 .height = 136,
 727         },
 728 };
 729
 730 static const struct drm_display_mode auo_b101xtn01_mode = {
 731         .clock = 72000,
 732         .hdisplay = 1366,
 733         .hsync_start = 1366 + 20,
 734         .hsync_end = 1366 + 20 + 70,
 735         .htotal = 1366 + 20 + 70,
 736         .vdisplay = 768,
 737         .vsync_start = 768 + 14,
 738         .vsync_end = 768 + 14 + 42,
 739         .vtotal = 768 + 14 + 42,
 740         .vrefresh = 60,
 741         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 742 };
 743
 744 static const struct panel_desc auo_b101xtn01 = {
 745         .modes = &auo_b101xtn01_mode,
 746         .num_modes = 1,
 747         .bpc = 6,
 748         .size = {
 749                 .width = 223,
 750                 .height = 125,
 751         },
 752 };
 753
 754 static const struct drm_display_mode auo_b116xw03_mode = {
 755         .clock = 70589,
 756         .hdisplay = 1366,
 757         .hsync_start = 1366 + 40,
 758         .hsync_end = 1366 + 40 + 40,
 759         .htotal = 1366 + 40 + 40 + 32,
 760         .vdisplay = 768,
 761         .vsync_start = 768 + 10,
 762         .vsync_end = 768 + 10 + 12,
 763         .vtotal = 768 + 10 + 12 + 6,
 764         .vrefresh = 60,
 765 };
 766
 767 static const struct panel_desc auo_b116xw03 = {
 768         .modes = &auo_b116xw03_mode,
 769         .num_modes = 1,
 770         .bpc = 6,
 771         .size = {
 772                 .width = 256,
 773                 .height = 144,
 774         },
 775 };
 776
 777 static const struct drm_display_mode auo_b125han03_mode = {
 778         .clock = 146900,
 779         .hdisplay = 1920,
 780         .hsync_start = 1920 + 48,
 781         .hsync_end = 1920 + 48 + 32,
 782         .htotal = 1920 + 48 + 32 + 140,
 783         .vdisplay = 1080,
 784         .vsync_start = 1080 + 2,
 785         .vsync_end = 1080 + 2 + 5,
 786         .vtotal = 1080 + 2 + 5 + 57,
 787         .vrefresh = 60,
 788         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 789 };
 790
 791 static const struct panel_desc auo_b125han03 = {
 792         .modes = &auo_b125han03_mode,
 793         .num_modes = 1,
 794         .bpc = 6,
 795         .size = {
 796                 .width = 276,
 797                 .height = 156,
 798         },
 799         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 800 };
 801
 802 static const struct drm_display_mode auo_b133xtn01_mode = {
 803         .clock = 69500,
 804         .hdisplay = 1366,
 805         .hsync_start = 1366 + 48,
 806         .hsync_end = 1366 + 48 + 32,
 807         .htotal = 1366 + 48 + 32 + 20,
 808         .vdisplay = 768,
 809         .vsync_start = 768 + 3,
 810         .vsync_end = 768 + 3 + 6,
 811         .vtotal = 768 + 3 + 6 + 13,
 812         .vrefresh = 60,
 813 };
 814
 815 static const struct panel_desc auo_b133xtn01 = {
 816         .modes = &auo_b133xtn01_mode,
 817         .num_modes = 1,
 818         .bpc = 6,
 819         .size = {
 820                 .width = 293,
 821                 .height = 165,
 822         },
 823 };
 824
 825 static const struct drm_display_mode auo_b133htn01_mode = {
 826         .clock = 150660,
 827         .hdisplay = 1920,
 828         .hsync_start = 1920 + 172,
 829         .hsync_end = 1920 + 172 + 80,
 830         .htotal = 1920 + 172 + 80 + 60,
 831         .vdisplay = 1080,
 832         .vsync_start = 1080 + 25,
 833         .vsync_end = 1080 + 25 + 10,
 834         .vtotal = 1080 + 25 + 10 + 10,
 835         .vrefresh = 60,
 836 };
 837
 838 static const struct panel_desc auo_b133htn01 = {
 839         .modes = &auo_b133htn01_mode,
 840         .num_modes = 1,
 841         .bpc = 6,
 842         .size = {
 843                 .width = 293,
 844                 .height = 165,
 845         },
 846         .delay = {
 847                 .prepare = 105,
 848                 .enable = 20,
 849                 .unprepare = 50,
 850         },
 851 };
 852
 853 static const struct drm_display_mode avic_tm070ddh03_mode = {
 854         .clock = 51200,
 855         .hdisplay = 1024,
 856         .hsync_start = 1024 + 160,
 857         .hsync_end = 1024 + 160 + 4,
 858         .htotal = 1024 + 160 + 4 + 156,
 859         .vdisplay = 600,
 860         .vsync_start = 600 + 17,
 861         .vsync_end = 600 + 17 + 1,
 862         .vtotal = 600 + 17 + 1 + 17,
 863         .vrefresh = 60,
 864 };
 865
 866 static const struct panel_desc avic_tm070ddh03 = {
 867         .modes = &avic_tm070ddh03_mode,
 868         .num_modes = 1,
 869         .bpc = 8,
 870         .size = {
 871                 .width = 154,
 872                 .height = 90,
 873         },
 874         .delay = {
 875                 .prepare = 20,
 876                 .enable = 200,
 877                 .disable = 200,
 878         },
 879 };
 880
 881 static const struct drm_display_mode boe_nv125fhm_n73_mode = {
 882         .clock = 72300,
 883         .hdisplay = 1366,
 884         .hsync_start = 1366 + 80,
 885         .hsync_end = 1366 + 80 + 20,
 886         .htotal = 1366 + 80 + 20 + 60,
 887         .vdisplay = 768,
 888         .vsync_start = 768 + 12,
 889         .vsync_end = 768 + 12 + 2,
 890         .vtotal = 768 + 12 + 2 + 8,
 891         .vrefresh = 60,
 892         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 893 };
 894
 895 static const struct panel_desc boe_nv125fhm_n73 = {
 896         .modes = &boe_nv125fhm_n73_mode,
 897         .num_modes = 1,
 898         .bpc = 6,
 899         .size = {
 900                 .width = 276,
 901                 .height = 156,
 902         },
 903         .delay = {
 904                 .unprepare = 160,
 905         },
 906         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 907 };
 908
 909 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
 910         .clock = 67000,
 911         .hdisplay = 800,
 912         .hsync_start = 800 + 24,
 913         .hsync_end = 800 + 24 + 16,
 914         .htotal = 800 + 24 + 16 + 24,
 915         .vdisplay = 1280,
 916         .vsync_start = 1280 + 2,
 917         .vsync_end = 1280 + 2 + 2,
 918         .vtotal = 1280 + 2 + 2 + 4,
 919         .vrefresh = 60,
 920 };
 921
 922 static const struct panel_desc chunghwa_claa070wp03xg = {
 923         .modes = &chunghwa_claa070wp03xg_mode,
 924         .num_modes = 1,
 925         .bpc = 6,
 926         .size = {
 927                 .width = 94,
 928                 .height = 151,
 929         },
 930 };
 931
 932 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
 933         .clock = 72070,
 934         .hdisplay = 1366,
 935         .hsync_start = 1366 + 58,
 936         .hsync_end = 1366 + 58 + 58,
 937         .htotal = 1366 + 58 + 58 + 58,
 938         .vdisplay = 768,
 939         .vsync_start = 768 + 4,
 940         .vsync_end = 768 + 4 + 4,
 941         .vtotal = 768 + 4 + 4 + 4,
 942         .vrefresh = 60,
 943 };
 944
 945 static const struct panel_desc chunghwa_claa101wa01a = {
 946         .modes = &chunghwa_claa101wa01a_mode,
 947         .num_modes = 1,
 948         .bpc = 6,
 949         .size = {
 950                 .width = 220,
 951                 .height = 120,
 952         },
 953 };
 954
 955 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
 956         .clock = 69300,
 957         .hdisplay = 1366,
 958         .hsync_start = 1366 + 48,
 959         .hsync_end = 1366 + 48 + 32,
 960         .htotal = 1366 + 48 + 32 + 20,
 961         .vdisplay = 768,
 962         .vsync_start = 768 + 16,
 963         .vsync_end = 768 + 16 + 8,
 964         .vtotal = 768 + 16 + 8 + 16,
 965         .vrefresh = 60,
 966 };
 967
 968 static const struct panel_desc chunghwa_claa101wb01 = {
 969         .modes = &chunghwa_claa101wb01_mode,
 970         .num_modes = 1,
 971         .bpc = 6,
 972         .size = {
 973                 .width = 223,
 974                 .height = 125,
 975         },
 976 };
 977
 978 static const struct drm_display_mode edt_et057090dhu_mode = {
 979         .clock = 25175,
 980         .hdisplay = 640,
 981         .hsync_start = 640 + 16,
 982         .hsync_end = 640 + 16 + 30,
 983         .htotal = 640 + 16 + 30 + 114,
 984         .vdisplay = 480,
 985         .vsync_start = 480 + 10,
 986         .vsync_end = 480 + 10 + 3,
 987         .vtotal = 480 + 10 + 3 + 32,
 988         .vrefresh = 60,
 989         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 990 };
 991
 992 static const struct panel_desc edt_et057090dhu = {
 993         .modes = &edt_et057090dhu_mode,
 994         .num_modes = 1,
 995         .bpc = 6,
 996         .size = {
 997                 .width = 115,
 998                 .height = 86,
 999         },
1000 };
1001
1002 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1003         .clock = 33260,
1004         .hdisplay = 800,
1005         .hsync_start = 800 + 40,
1006         .hsync_end = 800 + 40 + 128,
1007         .htotal = 800 + 40 + 128 + 88,
1008         .vdisplay = 480,
1009         .vsync_start = 480 + 10,
1010         .vsync_end = 480 + 10 + 2,
1011         .vtotal = 480 + 10 + 2 + 33,
1012         .vrefresh = 60,
1013         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1014 };
1015
1016 static const struct panel_desc edt_etm0700g0dh6 = {
1017         .modes = &edt_etm0700g0dh6_mode,
1018         .num_modes = 1,
1019         .bpc = 6,
1020         .size = {
1021                 .width = 152,
1022                 .height = 91,
1023         },
1024 };
1025
1026 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1027         .clock = 32260,
1028         .hdisplay = 800,
1029         .hsync_start = 800 + 168,
1030         .hsync_end = 800 + 168 + 64,
1031         .htotal = 800 + 168 + 64 + 88,
1032         .vdisplay = 480,
1033         .vsync_start = 480 + 37,
1034         .vsync_end = 480 + 37 + 2,
1035         .vtotal = 480 + 37 + 2 + 8,
1036         .vrefresh = 60,
1037 };
1038
1039 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1040         .modes = &foxlink_fl500wvr00_a0t_mode,
1041         .num_modes = 1,
1042         .bpc = 8,
1043         .size = {
1044                 .width = 108,
1045                 .height = 65,
1046         },
1047         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1048 };
1049
1050 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1051         .clock = 9000,
1052         .hdisplay = 480,
1053         .hsync_start = 480 + 5,
1054         .hsync_end = 480 + 5 + 1,
1055         .htotal = 480 + 5 + 1 + 40,
1056         .vdisplay = 272,
1057         .vsync_start = 272 + 8,
1058         .vsync_end = 272 + 8 + 1,
1059         .vtotal = 272 + 8 + 1 + 8,
1060         .vrefresh = 60,
1061 };
1062
1063 static const struct panel_desc giantplus_gpg482739qs5 = {
1064         .modes = &giantplus_gpg482739qs5_mode,
1065         .num_modes = 1,
1066         .bpc = 8,
1067         .size = {
1068                 .width = 95,
1069                 .height = 54,
1070         },
1071         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1072 };
1073
1074 static const struct display_timing hannstar_hsd070pww1_timing = {
1075         .pixelclock = { 64300000, 71100000, 82000000 },
1076         .hactive = { 1280, 1280, 1280 },
1077         .hfront_porch = { 1, 1, 10 },
1078         .hback_porch = { 1, 1, 10 },
1079         /*
1080          * According to the data sheet, the minimum horizontal blanking interval
1081          * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1082          * minimum working horizontal blanking interval to be 60 clocks.
1083          */
1084         .hsync_len = { 58, 158, 661 },
1085         .vactive = { 800, 800, 800 },
1086         .vfront_porch = { 1, 1, 10 },
1087         .vback_porch = { 1, 1, 10 },
1088         .vsync_len = { 1, 21, 203 },
1089         .flags = DISPLAY_FLAGS_DE_HIGH,
1090 };
1091
1092 static const struct panel_desc hannstar_hsd070pww1 = {
1093         .timings = &hannstar_hsd070pww1_timing,
1094         .num_timings = 1,
1095         .bpc = 6,
1096         .size = {
1097                 .width = 151,
1098                 .height = 94,
1099         },
1100         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1101 };
1102
1103 static const struct display_timing hannstar_hsd100pxn1_timing = {
1104         .pixelclock = { 55000000, 65000000, 75000000 },
1105         .hactive = { 1024, 1024, 1024 },
1106         .hfront_porch = { 40, 40, 40 },
1107         .hback_porch = { 220, 220, 220 },
1108         .hsync_len = { 20, 60, 100 },
1109         .vactive = { 768, 768, 768 },
1110         .vfront_porch = { 7, 7, 7 },
1111         .vback_porch = { 21, 21, 21 },
1112         .vsync_len = { 10, 10, 10 },
1113         .flags = DISPLAY_FLAGS_DE_HIGH,
1114 };
1115
1116 static const struct panel_desc hannstar_hsd100pxn1 = {
1117         .timings = &hannstar_hsd100pxn1_timing,
1118         .num_timings = 1,
1119         .bpc = 6,
1120         .size = {
1121                 .width = 203,
1122                 .height = 152,
1123         },
1124         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1125 };
1126
1127 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1128         .clock = 33333,
1129         .hdisplay = 800,
1130         .hsync_start = 800 + 85,
1131         .hsync_end = 800 + 85 + 86,
1132         .htotal = 800 + 85 + 86 + 85,
1133         .vdisplay = 480,
1134         .vsync_start = 480 + 16,
1135         .vsync_end = 480 + 16 + 13,
1136         .vtotal = 480 + 16 + 13 + 16,
1137         .vrefresh = 60,
1138 };
1139
1140 static const struct panel_desc hitachi_tx23d38vm0caa = {
1141         .modes = &hitachi_tx23d38vm0caa_mode,
1142         .num_modes = 1,
1143         .bpc = 6,
1144         .size = {
1145                 .width = 195,
1146                 .height = 117,
1147         },
1148 };
1149
1150 static const struct drm_display_mode innolux_at043tn24_mode = {
1151         .clock = 9000,
1152         .hdisplay = 480,
1153         .hsync_start = 480 + 2,
1154         .hsync_end = 480 + 2 + 41,
1155         .htotal = 480 + 2 + 41 + 2,
1156         .vdisplay = 272,
1157         .vsync_start = 272 + 2,
1158         .vsync_end = 272 + 2 + 11,
1159         .vtotal = 272 + 2 + 11 + 2,
1160         .vrefresh = 60,
1161         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1162 };
1163
1164 static const struct panel_desc innolux_at043tn24 = {
1165         .modes = &innolux_at043tn24_mode,
1166         .num_modes = 1,
1167         .bpc = 8,
1168         .size = {
1169                 .width = 95,
1170                 .height = 54,
1171         },
1172         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1173 };
1174
1175 static const struct drm_display_mode innolux_g121i1_l01_mode = {
1176         .clock = 71000,
1177         .hdisplay = 1280,
1178         .hsync_start = 1280 + 64,
1179         .hsync_end = 1280 + 64 + 32,
1180         .htotal = 1280 + 64 + 32 + 64,
1181         .vdisplay = 800,
1182         .vsync_start = 800 + 9,
1183         .vsync_end = 800 + 9 + 6,
1184         .vtotal = 800 + 9 + 6 + 9,
1185         .vrefresh = 60,
1186 };
1187
1188 static const struct panel_desc innolux_g121i1_l01 = {
1189         .modes = &innolux_g121i1_l01_mode,
1190         .num_modes = 1,
1191         .bpc = 6,
1192         .size = {
1193                 .width = 261,
1194                 .height = 163,
1195         },
1196 };
1197
1198 static const struct drm_display_mode innolux_n116bge_mode = {
1199         .clock = 76420,
1200         .hdisplay = 1366,
1201         .hsync_start = 1366 + 136,
1202         .hsync_end = 1366 + 136 + 30,
1203         .htotal = 1366 + 136 + 30 + 60,
1204         .vdisplay = 768,
1205         .vsync_start = 768 + 8,
1206         .vsync_end = 768 + 8 + 12,
1207         .vtotal = 768 + 8 + 12 + 12,
1208         .vrefresh = 60,
1209         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1210 };
1211
1212 static const struct panel_desc innolux_n116bge = {
1213         .modes = &innolux_n116bge_mode,
1214         .num_modes = 1,
1215         .bpc = 6,
1216         .size = {
1217                 .width = 256,
1218                 .height = 144,
1219         },
1220 };
1221
1222 static const struct drm_display_mode innolux_n125hce_mode = {
1223         .clock = 138780,
1224         .hdisplay = 1920,
1225         .hsync_start = 1920 + 80,
1226         .hsync_end = 1920 + 80 + 30,
1227         .htotal = 1920 + 80 + 30 + 50,
1228         .vdisplay = 1080,
1229         .vsync_start = 1080 + 12,
1230         .vsync_end = 1080 + 12 + 4,
1231         .vtotal = 1080 + 12 + 4 + 16,
1232         .vrefresh = 60,
1233         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1234 };
1235
1236 static const struct panel_desc innolux_n125hce = {
1237         .modes = &innolux_n125hce_mode,
1238         .num_modes = 1,
1239         .bpc = 6,
1240         .size = {
1241                 .width = 283,
1242                 .height = 168,
1243         },
1244         .delay = {
1245                 .unprepare = 600,
1246                 .enable = 100,
1247         },
1248         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1249 };
1250
1251 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1252         .clock = 69300,
1253         .hdisplay = 1366,
1254         .hsync_start = 1366 + 16,
1255         .hsync_end = 1366 + 16 + 34,
1256         .htotal = 1366 + 16 + 34 + 50,
1257         .vdisplay = 768,
1258         .vsync_start = 768 + 2,
1259         .vsync_end = 768 + 2 + 6,
1260         .vtotal = 768 + 2 + 6 + 12,
1261         .vrefresh = 60,
1262 };
1263
1264 static const struct panel_desc innolux_n156bge_l21 = {
1265         .modes = &innolux_n156bge_l21_mode,
1266         .num_modes = 1,
1267         .bpc = 6,
1268         .size = {
1269                 .width = 344,
1270                 .height = 193,
1271         },
1272 };
1273
1274 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1275         .clock = 51501,
1276         .hdisplay = 1024,
1277         .hsync_start = 1024 + 128,
1278         .hsync_end = 1024 + 128 + 64,
1279         .htotal = 1024 + 128 + 64 + 128,
1280         .vdisplay = 600,
1281         .vsync_start = 600 + 16,
1282         .vsync_end = 600 + 16 + 4,
1283         .vtotal = 600 + 16 + 4 + 16,
1284         .vrefresh = 60,
1285 };
1286
1287 static const struct panel_desc innolux_zj070na_01p = {
1288         .modes = &innolux_zj070na_01p_mode,
1289         .num_modes = 1,
1290         .bpc = 6,
1291         .size = {
1292                 .width = 1024,
1293                 .height = 600,
1294         },
1295 };
1296
1297 static const struct drm_display_mode lg_lb070wv8_mode = {
1298         .clock = 33246,
1299         .hdisplay = 800,
1300         .hsync_start = 800 + 88,
1301         .hsync_end = 800 + 88 + 80,
1302         .htotal = 800 + 88 + 80 + 88,
1303         .vdisplay = 480,
1304         .vsync_start = 480 + 10,
1305         .vsync_end = 480 + 10 + 25,
1306         .vtotal = 480 + 10 + 25 + 10,
1307         .vrefresh = 60,
1308 };
1309
1310 static const struct panel_desc lg_lb070wv8 = {
1311         .modes = &lg_lb070wv8_mode,
1312         .num_modes = 1,
1313         .bpc = 16,
1314         .size = {
1315                 .width = 151,
1316                 .height = 91,
1317         },
1318         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1319 };
1320
1321 static const struct drm_display_mode sharp_lcd_f402_mode = {
1322         .clock = 205000,
1323         .hdisplay = 1536,
1324         .hsync_start = 1536 + 12,
1325         .hsync_end = 1536 + 12 + 48,
1326         .htotal = 1536 + 12 + 48 + 16,
1327         .vdisplay = 2048,
1328         .vsync_start = 2048 + 8,
1329         .vsync_end = 2048 + 8 + 8,
1330         .vtotal = 2048 + 8 + 8 + 4,
1331         .vrefresh = 60,
1332         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1333 };
1334
1335 static const struct panel_desc sharp_lcd_f402 = {
1336         .modes = &sharp_lcd_f402_mode,
1337         .num_modes = 1,
1338         .bpc = 8,
1339         .size = {
1340                 .width = 95,
1341                 .height = 54,
1342         },
1343         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1344 };
1345
1346 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1347         .clock = 200000,
1348         .hdisplay = 1536,
1349         .hsync_start = 1536 + 12,
1350         .hsync_end = 1536 + 12 + 16,
1351         .htotal = 1536 + 12 + 16 + 48,
1352         .vdisplay = 2048,
1353         .vsync_start = 2048 + 8,
1354         .vsync_end = 2048 + 8 + 4,
1355         .vtotal = 2048 + 8 + 4 + 8,
1356         .vrefresh = 60,
1357         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1358 };
1359
1360 static const struct panel_desc lg_lp079qx1_sp0v = {
1361         .modes = &lg_lp079qx1_sp0v_mode,
1362         .num_modes = 1,
1363         .size = {
1364                 .width = 129,
1365                 .height = 171,
1366         },
1367         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1368 };
1369
1370 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1371         .clock = 205210,
1372         .hdisplay = 2048,
1373         .hsync_start = 2048 + 150,
1374         .hsync_end = 2048 + 150 + 5,
1375         .htotal = 2048 + 150 + 5 + 5,
1376         .vdisplay = 1536,
1377         .vsync_start = 1536 + 3,
1378         .vsync_end = 1536 + 3 + 1,
1379         .vtotal = 1536 + 3 + 1 + 9,
1380         .vrefresh = 60,
1381 };
1382
1383 static const struct panel_desc lg_lp097qx1_spa1 = {
1384         .modes = &lg_lp097qx1_spa1_mode,
1385         .num_modes = 1,
1386         .size = {
1387                 .width = 320,
1388                 .height = 187,
1389         },
1390 };
1391
1392 static const struct drm_display_mode lg_lp129qe_mode = {
1393         .clock = 285250,
1394         .hdisplay = 2560,
1395         .hsync_start = 2560 + 48,
1396         .hsync_end = 2560 + 48 + 32,
1397         .htotal = 2560 + 48 + 32 + 80,
1398         .vdisplay = 1700,
1399         .vsync_start = 1700 + 3,
1400         .vsync_end = 1700 + 3 + 10,
1401         .vtotal = 1700 + 3 + 10 + 36,
1402         .vrefresh = 60,
1403 };
1404
1405 static const struct panel_desc lg_lp129qe = {
1406         .modes = &lg_lp129qe_mode,
1407         .num_modes = 1,
1408         .bpc = 8,
1409         .size = {
1410                 .width = 272,
1411                 .height = 181,
1412         },
1413 };
1414
1415 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1416         .clock = 10870,
1417         .hdisplay = 480,
1418         .hsync_start = 480 + 2,
1419         .hsync_end = 480 + 2 + 41,
1420         .htotal = 480 + 2 + 41 + 2,
1421         .vdisplay = 272,
1422         .vsync_start = 272 + 2,
1423         .vsync_end = 272 + 2 + 4,
1424         .vtotal = 272 + 2 + 4 + 2,
1425         .vrefresh = 74,
1426 };
1427
1428 static const struct panel_desc nec_nl4827hc19_05b = {
1429         .modes = &nec_nl4827hc19_05b_mode,
1430         .num_modes = 1,
1431         .bpc = 8,
1432         .size = {
1433                 .width = 95,
1434                 .height = 54,
1435         },
1436         .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1437 };
1438
1439 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1440         .pixelclock = { 30000000, 30000000, 40000000 },
1441         .hactive = { 800, 800, 800 },
1442         .hfront_porch = { 40, 40, 40 },
1443         .hback_porch = { 40, 40, 40 },
1444         .hsync_len = { 1, 48, 48 },
1445         .vactive = { 480, 480, 480 },
1446         .vfront_porch = { 13, 13, 13 },
1447         .vback_porch = { 29, 29, 29 },
1448         .vsync_len = { 3, 3, 3 },
1449         .flags = DISPLAY_FLAGS_DE_HIGH,
1450 };
1451
1452 static const struct panel_desc okaya_rs800480t_7x0gp = {
1453         .timings = &okaya_rs800480t_7x0gp_timing,
1454         .num_timings = 1,
1455         .bpc = 6,
1456         .size = {
1457                 .width = 154,
1458                 .height = 87,
1459         },
1460         .delay = {
1461                 .prepare = 41,
1462                 .enable = 50,
1463                 .unprepare = 41,
1464                 .disable = 50,
1465         },
1466         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1467 };
1468
1469 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
1470         .clock = 25000,
1471         .hdisplay = 480,
1472         .hsync_start = 480 + 10,
1473         .hsync_end = 480 + 10 + 10,
1474         .htotal = 480 + 10 + 10 + 15,
1475         .vdisplay = 800,
1476         .vsync_start = 800 + 3,
1477         .vsync_end = 800 + 3 + 3,
1478         .vtotal = 800 + 3 + 3 + 3,
1479         .vrefresh = 60,
1480 };
1481
1482 static const struct panel_desc ortustech_com43h4m85ulc = {
1483         .modes = &ortustech_com43h4m85ulc_mode,
1484         .num_modes = 1,
1485         .bpc = 8,
1486         .size = {
1487                 .width = 56,
1488                 .height = 93,
1489         },
1490         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1491 };
1492
1493 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1494         .clock = 271560,
1495         .hdisplay = 2560,
1496         .hsync_start = 2560 + 48,
1497         .hsync_end = 2560 + 48 + 32,
1498         .htotal = 2560 + 48 + 32 + 80,
1499         .vdisplay = 1600,
1500         .vsync_start = 1600 + 2,
1501         .vsync_end = 1600 + 2 + 5,
1502         .vtotal = 1600 + 2 + 5 + 57,
1503         .vrefresh = 60,
1504 };
1505
1506 static const struct panel_desc samsung_lsn122dl01_c01 = {
1507         .modes = &samsung_lsn122dl01_c01_mode,
1508         .num_modes = 1,
1509         .size = {
1510                 .width = 2560,
1511                 .height = 1600,
1512         },
1513 };
1514
1515 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1516         .clock = 54030,
1517         .hdisplay = 1024,
1518         .hsync_start = 1024 + 24,
1519         .hsync_end = 1024 + 24 + 136,
1520         .htotal = 1024 + 24 + 136 + 160,
1521         .vdisplay = 600,
1522         .vsync_start = 600 + 3,
1523         .vsync_end = 600 + 3 + 6,
1524         .vtotal = 600 + 3 + 6 + 61,
1525         .vrefresh = 60,
1526 };
1527
1528 static const struct panel_desc samsung_ltn101nt05 = {
1529         .modes = &samsung_ltn101nt05_mode,
1530         .num_modes = 1,
1531         .bpc = 6,
1532         .size = {
1533                 .width = 1024,
1534                 .height = 600,
1535         },
1536 };
1537
1538 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1539         .clock = 76300,
1540         .hdisplay = 1366,
1541         .hsync_start = 1366 + 64,
1542         .hsync_end = 1366 + 64 + 48,
1543         .htotal = 1366 + 64 + 48 + 128,
1544         .vdisplay = 768,
1545         .vsync_start = 768 + 2,
1546         .vsync_end = 768 + 2 + 5,
1547         .vtotal = 768 + 2 + 5 + 17,
1548         .vrefresh = 60,
1549 };
1550
1551 static const struct panel_desc samsung_ltn140at29_301 = {
1552         .modes = &samsung_ltn140at29_301_mode,
1553         .num_modes = 1,
1554         .bpc = 6,
1555         .size = {
1556                 .width = 320,
1557                 .height = 187,
1558         },
1559 };
1560
1561 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1562         .clock = 33300,
1563         .hdisplay = 800,
1564         .hsync_start = 800 + 1,
1565         .hsync_end = 800 + 1 + 64,
1566         .htotal = 800 + 1 + 64 + 64,
1567         .vdisplay = 480,
1568         .vsync_start = 480 + 1,
1569         .vsync_end = 480 + 1 + 23,
1570         .vtotal = 480 + 1 + 23 + 22,
1571         .vrefresh = 60,
1572 };
1573
1574 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1575         .modes = &shelly_sca07010_bfn_lnn_mode,
1576         .num_modes = 1,
1577         .size = {
1578                 .width = 152,
1579                 .height = 91,
1580         },
1581         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1582 };
1583
1584 static const struct of_device_id platform_of_match[] = {
1585         {
1586                 .compatible = "simple-panel",
1587                 .data = NULL,
1588         }, {
1589                 .compatible = "ampire,am800480r3tmqwa1h",
1590                 .data = &ampire_am800480r3tmqwa1h,
1591         }, {
1592                 .compatible = "auo,b101aw03",
1593                 .data = &auo_b101aw03,
1594         }, {
1595                 .compatible = "auo,b101ean01",
1596                 .data = &auo_b101ean01,
1597         }, {
1598                 .compatible = "auo,b101ew05",
1599                 .data = &auo_b101ew05,
1600         }, {
1601                 .compatible = "auo,b101xtn01",
1602                 .data = &auo_b101xtn01,
1603         }, {
1604                 .compatible = "auo,b116xw03",
1605                 .data = &auo_b116xw03,
1606         }, {
1607                 .compatible = "auo,b125han03",
1608                 .data = &auo_b125han03,
1609         }, {
1610                 .compatible = "auo,b133htn01",
1611                 .data = &auo_b133htn01,
1612         }, {
1613                 .compatible = "auo,b133xtn01",
1614                 .data = &auo_b133xtn01,
1615         }, {
1616                 .compatible = "avic,tm070ddh03",
1617                 .data = &avic_tm070ddh03,
1618         }, {
1619                 .compatible = "boe,nv125fhm-n73",
1620                 .data = &boe_nv125fhm_n73,
1621         }, {
1622                 .compatible = "chunghwa,claa070wp03xg",
1623                 .data = &chunghwa_claa070wp03xg,
1624         }, {
1625                 .compatible = "chunghwa,claa101wa01a",
1626                 .data = &chunghwa_claa101wa01a
1627         }, {
1628                 .compatible = "chunghwa,claa101wb01",
1629                 .data = &chunghwa_claa101wb01
1630         }, {
1631                 .compatible = "edt,et057090dhu",
1632                 .data = &edt_et057090dhu,
1633         }, {
1634                 .compatible = "edt,et070080dh6",
1635                 .data = &edt_etm0700g0dh6,
1636         }, {
1637                 .compatible = "edt,etm0700g0dh6",
1638                 .data = &edt_etm0700g0dh6,
1639         }, {
1640                 .compatible = "foxlink,fl500wvr00-a0t",
1641                 .data = &foxlink_fl500wvr00_a0t,
1642         }, {
1643                 .compatible = "giantplus,gpg482739qs5",
1644                 .data = &giantplus_gpg482739qs5
1645         }, {
1646                 .compatible = "hannstar,hsd070pww1",
1647                 .data = &hannstar_hsd070pww1,
1648         }, {
1649                 .compatible = "hannstar,hsd100pxn1",
1650                 .data = &hannstar_hsd100pxn1,
1651         }, {
1652                 .compatible = "hit,tx23d38vm0caa",
1653                 .data = &hitachi_tx23d38vm0caa
1654         }, {
1655                 .compatible = "innolux,at043tn24",
1656                 .data = &innolux_at043tn24,
1657         }, {
1658                 .compatible ="innolux,g121i1-l01",
1659                 .data = &innolux_g121i1_l01
1660         }, {
1661                 .compatible = "innolux,n116bge",
1662                 .data = &innolux_n116bge,
1663         }, {
1664                 .compatible = "innolux,n125hce",
1665                 .data = &innolux_n125hce,
1666         }, {
1667                 .compatible = "innolux,n156bge-l21",
1668                 .data = &innolux_n156bge_l21,
1669         }, {
1670                 .compatible = "innolux,zj070na-01p",
1671                 .data = &innolux_zj070na_01p,
1672         }, {
1673                 .compatible = "lg,lb070wv8",
1674                 .data = &lg_lb070wv8,
1675         }, {
1676                 .compatible = "lg,lp079qx1-sp0v",
1677                 .data = &lg_lp079qx1_sp0v,
1678         }, {
1679                 .compatible = "lg,lp097qx1-spa1",
1680                 .data = &lg_lp097qx1_spa1,
1681         }, {
1682                 .compatible = "lg,lp129qe",
1683                 .data = &lg_lp129qe,
1684         }, {
1685                 .compatible = "nec,nl4827hc19-05b",
1686                 .data = &nec_nl4827hc19_05b,
1687         }, {
1688                 .compatible = "okaya,rs800480t-7x0gp",
1689                 .data = &okaya_rs800480t_7x0gp,
1690         }, {
1691                 .compatible = "ortustech,com43h4m85ulc",
1692                 .data = &ortustech_com43h4m85ulc,
1693         }, {
1694                 .compatible = "samsung,lsn122dl01-c01",
1695                 .data = &samsung_lsn122dl01_c01,
1696         }, {
1697                 .compatible = "samsung,ltn101nt05",
1698                 .data = &samsung_ltn101nt05,
1699         }, {
1700                 .compatible = "samsung,ltn140at29-301",
1701                 .data = &samsung_ltn140at29_301,
1702         }, {
1703                 .compatible = "sharp,lcd-f402",
1704                 .data = &sharp_lcd_f402,
1705         }, {
1706                 .compatible = "shelly,sca07010-bfn-lnn",
1707                 .data = &shelly_sca07010_bfn_lnn,
1708         }, {
1709                 /* sentinel */
1710         }
1711 };
1712 MODULE_DEVICE_TABLE(of, platform_of_match);
1713
1714 static int panel_simple_platform_probe(struct platform_device *pdev)
1715 {
1716         const struct of_device_id *id;
1717
1718         id = of_match_node(platform_of_match, pdev->dev.of_node);
1719         if (!id)
1720                 return -ENODEV;
1721
1722         return panel_simple_probe(&pdev->dev, id->data);
1723 }
1724
1725 static int panel_simple_platform_remove(struct platform_device *pdev)
1726 {
1727         return panel_simple_remove(&pdev->dev);
1728 }
1729
1730 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1731 {
1732         panel_simple_shutdown(&pdev->dev);
1733 }
1734
1735 static struct platform_driver panel_simple_platform_driver = {
1736         .driver = {
1737                 .name = "panel-simple",
1738                 .of_match_table = platform_of_match,
1739         },
1740         .probe = panel_simple_platform_probe,
1741         .remove = panel_simple_platform_remove,
1742         .shutdown = panel_simple_platform_shutdown,
1743 };
1744
1745 struct panel_desc_dsi {
1746         struct panel_desc desc;
1747
1748         unsigned long flags;
1749         enum mipi_dsi_pixel_format format;
1750         unsigned int lanes;
1751 };
1752
1753 static const struct drm_display_mode auo_b080uan01_mode = {
1754         .clock = 154500,
1755         .hdisplay = 1200,
1756         .hsync_start = 1200 + 62,
1757         .hsync_end = 1200 + 62 + 4,
1758         .htotal = 1200 + 62 + 4 + 62,
1759         .vdisplay = 1920,
1760         .vsync_start = 1920 + 9,
1761         .vsync_end = 1920 + 9 + 2,
1762         .vtotal = 1920 + 9 + 2 + 8,
1763         .vrefresh = 60,
1764 };
1765
1766 static const struct panel_desc_dsi auo_b080uan01 = {
1767         .desc = {
1768                 .modes = &auo_b080uan01_mode,
1769                 .num_modes = 1,
1770                 .bpc = 8,
1771                 .size = {
1772                         .width = 108,
1773                         .height = 272,
1774                 },
1775         },
1776         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1777         .format = MIPI_DSI_FMT_RGB888,
1778         .lanes = 4,
1779 };
1780
1781 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1782         .clock = 160000,
1783         .hdisplay = 1200,
1784         .hsync_start = 1200 + 120,
1785         .hsync_end = 1200 + 120 + 20,
1786         .htotal = 1200 + 120 + 20 + 21,
1787         .vdisplay = 1920,
1788         .vsync_start = 1920 + 21,
1789         .vsync_end = 1920 + 21 + 3,
1790         .vtotal = 1920 + 21 + 3 + 18,
1791         .vrefresh = 60,
1792         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1793 };
1794
1795 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1796         .desc = {
1797                 .modes = &boe_tv080wum_nl0_mode,
1798                 .num_modes = 1,
1799                 .size = {
1800                         .width = 107,
1801                         .height = 172,
1802                 },
1803         },
1804         .flags = MIPI_DSI_MODE_VIDEO |
1805                  MIPI_DSI_MODE_VIDEO_BURST |
1806                  MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1807         .format = MIPI_DSI_FMT_RGB888,
1808         .lanes = 4,
1809 };
1810
1811 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1812         .clock = 71000,
1813         .hdisplay = 800,
1814         .hsync_start = 800 + 32,
1815         .hsync_end = 800 + 32 + 1,
1816         .htotal = 800 + 32 + 1 + 57,
1817         .vdisplay = 1280,
1818         .vsync_start = 1280 + 28,
1819         .vsync_end = 1280 + 28 + 1,
1820         .vtotal = 1280 + 28 + 1 + 14,
1821         .vrefresh = 60,
1822 };
1823
1824 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1825         .desc = {
1826                 .modes = &lg_ld070wx3_sl01_mode,
1827                 .num_modes = 1,
1828                 .bpc = 8,
1829                 .size = {
1830                         .width = 94,
1831                         .height = 151,
1832                 },
1833         },
1834         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1835         .format = MIPI_DSI_FMT_RGB888,
1836         .lanes = 4,
1837 };
1838
1839 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1840         .clock = 67000,
1841         .hdisplay = 720,
1842         .hsync_start = 720 + 12,
1843         .hsync_end = 720 + 12 + 4,
1844         .htotal = 720 + 12 + 4 + 112,
1845         .vdisplay = 1280,
1846         .vsync_start = 1280 + 8,
1847         .vsync_end = 1280 + 8 + 4,
1848         .vtotal = 1280 + 8 + 4 + 12,
1849         .vrefresh = 60,
1850 };
1851
1852 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1853         .desc = {
1854                 .modes = &lg_lh500wx1_sd03_mode,
1855                 .num_modes = 1,
1856                 .bpc = 8,
1857                 .size = {
1858                         .width = 62,
1859                         .height = 110,
1860                 },
1861         },
1862         .flags = MIPI_DSI_MODE_VIDEO,
1863         .format = MIPI_DSI_FMT_RGB888,
1864         .lanes = 4,
1865 };
1866
1867 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1868         .clock = 157200,
1869         .hdisplay = 1920,
1870         .hsync_start = 1920 + 154,
1871         .hsync_end = 1920 + 154 + 16,
1872         .htotal = 1920 + 154 + 16 + 32,
1873         .vdisplay = 1200,
1874         .vsync_start = 1200 + 17,
1875         .vsync_end = 1200 + 17 + 2,
1876         .vtotal = 1200 + 17 + 2 + 16,
1877         .vrefresh = 60,
1878 };
1879
1880 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1881         .desc = {
1882                 .modes = &panasonic_vvx10f004b00_mode,
1883                 .num_modes = 1,
1884                 .bpc = 8,
1885                 .size = {
1886                         .width = 217,
1887                         .height = 136,
1888                 },
1889         },
1890         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1891                  MIPI_DSI_CLOCK_NON_CONTINUOUS,
1892         .format = MIPI_DSI_FMT_RGB888,
1893         .lanes = 4,
1894 };
1895
1896
1897 static const struct of_device_id dsi_of_match[] = {
1898         {
1899                 .compatible = "simple-panel-dsi",
1900                 .data = NULL
1901         }, {
1902                 .compatible = "auo,b080uan01",
1903                 .data = &auo_b080uan01
1904         }, {
1905                 .compatible = "boe,tv080wum-nl0",
1906                 .data = &boe_tv080wum_nl0
1907         }, {
1908                 .compatible = "lg,ld070wx3-sl01",
1909                 .data = &lg_ld070wx3_sl01
1910         }, {
1911                 .compatible = "lg,lh500wx1-sd03",
1912                 .data = &lg_lh500wx1_sd03
1913         }, {
1914                 .compatible = "panasonic,vvx10f004b00",
1915                 .data = &panasonic_vvx10f004b00
1916         }, {
1917                 /* sentinel */
1918         }
1919 };
1920 MODULE_DEVICE_TABLE(of, dsi_of_match);
1921
1922 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1923 {
1924         struct panel_simple *panel;
1925         const struct panel_desc_dsi *desc;
1926         const struct of_device_id *id;
1927         const struct panel_desc *pdesc;
1928         const void *data;
1929         int len;
1930         u32 val;
1931         int err;
1932
1933         id = of_match_node(dsi_of_match, dsi->dev.of_node);
1934         if (!id)
1935                 return -ENODEV;
1936
1937         desc = id->data;
1938
1939         if (desc) {
1940                 dsi->mode_flags = desc->flags;
1941                 dsi->format = desc->format;
1942                 dsi->lanes = desc->lanes;
1943                 pdesc = &desc->desc;
1944         } else {
1945                 pdesc = NULL;
1946         }
1947
1948         err = panel_simple_probe(&dsi->dev, pdesc);
1949         if (err < 0)
1950                 return err;
1951
1952         panel = dev_get_drvdata(&dsi->dev);
1953         panel->dsi = dsi;
1954
1955         if (!of_property_read_u32(dsi->dev.of_node, "dsi,flags", &val))
1956                 dsi->mode_flags = val;
1957
1958         if (!of_property_read_u32(dsi->dev.of_node, "dsi,format", &val))
1959                 dsi->format = val;
1960
1961         if (!of_property_read_u32(dsi->dev.of_node, "dsi,lanes", &val))
1962                 dsi->lanes = val;
1963
1964         if (!of_property_read_u32(dsi->dev.of_node, "reset-delay-ms", &val))
1965                 panel->reset_delay = val;
1966
1967         data = of_get_property(dsi->dev.of_node, "panel-init-sequence", &len);
1968         if (data) {
1969                 panel->on_cmds = devm_kzalloc(&dsi->dev,
1970                                               sizeof(*panel->on_cmds),
1971                                               GFP_KERNEL);
1972                 if (!panel->on_cmds)
1973                         return -ENOMEM;
1974
1975                 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
1976                                                       panel->on_cmds);
1977                 if (err) {
1978                         dev_err(&dsi->dev, "failed to parse panel init sequence\n");
1979                         return err;
1980                 }
1981         }
1982
1983         data = of_get_property(dsi->dev.of_node, "panel-exit-sequence", &len);
1984         if (data) {
1985                 panel->off_cmds = devm_kzalloc(&dsi->dev,
1986                                                sizeof(*panel->off_cmds),
1987                                                GFP_KERNEL);
1988                 if (!panel->off_cmds)
1989                         return -ENOMEM;
1990
1991                 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
1992                                                       panel->off_cmds);
1993                 if (err) {
1994                         dev_err(&dsi->dev, "failed to parse panel exit sequence\n");
1995                         return err;
1996                 }
1997         }
1998
1999         return mipi_dsi_attach(dsi);
2000 }
2001
2002 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2003 {
2004         int err;
2005
2006         err = mipi_dsi_detach(dsi);
2007         if (err < 0)
2008                 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2009
2010         return panel_simple_remove(&dsi->dev);
2011 }
2012
2013 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2014 {
2015         panel_simple_shutdown(&dsi->dev);
2016 }
2017
2018 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2019         .driver = {
2020                 .name = "panel-simple-dsi",
2021                 .of_match_table = dsi_of_match,
2022         },
2023         .probe = panel_simple_dsi_probe,
2024         .remove = panel_simple_dsi_remove,
2025         .shutdown = panel_simple_dsi_shutdown,
2026 };
2027
2028 static int __init panel_simple_init(void)
2029 {
2030         int err;
2031
2032         err = platform_driver_register(&panel_simple_platform_driver);
2033         if (err < 0)
2034                 return err;
2035
2036         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2037                 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2038                 if (err < 0)
2039                         return err;
2040         }
2041
2042         return 0;
2043 }
2044 module_init(panel_simple_init);
2045
2046 static void __exit panel_simple_exit(void)
2047 {
2048         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2049                 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2050
2051         platform_driver_unregister(&panel_simple_platform_driver);
2052 }
2053 module_exit(panel_simple_exit);
2054
2055 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2056 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2057 MODULE_LICENSE("GPL and additional rights");