drivers/gpu/drm/panel/panel-simple.c

   1 /*
   2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/backlight.h>
  25 #include <linux/gpio/consumer.h>
  26 #include <linux/module.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_mipi_dsi.h>
  34 #include <drm/drm_panel.h>
  35
  36 #include <video/display_timing.h>
  37 #include <video/mipi_display.h>
  38 #include <video/of_display_timing.h>
  39 #include <video/videomode.h>
  40
  41 struct dsi_ctrl_hdr {
  42         u8 dtype;       /* data type */
  43         u8 wait;        /* ms */
  44         u8 dlen;        /* payload len */
  45 } __packed;
  46
  47 struct dsi_cmd_desc {
  48         struct dsi_ctrl_hdr dchdr;
  49         u8 *payload;
  50 };
  51
  52 struct dsi_panel_cmds {
  53         u8 *buf;
  54         int blen;
  55         struct dsi_cmd_desc *cmds;
  56         int cmd_cnt;
  57 };
  58
  59 struct panel_desc {
  60         const struct drm_display_mode *modes;
  61         unsigned int num_modes;
  62         const struct display_timing *timings;
  63         unsigned int num_timings;
  64
  65         unsigned int bpc;
  66
  67         struct {
  68                 unsigned int width;
  69                 unsigned int height;
  70         } size;
  71
  72         /**
  73          * @reset: the time (in milliseconds) indicates the delay time
  74          *         after the panel to operate reset gpio
  75          * @init: the time (in milliseconds) that it takes for the panel to
  76          *           power on and dsi host can send command to panel
  77          * @prepare: the time (in milliseconds) that it takes for the panel to
  78          *           become ready and start receiving video data
  79          * @enable: the time (in milliseconds) that it takes for the panel to
  80          *          display the first valid frame after starting to receive
  81          *          video data
  82          * @disable: the time (in milliseconds) that it takes for the panel to
  83          *           turn the display off (no content is visible)
  84          * @unprepare: the time (in milliseconds) that it takes for the panel
  85          *             to power itself down completely
  86          */
  87         struct {
  88                 unsigned int reset;
  89                 unsigned int init;
  90                 unsigned int prepare;
  91                 unsigned int enable;
  92                 unsigned int disable;
  93                 unsigned int unprepare;
  94         } delay;
  95
  96         u32 bus_format;
  97 };
  98
  99 struct panel_simple {
 100         struct drm_panel base;
 101         struct mipi_dsi_device *dsi;
 102         bool prepared;
 103         bool enabled;
 104
 105         struct device *dev;
 106         const struct panel_desc *desc;
 107
 108         struct backlight_device *backlight;
 109         struct regulator *supply;
 110         struct i2c_adapter *ddc;
 111
 112         struct gpio_desc *enable_gpio;
 113         struct gpio_desc *reset_gpio;
 114
 115         struct dsi_panel_cmds *on_cmds;
 116         struct dsi_panel_cmds *off_cmds;
 117 };
 118
 119 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
 120 {
 121         return container_of(panel, struct panel_simple, base);
 122 }
 123
 124 static void panel_simple_dsi_cmds_cleanup(struct panel_simple *p)
 125 {
 126         if (p->on_cmds) {
 127                 kfree(p->on_cmds->buf);
 128                 kfree(p->on_cmds->cmds);
 129         }
 130
 131         if (p->off_cmds) {
 132                 kfree(p->off_cmds->buf);
 133                 kfree(p->off_cmds->cmds);
 134         }
 135 }
 136
 137 static int panel_simple_dsi_parse_dcs_cmds(struct device *dev,
 138                                            const u8 *data, int blen,
 139                                            struct dsi_panel_cmds *pcmds)
 140 {
 141         int len;
 142         char *buf, *bp;
 143         struct dsi_ctrl_hdr *dchdr;
 144         int i, cnt;
 145
 146         if (!pcmds)
 147                 return -EINVAL;
 148
 149         buf = kmemdup(data, blen, GFP_KERNEL);
 150         if (!buf)
 151                 return -ENOMEM;
 152
 153         /* scan dcs commands */
 154         bp = buf;
 155         len = blen;
 156         cnt = 0;
 157         while (len > sizeof(*dchdr)) {
 158                 dchdr = (struct dsi_ctrl_hdr *)bp;
 159
 160                 if (dchdr->dlen > len) {
 161                         dev_err(dev, "%s: error, len=%d", __func__,
 162                                 dchdr->dlen);
 163                         return -EINVAL;
 164                 }
 165
 166                 bp += sizeof(*dchdr);
 167                 len -= sizeof(*dchdr);
 168                 bp += dchdr->dlen;
 169                 len -= dchdr->dlen;
 170                 cnt++;
 171         }
 172
 173         if (len != 0) {
 174                 dev_err(dev, "%s: dcs_cmd=%x len=%d error!",
 175                         __func__, buf[0], blen);
 176                 kfree(buf);
 177                 return -EINVAL;
 178         }
 179
 180         pcmds->cmds = kcalloc(cnt, sizeof(struct dsi_cmd_desc), GFP_KERNEL);
 181         if (!pcmds->cmds) {
 182                 kfree(buf);
 183                 return -ENOMEM;
 184         }
 185
 186         pcmds->cmd_cnt = cnt;
 187         pcmds->buf = buf;
 188         pcmds->blen = blen;
 189
 190         bp = buf;
 191         len = blen;
 192         for (i = 0; i < cnt; i++) {
 193                 dchdr = (struct dsi_ctrl_hdr *)bp;
 194                 len -= sizeof(*dchdr);
 195                 bp += sizeof(*dchdr);
 196                 pcmds->cmds[i].dchdr = *dchdr;
 197                 pcmds->cmds[i].payload = bp;
 198                 bp += dchdr->dlen;
 199                 len -= dchdr->dlen;
 200         }
 201
 202         dev_info(dev, "%s: dcs_cmd=%x len=%d, cmd_cnt=%d\n", __func__,
 203                  pcmds->buf[0], pcmds->blen, pcmds->cmd_cnt);
 204         return 0;
 205 }
 206
 207 static int panel_simple_dsi_send_cmds(struct panel_simple *panel,
 208                                       struct dsi_panel_cmds *cmds)
 209 {
 210         struct mipi_dsi_device *dsi = panel->dsi;
 211         int i, err;
 212
 213         if (!cmds)
 214                 return -EINVAL;
 215
 216         for (i = 0; i < cmds->cmd_cnt; i++) {
 217                 struct dsi_cmd_desc *cmd = &cmds->cmds[i];
 218
 219                 switch (cmd->dchdr.dtype) {
 220                 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 221                 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 222                 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 223                 case MIPI_DSI_GENERIC_LONG_WRITE:
 224                         err = mipi_dsi_generic_write(dsi, cmd->payload,
 225                                                      cmd->dchdr.dlen);
 226                         break;
 227                 case MIPI_DSI_DCS_SHORT_WRITE:
 228                 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 229                 case MIPI_DSI_DCS_LONG_WRITE:
 230                         err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
 231                                                         cmd->dchdr.dlen);
 232                         break;
 233                 default:
 234                         return -EINVAL;
 235                 }
 236
 237                 if (err < 0)
 238                         dev_err(panel->dev, "failed to write dcs cmd: %d\n",
 239                                 err);
 240
 241                 if (cmd->dchdr.wait)
 242                         msleep(cmd->dchdr.wait);
 243         }
 244
 245         return 0;
 246 }
 247
 248 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
 249 {
 250         struct drm_connector *connector = panel->base.connector;
 251         struct drm_device *drm = panel->base.drm;
 252         struct drm_display_mode *mode;
 253         unsigned int i, num = 0;
 254
 255         if (!panel->desc)
 256                 return 0;
 257
 258         for (i = 0; i < panel->desc->num_timings; i++) {
 259                 const struct display_timing *dt = &panel->desc->timings[i];
 260                 struct videomode vm;
 261
 262                 videomode_from_timing(dt, &vm);
 263                 mode = drm_mode_create(drm);
 264                 if (!mode) {
 265                         dev_err(drm->dev, "failed to add mode %ux%u\n",
 266                                 dt->hactive.typ, dt->vactive.typ);
 267                         continue;
 268                 }
 269
 270                 drm_display_mode_from_videomode(&vm, mode);
 271                 drm_mode_set_name(mode);
 272
 273                 drm_mode_probed_add(connector, mode);
 274                 num++;
 275         }
 276
 277         for (i = 0; i < panel->desc->num_modes; i++) {
 278                 const struct drm_display_mode *m = &panel->desc->modes[i];
 279
 280                 mode = drm_mode_duplicate(drm, m);
 281                 if (!mode) {
 282                         dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
 283                                 m->hdisplay, m->vdisplay, m->vrefresh);
 284                         continue;
 285                 }
 286
 287                 drm_mode_set_name(mode);
 288
 289                 drm_mode_probed_add(connector, mode);
 290                 num++;
 291         }
 292
 293         connector->display_info.bpc = panel->desc->bpc;
 294         connector->display_info.width_mm = panel->desc->size.width;
 295         connector->display_info.height_mm = panel->desc->size.height;
 296         if (panel->desc->bus_format)
 297                 drm_display_info_set_bus_formats(&connector->display_info,
 298                                                  &panel->desc->bus_format, 1);
 299
 300         return num;
 301 }
 302
 303 static int panel_simple_of_get_native_mode(struct panel_simple *panel)
 304 {
 305         struct drm_connector *connector = panel->base.connector;
 306         struct drm_device *drm = panel->base.drm;
 307         struct drm_display_mode *mode;
 308         struct device_node *timings_np;
 309         int ret;
 310
 311         timings_np = of_get_child_by_name(panel->dev->of_node,
 312                                           "display-timings");
 313         if (!timings_np) {
 314                 dev_dbg(panel->dev, "failed to find display-timings node\n");
 315                 return 0;
 316         }
 317
 318         of_node_put(timings_np);
 319         mode = drm_mode_create(drm);
 320         if (!mode)
 321                 return 0;
 322
 323         ret = of_get_drm_display_mode(panel->dev->of_node, mode,
 324                                       OF_USE_NATIVE_MODE);
 325         if (ret) {
 326                 dev_dbg(panel->dev, "failed to find dts display timings\n");
 327                 drm_mode_destroy(drm, mode);
 328                 return 0;
 329         }
 330
 331         drm_mode_set_name(mode);
 332         mode->type |= DRM_MODE_TYPE_PREFERRED;
 333         drm_mode_probed_add(connector, mode);
 334
 335         return 1;
 336 }
 337
 338 static int panel_simple_loader_protect(struct drm_panel *panel, bool on)
 339 {
 340         struct panel_simple *p = to_panel_simple(panel);
 341         int err;
 342
 343         if (on) {
 344                 err = regulator_enable(p->supply);
 345                 if (err < 0) {
 346                         dev_err(panel->dev, "failed to enable supply: %d\n",
 347                                 err);
 348                         return err;
 349                 }
 350         } else {
 351                 regulator_disable(p->supply);
 352         }
 353
 354         return 0;
 355 }
 356
 357 static int panel_simple_disable(struct drm_panel *panel)
 358 {
 359         struct panel_simple *p = to_panel_simple(panel);
 360
 361         if (!p->enabled)
 362                 return 0;
 363
 364         if (p->backlight) {
 365                 p->backlight->props.power = FB_BLANK_POWERDOWN;
 366                 backlight_update_status(p->backlight);
 367         }
 368
 369         if (p->desc && p->desc->delay.disable)
 370                 msleep(p->desc->delay.disable);
 371
 372         p->enabled = false;
 373
 374         return 0;
 375 }
 376
 377 static int panel_simple_unprepare(struct drm_panel *panel)
 378 {
 379         struct panel_simple *p = to_panel_simple(panel);
 380         int err;
 381
 382         if (!p->prepared)
 383                 return 0;
 384
 385         if (p->off_cmds) {
 386                 err = panel_simple_dsi_send_cmds(p, p->off_cmds);
 387                 if (err)
 388                         dev_err(p->dev, "failed to send off cmds\n");
 389         }
 390
 391         if (p->reset_gpio)
 392                 gpiod_direction_output(p->reset_gpio, 1);
 393
 394         if (p->enable_gpio)
 395                 gpiod_direction_output(p->enable_gpio, 0);
 396
 397         regulator_disable(p->supply);
 398
 399         if (p->desc && p->desc->delay.unprepare)
 400                 msleep(p->desc->delay.unprepare);
 401
 402         p->prepared = false;
 403
 404         return 0;
 405 }
 406
 407 static int panel_simple_prepare(struct drm_panel *panel)
 408 {
 409         struct panel_simple *p = to_panel_simple(panel);
 410         int err;
 411
 412         if (p->prepared)
 413                 return 0;
 414
 415         err = regulator_enable(p->supply);
 416         if (err < 0) {
 417                 dev_err(panel->dev, "failed to enable supply: %d\n", err);
 418                 return err;
 419         }
 420
 421         if (p->enable_gpio)
 422                 gpiod_direction_output(p->enable_gpio, 1);
 423
 424         if (p->desc && p->desc->delay.prepare)
 425                 msleep(p->desc->delay.prepare);
 426
 427         if (p->reset_gpio)
 428                 gpiod_direction_output(p->reset_gpio, 1);
 429
 430         if (p->desc && p->desc->delay.reset)
 431                 msleep(p->desc->delay.reset);
 432
 433         if (p->reset_gpio)
 434                 gpiod_direction_output(p->reset_gpio, 0);
 435
 436         if (p->desc && p->desc->delay.init)
 437                 msleep(p->desc->delay.init);
 438
 439
 440
 441         p->prepared = true;
 442
 443         return 0;
 444 }
 445
 446 static int panel_simple_enable(struct drm_panel *panel)
 447 {
 448         struct panel_simple *p = to_panel_simple(panel);
 449         int err;
 450
 451         if (p->enabled)
 452                 return 0;
 453
 454         if (p->desc && p->desc->delay.enable)
 455                 msleep(p->desc->delay.enable);
 456
 457         if (p->on_cmds) {
 458                 err = panel_simple_dsi_send_cmds(p, p->on_cmds);
 459                 if (err)
 460                         dev_err(p->dev, "failed to send on cmds\n");
 461         }
 462
 463         if (p->backlight) {
 464                 p->backlight->props.power = FB_BLANK_UNBLANK;
 465                 backlight_update_status(p->backlight);
 466         }
 467
 468         p->enabled = true;
 469
 470         return 0;
 471 }
 472
 473 static int panel_simple_get_modes(struct drm_panel *panel)
 474 {
 475         struct panel_simple *p = to_panel_simple(panel);
 476         int num = 0;
 477
 478         /* add device node plane modes */
 479         num += panel_simple_of_get_native_mode(p);
 480
 481         /* add hard-coded panel modes */
 482         num += panel_simple_get_fixed_modes(p);
 483
 484         /* probe EDID if a DDC bus is available */
 485         if (p->ddc) {
 486                 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
 487                 drm_mode_connector_update_edid_property(panel->connector, edid);
 488                 if (edid) {
 489                         num += drm_add_edid_modes(panel->connector, edid);
 490                         kfree(edid);
 491                 }
 492         }
 493
 494         return num;
 495 }
 496
 497 static int panel_simple_get_timings(struct drm_panel *panel,
 498                                     unsigned int num_timings,
 499                                     struct display_timing *timings)
 500 {
 501         struct panel_simple *p = to_panel_simple(panel);
 502         unsigned int i;
 503
 504         if (!p->desc)
 505                 return 0;
 506
 507         if (p->desc->num_timings < num_timings)
 508                 num_timings = p->desc->num_timings;
 509
 510         if (timings)
 511                 for (i = 0; i < num_timings; i++)
 512                         timings[i] = p->desc->timings[i];
 513
 514         return p->desc->num_timings;
 515 }
 516
 517 static const struct drm_panel_funcs panel_simple_funcs = {
 518         .loader_protect = panel_simple_loader_protect,
 519         .disable = panel_simple_disable,
 520         .unprepare = panel_simple_unprepare,
 521         .prepare = panel_simple_prepare,
 522         .enable = panel_simple_enable,
 523         .get_modes = panel_simple_get_modes,
 524         .get_timings = panel_simple_get_timings,
 525 };
 526
 527 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 528 {
 529         struct device_node *backlight, *ddc;
 530         struct panel_simple *panel;
 531         struct panel_desc *of_desc;
 532         u32 val;
 533         int err;
 534
 535         panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
 536         if (!panel)
 537                 return -ENOMEM;
 538
 539         if (!desc)
 540                 of_desc = devm_kzalloc(dev, sizeof(*of_desc), GFP_KERNEL);
 541         else
 542                 of_desc = devm_kmemdup(dev, desc, sizeof(*of_desc), GFP_KERNEL);
 543
 544         if (!of_property_read_u32(dev->of_node, "bus-format", &val))
 545                 of_desc->bus_format = val;
 546         if (!of_property_read_u32(dev->of_node, "prepare-delay-ms", &val))
 547                 of_desc->delay.prepare = val;
 548         if (!of_property_read_u32(dev->of_node, "enable-delay-ms", &val))
 549                 of_desc->delay.enable = val;
 550         if (!of_property_read_u32(dev->of_node, "disable-delay-ms", &val))
 551                 of_desc->delay.disable = val;
 552         if (!of_property_read_u32(dev->of_node, "unprepare-delay-ms", &val))
 553                 of_desc->delay.unprepare = val;
 554         if (!of_property_read_u32(dev->of_node, "reset-delay-ms", &val))
 555                 of_desc->delay.reset = val;
 556         if (!of_property_read_u32(dev->of_node, "init-delay-ms", &val))
 557                 of_desc->delay.init = val;
 558
 559         panel->enabled = false;
 560         panel->prepared = false;
 561         panel->desc = of_desc;
 562         panel->dev = dev;
 563
 564         panel->supply = devm_regulator_get(dev, "power");
 565         if (IS_ERR(panel->supply))
 566                 return PTR_ERR(panel->supply);
 567
 568         panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 0);
 569         if (IS_ERR(panel->enable_gpio)) {
 570                 err = PTR_ERR(panel->enable_gpio);
 571                 dev_err(dev, "failed to request enable GPIO: %d\n", err);
 572                 return err;
 573         }
 574
 575         panel->reset_gpio = devm_gpiod_get_optional(dev, "reset", 0);
 576         if (IS_ERR(panel->reset_gpio)) {
 577                 err = PTR_ERR(panel->reset_gpio);
 578                 dev_err(dev, "failed to request reset GPIO: %d\n", err);
 579                 return err;
 580         }
 581
 582         backlight = of_parse_phandle(dev->of_node, "backlight", 0);
 583         if (backlight) {
 584                 panel->backlight = of_find_backlight_by_node(backlight);
 585                 of_node_put(backlight);
 586
 587                 if (!panel->backlight)
 588                         return -EPROBE_DEFER;
 589         }
 590
 591         ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
 592         if (ddc) {
 593                 panel->ddc = of_find_i2c_adapter_by_node(ddc);
 594                 of_node_put(ddc);
 595
 596                 if (!panel->ddc) {
 597                         err = -EPROBE_DEFER;
 598                         goto free_backlight;
 599                 }
 600         }
 601
 602         drm_panel_init(&panel->base);
 603         panel->base.dev = dev;
 604         panel->base.funcs = &panel_simple_funcs;
 605
 606         err = drm_panel_add(&panel->base);
 607         if (err < 0)
 608                 goto free_ddc;
 609
 610         dev_set_drvdata(dev, panel);
 611
 612         return 0;
 613
 614 free_ddc:
 615         if (panel->ddc)
 616                 put_device(&panel->ddc->dev);
 617 free_backlight:
 618         if (panel->backlight)
 619                 put_device(&panel->backlight->dev);
 620
 621         return err;
 622 }
 623
 624 static int panel_simple_remove(struct device *dev)
 625 {
 626         struct panel_simple *panel = dev_get_drvdata(dev);
 627
 628         drm_panel_detach(&panel->base);
 629         drm_panel_remove(&panel->base);
 630
 631         panel_simple_disable(&panel->base);
 632
 633         if (panel->ddc)
 634                 put_device(&panel->ddc->dev);
 635
 636         if (panel->backlight)
 637                 put_device(&panel->backlight->dev);
 638
 639         panel_simple_dsi_cmds_cleanup(panel);
 640
 641         return 0;
 642 }
 643
 644 static void panel_simple_shutdown(struct device *dev)
 645 {
 646         struct panel_simple *panel = dev_get_drvdata(dev);
 647
 648         panel_simple_disable(&panel->base);
 649 }
 650
 651 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
 652         .clock = 33333,
 653         .hdisplay = 800,
 654         .hsync_start = 800 + 0,
 655         .hsync_end = 800 + 0 + 255,
 656         .htotal = 800 + 0 + 255 + 0,
 657         .vdisplay = 480,
 658         .vsync_start = 480 + 2,
 659         .vsync_end = 480 + 2 + 45,
 660         .vtotal = 480 + 2 + 45 + 0,
 661         .vrefresh = 60,
 662         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 663 };
 664
 665 static const struct panel_desc ampire_am800480r3tmqwa1h = {
 666         .modes = &ampire_am800480r3tmqwa1h_mode,
 667         .num_modes = 1,
 668         .bpc = 6,
 669         .size = {
 670                 .width = 152,
 671                 .height = 91,
 672         },
 673         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 674 };
 675
 676 static const struct drm_display_mode auo_b101aw03_mode = {
 677         .clock = 51450,
 678         .hdisplay = 1024,
 679         .hsync_start = 1024 + 156,
 680         .hsync_end = 1024 + 156 + 8,
 681         .htotal = 1024 + 156 + 8 + 156,
 682         .vdisplay = 600,
 683         .vsync_start = 600 + 16,
 684         .vsync_end = 600 + 16 + 6,
 685         .vtotal = 600 + 16 + 6 + 16,
 686         .vrefresh = 60,
 687 };
 688
 689 static const struct panel_desc auo_b101aw03 = {
 690         .modes = &auo_b101aw03_mode,
 691         .num_modes = 1,
 692         .bpc = 6,
 693         .size = {
 694                 .width = 223,
 695                 .height = 125,
 696         },
 697 };
 698
 699 static const struct drm_display_mode auo_b101ean01_mode = {
 700         .clock = 72500,
 701         .hdisplay = 1280,
 702         .hsync_start = 1280 + 119,
 703         .hsync_end = 1280 + 119 + 32,
 704         .htotal = 1280 + 119 + 32 + 21,
 705         .vdisplay = 800,
 706         .vsync_start = 800 + 4,
 707         .vsync_end = 800 + 4 + 20,
 708         .vtotal = 800 + 4 + 20 + 8,
 709         .vrefresh = 60,
 710 };
 711
 712 static const struct panel_desc auo_b101ean01 = {
 713         .modes = &auo_b101ean01_mode,
 714         .num_modes = 1,
 715         .bpc = 6,
 716         .size = {
 717                 .width = 217,
 718                 .height = 136,
 719         },
 720 };
 721
 722 static const struct drm_display_mode auo_b101ew05_mode = {
 723         .clock = 78000,
 724         .hdisplay = 1280,
 725         .hsync_start = 1280 + 18,
 726         .hsync_end = 1280 + 18 + 100,
 727         .htotal = 1280 + 18 + 100 + 10,
 728         .vdisplay = 800,
 729         .vsync_start = 800 + 6,
 730         .vsync_end = 800 + 6 + 8,
 731         .vtotal = 800 + 6 + 8 + 2,
 732         .vrefresh = 60,
 733 };
 734
 735 static const struct panel_desc auo_b101ew05 = {
 736         .modes = &auo_b101ew05_mode,
 737         .num_modes = 1,
 738         .bpc = 6,
 739         .size = {
 740                 .width = 217,
 741                 .height = 136,
 742         },
 743 };
 744
 745 static const struct drm_display_mode auo_b101xtn01_mode = {
 746         .clock = 72000,
 747         .hdisplay = 1366,
 748         .hsync_start = 1366 + 20,
 749         .hsync_end = 1366 + 20 + 70,
 750         .htotal = 1366 + 20 + 70,
 751         .vdisplay = 768,
 752         .vsync_start = 768 + 14,
 753         .vsync_end = 768 + 14 + 42,
 754         .vtotal = 768 + 14 + 42,
 755         .vrefresh = 60,
 756         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 757 };
 758
 759 static const struct panel_desc auo_b101xtn01 = {
 760         .modes = &auo_b101xtn01_mode,
 761         .num_modes = 1,
 762         .bpc = 6,
 763         .size = {
 764                 .width = 223,
 765                 .height = 125,
 766         },
 767 };
 768
 769 static const struct drm_display_mode auo_b116xw03_mode = {
 770         .clock = 70589,
 771         .hdisplay = 1366,
 772         .hsync_start = 1366 + 40,
 773         .hsync_end = 1366 + 40 + 40,
 774         .htotal = 1366 + 40 + 40 + 32,
 775         .vdisplay = 768,
 776         .vsync_start = 768 + 10,
 777         .vsync_end = 768 + 10 + 12,
 778         .vtotal = 768 + 10 + 12 + 6,
 779         .vrefresh = 60,
 780 };
 781
 782 static const struct panel_desc auo_b116xw03 = {
 783         .modes = &auo_b116xw03_mode,
 784         .num_modes = 1,
 785         .bpc = 6,
 786         .size = {
 787                 .width = 256,
 788                 .height = 144,
 789         },
 790 };
 791
 792 static const struct drm_display_mode auo_b125han03_mode = {
 793         .clock = 146900,
 794         .hdisplay = 1920,
 795         .hsync_start = 1920 + 48,
 796         .hsync_end = 1920 + 48 + 32,
 797         .htotal = 1920 + 48 + 32 + 140,
 798         .vdisplay = 1080,
 799         .vsync_start = 1080 + 2,
 800         .vsync_end = 1080 + 2 + 5,
 801         .vtotal = 1080 + 2 + 5 + 57,
 802         .vrefresh = 60,
 803         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 804 };
 805
 806 static const struct panel_desc auo_b125han03 = {
 807         .modes = &auo_b125han03_mode,
 808         .num_modes = 1,
 809         .bpc = 6,
 810         .size = {
 811                 .width = 276,
 812                 .height = 156,
 813         },
 814         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 815 };
 816
 817 static const struct drm_display_mode auo_b133xtn01_mode = {
 818         .clock = 69500,
 819         .hdisplay = 1366,
 820         .hsync_start = 1366 + 48,
 821         .hsync_end = 1366 + 48 + 32,
 822         .htotal = 1366 + 48 + 32 + 20,
 823         .vdisplay = 768,
 824         .vsync_start = 768 + 3,
 825         .vsync_end = 768 + 3 + 6,
 826         .vtotal = 768 + 3 + 6 + 13,
 827         .vrefresh = 60,
 828 };
 829
 830 static const struct panel_desc auo_b133xtn01 = {
 831         .modes = &auo_b133xtn01_mode,
 832         .num_modes = 1,
 833         .bpc = 6,
 834         .size = {
 835                 .width = 293,
 836                 .height = 165,
 837         },
 838 };
 839
 840 static const struct drm_display_mode auo_b133htn01_mode = {
 841         .clock = 150660,
 842         .hdisplay = 1920,
 843         .hsync_start = 1920 + 172,
 844         .hsync_end = 1920 + 172 + 80,
 845         .htotal = 1920 + 172 + 80 + 60,
 846         .vdisplay = 1080,
 847         .vsync_start = 1080 + 25,
 848         .vsync_end = 1080 + 25 + 10,
 849         .vtotal = 1080 + 25 + 10 + 10,
 850         .vrefresh = 60,
 851 };
 852
 853 static const struct panel_desc auo_b133htn01 = {
 854         .modes = &auo_b133htn01_mode,
 855         .num_modes = 1,
 856         .bpc = 6,
 857         .size = {
 858                 .width = 293,
 859                 .height = 165,
 860         },
 861         .delay = {
 862                 .prepare = 105,
 863                 .enable = 20,
 864                 .unprepare = 50,
 865         },
 866 };
 867
 868 static const struct drm_display_mode avic_tm070ddh03_mode = {
 869         .clock = 51200,
 870         .hdisplay = 1024,
 871         .hsync_start = 1024 + 160,
 872         .hsync_end = 1024 + 160 + 4,
 873         .htotal = 1024 + 160 + 4 + 156,
 874         .vdisplay = 600,
 875         .vsync_start = 600 + 17,
 876         .vsync_end = 600 + 17 + 1,
 877         .vtotal = 600 + 17 + 1 + 17,
 878         .vrefresh = 60,
 879 };
 880
 881 static const struct panel_desc avic_tm070ddh03 = {
 882         .modes = &avic_tm070ddh03_mode,
 883         .num_modes = 1,
 884         .bpc = 8,
 885         .size = {
 886                 .width = 154,
 887                 .height = 90,
 888         },
 889         .delay = {
 890                 .prepare = 20,
 891                 .enable = 200,
 892                 .disable = 200,
 893         },
 894 };
 895
 896 static const struct drm_display_mode boe_nv125fhm_n73_mode = {
 897         .clock = 72300,
 898         .hdisplay = 1366,
 899         .hsync_start = 1366 + 80,
 900         .hsync_end = 1366 + 80 + 20,
 901         .htotal = 1366 + 80 + 20 + 60,
 902         .vdisplay = 768,
 903         .vsync_start = 768 + 12,
 904         .vsync_end = 768 + 12 + 2,
 905         .vtotal = 768 + 12 + 2 + 8,
 906         .vrefresh = 60,
 907         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 908 };
 909
 910 static const struct panel_desc boe_nv125fhm_n73 = {
 911         .modes = &boe_nv125fhm_n73_mode,
 912         .num_modes = 1,
 913         .bpc = 6,
 914         .size = {
 915                 .width = 276,
 916                 .height = 156,
 917         },
 918         .delay = {
 919                 .unprepare = 160,
 920         },
 921         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 922 };
 923
 924 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
 925         .clock = 67000,
 926         .hdisplay = 800,
 927         .hsync_start = 800 + 24,
 928         .hsync_end = 800 + 24 + 16,
 929         .htotal = 800 + 24 + 16 + 24,
 930         .vdisplay = 1280,
 931         .vsync_start = 1280 + 2,
 932         .vsync_end = 1280 + 2 + 2,
 933         .vtotal = 1280 + 2 + 2 + 4,
 934         .vrefresh = 60,
 935 };
 936
 937 static const struct panel_desc chunghwa_claa070wp03xg = {
 938         .modes = &chunghwa_claa070wp03xg_mode,
 939         .num_modes = 1,
 940         .bpc = 6,
 941         .size = {
 942                 .width = 94,
 943                 .height = 151,
 944         },
 945 };
 946
 947 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
 948         .clock = 72070,
 949         .hdisplay = 1366,
 950         .hsync_start = 1366 + 58,
 951         .hsync_end = 1366 + 58 + 58,
 952         .htotal = 1366 + 58 + 58 + 58,
 953         .vdisplay = 768,
 954         .vsync_start = 768 + 4,
 955         .vsync_end = 768 + 4 + 4,
 956         .vtotal = 768 + 4 + 4 + 4,
 957         .vrefresh = 60,
 958 };
 959
 960 static const struct panel_desc chunghwa_claa101wa01a = {
 961         .modes = &chunghwa_claa101wa01a_mode,
 962         .num_modes = 1,
 963         .bpc = 6,
 964         .size = {
 965                 .width = 220,
 966                 .height = 120,
 967         },
 968 };
 969
 970 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
 971         .clock = 69300,
 972         .hdisplay = 1366,
 973         .hsync_start = 1366 + 48,
 974         .hsync_end = 1366 + 48 + 32,
 975         .htotal = 1366 + 48 + 32 + 20,
 976         .vdisplay = 768,
 977         .vsync_start = 768 + 16,
 978         .vsync_end = 768 + 16 + 8,
 979         .vtotal = 768 + 16 + 8 + 16,
 980         .vrefresh = 60,
 981 };
 982
 983 static const struct panel_desc chunghwa_claa101wb01 = {
 984         .modes = &chunghwa_claa101wb01_mode,
 985         .num_modes = 1,
 986         .bpc = 6,
 987         .size = {
 988                 .width = 223,
 989                 .height = 125,
 990         },
 991 };
 992
 993 static const struct drm_display_mode edt_et057090dhu_mode = {
 994         .clock = 25175,
 995         .hdisplay = 640,
 996         .hsync_start = 640 + 16,
 997         .hsync_end = 640 + 16 + 30,
 998         .htotal = 640 + 16 + 30 + 114,
 999         .vdisplay = 480,
1000         .vsync_start = 480 + 10,
1001         .vsync_end = 480 + 10 + 3,
1002         .vtotal = 480 + 10 + 3 + 32,
1003         .vrefresh = 60,
1004         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1005 };
1006
1007 static const struct panel_desc edt_et057090dhu = {
1008         .modes = &edt_et057090dhu_mode,
1009         .num_modes = 1,
1010         .bpc = 6,
1011         .size = {
1012                 .width = 115,
1013                 .height = 86,
1014         },
1015 };
1016
1017 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1018         .clock = 33260,
1019         .hdisplay = 800,
1020         .hsync_start = 800 + 40,
1021         .hsync_end = 800 + 40 + 128,
1022         .htotal = 800 + 40 + 128 + 88,
1023         .vdisplay = 480,
1024         .vsync_start = 480 + 10,
1025         .vsync_end = 480 + 10 + 2,
1026         .vtotal = 480 + 10 + 2 + 33,
1027         .vrefresh = 60,
1028         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1029 };
1030
1031 static const struct panel_desc edt_etm0700g0dh6 = {
1032         .modes = &edt_etm0700g0dh6_mode,
1033         .num_modes = 1,
1034         .bpc = 6,
1035         .size = {
1036                 .width = 152,
1037                 .height = 91,
1038         },
1039 };
1040
1041 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1042         .clock = 32260,
1043         .hdisplay = 800,
1044         .hsync_start = 800 + 168,
1045         .hsync_end = 800 + 168 + 64,
1046         .htotal = 800 + 168 + 64 + 88,
1047         .vdisplay = 480,
1048         .vsync_start = 480 + 37,
1049         .vsync_end = 480 + 37 + 2,
1050         .vtotal = 480 + 37 + 2 + 8,
1051         .vrefresh = 60,
1052 };
1053
1054 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1055         .modes = &foxlink_fl500wvr00_a0t_mode,
1056         .num_modes = 1,
1057         .bpc = 8,
1058         .size = {
1059                 .width = 108,
1060                 .height = 65,
1061         },
1062         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1063 };
1064
1065 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1066         .clock = 9000,
1067         .hdisplay = 480,
1068         .hsync_start = 480 + 5,
1069         .hsync_end = 480 + 5 + 1,
1070         .htotal = 480 + 5 + 1 + 40,
1071         .vdisplay = 272,
1072         .vsync_start = 272 + 8,
1073         .vsync_end = 272 + 8 + 1,
1074         .vtotal = 272 + 8 + 1 + 8,
1075         .vrefresh = 60,
1076 };
1077
1078 static const struct panel_desc giantplus_gpg482739qs5 = {
1079         .modes = &giantplus_gpg482739qs5_mode,
1080         .num_modes = 1,
1081         .bpc = 8,
1082         .size = {
1083                 .width = 95,
1084                 .height = 54,
1085         },
1086         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1087 };
1088
1089 static const struct display_timing hannstar_hsd070pww1_timing = {
1090         .pixelclock = { 64300000, 71100000, 82000000 },
1091         .hactive = { 1280, 1280, 1280 },
1092         .hfront_porch = { 1, 1, 10 },
1093         .hback_porch = { 1, 1, 10 },
1094         /*
1095          * According to the data sheet, the minimum horizontal blanking interval
1096          * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1097          * minimum working horizontal blanking interval to be 60 clocks.
1098          */
1099         .hsync_len = { 58, 158, 661 },
1100         .vactive = { 800, 800, 800 },
1101         .vfront_porch = { 1, 1, 10 },
1102         .vback_porch = { 1, 1, 10 },
1103         .vsync_len = { 1, 21, 203 },
1104         .flags = DISPLAY_FLAGS_DE_HIGH,
1105 };
1106
1107 static const struct panel_desc hannstar_hsd070pww1 = {
1108         .timings = &hannstar_hsd070pww1_timing,
1109         .num_timings = 1,
1110         .bpc = 6,
1111         .size = {
1112                 .width = 151,
1113                 .height = 94,
1114         },
1115         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1116 };
1117
1118 static const struct display_timing hannstar_hsd100pxn1_timing = {
1119         .pixelclock = { 55000000, 65000000, 75000000 },
1120         .hactive = { 1024, 1024, 1024 },
1121         .hfront_porch = { 40, 40, 40 },
1122         .hback_porch = { 220, 220, 220 },
1123         .hsync_len = { 20, 60, 100 },
1124         .vactive = { 768, 768, 768 },
1125         .vfront_porch = { 7, 7, 7 },
1126         .vback_porch = { 21, 21, 21 },
1127         .vsync_len = { 10, 10, 10 },
1128         .flags = DISPLAY_FLAGS_DE_HIGH,
1129 };
1130
1131 static const struct panel_desc hannstar_hsd100pxn1 = {
1132         .timings = &hannstar_hsd100pxn1_timing,
1133         .num_timings = 1,
1134         .bpc = 6,
1135         .size = {
1136                 .width = 203,
1137                 .height = 152,
1138         },
1139         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1140 };
1141
1142 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1143         .clock = 33333,
1144         .hdisplay = 800,
1145         .hsync_start = 800 + 85,
1146         .hsync_end = 800 + 85 + 86,
1147         .htotal = 800 + 85 + 86 + 85,
1148         .vdisplay = 480,
1149         .vsync_start = 480 + 16,
1150         .vsync_end = 480 + 16 + 13,
1151         .vtotal = 480 + 16 + 13 + 16,
1152         .vrefresh = 60,
1153 };
1154
1155 static const struct panel_desc hitachi_tx23d38vm0caa = {
1156         .modes = &hitachi_tx23d38vm0caa_mode,
1157         .num_modes = 1,
1158         .bpc = 6,
1159         .size = {
1160                 .width = 195,
1161                 .height = 117,
1162         },
1163 };
1164
1165 static const struct drm_display_mode innolux_at043tn24_mode = {
1166         .clock = 9000,
1167         .hdisplay = 480,
1168         .hsync_start = 480 + 2,
1169         .hsync_end = 480 + 2 + 41,
1170         .htotal = 480 + 2 + 41 + 2,
1171         .vdisplay = 272,
1172         .vsync_start = 272 + 2,
1173         .vsync_end = 272 + 2 + 11,
1174         .vtotal = 272 + 2 + 11 + 2,
1175         .vrefresh = 60,
1176         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1177 };
1178
1179 static const struct panel_desc innolux_at043tn24 = {
1180         .modes = &innolux_at043tn24_mode,
1181         .num_modes = 1,
1182         .bpc = 8,
1183         .size = {
1184                 .width = 95,
1185                 .height = 54,
1186         },
1187         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1188 };
1189
1190 static const struct drm_display_mode innolux_g121i1_l01_mode = {
1191         .clock = 71000,
1192         .hdisplay = 1280,
1193         .hsync_start = 1280 + 64,
1194         .hsync_end = 1280 + 64 + 32,
1195         .htotal = 1280 + 64 + 32 + 64,
1196         .vdisplay = 800,
1197         .vsync_start = 800 + 9,
1198         .vsync_end = 800 + 9 + 6,
1199         .vtotal = 800 + 9 + 6 + 9,
1200         .vrefresh = 60,
1201 };
1202
1203 static const struct panel_desc innolux_g121i1_l01 = {
1204         .modes = &innolux_g121i1_l01_mode,
1205         .num_modes = 1,
1206         .bpc = 6,
1207         .size = {
1208                 .width = 261,
1209                 .height = 163,
1210         },
1211 };
1212
1213 static const struct drm_display_mode innolux_n116bge_mode = {
1214         .clock = 76420,
1215         .hdisplay = 1366,
1216         .hsync_start = 1366 + 136,
1217         .hsync_end = 1366 + 136 + 30,
1218         .htotal = 1366 + 136 + 30 + 60,
1219         .vdisplay = 768,
1220         .vsync_start = 768 + 8,
1221         .vsync_end = 768 + 8 + 12,
1222         .vtotal = 768 + 8 + 12 + 12,
1223         .vrefresh = 60,
1224         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1225 };
1226
1227 static const struct panel_desc innolux_n116bge = {
1228         .modes = &innolux_n116bge_mode,
1229         .num_modes = 1,
1230         .bpc = 6,
1231         .size = {
1232                 .width = 256,
1233                 .height = 144,
1234         },
1235 };
1236
1237 static const struct drm_display_mode innolux_n125hce_mode = {
1238         .clock = 138780,
1239         .hdisplay = 1920,
1240         .hsync_start = 1920 + 80,
1241         .hsync_end = 1920 + 80 + 30,
1242         .htotal = 1920 + 80 + 30 + 50,
1243         .vdisplay = 1080,
1244         .vsync_start = 1080 + 12,
1245         .vsync_end = 1080 + 12 + 4,
1246         .vtotal = 1080 + 12 + 4 + 16,
1247         .vrefresh = 60,
1248         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1249 };
1250
1251 static const struct panel_desc innolux_n125hce = {
1252         .modes = &innolux_n125hce_mode,
1253         .num_modes = 1,
1254         .bpc = 6,
1255         .size = {
1256                 .width = 283,
1257                 .height = 168,
1258         },
1259         .delay = {
1260                 .unprepare = 600,
1261                 .enable = 100,
1262         },
1263         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1264 };
1265
1266 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1267         .clock = 69300,
1268         .hdisplay = 1366,
1269         .hsync_start = 1366 + 16,
1270         .hsync_end = 1366 + 16 + 34,
1271         .htotal = 1366 + 16 + 34 + 50,
1272         .vdisplay = 768,
1273         .vsync_start = 768 + 2,
1274         .vsync_end = 768 + 2 + 6,
1275         .vtotal = 768 + 2 + 6 + 12,
1276         .vrefresh = 60,
1277 };
1278
1279 static const struct panel_desc innolux_n156bge_l21 = {
1280         .modes = &innolux_n156bge_l21_mode,
1281         .num_modes = 1,
1282         .bpc = 6,
1283         .size = {
1284                 .width = 344,
1285                 .height = 193,
1286         },
1287 };
1288
1289 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1290         .clock = 51501,
1291         .hdisplay = 1024,
1292         .hsync_start = 1024 + 128,
1293         .hsync_end = 1024 + 128 + 64,
1294         .htotal = 1024 + 128 + 64 + 128,
1295         .vdisplay = 600,
1296         .vsync_start = 600 + 16,
1297         .vsync_end = 600 + 16 + 4,
1298         .vtotal = 600 + 16 + 4 + 16,
1299         .vrefresh = 60,
1300 };
1301
1302 static const struct panel_desc innolux_zj070na_01p = {
1303         .modes = &innolux_zj070na_01p_mode,
1304         .num_modes = 1,
1305         .bpc = 6,
1306         .size = {
1307                 .width = 1024,
1308                 .height = 600,
1309         },
1310 };
1311
1312 static const struct drm_display_mode lg_lb070wv8_mode = {
1313         .clock = 33246,
1314         .hdisplay = 800,
1315         .hsync_start = 800 + 88,
1316         .hsync_end = 800 + 88 + 80,
1317         .htotal = 800 + 88 + 80 + 88,
1318         .vdisplay = 480,
1319         .vsync_start = 480 + 10,
1320         .vsync_end = 480 + 10 + 25,
1321         .vtotal = 480 + 10 + 25 + 10,
1322         .vrefresh = 60,
1323 };
1324
1325 static const struct panel_desc lg_lb070wv8 = {
1326         .modes = &lg_lb070wv8_mode,
1327         .num_modes = 1,
1328         .bpc = 16,
1329         .size = {
1330                 .width = 151,
1331                 .height = 91,
1332         },
1333         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1334 };
1335
1336 static const struct drm_display_mode sharp_lcd_f402_mode = {
1337         .clock = 205000,
1338         .hdisplay = 1536,
1339         .hsync_start = 1536 + 12,
1340         .hsync_end = 1536 + 12 + 48,
1341         .htotal = 1536 + 12 + 48 + 16,
1342         .vdisplay = 2048,
1343         .vsync_start = 2048 + 8,
1344         .vsync_end = 2048 + 8 + 8,
1345         .vtotal = 2048 + 8 + 8 + 4,
1346         .vrefresh = 60,
1347         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1348 };
1349
1350 static const struct panel_desc sharp_lcd_f402 = {
1351         .modes = &sharp_lcd_f402_mode,
1352         .num_modes = 1,
1353         .bpc = 8,
1354         .size = {
1355                 .width = 95,
1356                 .height = 54,
1357         },
1358         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1359 };
1360
1361 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1362         .clock = 200000,
1363         .hdisplay = 1536,
1364         .hsync_start = 1536 + 12,
1365         .hsync_end = 1536 + 12 + 16,
1366         .htotal = 1536 + 12 + 16 + 48,
1367         .vdisplay = 2048,
1368         .vsync_start = 2048 + 8,
1369         .vsync_end = 2048 + 8 + 4,
1370         .vtotal = 2048 + 8 + 4 + 8,
1371         .vrefresh = 60,
1372         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1373 };
1374
1375 static const struct panel_desc lg_lp079qx1_sp0v = {
1376         .modes = &lg_lp079qx1_sp0v_mode,
1377         .num_modes = 1,
1378         .size = {
1379                 .width = 129,
1380                 .height = 171,
1381         },
1382         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1383 };
1384
1385 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1386         .clock = 205210,
1387         .hdisplay = 2048,
1388         .hsync_start = 2048 + 150,
1389         .hsync_end = 2048 + 150 + 5,
1390         .htotal = 2048 + 150 + 5 + 5,
1391         .vdisplay = 1536,
1392         .vsync_start = 1536 + 3,
1393         .vsync_end = 1536 + 3 + 1,
1394         .vtotal = 1536 + 3 + 1 + 9,
1395         .vrefresh = 60,
1396 };
1397
1398 static const struct panel_desc lg_lp097qx1_spa1 = {
1399         .modes = &lg_lp097qx1_spa1_mode,
1400         .num_modes = 1,
1401         .size = {
1402                 .width = 320,
1403                 .height = 187,
1404         },
1405 };
1406
1407 static const struct drm_display_mode lg_lp129qe_mode = {
1408         .clock = 285250,
1409         .hdisplay = 2560,
1410         .hsync_start = 2560 + 48,
1411         .hsync_end = 2560 + 48 + 32,
1412         .htotal = 2560 + 48 + 32 + 80,
1413         .vdisplay = 1700,
1414         .vsync_start = 1700 + 3,
1415         .vsync_end = 1700 + 3 + 10,
1416         .vtotal = 1700 + 3 + 10 + 36,
1417         .vrefresh = 60,
1418 };
1419
1420 static const struct panel_desc lg_lp129qe = {
1421         .modes = &lg_lp129qe_mode,
1422         .num_modes = 1,
1423         .bpc = 8,
1424         .size = {
1425                 .width = 272,
1426                 .height = 181,
1427         },
1428 };
1429
1430 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1431         .clock = 10870,
1432         .hdisplay = 480,
1433         .hsync_start = 480 + 2,
1434         .hsync_end = 480 + 2 + 41,
1435         .htotal = 480 + 2 + 41 + 2,
1436         .vdisplay = 272,
1437         .vsync_start = 272 + 2,
1438         .vsync_end = 272 + 2 + 4,
1439         .vtotal = 272 + 2 + 4 + 2,
1440         .vrefresh = 74,
1441 };
1442
1443 static const struct panel_desc nec_nl4827hc19_05b = {
1444         .modes = &nec_nl4827hc19_05b_mode,
1445         .num_modes = 1,
1446         .bpc = 8,
1447         .size = {
1448                 .width = 95,
1449                 .height = 54,
1450         },
1451         .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1452 };
1453
1454 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1455         .pixelclock = { 30000000, 30000000, 40000000 },
1456         .hactive = { 800, 800, 800 },
1457         .hfront_porch = { 40, 40, 40 },
1458         .hback_porch = { 40, 40, 40 },
1459         .hsync_len = { 1, 48, 48 },
1460         .vactive = { 480, 480, 480 },
1461         .vfront_porch = { 13, 13, 13 },
1462         .vback_porch = { 29, 29, 29 },
1463         .vsync_len = { 3, 3, 3 },
1464         .flags = DISPLAY_FLAGS_DE_HIGH,
1465 };
1466
1467 static const struct panel_desc okaya_rs800480t_7x0gp = {
1468         .timings = &okaya_rs800480t_7x0gp_timing,
1469         .num_timings = 1,
1470         .bpc = 6,
1471         .size = {
1472                 .width = 154,
1473                 .height = 87,
1474         },
1475         .delay = {
1476                 .prepare = 41,
1477                 .enable = 50,
1478                 .unprepare = 41,
1479                 .disable = 50,
1480         },
1481         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1482 };
1483
1484 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
1485         .clock = 25000,
1486         .hdisplay = 480,
1487         .hsync_start = 480 + 10,
1488         .hsync_end = 480 + 10 + 10,
1489         .htotal = 480 + 10 + 10 + 15,
1490         .vdisplay = 800,
1491         .vsync_start = 800 + 3,
1492         .vsync_end = 800 + 3 + 3,
1493         .vtotal = 800 + 3 + 3 + 3,
1494         .vrefresh = 60,
1495 };
1496
1497 static const struct panel_desc ortustech_com43h4m85ulc = {
1498         .modes = &ortustech_com43h4m85ulc_mode,
1499         .num_modes = 1,
1500         .bpc = 8,
1501         .size = {
1502                 .width = 56,
1503                 .height = 93,
1504         },
1505         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1506 };
1507
1508 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1509         .clock = 271560,
1510         .hdisplay = 2560,
1511         .hsync_start = 2560 + 48,
1512         .hsync_end = 2560 + 48 + 32,
1513         .htotal = 2560 + 48 + 32 + 80,
1514         .vdisplay = 1600,
1515         .vsync_start = 1600 + 2,
1516         .vsync_end = 1600 + 2 + 5,
1517         .vtotal = 1600 + 2 + 5 + 57,
1518         .vrefresh = 60,
1519 };
1520
1521 static const struct panel_desc samsung_lsn122dl01_c01 = {
1522         .modes = &samsung_lsn122dl01_c01_mode,
1523         .num_modes = 1,
1524         .size = {
1525                 .width = 2560,
1526                 .height = 1600,
1527         },
1528 };
1529
1530 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1531         .clock = 54030,
1532         .hdisplay = 1024,
1533         .hsync_start = 1024 + 24,
1534         .hsync_end = 1024 + 24 + 136,
1535         .htotal = 1024 + 24 + 136 + 160,
1536         .vdisplay = 600,
1537         .vsync_start = 600 + 3,
1538         .vsync_end = 600 + 3 + 6,
1539         .vtotal = 600 + 3 + 6 + 61,
1540         .vrefresh = 60,
1541 };
1542
1543 static const struct panel_desc samsung_ltn101nt05 = {
1544         .modes = &samsung_ltn101nt05_mode,
1545         .num_modes = 1,
1546         .bpc = 6,
1547         .size = {
1548                 .width = 1024,
1549                 .height = 600,
1550         },
1551 };
1552
1553 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1554         .clock = 76300,
1555         .hdisplay = 1366,
1556         .hsync_start = 1366 + 64,
1557         .hsync_end = 1366 + 64 + 48,
1558         .htotal = 1366 + 64 + 48 + 128,
1559         .vdisplay = 768,
1560         .vsync_start = 768 + 2,
1561         .vsync_end = 768 + 2 + 5,
1562         .vtotal = 768 + 2 + 5 + 17,
1563         .vrefresh = 60,
1564 };
1565
1566 static const struct panel_desc samsung_ltn140at29_301 = {
1567         .modes = &samsung_ltn140at29_301_mode,
1568         .num_modes = 1,
1569         .bpc = 6,
1570         .size = {
1571                 .width = 320,
1572                 .height = 187,
1573         },
1574 };
1575
1576 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1577         .clock = 33300,
1578         .hdisplay = 800,
1579         .hsync_start = 800 + 1,
1580         .hsync_end = 800 + 1 + 64,
1581         .htotal = 800 + 1 + 64 + 64,
1582         .vdisplay = 480,
1583         .vsync_start = 480 + 1,
1584         .vsync_end = 480 + 1 + 23,
1585         .vtotal = 480 + 1 + 23 + 22,
1586         .vrefresh = 60,
1587 };
1588
1589 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1590         .modes = &shelly_sca07010_bfn_lnn_mode,
1591         .num_modes = 1,
1592         .size = {
1593                 .width = 152,
1594                 .height = 91,
1595         },
1596         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1597 };
1598
1599 static const struct of_device_id platform_of_match[] = {
1600         {
1601                 .compatible = "simple-panel",
1602                 .data = NULL,
1603         }, {
1604                 .compatible = "ampire,am800480r3tmqwa1h",
1605                 .data = &ampire_am800480r3tmqwa1h,
1606         }, {
1607                 .compatible = "auo,b101aw03",
1608                 .data = &auo_b101aw03,
1609         }, {
1610                 .compatible = "auo,b101ean01",
1611                 .data = &auo_b101ean01,
1612         }, {
1613                 .compatible = "auo,b101ew05",
1614                 .data = &auo_b101ew05,
1615         }, {
1616                 .compatible = "auo,b101xtn01",
1617                 .data = &auo_b101xtn01,
1618         }, {
1619                 .compatible = "auo,b116xw03",
1620                 .data = &auo_b116xw03,
1621         }, {
1622                 .compatible = "auo,b125han03",
1623                 .data = &auo_b125han03,
1624         }, {
1625                 .compatible = "auo,b133htn01",
1626                 .data = &auo_b133htn01,
1627         }, {
1628                 .compatible = "auo,b133xtn01",
1629                 .data = &auo_b133xtn01,
1630         }, {
1631                 .compatible = "avic,tm070ddh03",
1632                 .data = &avic_tm070ddh03,
1633         }, {
1634                 .compatible = "boe,nv125fhm-n73",
1635                 .data = &boe_nv125fhm_n73,
1636         }, {
1637                 .compatible = "chunghwa,claa070wp03xg",
1638                 .data = &chunghwa_claa070wp03xg,
1639         }, {
1640                 .compatible = "chunghwa,claa101wa01a",
1641                 .data = &chunghwa_claa101wa01a
1642         }, {
1643                 .compatible = "chunghwa,claa101wb01",
1644                 .data = &chunghwa_claa101wb01
1645         }, {
1646                 .compatible = "edt,et057090dhu",
1647                 .data = &edt_et057090dhu,
1648         }, {
1649                 .compatible = "edt,et070080dh6",
1650                 .data = &edt_etm0700g0dh6,
1651         }, {
1652                 .compatible = "edt,etm0700g0dh6",
1653                 .data = &edt_etm0700g0dh6,
1654         }, {
1655                 .compatible = "foxlink,fl500wvr00-a0t",
1656                 .data = &foxlink_fl500wvr00_a0t,
1657         }, {
1658                 .compatible = "giantplus,gpg482739qs5",
1659                 .data = &giantplus_gpg482739qs5
1660         }, {
1661                 .compatible = "hannstar,hsd070pww1",
1662                 .data = &hannstar_hsd070pww1,
1663         }, {
1664                 .compatible = "hannstar,hsd100pxn1",
1665                 .data = &hannstar_hsd100pxn1,
1666         }, {
1667                 .compatible = "hit,tx23d38vm0caa",
1668                 .data = &hitachi_tx23d38vm0caa
1669         }, {
1670                 .compatible = "innolux,at043tn24",
1671                 .data = &innolux_at043tn24,
1672         }, {
1673                 .compatible ="innolux,g121i1-l01",
1674                 .data = &innolux_g121i1_l01
1675         }, {
1676                 .compatible = "innolux,n116bge",
1677                 .data = &innolux_n116bge,
1678         }, {
1679                 .compatible = "innolux,n125hce",
1680                 .data = &innolux_n125hce,
1681         }, {
1682                 .compatible = "innolux,n156bge-l21",
1683                 .data = &innolux_n156bge_l21,
1684         }, {
1685                 .compatible = "innolux,zj070na-01p",
1686                 .data = &innolux_zj070na_01p,
1687         }, {
1688                 .compatible = "lg,lb070wv8",
1689                 .data = &lg_lb070wv8,
1690         }, {
1691                 .compatible = "lg,lp079qx1-sp0v",
1692                 .data = &lg_lp079qx1_sp0v,
1693         }, {
1694                 .compatible = "sharp,lcd-f402",
1695                 .data = &sharp_lcd_f402,
1696         }, {
1697                 .compatible = "lg,lp097qx1-spa1",
1698                 .data = &lg_lp097qx1_spa1,
1699         }, {
1700                 .compatible = "lg,lp129qe",
1701                 .data = &lg_lp129qe,
1702         }, {
1703                 .compatible = "nec,nl4827hc19-05b",
1704                 .data = &nec_nl4827hc19_05b,
1705         }, {
1706                 .compatible = "okaya,rs800480t-7x0gp",
1707                 .data = &okaya_rs800480t_7x0gp,
1708         }, {
1709                 .compatible = "ortustech,com43h4m85ulc",
1710                 .data = &ortustech_com43h4m85ulc,
1711         }, {
1712                 .compatible = "samsung,lsn122dl01-c01",
1713                 .data = &samsung_lsn122dl01_c01,
1714         }, {
1715                 .compatible = "samsung,ltn101nt05",
1716                 .data = &samsung_ltn101nt05,
1717         }, {
1718                 .compatible = "samsung,ltn140at29-301",
1719                 .data = &samsung_ltn140at29_301,
1720         }, {
1721                 .compatible = "sharp,lcd-f402",
1722                 .data = &sharp_lcd_f402,
1723         }, {
1724                 .compatible = "shelly,sca07010-bfn-lnn",
1725                 .data = &shelly_sca07010_bfn_lnn,
1726         }, {
1727                 /* sentinel */
1728         }
1729 };
1730 MODULE_DEVICE_TABLE(of, platform_of_match);
1731
1732 static int panel_simple_platform_probe(struct platform_device *pdev)
1733 {
1734         const struct of_device_id *id;
1735
1736         id = of_match_node(platform_of_match, pdev->dev.of_node);
1737         if (!id)
1738                 return -ENODEV;
1739
1740         return panel_simple_probe(&pdev->dev, id->data);
1741 }
1742
1743 static int panel_simple_platform_remove(struct platform_device *pdev)
1744 {
1745         return panel_simple_remove(&pdev->dev);
1746 }
1747
1748 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1749 {
1750         panel_simple_shutdown(&pdev->dev);
1751 }
1752
1753 static struct platform_driver panel_simple_platform_driver = {
1754         .driver = {
1755                 .name = "panel-simple",
1756                 .of_match_table = platform_of_match,
1757         },
1758         .probe = panel_simple_platform_probe,
1759         .remove = panel_simple_platform_remove,
1760         .shutdown = panel_simple_platform_shutdown,
1761 };
1762
1763 struct panel_desc_dsi {
1764         struct panel_desc desc;
1765
1766         unsigned long flags;
1767         enum mipi_dsi_pixel_format format;
1768         unsigned int lanes;
1769 };
1770
1771 static const struct drm_display_mode auo_b080uan01_mode = {
1772         .clock = 154500,
1773         .hdisplay = 1200,
1774         .hsync_start = 1200 + 62,
1775         .hsync_end = 1200 + 62 + 4,
1776         .htotal = 1200 + 62 + 4 + 62,
1777         .vdisplay = 1920,
1778         .vsync_start = 1920 + 9,
1779         .vsync_end = 1920 + 9 + 2,
1780         .vtotal = 1920 + 9 + 2 + 8,
1781         .vrefresh = 60,
1782 };
1783
1784 static const struct panel_desc_dsi auo_b080uan01 = {
1785         .desc = {
1786                 .modes = &auo_b080uan01_mode,
1787                 .num_modes = 1,
1788                 .bpc = 8,
1789                 .size = {
1790                         .width = 108,
1791                         .height = 272,
1792                 },
1793         },
1794         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1795         .format = MIPI_DSI_FMT_RGB888,
1796         .lanes = 4,
1797 };
1798
1799 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1800         .clock = 160000,
1801         .hdisplay = 1200,
1802         .hsync_start = 1200 + 120,
1803         .hsync_end = 1200 + 120 + 20,
1804         .htotal = 1200 + 120 + 20 + 21,
1805         .vdisplay = 1920,
1806         .vsync_start = 1920 + 21,
1807         .vsync_end = 1920 + 21 + 3,
1808         .vtotal = 1920 + 21 + 3 + 18,
1809         .vrefresh = 60,
1810         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1811 };
1812
1813 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1814         .desc = {
1815                 .modes = &boe_tv080wum_nl0_mode,
1816                 .num_modes = 1,
1817                 .size = {
1818                         .width = 107,
1819                         .height = 172,
1820                 },
1821         },
1822         .flags = MIPI_DSI_MODE_VIDEO |
1823                  MIPI_DSI_MODE_VIDEO_BURST |
1824                  MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1825         .format = MIPI_DSI_FMT_RGB888,
1826         .lanes = 4,
1827 };
1828
1829 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1830         .clock = 71000,
1831         .hdisplay = 800,
1832         .hsync_start = 800 + 32,
1833         .hsync_end = 800 + 32 + 1,
1834         .htotal = 800 + 32 + 1 + 57,
1835         .vdisplay = 1280,
1836         .vsync_start = 1280 + 28,
1837         .vsync_end = 1280 + 28 + 1,
1838         .vtotal = 1280 + 28 + 1 + 14,
1839         .vrefresh = 60,
1840 };
1841
1842 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1843         .desc = {
1844                 .modes = &lg_ld070wx3_sl01_mode,
1845                 .num_modes = 1,
1846                 .bpc = 8,
1847                 .size = {
1848                         .width = 94,
1849                         .height = 151,
1850                 },
1851         },
1852         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1853         .format = MIPI_DSI_FMT_RGB888,
1854         .lanes = 4,
1855 };
1856
1857 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1858         .clock = 67000,
1859         .hdisplay = 720,
1860         .hsync_start = 720 + 12,
1861         .hsync_end = 720 + 12 + 4,
1862         .htotal = 720 + 12 + 4 + 112,
1863         .vdisplay = 1280,
1864         .vsync_start = 1280 + 8,
1865         .vsync_end = 1280 + 8 + 4,
1866         .vtotal = 1280 + 8 + 4 + 12,
1867         .vrefresh = 60,
1868 };
1869
1870 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1871         .desc = {
1872                 .modes = &lg_lh500wx1_sd03_mode,
1873                 .num_modes = 1,
1874                 .bpc = 8,
1875                 .size = {
1876                         .width = 62,
1877                         .height = 110,
1878                 },
1879         },
1880         .flags = MIPI_DSI_MODE_VIDEO,
1881         .format = MIPI_DSI_FMT_RGB888,
1882         .lanes = 4,
1883 };
1884
1885 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1886         .clock = 157200,
1887         .hdisplay = 1920,
1888         .hsync_start = 1920 + 154,
1889         .hsync_end = 1920 + 154 + 16,
1890         .htotal = 1920 + 154 + 16 + 32,
1891         .vdisplay = 1200,
1892         .vsync_start = 1200 + 17,
1893         .vsync_end = 1200 + 17 + 2,
1894         .vtotal = 1200 + 17 + 2 + 16,
1895         .vrefresh = 60,
1896 };
1897
1898 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1899         .desc = {
1900                 .modes = &panasonic_vvx10f004b00_mode,
1901                 .num_modes = 1,
1902                 .bpc = 8,
1903                 .size = {
1904                         .width = 217,
1905                         .height = 136,
1906                 },
1907         },
1908         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1909                  MIPI_DSI_CLOCK_NON_CONTINUOUS,
1910         .format = MIPI_DSI_FMT_RGB888,
1911         .lanes = 4,
1912 };
1913
1914
1915 static const struct of_device_id dsi_of_match[] = {
1916         {
1917                 .compatible = "simple-panel-dsi",
1918                 .data = NULL
1919         }, {
1920                 .compatible = "auo,b080uan01",
1921                 .data = &auo_b080uan01
1922         }, {
1923                 .compatible = "boe,tv080wum-nl0",
1924                 .data = &boe_tv080wum_nl0
1925         }, {
1926                 .compatible = "lg,ld070wx3-sl01",
1927                 .data = &lg_ld070wx3_sl01
1928         }, {
1929                 .compatible = "lg,lh500wx1-sd03",
1930                 .data = &lg_lh500wx1_sd03
1931         }, {
1932                 .compatible = "panasonic,vvx10f004b00",
1933                 .data = &panasonic_vvx10f004b00
1934         }, {
1935                 /* sentinel */
1936         }
1937 };
1938 MODULE_DEVICE_TABLE(of, dsi_of_match);
1939
1940 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1941 {
1942         struct panel_simple *panel;
1943         const struct panel_desc_dsi *desc;
1944         const struct of_device_id *id;
1945         const struct panel_desc *pdesc;
1946         const void *data;
1947         int len;
1948         u32 val;
1949         int err;
1950
1951         id = of_match_node(dsi_of_match, dsi->dev.of_node);
1952         if (!id)
1953                 return -ENODEV;
1954
1955         desc = id->data;
1956
1957         if (desc) {
1958                 dsi->mode_flags = desc->flags;
1959                 dsi->format = desc->format;
1960                 dsi->lanes = desc->lanes;
1961                 pdesc = &desc->desc;
1962         } else {
1963                 pdesc = NULL;
1964         }
1965
1966         err = panel_simple_probe(&dsi->dev, pdesc);
1967         if (err < 0)
1968                 return err;
1969
1970         panel = dev_get_drvdata(&dsi->dev);
1971         panel->dsi = dsi;
1972
1973         if (!of_property_read_u32(dsi->dev.of_node, "dsi,flags", &val))
1974                 dsi->mode_flags = val;
1975
1976         if (!of_property_read_u32(dsi->dev.of_node, "dsi,format", &val))
1977                 dsi->format = val;
1978
1979         if (!of_property_read_u32(dsi->dev.of_node, "dsi,lanes", &val))
1980                 dsi->lanes = val;
1981
1982         data = of_get_property(dsi->dev.of_node, "panel-init-sequence", &len);
1983         if (data) {
1984                 panel->on_cmds = devm_kzalloc(&dsi->dev,
1985                                               sizeof(*panel->on_cmds),
1986                                               GFP_KERNEL);
1987                 if (!panel->on_cmds)
1988                         return -ENOMEM;
1989
1990                 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
1991                                                       panel->on_cmds);
1992                 if (err) {
1993                         dev_err(&dsi->dev, "failed to parse panel init sequence\n");
1994                         return err;
1995                 }
1996         }
1997
1998         data = of_get_property(dsi->dev.of_node, "panel-exit-sequence", &len);
1999         if (data) {
2000                 panel->off_cmds = devm_kzalloc(&dsi->dev,
2001                                                sizeof(*panel->off_cmds),
2002                                                GFP_KERNEL);
2003                 if (!panel->off_cmds)
2004                         return -ENOMEM;
2005
2006                 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
2007                                                       panel->off_cmds);
2008                 if (err) {
2009                         dev_err(&dsi->dev, "failed to parse panel exit sequence\n");
2010                         return err;
2011                 }
2012         }
2013
2014         return mipi_dsi_attach(dsi);
2015 }
2016
2017 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2018 {
2019         int err;
2020
2021         err = mipi_dsi_detach(dsi);
2022         if (err < 0)
2023                 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2024
2025         return panel_simple_remove(&dsi->dev);
2026 }
2027
2028 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2029 {
2030         panel_simple_shutdown(&dsi->dev);
2031 }
2032
2033 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2034         .driver = {
2035                 .name = "panel-simple-dsi",
2036                 .of_match_table = dsi_of_match,
2037         },
2038         .probe = panel_simple_dsi_probe,
2039         .remove = panel_simple_dsi_remove,
2040         .shutdown = panel_simple_dsi_shutdown,
2041 };
2042
2043 static int __init panel_simple_init(void)
2044 {
2045         int err;
2046
2047         err = platform_driver_register(&panel_simple_platform_driver);
2048         if (err < 0)
2049                 return err;
2050
2051         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2052                 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2053                 if (err < 0)
2054                         return err;
2055         }
2056
2057         return 0;
2058 }
2059 module_init(panel_simple_init);
2060
2061 static void __exit panel_simple_exit(void)
2062 {
2063         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2064                 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2065
2066         platform_driver_unregister(&panel_simple_platform_driver);
2067 }
2068 module_exit(panel_simple_exit);
2069
2070 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2071 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2072 MODULE_LICENSE("GPL and additional rights");