drivers/gpu/drm/panel/panel-simple.c

   1 /*
   2  * Copyright (C) 2013, NVIDIA Corporation.  All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sub license,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the
  12  * next paragraph) shall be included in all copies or substantial portions
  13  * of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/backlight.h>
  25 #include <linux/gpio/consumer.h>
  26 #include <linux/module.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_mipi_dsi.h>
  34 #include <drm/drm_panel.h>
  35
  36 #include <video/display_timing.h>
  37 #include <video/mipi_display.h>
  38 #include <video/of_display_timing.h>
  39 #include <video/videomode.h>
  40
  41 struct dsi_ctrl_hdr {
  42         u8 dtype;       /* data type */
  43         u8 wait;        /* ms */
  44         u8 dlen;        /* payload len */
  45 } __packed;
  46
  47 struct dsi_cmd_desc {
  48         struct dsi_ctrl_hdr dchdr;
  49         u8 *payload;
  50 };
  51
  52 struct dsi_panel_cmds {
  53         u8 *buf;
  54         int blen;
  55         struct dsi_cmd_desc *cmds;
  56         int cmd_cnt;
  57 };
  58
  59 struct panel_desc {
  60         const struct drm_display_mode *modes;
  61         unsigned int num_modes;
  62         const struct display_timing *timings;
  63         unsigned int num_timings;
  64
  65         unsigned int bpc;
  66
  67         struct {
  68                 unsigned int width;
  69                 unsigned int height;
  70         } size;
  71
  72         /**
  73          * @reset: the time (in milliseconds) indicates the delay time
  74          *         after the panel to operate reset gpio
  75          * @init: the time (in milliseconds) that it takes for the panel to
  76          *           power on and dsi host can send command to panel
  77          * @prepare: the time (in milliseconds) that it takes for the panel to
  78          *           become ready and start receiving video data
  79          * @enable: the time (in milliseconds) that it takes for the panel to
  80          *          display the first valid frame after starting to receive
  81          *          video data
  82          * @disable: the time (in milliseconds) that it takes for the panel to
  83          *           turn the display off (no content is visible)
  84          * @unprepare: the time (in milliseconds) that it takes for the panel
  85          *             to power itself down completely
  86          */
  87         struct {
  88                 unsigned int reset;
  89                 unsigned int init;
  90                 unsigned int prepare;
  91                 unsigned int enable;
  92                 unsigned int disable;
  93                 unsigned int unprepare;
  94         } delay;
  95
  96         u32 bus_format;
  97 };
  98
  99 struct panel_simple {
 100         struct drm_panel base;
 101         struct mipi_dsi_device *dsi;
 102         bool prepared;
 103         bool enabled;
 104
 105         struct device *dev;
 106         const struct panel_desc *desc;
 107
 108         struct backlight_device *backlight;
 109         struct regulator *supply;
 110         struct i2c_adapter *ddc;
 111
 112         struct gpio_desc *enable_gpio;
 113         struct gpio_desc *reset_gpio;
 114
 115         struct dsi_panel_cmds *on_cmds;
 116         struct dsi_panel_cmds *off_cmds;
 117 };
 118
 119 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
 120 {
 121         return container_of(panel, struct panel_simple, base);
 122 }
 123
 124 static void panel_simple_dsi_cmds_cleanup(struct panel_simple *p)
 125 {
 126         if (p->on_cmds) {
 127                 kfree(p->on_cmds->buf);
 128                 kfree(p->on_cmds->cmds);
 129         }
 130
 131         if (p->off_cmds) {
 132                 kfree(p->off_cmds->buf);
 133                 kfree(p->off_cmds->cmds);
 134         }
 135 }
 136
 137 static int panel_simple_dsi_parse_dcs_cmds(struct device *dev,
 138                                            const u8 *data, int blen,
 139                                            struct dsi_panel_cmds *pcmds)
 140 {
 141         int len;
 142         char *buf, *bp;
 143         struct dsi_ctrl_hdr *dchdr;
 144         int i, cnt;
 145
 146         if (!pcmds)
 147                 return -EINVAL;
 148
 149         buf = kmemdup(data, blen, GFP_KERNEL);
 150         if (!buf)
 151                 return -ENOMEM;
 152
 153         /* scan dcs commands */
 154         bp = buf;
 155         len = blen;
 156         cnt = 0;
 157         while (len > sizeof(*dchdr)) {
 158                 dchdr = (struct dsi_ctrl_hdr *)bp;
 159
 160                 if (dchdr->dlen > len) {
 161                         dev_err(dev, "%s: error, len=%d", __func__,
 162                                 dchdr->dlen);
 163                         return -EINVAL;
 164                 }
 165
 166                 bp += sizeof(*dchdr);
 167                 len -= sizeof(*dchdr);
 168                 bp += dchdr->dlen;
 169                 len -= dchdr->dlen;
 170                 cnt++;
 171         }
 172
 173         if (len != 0) {
 174                 dev_err(dev, "%s: dcs_cmd=%x len=%d error!",
 175                         __func__, buf[0], blen);
 176                 kfree(buf);
 177                 return -EINVAL;
 178         }
 179
 180         pcmds->cmds = kcalloc(cnt, sizeof(struct dsi_cmd_desc), GFP_KERNEL);
 181         if (!pcmds->cmds) {
 182                 kfree(buf);
 183                 return -ENOMEM;
 184         }
 185
 186         pcmds->cmd_cnt = cnt;
 187         pcmds->buf = buf;
 188         pcmds->blen = blen;
 189
 190         bp = buf;
 191         len = blen;
 192         for (i = 0; i < cnt; i++) {
 193                 dchdr = (struct dsi_ctrl_hdr *)bp;
 194                 len -= sizeof(*dchdr);
 195                 bp += sizeof(*dchdr);
 196                 pcmds->cmds[i].dchdr = *dchdr;
 197                 pcmds->cmds[i].payload = bp;
 198                 bp += dchdr->dlen;
 199                 len -= dchdr->dlen;
 200         }
 201
 202         dev_info(dev, "%s: dcs_cmd=%x len=%d, cmd_cnt=%d\n", __func__,
 203                  pcmds->buf[0], pcmds->blen, pcmds->cmd_cnt);
 204         return 0;
 205 }
 206
 207 static int panel_simple_dsi_send_cmds(struct panel_simple *panel,
 208                                       struct dsi_panel_cmds *cmds)
 209 {
 210         struct mipi_dsi_device *dsi = panel->dsi;
 211         int i, err;
 212
 213         if (!cmds)
 214                 return -EINVAL;
 215
 216         for (i = 0; i < cmds->cmd_cnt; i++) {
 217                 struct dsi_cmd_desc *cmd = &cmds->cmds[i];
 218
 219                 switch (cmd->dchdr.dtype) {
 220                 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 221                 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
 222                 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
 223                 case MIPI_DSI_GENERIC_LONG_WRITE:
 224                         err = mipi_dsi_generic_write(dsi, cmd->payload,
 225                                                      cmd->dchdr.dlen);
 226                         break;
 227                 case MIPI_DSI_DCS_SHORT_WRITE:
 228                 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
 229                 case MIPI_DSI_DCS_LONG_WRITE:
 230                         err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
 231                                                         cmd->dchdr.dlen);
 232                         break;
 233                 default:
 234                         return -EINVAL;
 235                 }
 236
 237                 if (err < 0)
 238                         dev_err(panel->dev, "failed to write dcs cmd: %d\n",
 239                                 err);
 240
 241                 if (cmd->dchdr.wait)
 242                         msleep(cmd->dchdr.wait);
 243         }
 244
 245         return 0;
 246 }
 247
 248 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
 249 {
 250         struct drm_connector *connector = panel->base.connector;
 251         struct drm_device *drm = panel->base.drm;
 252         struct drm_display_mode *mode;
 253         unsigned int i, num = 0;
 254
 255         if (!panel->desc)
 256                 return 0;
 257
 258         for (i = 0; i < panel->desc->num_timings; i++) {
 259                 const struct display_timing *dt = &panel->desc->timings[i];
 260                 struct videomode vm;
 261
 262                 videomode_from_timing(dt, &vm);
 263                 mode = drm_mode_create(drm);
 264                 if (!mode) {
 265                         dev_err(drm->dev, "failed to add mode %ux%u\n",
 266                                 dt->hactive.typ, dt->vactive.typ);
 267                         continue;
 268                 }
 269
 270                 drm_display_mode_from_videomode(&vm, mode);
 271                 drm_mode_set_name(mode);
 272
 273                 drm_mode_probed_add(connector, mode);
 274                 num++;
 275         }
 276
 277         for (i = 0; i < panel->desc->num_modes; i++) {
 278                 const struct drm_display_mode *m = &panel->desc->modes[i];
 279
 280                 mode = drm_mode_duplicate(drm, m);
 281                 if (!mode) {
 282                         dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
 283                                 m->hdisplay, m->vdisplay, m->vrefresh);
 284                         continue;
 285                 }
 286
 287                 drm_mode_set_name(mode);
 288
 289                 drm_mode_probed_add(connector, mode);
 290                 num++;
 291         }
 292
 293         connector->display_info.bpc = panel->desc->bpc;
 294         connector->display_info.width_mm = panel->desc->size.width;
 295         connector->display_info.height_mm = panel->desc->size.height;
 296         if (panel->desc->bus_format)
 297                 drm_display_info_set_bus_formats(&connector->display_info,
 298                                                  &panel->desc->bus_format, 1);
 299
 300         return num;
 301 }
 302
 303 static int panel_simple_of_get_native_mode(struct panel_simple *panel)
 304 {
 305         struct drm_connector *connector = panel->base.connector;
 306         struct drm_device *drm = panel->base.drm;
 307         struct drm_display_mode *mode;
 308         struct device_node *timings_np;
 309         int ret;
 310
 311         timings_np = of_get_child_by_name(panel->dev->of_node,
 312                                           "display-timings");
 313         if (!timings_np) {
 314                 dev_dbg(panel->dev, "failed to find display-timings node\n");
 315                 return 0;
 316         }
 317
 318         of_node_put(timings_np);
 319         mode = drm_mode_create(drm);
 320         if (!mode)
 321                 return 0;
 322
 323         ret = of_get_drm_display_mode(panel->dev->of_node, mode,
 324                                       OF_USE_NATIVE_MODE);
 325         if (ret) {
 326                 dev_dbg(panel->dev, "failed to find dts display timings\n");
 327                 drm_mode_destroy(drm, mode);
 328                 return 0;
 329         }
 330
 331         drm_mode_set_name(mode);
 332         mode->type |= DRM_MODE_TYPE_PREFERRED;
 333         drm_mode_probed_add(connector, mode);
 334
 335         return 1;
 336 }
 337
 338 static int panel_simple_loader_protect(struct drm_panel *panel, bool on)
 339 {
 340         struct panel_simple *p = to_panel_simple(panel);
 341         int err;
 342
 343         if (on) {
 344                 err = regulator_enable(p->supply);
 345                 if (err < 0) {
 346                         dev_err(panel->dev, "failed to enable supply: %d\n",
 347                                 err);
 348                         return err;
 349                 }
 350         } else {
 351                 regulator_disable(p->supply);
 352         }
 353
 354         return 0;
 355 }
 356
 357 static int panel_simple_disable(struct drm_panel *panel)
 358 {
 359         struct panel_simple *p = to_panel_simple(panel);
 360
 361         if (!p->enabled)
 362                 return 0;
 363
 364         if (p->backlight) {
 365                 p->backlight->props.power = FB_BLANK_POWERDOWN;
 366                 backlight_update_status(p->backlight);
 367         }
 368
 369         if (p->desc && p->desc->delay.disable)
 370                 msleep(p->desc->delay.disable);
 371
 372         p->enabled = false;
 373
 374         return 0;
 375 }
 376
 377 static int panel_simple_unprepare(struct drm_panel *panel)
 378 {
 379         struct panel_simple *p = to_panel_simple(panel);
 380         int err;
 381
 382         if (!p->prepared)
 383                 return 0;
 384
 385         if (p->off_cmds) {
 386                 err = panel_simple_dsi_send_cmds(p, p->off_cmds);
 387                 if (err)
 388                         dev_err(p->dev, "failed to send off cmds\n");
 389         }
 390
 391         if (p->reset_gpio)
 392                 gpiod_direction_output(p->reset_gpio, 1);
 393
 394         if (p->enable_gpio)
 395                 gpiod_direction_output(p->enable_gpio, 0);
 396
 397         regulator_disable(p->supply);
 398
 399         if (p->desc && p->desc->delay.unprepare)
 400                 msleep(p->desc->delay.unprepare);
 401
 402         p->prepared = false;
 403
 404         return 0;
 405 }
 406
 407 static int panel_simple_prepare(struct drm_panel *panel)
 408 {
 409         struct panel_simple *p = to_panel_simple(panel);
 410         int err;
 411
 412         if (p->prepared)
 413                 return 0;
 414
 415         err = regulator_enable(p->supply);
 416         if (err < 0) {
 417                 dev_err(panel->dev, "failed to enable supply: %d\n", err);
 418                 return err;
 419         }
 420
 421         if (p->enable_gpio)
 422                 gpiod_direction_output(p->enable_gpio, 1);
 423
 424         if (p->desc && p->desc->delay.prepare)
 425                 msleep(p->desc->delay.prepare);
 426
 427         if (p->reset_gpio)
 428                 gpiod_direction_output(p->reset_gpio, 1);
 429
 430         if (p->desc && p->desc->delay.reset)
 431                 msleep(p->desc->delay.reset);
 432
 433         if (p->reset_gpio)
 434                 gpiod_direction_output(p->reset_gpio, 0);
 435
 436         if (p->desc && p->desc->delay.init)
 437                 msleep(p->desc->delay.init);
 438
 439         if (p->on_cmds) {
 440                 err = panel_simple_dsi_send_cmds(p, p->on_cmds);
 441                 if (err)
 442                         dev_err(p->dev, "failed to send on cmds\n");
 443         }
 444
 445         p->prepared = true;
 446
 447         return 0;
 448 }
 449
 450 static int panel_simple_enable(struct drm_panel *panel)
 451 {
 452         struct panel_simple *p = to_panel_simple(panel);
 453
 454         if (p->enabled)
 455                 return 0;
 456
 457         if (p->desc && p->desc->delay.enable)
 458                 msleep(p->desc->delay.enable);
 459
 460         if (p->backlight) {
 461                 p->backlight->props.power = FB_BLANK_UNBLANK;
 462                 backlight_update_status(p->backlight);
 463         }
 464
 465         p->enabled = true;
 466
 467         return 0;
 468 }
 469
 470 static int panel_simple_get_modes(struct drm_panel *panel)
 471 {
 472         struct panel_simple *p = to_panel_simple(panel);
 473         int num = 0;
 474
 475         /* add device node plane modes */
 476         num += panel_simple_of_get_native_mode(p);
 477
 478         /* add hard-coded panel modes */
 479         num += panel_simple_get_fixed_modes(p);
 480
 481         /* probe EDID if a DDC bus is available */
 482         if (p->ddc) {
 483                 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
 484                 drm_mode_connector_update_edid_property(panel->connector, edid);
 485                 if (edid) {
 486                         num += drm_add_edid_modes(panel->connector, edid);
 487                         kfree(edid);
 488                 }
 489         }
 490
 491         return num;
 492 }
 493
 494 static int panel_simple_get_timings(struct drm_panel *panel,
 495                                     unsigned int num_timings,
 496                                     struct display_timing *timings)
 497 {
 498         struct panel_simple *p = to_panel_simple(panel);
 499         unsigned int i;
 500
 501         if (!p->desc)
 502                 return 0;
 503
 504         if (p->desc->num_timings < num_timings)
 505                 num_timings = p->desc->num_timings;
 506
 507         if (timings)
 508                 for (i = 0; i < num_timings; i++)
 509                         timings[i] = p->desc->timings[i];
 510
 511         return p->desc->num_timings;
 512 }
 513
 514 static const struct drm_panel_funcs panel_simple_funcs = {
 515         .loader_protect = panel_simple_loader_protect,
 516         .disable = panel_simple_disable,
 517         .unprepare = panel_simple_unprepare,
 518         .prepare = panel_simple_prepare,
 519         .enable = panel_simple_enable,
 520         .get_modes = panel_simple_get_modes,
 521         .get_timings = panel_simple_get_timings,
 522 };
 523
 524 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
 525 {
 526         struct device_node *backlight, *ddc;
 527         struct panel_simple *panel;
 528         struct panel_desc *of_desc;
 529         u32 val;
 530         int err;
 531
 532         panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
 533         if (!panel)
 534                 return -ENOMEM;
 535
 536         if (!desc)
 537                 of_desc = devm_kzalloc(dev, sizeof(*of_desc), GFP_KERNEL);
 538         else
 539                 of_desc = devm_kmemdup(dev, desc, sizeof(*of_desc), GFP_KERNEL);
 540
 541         if (!of_property_read_u32(dev->of_node, "bus-format", &val))
 542                 of_desc->bus_format = val;
 543         if (!of_property_read_u32(dev->of_node, "prepare-delay-ms", &val))
 544                 of_desc->delay.prepare = val;
 545         if (!of_property_read_u32(dev->of_node, "enable-delay-ms", &val))
 546                 of_desc->delay.enable = val;
 547         if (!of_property_read_u32(dev->of_node, "disable-delay-ms", &val))
 548                 of_desc->delay.disable = val;
 549         if (!of_property_read_u32(dev->of_node, "unprepare-delay-ms", &val))
 550                 of_desc->delay.unprepare = val;
 551         if (!of_property_read_u32(dev->of_node, "reset-delay-ms", &val))
 552                 of_desc->delay.reset = val;
 553         if (!of_property_read_u32(dev->of_node, "init-delay-ms", &val))
 554                 of_desc->delay.init = val;
 555
 556         panel->enabled = false;
 557         panel->prepared = false;
 558         panel->desc = of_desc;
 559         panel->dev = dev;
 560
 561         panel->supply = devm_regulator_get(dev, "power");
 562         if (IS_ERR(panel->supply))
 563                 return PTR_ERR(panel->supply);
 564
 565         panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 0);
 566         if (IS_ERR(panel->enable_gpio)) {
 567                 err = PTR_ERR(panel->enable_gpio);
 568                 dev_err(dev, "failed to request enable GPIO: %d\n", err);
 569                 return err;
 570         }
 571
 572         panel->reset_gpio = devm_gpiod_get_optional(dev, "reset", 0);
 573         if (IS_ERR(panel->reset_gpio)) {
 574                 err = PTR_ERR(panel->reset_gpio);
 575                 dev_err(dev, "failed to request reset GPIO: %d\n", err);
 576                 return err;
 577         }
 578
 579         backlight = of_parse_phandle(dev->of_node, "backlight", 0);
 580         if (backlight) {
 581                 panel->backlight = of_find_backlight_by_node(backlight);
 582                 of_node_put(backlight);
 583
 584                 if (!panel->backlight)
 585                         return -EPROBE_DEFER;
 586         }
 587
 588         ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
 589         if (ddc) {
 590                 panel->ddc = of_find_i2c_adapter_by_node(ddc);
 591                 of_node_put(ddc);
 592
 593                 if (!panel->ddc) {
 594                         err = -EPROBE_DEFER;
 595                         goto free_backlight;
 596                 }
 597         }
 598
 599         drm_panel_init(&panel->base);
 600         panel->base.dev = dev;
 601         panel->base.funcs = &panel_simple_funcs;
 602
 603         err = drm_panel_add(&panel->base);
 604         if (err < 0)
 605                 goto free_ddc;
 606
 607         dev_set_drvdata(dev, panel);
 608
 609         return 0;
 610
 611 free_ddc:
 612         if (panel->ddc)
 613                 put_device(&panel->ddc->dev);
 614 free_backlight:
 615         if (panel->backlight)
 616                 put_device(&panel->backlight->dev);
 617
 618         return err;
 619 }
 620
 621 static int panel_simple_remove(struct device *dev)
 622 {
 623         struct panel_simple *panel = dev_get_drvdata(dev);
 624
 625         drm_panel_detach(&panel->base);
 626         drm_panel_remove(&panel->base);
 627
 628         panel_simple_disable(&panel->base);
 629
 630         if (panel->ddc)
 631                 put_device(&panel->ddc->dev);
 632
 633         if (panel->backlight)
 634                 put_device(&panel->backlight->dev);
 635
 636         panel_simple_dsi_cmds_cleanup(panel);
 637
 638         return 0;
 639 }
 640
 641 static void panel_simple_shutdown(struct device *dev)
 642 {
 643         struct panel_simple *panel = dev_get_drvdata(dev);
 644
 645         panel_simple_disable(&panel->base);
 646 }
 647
 648 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
 649         .clock = 33333,
 650         .hdisplay = 800,
 651         .hsync_start = 800 + 0,
 652         .hsync_end = 800 + 0 + 255,
 653         .htotal = 800 + 0 + 255 + 0,
 654         .vdisplay = 480,
 655         .vsync_start = 480 + 2,
 656         .vsync_end = 480 + 2 + 45,
 657         .vtotal = 480 + 2 + 45 + 0,
 658         .vrefresh = 60,
 659         .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
 660 };
 661
 662 static const struct panel_desc ampire_am800480r3tmqwa1h = {
 663         .modes = &ampire_am800480r3tmqwa1h_mode,
 664         .num_modes = 1,
 665         .bpc = 6,
 666         .size = {
 667                 .width = 152,
 668                 .height = 91,
 669         },
 670         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 671 };
 672
 673 static const struct drm_display_mode auo_b101aw03_mode = {
 674         .clock = 51450,
 675         .hdisplay = 1024,
 676         .hsync_start = 1024 + 156,
 677         .hsync_end = 1024 + 156 + 8,
 678         .htotal = 1024 + 156 + 8 + 156,
 679         .vdisplay = 600,
 680         .vsync_start = 600 + 16,
 681         .vsync_end = 600 + 16 + 6,
 682         .vtotal = 600 + 16 + 6 + 16,
 683         .vrefresh = 60,
 684 };
 685
 686 static const struct panel_desc auo_b101aw03 = {
 687         .modes = &auo_b101aw03_mode,
 688         .num_modes = 1,
 689         .bpc = 6,
 690         .size = {
 691                 .width = 223,
 692                 .height = 125,
 693         },
 694 };
 695
 696 static const struct drm_display_mode auo_b101ean01_mode = {
 697         .clock = 72500,
 698         .hdisplay = 1280,
 699         .hsync_start = 1280 + 119,
 700         .hsync_end = 1280 + 119 + 32,
 701         .htotal = 1280 + 119 + 32 + 21,
 702         .vdisplay = 800,
 703         .vsync_start = 800 + 4,
 704         .vsync_end = 800 + 4 + 20,
 705         .vtotal = 800 + 4 + 20 + 8,
 706         .vrefresh = 60,
 707 };
 708
 709 static const struct panel_desc auo_b101ean01 = {
 710         .modes = &auo_b101ean01_mode,
 711         .num_modes = 1,
 712         .bpc = 6,
 713         .size = {
 714                 .width = 217,
 715                 .height = 136,
 716         },
 717 };
 718
 719 static const struct drm_display_mode auo_b101ew05_mode = {
 720         .clock = 71000,
 721         .hdisplay = 1280,
 722         .hsync_start = 1280 + 18,
 723         .hsync_end = 1280 + 18 + 10,
 724         .htotal = 1280 + 18 + 10 + 100,
 725         .vdisplay = 800,
 726         .vsync_start = 800 + 6,
 727         .vsync_end = 800 + 6 + 2,
 728         .vtotal = 800 + 6 + 2 + 8,
 729         .vrefresh = 60,
 730 };
 731
 732 static const struct panel_desc auo_b101ew05 = {
 733         .modes = &auo_b101ew05_mode,
 734         .num_modes = 1,
 735         .bpc = 6,
 736         .size = {
 737                 .width = 217,
 738                 .height = 136,
 739         },
 740 };
 741
 742 static const struct drm_display_mode auo_b101xtn01_mode = {
 743         .clock = 72000,
 744         .hdisplay = 1366,
 745         .hsync_start = 1366 + 20,
 746         .hsync_end = 1366 + 20 + 70,
 747         .htotal = 1366 + 20 + 70,
 748         .vdisplay = 768,
 749         .vsync_start = 768 + 14,
 750         .vsync_end = 768 + 14 + 42,
 751         .vtotal = 768 + 14 + 42,
 752         .vrefresh = 60,
 753         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 754 };
 755
 756 static const struct panel_desc auo_b101xtn01 = {
 757         .modes = &auo_b101xtn01_mode,
 758         .num_modes = 1,
 759         .bpc = 6,
 760         .size = {
 761                 .width = 223,
 762                 .height = 125,
 763         },
 764 };
 765
 766 static const struct drm_display_mode auo_b116xw03_mode = {
 767         .clock = 70589,
 768         .hdisplay = 1366,
 769         .hsync_start = 1366 + 40,
 770         .hsync_end = 1366 + 40 + 40,
 771         .htotal = 1366 + 40 + 40 + 32,
 772         .vdisplay = 768,
 773         .vsync_start = 768 + 10,
 774         .vsync_end = 768 + 10 + 12,
 775         .vtotal = 768 + 10 + 12 + 6,
 776         .vrefresh = 60,
 777 };
 778
 779 static const struct panel_desc auo_b116xw03 = {
 780         .modes = &auo_b116xw03_mode,
 781         .num_modes = 1,
 782         .bpc = 6,
 783         .size = {
 784                 .width = 256,
 785                 .height = 144,
 786         },
 787 };
 788
 789 static const struct drm_display_mode auo_b125han03_mode = {
 790         .clock = 146900,
 791         .hdisplay = 1920,
 792         .hsync_start = 1920 + 48,
 793         .hsync_end = 1920 + 48 + 32,
 794         .htotal = 1920 + 48 + 32 + 140,
 795         .vdisplay = 1080,
 796         .vsync_start = 1080 + 2,
 797         .vsync_end = 1080 + 2 + 5,
 798         .vtotal = 1080 + 2 + 5 + 57,
 799         .vrefresh = 60,
 800         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 801 };
 802
 803 static const struct panel_desc auo_b125han03 = {
 804         .modes = &auo_b125han03_mode,
 805         .num_modes = 1,
 806         .bpc = 6,
 807         .size = {
 808                 .width = 276,
 809                 .height = 156,
 810         },
 811         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 812 };
 813
 814 static const struct drm_display_mode auo_b133xtn01_mode = {
 815         .clock = 69500,
 816         .hdisplay = 1366,
 817         .hsync_start = 1366 + 48,
 818         .hsync_end = 1366 + 48 + 32,
 819         .htotal = 1366 + 48 + 32 + 20,
 820         .vdisplay = 768,
 821         .vsync_start = 768 + 3,
 822         .vsync_end = 768 + 3 + 6,
 823         .vtotal = 768 + 3 + 6 + 13,
 824         .vrefresh = 60,
 825 };
 826
 827 static const struct panel_desc auo_b133xtn01 = {
 828         .modes = &auo_b133xtn01_mode,
 829         .num_modes = 1,
 830         .bpc = 6,
 831         .size = {
 832                 .width = 293,
 833                 .height = 165,
 834         },
 835 };
 836
 837 static const struct drm_display_mode auo_b133htn01_mode = {
 838         .clock = 150660,
 839         .hdisplay = 1920,
 840         .hsync_start = 1920 + 172,
 841         .hsync_end = 1920 + 172 + 80,
 842         .htotal = 1920 + 172 + 80 + 60,
 843         .vdisplay = 1080,
 844         .vsync_start = 1080 + 25,
 845         .vsync_end = 1080 + 25 + 10,
 846         .vtotal = 1080 + 25 + 10 + 10,
 847         .vrefresh = 60,
 848 };
 849
 850 static const struct panel_desc auo_b133htn01 = {
 851         .modes = &auo_b133htn01_mode,
 852         .num_modes = 1,
 853         .bpc = 6,
 854         .size = {
 855                 .width = 293,
 856                 .height = 165,
 857         },
 858         .delay = {
 859                 .prepare = 105,
 860                 .enable = 20,
 861                 .unprepare = 50,
 862         },
 863 };
 864
 865 static const struct drm_display_mode avic_tm070ddh03_mode = {
 866         .clock = 51200,
 867         .hdisplay = 1024,
 868         .hsync_start = 1024 + 160,
 869         .hsync_end = 1024 + 160 + 4,
 870         .htotal = 1024 + 160 + 4 + 156,
 871         .vdisplay = 600,
 872         .vsync_start = 600 + 17,
 873         .vsync_end = 600 + 17 + 1,
 874         .vtotal = 600 + 17 + 1 + 17,
 875         .vrefresh = 60,
 876 };
 877
 878 static const struct panel_desc avic_tm070ddh03 = {
 879         .modes = &avic_tm070ddh03_mode,
 880         .num_modes = 1,
 881         .bpc = 8,
 882         .size = {
 883                 .width = 154,
 884                 .height = 90,
 885         },
 886         .delay = {
 887                 .prepare = 20,
 888                 .enable = 200,
 889                 .disable = 200,
 890         },
 891 };
 892
 893 static const struct drm_display_mode boe_nv125fhm_n73_mode = {
 894         .clock = 72300,
 895         .hdisplay = 1366,
 896         .hsync_start = 1366 + 80,
 897         .hsync_end = 1366 + 80 + 20,
 898         .htotal = 1366 + 80 + 20 + 60,
 899         .vdisplay = 768,
 900         .vsync_start = 768 + 12,
 901         .vsync_end = 768 + 12 + 2,
 902         .vtotal = 768 + 12 + 2 + 8,
 903         .vrefresh = 60,
 904         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
 905 };
 906
 907 static const struct panel_desc boe_nv125fhm_n73 = {
 908         .modes = &boe_nv125fhm_n73_mode,
 909         .num_modes = 1,
 910         .bpc = 6,
 911         .size = {
 912                 .width = 276,
 913                 .height = 156,
 914         },
 915         .delay = {
 916                 .unprepare = 160,
 917         },
 918         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
 919 };
 920
 921 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
 922         .clock = 67000,
 923         .hdisplay = 800,
 924         .hsync_start = 800 + 24,
 925         .hsync_end = 800 + 24 + 16,
 926         .htotal = 800 + 24 + 16 + 24,
 927         .vdisplay = 1280,
 928         .vsync_start = 1280 + 2,
 929         .vsync_end = 1280 + 2 + 2,
 930         .vtotal = 1280 + 2 + 2 + 4,
 931         .vrefresh = 60,
 932 };
 933
 934 static const struct panel_desc chunghwa_claa070wp03xg = {
 935         .modes = &chunghwa_claa070wp03xg_mode,
 936         .num_modes = 1,
 937         .bpc = 6,
 938         .size = {
 939                 .width = 94,
 940                 .height = 151,
 941         },
 942 };
 943
 944 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
 945         .clock = 72070,
 946         .hdisplay = 1366,
 947         .hsync_start = 1366 + 58,
 948         .hsync_end = 1366 + 58 + 58,
 949         .htotal = 1366 + 58 + 58 + 58,
 950         .vdisplay = 768,
 951         .vsync_start = 768 + 4,
 952         .vsync_end = 768 + 4 + 4,
 953         .vtotal = 768 + 4 + 4 + 4,
 954         .vrefresh = 60,
 955 };
 956
 957 static const struct panel_desc chunghwa_claa101wa01a = {
 958         .modes = &chunghwa_claa101wa01a_mode,
 959         .num_modes = 1,
 960         .bpc = 6,
 961         .size = {
 962                 .width = 220,
 963                 .height = 120,
 964         },
 965 };
 966
 967 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
 968         .clock = 69300,
 969         .hdisplay = 1366,
 970         .hsync_start = 1366 + 48,
 971         .hsync_end = 1366 + 48 + 32,
 972         .htotal = 1366 + 48 + 32 + 20,
 973         .vdisplay = 768,
 974         .vsync_start = 768 + 16,
 975         .vsync_end = 768 + 16 + 8,
 976         .vtotal = 768 + 16 + 8 + 16,
 977         .vrefresh = 60,
 978 };
 979
 980 static const struct panel_desc chunghwa_claa101wb01 = {
 981         .modes = &chunghwa_claa101wb01_mode,
 982         .num_modes = 1,
 983         .bpc = 6,
 984         .size = {
 985                 .width = 223,
 986                 .height = 125,
 987         },
 988 };
 989
 990 static const struct drm_display_mode edt_et057090dhu_mode = {
 991         .clock = 25175,
 992         .hdisplay = 640,
 993         .hsync_start = 640 + 16,
 994         .hsync_end = 640 + 16 + 30,
 995         .htotal = 640 + 16 + 30 + 114,
 996         .vdisplay = 480,
 997         .vsync_start = 480 + 10,
 998         .vsync_end = 480 + 10 + 3,
 999         .vtotal = 480 + 10 + 3 + 32,
1000         .vrefresh = 60,
1001         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1002 };
1003
1004 static const struct panel_desc edt_et057090dhu = {
1005         .modes = &edt_et057090dhu_mode,
1006         .num_modes = 1,
1007         .bpc = 6,
1008         .size = {
1009                 .width = 115,
1010                 .height = 86,
1011         },
1012 };
1013
1014 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1015         .clock = 33260,
1016         .hdisplay = 800,
1017         .hsync_start = 800 + 40,
1018         .hsync_end = 800 + 40 + 128,
1019         .htotal = 800 + 40 + 128 + 88,
1020         .vdisplay = 480,
1021         .vsync_start = 480 + 10,
1022         .vsync_end = 480 + 10 + 2,
1023         .vtotal = 480 + 10 + 2 + 33,
1024         .vrefresh = 60,
1025         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1026 };
1027
1028 static const struct panel_desc edt_etm0700g0dh6 = {
1029         .modes = &edt_etm0700g0dh6_mode,
1030         .num_modes = 1,
1031         .bpc = 6,
1032         .size = {
1033                 .width = 152,
1034                 .height = 91,
1035         },
1036 };
1037
1038 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1039         .clock = 32260,
1040         .hdisplay = 800,
1041         .hsync_start = 800 + 168,
1042         .hsync_end = 800 + 168 + 64,
1043         .htotal = 800 + 168 + 64 + 88,
1044         .vdisplay = 480,
1045         .vsync_start = 480 + 37,
1046         .vsync_end = 480 + 37 + 2,
1047         .vtotal = 480 + 37 + 2 + 8,
1048         .vrefresh = 60,
1049 };
1050
1051 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1052         .modes = &foxlink_fl500wvr00_a0t_mode,
1053         .num_modes = 1,
1054         .bpc = 8,
1055         .size = {
1056                 .width = 108,
1057                 .height = 65,
1058         },
1059         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1060 };
1061
1062 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1063         .clock = 9000,
1064         .hdisplay = 480,
1065         .hsync_start = 480 + 5,
1066         .hsync_end = 480 + 5 + 1,
1067         .htotal = 480 + 5 + 1 + 40,
1068         .vdisplay = 272,
1069         .vsync_start = 272 + 8,
1070         .vsync_end = 272 + 8 + 1,
1071         .vtotal = 272 + 8 + 1 + 8,
1072         .vrefresh = 60,
1073 };
1074
1075 static const struct panel_desc giantplus_gpg482739qs5 = {
1076         .modes = &giantplus_gpg482739qs5_mode,
1077         .num_modes = 1,
1078         .bpc = 8,
1079         .size = {
1080                 .width = 95,
1081                 .height = 54,
1082         },
1083         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1084 };
1085
1086 static const struct display_timing hannstar_hsd070pww1_timing = {
1087         .pixelclock = { 64300000, 71100000, 82000000 },
1088         .hactive = { 1280, 1280, 1280 },
1089         .hfront_porch = { 1, 1, 10 },
1090         .hback_porch = { 1, 1, 10 },
1091         /*
1092          * According to the data sheet, the minimum horizontal blanking interval
1093          * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1094          * minimum working horizontal blanking interval to be 60 clocks.
1095          */
1096         .hsync_len = { 58, 158, 661 },
1097         .vactive = { 800, 800, 800 },
1098         .vfront_porch = { 1, 1, 10 },
1099         .vback_porch = { 1, 1, 10 },
1100         .vsync_len = { 1, 21, 203 },
1101         .flags = DISPLAY_FLAGS_DE_HIGH,
1102 };
1103
1104 static const struct panel_desc hannstar_hsd070pww1 = {
1105         .timings = &hannstar_hsd070pww1_timing,
1106         .num_timings = 1,
1107         .bpc = 6,
1108         .size = {
1109                 .width = 151,
1110                 .height = 94,
1111         },
1112         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1113 };
1114
1115 static const struct display_timing hannstar_hsd100pxn1_timing = {
1116         .pixelclock = { 55000000, 65000000, 75000000 },
1117         .hactive = { 1024, 1024, 1024 },
1118         .hfront_porch = { 40, 40, 40 },
1119         .hback_porch = { 220, 220, 220 },
1120         .hsync_len = { 20, 60, 100 },
1121         .vactive = { 768, 768, 768 },
1122         .vfront_porch = { 7, 7, 7 },
1123         .vback_porch = { 21, 21, 21 },
1124         .vsync_len = { 10, 10, 10 },
1125         .flags = DISPLAY_FLAGS_DE_HIGH,
1126 };
1127
1128 static const struct panel_desc hannstar_hsd100pxn1 = {
1129         .timings = &hannstar_hsd100pxn1_timing,
1130         .num_timings = 1,
1131         .bpc = 6,
1132         .size = {
1133                 .width = 203,
1134                 .height = 152,
1135         },
1136         .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1137 };
1138
1139 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1140         .clock = 33333,
1141         .hdisplay = 800,
1142         .hsync_start = 800 + 85,
1143         .hsync_end = 800 + 85 + 86,
1144         .htotal = 800 + 85 + 86 + 85,
1145         .vdisplay = 480,
1146         .vsync_start = 480 + 16,
1147         .vsync_end = 480 + 16 + 13,
1148         .vtotal = 480 + 16 + 13 + 16,
1149         .vrefresh = 60,
1150 };
1151
1152 static const struct panel_desc hitachi_tx23d38vm0caa = {
1153         .modes = &hitachi_tx23d38vm0caa_mode,
1154         .num_modes = 1,
1155         .bpc = 6,
1156         .size = {
1157                 .width = 195,
1158                 .height = 117,
1159         },
1160 };
1161
1162 static const struct drm_display_mode innolux_at043tn24_mode = {
1163         .clock = 9000,
1164         .hdisplay = 480,
1165         .hsync_start = 480 + 2,
1166         .hsync_end = 480 + 2 + 41,
1167         .htotal = 480 + 2 + 41 + 2,
1168         .vdisplay = 272,
1169         .vsync_start = 272 + 2,
1170         .vsync_end = 272 + 2 + 11,
1171         .vtotal = 272 + 2 + 11 + 2,
1172         .vrefresh = 60,
1173         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1174 };
1175
1176 static const struct panel_desc innolux_at043tn24 = {
1177         .modes = &innolux_at043tn24_mode,
1178         .num_modes = 1,
1179         .bpc = 8,
1180         .size = {
1181                 .width = 95,
1182                 .height = 54,
1183         },
1184         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1185 };
1186
1187 static const struct drm_display_mode innolux_g121i1_l01_mode = {
1188         .clock = 71000,
1189         .hdisplay = 1280,
1190         .hsync_start = 1280 + 64,
1191         .hsync_end = 1280 + 64 + 32,
1192         .htotal = 1280 + 64 + 32 + 64,
1193         .vdisplay = 800,
1194         .vsync_start = 800 + 9,
1195         .vsync_end = 800 + 9 + 6,
1196         .vtotal = 800 + 9 + 6 + 9,
1197         .vrefresh = 60,
1198 };
1199
1200 static const struct panel_desc innolux_g121i1_l01 = {
1201         .modes = &innolux_g121i1_l01_mode,
1202         .num_modes = 1,
1203         .bpc = 6,
1204         .size = {
1205                 .width = 261,
1206                 .height = 163,
1207         },
1208 };
1209
1210 static const struct drm_display_mode innolux_n116bge_mode = {
1211         .clock = 76420,
1212         .hdisplay = 1366,
1213         .hsync_start = 1366 + 136,
1214         .hsync_end = 1366 + 136 + 30,
1215         .htotal = 1366 + 136 + 30 + 60,
1216         .vdisplay = 768,
1217         .vsync_start = 768 + 8,
1218         .vsync_end = 768 + 8 + 12,
1219         .vtotal = 768 + 8 + 12 + 12,
1220         .vrefresh = 60,
1221         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1222 };
1223
1224 static const struct panel_desc innolux_n116bge = {
1225         .modes = &innolux_n116bge_mode,
1226         .num_modes = 1,
1227         .bpc = 6,
1228         .size = {
1229                 .width = 256,
1230                 .height = 144,
1231         },
1232 };
1233
1234 static const struct drm_display_mode innolux_n125hce_mode = {
1235         .clock = 138780,
1236         .hdisplay = 1920,
1237         .hsync_start = 1920 + 80,
1238         .hsync_end = 1920 + 80 + 30,
1239         .htotal = 1920 + 80 + 30 + 50,
1240         .vdisplay = 1080,
1241         .vsync_start = 1080 + 12,
1242         .vsync_end = 1080 + 12 + 4,
1243         .vtotal = 1080 + 12 + 4 + 16,
1244         .vrefresh = 60,
1245         .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1246 };
1247
1248 static const struct panel_desc innolux_n125hce = {
1249         .modes = &innolux_n125hce_mode,
1250         .num_modes = 1,
1251         .bpc = 6,
1252         .size = {
1253                 .width = 283,
1254                 .height = 168,
1255         },
1256         .delay = {
1257                 .unprepare = 600,
1258                 .enable = 100,
1259         },
1260         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1261 };
1262
1263 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1264         .clock = 69300,
1265         .hdisplay = 1366,
1266         .hsync_start = 1366 + 16,
1267         .hsync_end = 1366 + 16 + 34,
1268         .htotal = 1366 + 16 + 34 + 50,
1269         .vdisplay = 768,
1270         .vsync_start = 768 + 2,
1271         .vsync_end = 768 + 2 + 6,
1272         .vtotal = 768 + 2 + 6 + 12,
1273         .vrefresh = 60,
1274 };
1275
1276 static const struct panel_desc innolux_n156bge_l21 = {
1277         .modes = &innolux_n156bge_l21_mode,
1278         .num_modes = 1,
1279         .bpc = 6,
1280         .size = {
1281                 .width = 344,
1282                 .height = 193,
1283         },
1284 };
1285
1286 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1287         .clock = 51501,
1288         .hdisplay = 1024,
1289         .hsync_start = 1024 + 128,
1290         .hsync_end = 1024 + 128 + 64,
1291         .htotal = 1024 + 128 + 64 + 128,
1292         .vdisplay = 600,
1293         .vsync_start = 600 + 16,
1294         .vsync_end = 600 + 16 + 4,
1295         .vtotal = 600 + 16 + 4 + 16,
1296         .vrefresh = 60,
1297 };
1298
1299 static const struct panel_desc innolux_zj070na_01p = {
1300         .modes = &innolux_zj070na_01p_mode,
1301         .num_modes = 1,
1302         .bpc = 6,
1303         .size = {
1304                 .width = 1024,
1305                 .height = 600,
1306         },
1307 };
1308
1309 static const struct drm_display_mode lg_lb070wv8_mode = {
1310         .clock = 33246,
1311         .hdisplay = 800,
1312         .hsync_start = 800 + 88,
1313         .hsync_end = 800 + 88 + 80,
1314         .htotal = 800 + 88 + 80 + 88,
1315         .vdisplay = 480,
1316         .vsync_start = 480 + 10,
1317         .vsync_end = 480 + 10 + 25,
1318         .vtotal = 480 + 10 + 25 + 10,
1319         .vrefresh = 60,
1320 };
1321
1322 static const struct panel_desc lg_lb070wv8 = {
1323         .modes = &lg_lb070wv8_mode,
1324         .num_modes = 1,
1325         .bpc = 16,
1326         .size = {
1327                 .width = 151,
1328                 .height = 91,
1329         },
1330         .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1331 };
1332
1333 static const struct drm_display_mode sharp_lcd_f402_mode = {
1334         .clock = 205000,
1335         .hdisplay = 1536,
1336         .hsync_start = 1536 + 12,
1337         .hsync_end = 1536 + 12 + 48,
1338         .htotal = 1536 + 12 + 48 + 16,
1339         .vdisplay = 2048,
1340         .vsync_start = 2048 + 8,
1341         .vsync_end = 2048 + 8 + 8,
1342         .vtotal = 2048 + 8 + 8 + 4,
1343         .vrefresh = 60,
1344         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1345 };
1346
1347 static const struct panel_desc sharp_lcd_f402 = {
1348         .modes = &sharp_lcd_f402_mode,
1349         .num_modes = 1,
1350         .bpc = 8,
1351         .size = {
1352                 .width = 95,
1353                 .height = 54,
1354         },
1355         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1356 };
1357
1358 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1359         .clock = 200000,
1360         .hdisplay = 1536,
1361         .hsync_start = 1536 + 12,
1362         .hsync_end = 1536 + 12 + 16,
1363         .htotal = 1536 + 12 + 16 + 48,
1364         .vdisplay = 2048,
1365         .vsync_start = 2048 + 8,
1366         .vsync_end = 2048 + 8 + 4,
1367         .vtotal = 2048 + 8 + 4 + 8,
1368         .vrefresh = 60,
1369         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1370 };
1371
1372 static const struct panel_desc lg_lp079qx1_sp0v = {
1373         .modes = &lg_lp079qx1_sp0v_mode,
1374         .num_modes = 1,
1375         .size = {
1376                 .width = 129,
1377                 .height = 171,
1378         },
1379         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1380 };
1381
1382 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1383         .clock = 205210,
1384         .hdisplay = 2048,
1385         .hsync_start = 2048 + 150,
1386         .hsync_end = 2048 + 150 + 5,
1387         .htotal = 2048 + 150 + 5 + 5,
1388         .vdisplay = 1536,
1389         .vsync_start = 1536 + 3,
1390         .vsync_end = 1536 + 3 + 1,
1391         .vtotal = 1536 + 3 + 1 + 9,
1392         .vrefresh = 60,
1393 };
1394
1395 static const struct panel_desc lg_lp097qx1_spa1 = {
1396         .modes = &lg_lp097qx1_spa1_mode,
1397         .num_modes = 1,
1398         .size = {
1399                 .width = 320,
1400                 .height = 187,
1401         },
1402 };
1403
1404 static const struct drm_display_mode lg_lp129qe_mode = {
1405         .clock = 285250,
1406         .hdisplay = 2560,
1407         .hsync_start = 2560 + 48,
1408         .hsync_end = 2560 + 48 + 32,
1409         .htotal = 2560 + 48 + 32 + 80,
1410         .vdisplay = 1700,
1411         .vsync_start = 1700 + 3,
1412         .vsync_end = 1700 + 3 + 10,
1413         .vtotal = 1700 + 3 + 10 + 36,
1414         .vrefresh = 60,
1415 };
1416
1417 static const struct panel_desc lg_lp129qe = {
1418         .modes = &lg_lp129qe_mode,
1419         .num_modes = 1,
1420         .bpc = 8,
1421         .size = {
1422                 .width = 272,
1423                 .height = 181,
1424         },
1425 };
1426
1427 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1428         .clock = 10870,
1429         .hdisplay = 480,
1430         .hsync_start = 480 + 2,
1431         .hsync_end = 480 + 2 + 41,
1432         .htotal = 480 + 2 + 41 + 2,
1433         .vdisplay = 272,
1434         .vsync_start = 272 + 2,
1435         .vsync_end = 272 + 2 + 4,
1436         .vtotal = 272 + 2 + 4 + 2,
1437         .vrefresh = 74,
1438 };
1439
1440 static const struct panel_desc nec_nl4827hc19_05b = {
1441         .modes = &nec_nl4827hc19_05b_mode,
1442         .num_modes = 1,
1443         .bpc = 8,
1444         .size = {
1445                 .width = 95,
1446                 .height = 54,
1447         },
1448         .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1449 };
1450
1451 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1452         .pixelclock = { 30000000, 30000000, 40000000 },
1453         .hactive = { 800, 800, 800 },
1454         .hfront_porch = { 40, 40, 40 },
1455         .hback_porch = { 40, 40, 40 },
1456         .hsync_len = { 1, 48, 48 },
1457         .vactive = { 480, 480, 480 },
1458         .vfront_porch = { 13, 13, 13 },
1459         .vback_porch = { 29, 29, 29 },
1460         .vsync_len = { 3, 3, 3 },
1461         .flags = DISPLAY_FLAGS_DE_HIGH,
1462 };
1463
1464 static const struct panel_desc okaya_rs800480t_7x0gp = {
1465         .timings = &okaya_rs800480t_7x0gp_timing,
1466         .num_timings = 1,
1467         .bpc = 6,
1468         .size = {
1469                 .width = 154,
1470                 .height = 87,
1471         },
1472         .delay = {
1473                 .prepare = 41,
1474                 .enable = 50,
1475                 .unprepare = 41,
1476                 .disable = 50,
1477         },
1478         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1479 };
1480
1481 static const struct drm_display_mode ortustech_com43h4m85ulc_mode  = {
1482         .clock = 25000,
1483         .hdisplay = 480,
1484         .hsync_start = 480 + 10,
1485         .hsync_end = 480 + 10 + 10,
1486         .htotal = 480 + 10 + 10 + 15,
1487         .vdisplay = 800,
1488         .vsync_start = 800 + 3,
1489         .vsync_end = 800 + 3 + 3,
1490         .vtotal = 800 + 3 + 3 + 3,
1491         .vrefresh = 60,
1492 };
1493
1494 static const struct panel_desc ortustech_com43h4m85ulc = {
1495         .modes = &ortustech_com43h4m85ulc_mode,
1496         .num_modes = 1,
1497         .bpc = 8,
1498         .size = {
1499                 .width = 56,
1500                 .height = 93,
1501         },
1502         .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1503 };
1504
1505 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1506         .clock = 271560,
1507         .hdisplay = 2560,
1508         .hsync_start = 2560 + 48,
1509         .hsync_end = 2560 + 48 + 32,
1510         .htotal = 2560 + 48 + 32 + 80,
1511         .vdisplay = 1600,
1512         .vsync_start = 1600 + 2,
1513         .vsync_end = 1600 + 2 + 5,
1514         .vtotal = 1600 + 2 + 5 + 57,
1515         .vrefresh = 60,
1516 };
1517
1518 static const struct panel_desc samsung_lsn122dl01_c01 = {
1519         .modes = &samsung_lsn122dl01_c01_mode,
1520         .num_modes = 1,
1521         .size = {
1522                 .width = 2560,
1523                 .height = 1600,
1524         },
1525 };
1526
1527 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1528         .clock = 54030,
1529         .hdisplay = 1024,
1530         .hsync_start = 1024 + 24,
1531         .hsync_end = 1024 + 24 + 136,
1532         .htotal = 1024 + 24 + 136 + 160,
1533         .vdisplay = 600,
1534         .vsync_start = 600 + 3,
1535         .vsync_end = 600 + 3 + 6,
1536         .vtotal = 600 + 3 + 6 + 61,
1537         .vrefresh = 60,
1538 };
1539
1540 static const struct panel_desc samsung_ltn101nt05 = {
1541         .modes = &samsung_ltn101nt05_mode,
1542         .num_modes = 1,
1543         .bpc = 6,
1544         .size = {
1545                 .width = 1024,
1546                 .height = 600,
1547         },
1548 };
1549
1550 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1551         .clock = 76300,
1552         .hdisplay = 1366,
1553         .hsync_start = 1366 + 64,
1554         .hsync_end = 1366 + 64 + 48,
1555         .htotal = 1366 + 64 + 48 + 128,
1556         .vdisplay = 768,
1557         .vsync_start = 768 + 2,
1558         .vsync_end = 768 + 2 + 5,
1559         .vtotal = 768 + 2 + 5 + 17,
1560         .vrefresh = 60,
1561 };
1562
1563 static const struct panel_desc samsung_ltn140at29_301 = {
1564         .modes = &samsung_ltn140at29_301_mode,
1565         .num_modes = 1,
1566         .bpc = 6,
1567         .size = {
1568                 .width = 320,
1569                 .height = 187,
1570         },
1571 };
1572
1573 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1574         .clock = 33300,
1575         .hdisplay = 800,
1576         .hsync_start = 800 + 1,
1577         .hsync_end = 800 + 1 + 64,
1578         .htotal = 800 + 1 + 64 + 64,
1579         .vdisplay = 480,
1580         .vsync_start = 480 + 1,
1581         .vsync_end = 480 + 1 + 23,
1582         .vtotal = 480 + 1 + 23 + 22,
1583         .vrefresh = 60,
1584 };
1585
1586 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1587         .modes = &shelly_sca07010_bfn_lnn_mode,
1588         .num_modes = 1,
1589         .size = {
1590                 .width = 152,
1591                 .height = 91,
1592         },
1593         .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1594 };
1595
1596 static const struct of_device_id platform_of_match[] = {
1597         {
1598                 .compatible = "simple-panel",
1599                 .data = NULL,
1600         }, {
1601                 .compatible = "ampire,am800480r3tmqwa1h",
1602                 .data = &ampire_am800480r3tmqwa1h,
1603         }, {
1604                 .compatible = "auo,b101aw03",
1605                 .data = &auo_b101aw03,
1606         }, {
1607                 .compatible = "auo,b101ean01",
1608                 .data = &auo_b101ean01,
1609         }, {
1610                 .compatible = "auo,b101ew05",
1611                 .data = &auo_b101ew05,
1612         }, {
1613                 .compatible = "auo,b101xtn01",
1614                 .data = &auo_b101xtn01,
1615         }, {
1616                 .compatible = "auo,b116xw03",
1617                 .data = &auo_b116xw03,
1618         }, {
1619                 .compatible = "auo,b125han03",
1620                 .data = &auo_b125han03,
1621         }, {
1622                 .compatible = "auo,b133htn01",
1623                 .data = &auo_b133htn01,
1624         }, {
1625                 .compatible = "auo,b133xtn01",
1626                 .data = &auo_b133xtn01,
1627         }, {
1628                 .compatible = "avic,tm070ddh03",
1629                 .data = &avic_tm070ddh03,
1630         }, {
1631                 .compatible = "boe,nv125fhm-n73",
1632                 .data = &boe_nv125fhm_n73,
1633         }, {
1634                 .compatible = "chunghwa,claa070wp03xg",
1635                 .data = &chunghwa_claa070wp03xg,
1636         }, {
1637                 .compatible = "chunghwa,claa101wa01a",
1638                 .data = &chunghwa_claa101wa01a
1639         }, {
1640                 .compatible = "chunghwa,claa101wb01",
1641                 .data = &chunghwa_claa101wb01
1642         }, {
1643                 .compatible = "edt,et057090dhu",
1644                 .data = &edt_et057090dhu,
1645         }, {
1646                 .compatible = "edt,et070080dh6",
1647                 .data = &edt_etm0700g0dh6,
1648         }, {
1649                 .compatible = "edt,etm0700g0dh6",
1650                 .data = &edt_etm0700g0dh6,
1651         }, {
1652                 .compatible = "foxlink,fl500wvr00-a0t",
1653                 .data = &foxlink_fl500wvr00_a0t,
1654         }, {
1655                 .compatible = "giantplus,gpg482739qs5",
1656                 .data = &giantplus_gpg482739qs5
1657         }, {
1658                 .compatible = "hannstar,hsd070pww1",
1659                 .data = &hannstar_hsd070pww1,
1660         }, {
1661                 .compatible = "hannstar,hsd100pxn1",
1662                 .data = &hannstar_hsd100pxn1,
1663         }, {
1664                 .compatible = "hit,tx23d38vm0caa",
1665                 .data = &hitachi_tx23d38vm0caa
1666         }, {
1667                 .compatible = "innolux,at043tn24",
1668                 .data = &innolux_at043tn24,
1669         }, {
1670                 .compatible ="innolux,g121i1-l01",
1671                 .data = &innolux_g121i1_l01
1672         }, {
1673                 .compatible = "innolux,n116bge",
1674                 .data = &innolux_n116bge,
1675         }, {
1676                 .compatible = "innolux,n125hce",
1677                 .data = &innolux_n125hce,
1678         }, {
1679                 .compatible = "innolux,n156bge-l21",
1680                 .data = &innolux_n156bge_l21,
1681         }, {
1682                 .compatible = "innolux,zj070na-01p",
1683                 .data = &innolux_zj070na_01p,
1684         }, {
1685                 .compatible = "lg,lb070wv8",
1686                 .data = &lg_lb070wv8,
1687         }, {
1688                 .compatible = "lg,lp079qx1-sp0v",
1689                 .data = &lg_lp079qx1_sp0v,
1690         }, {
1691                 .compatible = "lg,lp097qx1-spa1",
1692                 .data = &lg_lp097qx1_spa1,
1693         }, {
1694                 .compatible = "lg,lp129qe",
1695                 .data = &lg_lp129qe,
1696         }, {
1697                 .compatible = "nec,nl4827hc19-05b",
1698                 .data = &nec_nl4827hc19_05b,
1699         }, {
1700                 .compatible = "okaya,rs800480t-7x0gp",
1701                 .data = &okaya_rs800480t_7x0gp,
1702         }, {
1703                 .compatible = "ortustech,com43h4m85ulc",
1704                 .data = &ortustech_com43h4m85ulc,
1705         }, {
1706                 .compatible = "samsung,lsn122dl01-c01",
1707                 .data = &samsung_lsn122dl01_c01,
1708         }, {
1709                 .compatible = "samsung,ltn101nt05",
1710                 .data = &samsung_ltn101nt05,
1711         }, {
1712                 .compatible = "samsung,ltn140at29-301",
1713                 .data = &samsung_ltn140at29_301,
1714         }, {
1715                 .compatible = "sharp,lcd-f402",
1716                 .data = &sharp_lcd_f402,
1717         }, {
1718                 .compatible = "shelly,sca07010-bfn-lnn",
1719                 .data = &shelly_sca07010_bfn_lnn,
1720         }, {
1721                 /* sentinel */
1722         }
1723 };
1724 MODULE_DEVICE_TABLE(of, platform_of_match);
1725
1726 static int panel_simple_platform_probe(struct platform_device *pdev)
1727 {
1728         const struct of_device_id *id;
1729
1730         id = of_match_node(platform_of_match, pdev->dev.of_node);
1731         if (!id)
1732                 return -ENODEV;
1733
1734         return panel_simple_probe(&pdev->dev, id->data);
1735 }
1736
1737 static int panel_simple_platform_remove(struct platform_device *pdev)
1738 {
1739         return panel_simple_remove(&pdev->dev);
1740 }
1741
1742 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1743 {
1744         panel_simple_shutdown(&pdev->dev);
1745 }
1746
1747 static struct platform_driver panel_simple_platform_driver = {
1748         .driver = {
1749                 .name = "panel-simple",
1750                 .of_match_table = platform_of_match,
1751         },
1752         .probe = panel_simple_platform_probe,
1753         .remove = panel_simple_platform_remove,
1754         .shutdown = panel_simple_platform_shutdown,
1755 };
1756
1757 struct panel_desc_dsi {
1758         struct panel_desc desc;
1759
1760         unsigned long flags;
1761         enum mipi_dsi_pixel_format format;
1762         unsigned int lanes;
1763 };
1764
1765 static const struct drm_display_mode auo_b080uan01_mode = {
1766         .clock = 154500,
1767         .hdisplay = 1200,
1768         .hsync_start = 1200 + 62,
1769         .hsync_end = 1200 + 62 + 4,
1770         .htotal = 1200 + 62 + 4 + 62,
1771         .vdisplay = 1920,
1772         .vsync_start = 1920 + 9,
1773         .vsync_end = 1920 + 9 + 2,
1774         .vtotal = 1920 + 9 + 2 + 8,
1775         .vrefresh = 60,
1776 };
1777
1778 static const struct panel_desc_dsi auo_b080uan01 = {
1779         .desc = {
1780                 .modes = &auo_b080uan01_mode,
1781                 .num_modes = 1,
1782                 .bpc = 8,
1783                 .size = {
1784                         .width = 108,
1785                         .height = 272,
1786                 },
1787         },
1788         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1789         .format = MIPI_DSI_FMT_RGB888,
1790         .lanes = 4,
1791 };
1792
1793 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1794         .clock = 160000,
1795         .hdisplay = 1200,
1796         .hsync_start = 1200 + 120,
1797         .hsync_end = 1200 + 120 + 20,
1798         .htotal = 1200 + 120 + 20 + 21,
1799         .vdisplay = 1920,
1800         .vsync_start = 1920 + 21,
1801         .vsync_end = 1920 + 21 + 3,
1802         .vtotal = 1920 + 21 + 3 + 18,
1803         .vrefresh = 60,
1804         .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1805 };
1806
1807 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1808         .desc = {
1809                 .modes = &boe_tv080wum_nl0_mode,
1810                 .num_modes = 1,
1811                 .size = {
1812                         .width = 107,
1813                         .height = 172,
1814                 },
1815         },
1816         .flags = MIPI_DSI_MODE_VIDEO |
1817                  MIPI_DSI_MODE_VIDEO_BURST |
1818                  MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1819         .format = MIPI_DSI_FMT_RGB888,
1820         .lanes = 4,
1821 };
1822
1823 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1824         .clock = 71000,
1825         .hdisplay = 800,
1826         .hsync_start = 800 + 32,
1827         .hsync_end = 800 + 32 + 1,
1828         .htotal = 800 + 32 + 1 + 57,
1829         .vdisplay = 1280,
1830         .vsync_start = 1280 + 28,
1831         .vsync_end = 1280 + 28 + 1,
1832         .vtotal = 1280 + 28 + 1 + 14,
1833         .vrefresh = 60,
1834 };
1835
1836 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1837         .desc = {
1838                 .modes = &lg_ld070wx3_sl01_mode,
1839                 .num_modes = 1,
1840                 .bpc = 8,
1841                 .size = {
1842                         .width = 94,
1843                         .height = 151,
1844                 },
1845         },
1846         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1847         .format = MIPI_DSI_FMT_RGB888,
1848         .lanes = 4,
1849 };
1850
1851 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1852         .clock = 67000,
1853         .hdisplay = 720,
1854         .hsync_start = 720 + 12,
1855         .hsync_end = 720 + 12 + 4,
1856         .htotal = 720 + 12 + 4 + 112,
1857         .vdisplay = 1280,
1858         .vsync_start = 1280 + 8,
1859         .vsync_end = 1280 + 8 + 4,
1860         .vtotal = 1280 + 8 + 4 + 12,
1861         .vrefresh = 60,
1862 };
1863
1864 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1865         .desc = {
1866                 .modes = &lg_lh500wx1_sd03_mode,
1867                 .num_modes = 1,
1868                 .bpc = 8,
1869                 .size = {
1870                         .width = 62,
1871                         .height = 110,
1872                 },
1873         },
1874         .flags = MIPI_DSI_MODE_VIDEO,
1875         .format = MIPI_DSI_FMT_RGB888,
1876         .lanes = 4,
1877 };
1878
1879 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1880         .clock = 157200,
1881         .hdisplay = 1920,
1882         .hsync_start = 1920 + 154,
1883         .hsync_end = 1920 + 154 + 16,
1884         .htotal = 1920 + 154 + 16 + 32,
1885         .vdisplay = 1200,
1886         .vsync_start = 1200 + 17,
1887         .vsync_end = 1200 + 17 + 2,
1888         .vtotal = 1200 + 17 + 2 + 16,
1889         .vrefresh = 60,
1890 };
1891
1892 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1893         .desc = {
1894                 .modes = &panasonic_vvx10f004b00_mode,
1895                 .num_modes = 1,
1896                 .bpc = 8,
1897                 .size = {
1898                         .width = 217,
1899                         .height = 136,
1900                 },
1901         },
1902         .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1903                  MIPI_DSI_CLOCK_NON_CONTINUOUS,
1904         .format = MIPI_DSI_FMT_RGB888,
1905         .lanes = 4,
1906 };
1907
1908
1909 static const struct of_device_id dsi_of_match[] = {
1910         {
1911                 .compatible = "simple-panel-dsi",
1912                 .data = NULL
1913         }, {
1914                 .compatible = "auo,b080uan01",
1915                 .data = &auo_b080uan01
1916         }, {
1917                 .compatible = "boe,tv080wum-nl0",
1918                 .data = &boe_tv080wum_nl0
1919         }, {
1920                 .compatible = "lg,ld070wx3-sl01",
1921                 .data = &lg_ld070wx3_sl01
1922         }, {
1923                 .compatible = "lg,lh500wx1-sd03",
1924                 .data = &lg_lh500wx1_sd03
1925         }, {
1926                 .compatible = "panasonic,vvx10f004b00",
1927                 .data = &panasonic_vvx10f004b00
1928         }, {
1929                 /* sentinel */
1930         }
1931 };
1932 MODULE_DEVICE_TABLE(of, dsi_of_match);
1933
1934 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1935 {
1936         struct panel_simple *panel;
1937         const struct panel_desc_dsi *desc;
1938         const struct of_device_id *id;
1939         const struct panel_desc *pdesc;
1940         const void *data;
1941         int len;
1942         u32 val;
1943         int err;
1944
1945         id = of_match_node(dsi_of_match, dsi->dev.of_node);
1946         if (!id)
1947                 return -ENODEV;
1948
1949         desc = id->data;
1950
1951         if (desc) {
1952                 dsi->mode_flags = desc->flags;
1953                 dsi->format = desc->format;
1954                 dsi->lanes = desc->lanes;
1955                 pdesc = &desc->desc;
1956         } else {
1957                 pdesc = NULL;
1958         }
1959
1960         err = panel_simple_probe(&dsi->dev, pdesc);
1961         if (err < 0)
1962                 return err;
1963
1964         panel = dev_get_drvdata(&dsi->dev);
1965         panel->dsi = dsi;
1966
1967         if (!of_property_read_u32(dsi->dev.of_node, "dsi,flags", &val))
1968                 dsi->mode_flags = val;
1969
1970         if (!of_property_read_u32(dsi->dev.of_node, "dsi,format", &val))
1971                 dsi->format = val;
1972
1973         if (!of_property_read_u32(dsi->dev.of_node, "dsi,lanes", &val))
1974                 dsi->lanes = val;
1975
1976         data = of_get_property(dsi->dev.of_node, "panel-init-sequence", &len);
1977         if (data) {
1978                 panel->on_cmds = devm_kzalloc(&dsi->dev,
1979                                               sizeof(*panel->on_cmds),
1980                                               GFP_KERNEL);
1981                 if (!panel->on_cmds)
1982                         return -ENOMEM;
1983
1984                 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
1985                                                       panel->on_cmds);
1986                 if (err) {
1987                         dev_err(&dsi->dev, "failed to parse panel init sequence\n");
1988                         return err;
1989                 }
1990         }
1991
1992         data = of_get_property(dsi->dev.of_node, "panel-exit-sequence", &len);
1993         if (data) {
1994                 panel->off_cmds = devm_kzalloc(&dsi->dev,
1995                                                sizeof(*panel->off_cmds),
1996                                                GFP_KERNEL);
1997                 if (!panel->off_cmds)
1998                         return -ENOMEM;
1999
2000                 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
2001                                                       panel->off_cmds);
2002                 if (err) {
2003                         dev_err(&dsi->dev, "failed to parse panel exit sequence\n");
2004                         return err;
2005                 }
2006         }
2007
2008         return mipi_dsi_attach(dsi);
2009 }
2010
2011 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
2012 {
2013         int err;
2014
2015         err = mipi_dsi_detach(dsi);
2016         if (err < 0)
2017                 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
2018
2019         return panel_simple_remove(&dsi->dev);
2020 }
2021
2022 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
2023 {
2024         panel_simple_shutdown(&dsi->dev);
2025 }
2026
2027 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2028         .driver = {
2029                 .name = "panel-simple-dsi",
2030                 .of_match_table = dsi_of_match,
2031         },
2032         .probe = panel_simple_dsi_probe,
2033         .remove = panel_simple_dsi_remove,
2034         .shutdown = panel_simple_dsi_shutdown,
2035 };
2036
2037 static int __init panel_simple_init(void)
2038 {
2039         int err;
2040
2041         err = platform_driver_register(&panel_simple_platform_driver);
2042         if (err < 0)
2043                 return err;
2044
2045         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2046                 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2047                 if (err < 0)
2048                         return err;
2049         }
2050
2051         return 0;
2052 }
2053 module_init(panel_simple_init);
2054
2055 static void __exit panel_simple_exit(void)
2056 {
2057         if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2058                 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2059
2060         platform_driver_unregister(&panel_simple_platform_driver);
2061 }
2062 module_exit(panel_simple_exit);
2063
2064 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2065 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2066 MODULE_LICENSE("GPL and additional rights");