2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
36 #include <video/display_timing.h>
37 #include <video/videomode.h>
40 const struct drm_display_mode *modes;
41 unsigned int num_modes;
42 const struct display_timing *timings;
43 unsigned int num_timings;
53 * @prepare: the time (in milliseconds) that it takes for the panel to
54 * become ready and start receiving video data
55 * @enable: the time (in milliseconds) that it takes for the panel to
56 * display the first valid frame after starting to receive
58 * @disable: the time (in milliseconds) that it takes for the panel to
59 * turn the display off (no content is visible)
60 * @unprepare: the time (in milliseconds) that it takes for the panel
61 * to power itself down completely
67 unsigned int unprepare;
74 struct drm_panel base;
78 const struct panel_desc *desc;
80 struct backlight_device *backlight;
81 struct regulator *supply;
82 struct i2c_adapter *ddc;
84 struct gpio_desc *enable_gpio;
87 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
89 return container_of(panel, struct panel_simple, base);
92 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
94 struct drm_connector *connector = panel->base.connector;
95 struct drm_device *drm = panel->base.drm;
96 struct drm_display_mode *mode;
97 unsigned int i, num = 0;
102 for (i = 0; i < panel->desc->num_timings; i++) {
103 const struct display_timing *dt = &panel->desc->timings[i];
106 videomode_from_timing(dt, &vm);
107 mode = drm_mode_create(drm);
109 dev_err(drm->dev, "failed to add mode %ux%u\n",
110 dt->hactive.typ, dt->vactive.typ);
114 drm_display_mode_from_videomode(&vm, mode);
115 drm_mode_set_name(mode);
117 drm_mode_probed_add(connector, mode);
121 for (i = 0; i < panel->desc->num_modes; i++) {
122 const struct drm_display_mode *m = &panel->desc->modes[i];
124 mode = drm_mode_duplicate(drm, m);
126 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
127 m->hdisplay, m->vdisplay, m->vrefresh);
131 drm_mode_set_name(mode);
133 drm_mode_probed_add(connector, mode);
137 connector->display_info.bpc = panel->desc->bpc;
138 connector->display_info.width_mm = panel->desc->size.width;
139 connector->display_info.height_mm = panel->desc->size.height;
140 if (panel->desc->bus_format)
141 drm_display_info_set_bus_formats(&connector->display_info,
142 &panel->desc->bus_format, 1);
147 static int panel_simple_disable(struct drm_panel *panel)
149 struct panel_simple *p = to_panel_simple(panel);
155 p->backlight->props.power = FB_BLANK_POWERDOWN;
156 backlight_update_status(p->backlight);
159 if (p->desc->delay.disable)
160 msleep(p->desc->delay.disable);
167 static int panel_simple_unprepare(struct drm_panel *panel)
169 struct panel_simple *p = to_panel_simple(panel);
175 gpiod_set_value_cansleep(p->enable_gpio, 0);
177 regulator_disable(p->supply);
179 if (p->desc->delay.unprepare)
180 msleep(p->desc->delay.unprepare);
187 static int panel_simple_prepare(struct drm_panel *panel)
189 struct panel_simple *p = to_panel_simple(panel);
195 err = regulator_enable(p->supply);
197 dev_err(panel->dev, "failed to enable supply: %d\n", err);
202 gpiod_set_value_cansleep(p->enable_gpio, 1);
204 if (p->desc->delay.prepare)
205 msleep(p->desc->delay.prepare);
212 static int panel_simple_enable(struct drm_panel *panel)
214 struct panel_simple *p = to_panel_simple(panel);
219 if (p->desc->delay.enable)
220 msleep(p->desc->delay.enable);
223 p->backlight->props.power = FB_BLANK_UNBLANK;
224 backlight_update_status(p->backlight);
232 static int panel_simple_get_modes(struct drm_panel *panel)
234 struct panel_simple *p = to_panel_simple(panel);
237 /* probe EDID if a DDC bus is available */
239 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
240 drm_mode_connector_update_edid_property(panel->connector, edid);
242 num += drm_add_edid_modes(panel->connector, edid);
247 /* add hard-coded panel modes */
248 num += panel_simple_get_fixed_modes(p);
253 static int panel_simple_get_timings(struct drm_panel *panel,
254 unsigned int num_timings,
255 struct display_timing *timings)
257 struct panel_simple *p = to_panel_simple(panel);
260 if (p->desc->num_timings < num_timings)
261 num_timings = p->desc->num_timings;
264 for (i = 0; i < num_timings; i++)
265 timings[i] = p->desc->timings[i];
267 return p->desc->num_timings;
270 static const struct drm_panel_funcs panel_simple_funcs = {
271 .disable = panel_simple_disable,
272 .unprepare = panel_simple_unprepare,
273 .prepare = panel_simple_prepare,
274 .enable = panel_simple_enable,
275 .get_modes = panel_simple_get_modes,
276 .get_timings = panel_simple_get_timings,
279 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
281 struct device_node *backlight, *ddc;
282 struct panel_simple *panel;
285 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
289 panel->enabled = false;
290 panel->prepared = false;
293 panel->supply = devm_regulator_get(dev, "power");
294 if (IS_ERR(panel->supply))
295 return PTR_ERR(panel->supply);
297 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
299 if (IS_ERR(panel->enable_gpio)) {
300 err = PTR_ERR(panel->enable_gpio);
301 dev_err(dev, "failed to request GPIO: %d\n", err);
305 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
307 panel->backlight = of_find_backlight_by_node(backlight);
308 of_node_put(backlight);
310 if (!panel->backlight)
311 return -EPROBE_DEFER;
314 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
316 panel->ddc = of_find_i2c_adapter_by_node(ddc);
325 drm_panel_init(&panel->base);
326 panel->base.dev = dev;
327 panel->base.funcs = &panel_simple_funcs;
329 err = drm_panel_add(&panel->base);
333 dev_set_drvdata(dev, panel);
339 put_device(&panel->ddc->dev);
341 if (panel->backlight)
342 put_device(&panel->backlight->dev);
347 static int panel_simple_remove(struct device *dev)
349 struct panel_simple *panel = dev_get_drvdata(dev);
351 drm_panel_detach(&panel->base);
352 drm_panel_remove(&panel->base);
354 panel_simple_disable(&panel->base);
357 put_device(&panel->ddc->dev);
359 if (panel->backlight)
360 put_device(&panel->backlight->dev);
365 static void panel_simple_shutdown(struct device *dev)
367 struct panel_simple *panel = dev_get_drvdata(dev);
369 panel_simple_disable(&panel->base);
372 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
375 .hsync_start = 800 + 0,
376 .hsync_end = 800 + 0 + 255,
377 .htotal = 800 + 0 + 255 + 0,
379 .vsync_start = 480 + 2,
380 .vsync_end = 480 + 2 + 45,
381 .vtotal = 480 + 2 + 45 + 0,
383 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
386 static const struct panel_desc ampire_am800480r3tmqwa1h = {
387 .modes = &ire_am800480r3tmqwa1h_mode,
394 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
397 static const struct drm_display_mode auo_b101aw03_mode = {
400 .hsync_start = 1024 + 156,
401 .hsync_end = 1024 + 156 + 8,
402 .htotal = 1024 + 156 + 8 + 156,
404 .vsync_start = 600 + 16,
405 .vsync_end = 600 + 16 + 6,
406 .vtotal = 600 + 16 + 6 + 16,
410 static const struct panel_desc auo_b101aw03 = {
411 .modes = &auo_b101aw03_mode,
420 static const struct drm_display_mode auo_b101ean01_mode = {
423 .hsync_start = 1280 + 119,
424 .hsync_end = 1280 + 119 + 32,
425 .htotal = 1280 + 119 + 32 + 21,
427 .vsync_start = 800 + 4,
428 .vsync_end = 800 + 4 + 20,
429 .vtotal = 800 + 4 + 20 + 8,
433 static const struct panel_desc auo_b101ean01 = {
434 .modes = &auo_b101ean01_mode,
443 static const struct drm_display_mode auo_b101ew05_mode = {
446 .hsync_start = 1280 + 18,
447 .hsync_end = 1280 + 18 + 10,
448 .htotal = 1280 + 18 + 10 + 100,
450 .vsync_start = 800 + 6,
451 .vsync_end = 800 + 6 + 2,
452 .vtotal = 800 + 6 + 2 + 8,
456 static const struct panel_desc auo_b101ew05 = {
457 .modes = &auo_b101ew05_mode,
466 static const struct drm_display_mode auo_b101xtn01_mode = {
469 .hsync_start = 1366 + 20,
470 .hsync_end = 1366 + 20 + 70,
471 .htotal = 1366 + 20 + 70,
473 .vsync_start = 768 + 14,
474 .vsync_end = 768 + 14 + 42,
475 .vtotal = 768 + 14 + 42,
477 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
480 static const struct panel_desc auo_b101xtn01 = {
481 .modes = &auo_b101xtn01_mode,
490 static const struct drm_display_mode auo_b116xw03_mode = {
493 .hsync_start = 1366 + 40,
494 .hsync_end = 1366 + 40 + 40,
495 .htotal = 1366 + 40 + 40 + 32,
497 .vsync_start = 768 + 10,
498 .vsync_end = 768 + 10 + 12,
499 .vtotal = 768 + 10 + 12 + 6,
503 static const struct panel_desc auo_b116xw03 = {
504 .modes = &auo_b116xw03_mode,
513 static const struct drm_display_mode auo_b133xtn01_mode = {
516 .hsync_start = 1366 + 48,
517 .hsync_end = 1366 + 48 + 32,
518 .htotal = 1366 + 48 + 32 + 20,
520 .vsync_start = 768 + 3,
521 .vsync_end = 768 + 3 + 6,
522 .vtotal = 768 + 3 + 6 + 13,
526 static const struct panel_desc auo_b133xtn01 = {
527 .modes = &auo_b133xtn01_mode,
536 static const struct drm_display_mode auo_b133htn01_mode = {
539 .hsync_start = 1920 + 172,
540 .hsync_end = 1920 + 172 + 80,
541 .htotal = 1920 + 172 + 80 + 60,
543 .vsync_start = 1080 + 25,
544 .vsync_end = 1080 + 25 + 10,
545 .vtotal = 1080 + 25 + 10 + 10,
549 static const struct panel_desc auo_b133htn01 = {
550 .modes = &auo_b133htn01_mode,
564 static const struct drm_display_mode avic_tm070ddh03_mode = {
567 .hsync_start = 1024 + 160,
568 .hsync_end = 1024 + 160 + 4,
569 .htotal = 1024 + 160 + 4 + 156,
571 .vsync_start = 600 + 17,
572 .vsync_end = 600 + 17 + 1,
573 .vtotal = 600 + 17 + 1 + 17,
577 static const struct panel_desc avic_tm070ddh03 = {
578 .modes = &avic_tm070ddh03_mode,
592 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
595 .hsync_start = 800 + 24,
596 .hsync_end = 800 + 24 + 16,
597 .htotal = 800 + 24 + 16 + 24,
599 .vsync_start = 1280 + 2,
600 .vsync_end = 1280 + 2 + 2,
601 .vtotal = 1280 + 2 + 2 + 4,
605 static const struct panel_desc chunghwa_claa070wp03xg = {
606 .modes = &chunghwa_claa070wp03xg_mode,
615 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
618 .hsync_start = 1366 + 58,
619 .hsync_end = 1366 + 58 + 58,
620 .htotal = 1366 + 58 + 58 + 58,
622 .vsync_start = 768 + 4,
623 .vsync_end = 768 + 4 + 4,
624 .vtotal = 768 + 4 + 4 + 4,
628 static const struct panel_desc chunghwa_claa101wa01a = {
629 .modes = &chunghwa_claa101wa01a_mode,
638 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
641 .hsync_start = 1366 + 48,
642 .hsync_end = 1366 + 48 + 32,
643 .htotal = 1366 + 48 + 32 + 20,
645 .vsync_start = 768 + 16,
646 .vsync_end = 768 + 16 + 8,
647 .vtotal = 768 + 16 + 8 + 16,
651 static const struct panel_desc chunghwa_claa101wb01 = {
652 .modes = &chunghwa_claa101wb01_mode,
661 static const struct drm_display_mode edt_et057090dhu_mode = {
664 .hsync_start = 640 + 16,
665 .hsync_end = 640 + 16 + 30,
666 .htotal = 640 + 16 + 30 + 114,
668 .vsync_start = 480 + 10,
669 .vsync_end = 480 + 10 + 3,
670 .vtotal = 480 + 10 + 3 + 32,
672 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
675 static const struct panel_desc edt_et057090dhu = {
676 .modes = &edt_et057090dhu_mode,
685 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
688 .hsync_start = 800 + 40,
689 .hsync_end = 800 + 40 + 128,
690 .htotal = 800 + 40 + 128 + 88,
692 .vsync_start = 480 + 10,
693 .vsync_end = 480 + 10 + 2,
694 .vtotal = 480 + 10 + 2 + 33,
696 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
699 static const struct panel_desc edt_etm0700g0dh6 = {
700 .modes = &edt_etm0700g0dh6_mode,
709 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
712 .hsync_start = 800 + 168,
713 .hsync_end = 800 + 168 + 64,
714 .htotal = 800 + 168 + 64 + 88,
716 .vsync_start = 480 + 37,
717 .vsync_end = 480 + 37 + 2,
718 .vtotal = 480 + 37 + 2 + 8,
722 static const struct panel_desc foxlink_fl500wvr00_a0t = {
723 .modes = &foxlink_fl500wvr00_a0t_mode,
730 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
733 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
736 .hsync_start = 480 + 5,
737 .hsync_end = 480 + 5 + 1,
738 .htotal = 480 + 5 + 1 + 40,
740 .vsync_start = 272 + 8,
741 .vsync_end = 272 + 8 + 1,
742 .vtotal = 272 + 8 + 1 + 8,
746 static const struct panel_desc giantplus_gpg482739qs5 = {
747 .modes = &giantplus_gpg482739qs5_mode,
754 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
757 static const struct display_timing hannstar_hsd070pww1_timing = {
758 .pixelclock = { 64300000, 71100000, 82000000 },
759 .hactive = { 1280, 1280, 1280 },
760 .hfront_porch = { 1, 1, 10 },
761 .hback_porch = { 1, 1, 10 },
763 * According to the data sheet, the minimum horizontal blanking interval
764 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
765 * minimum working horizontal blanking interval to be 60 clocks.
767 .hsync_len = { 58, 158, 661 },
768 .vactive = { 800, 800, 800 },
769 .vfront_porch = { 1, 1, 10 },
770 .vback_porch = { 1, 1, 10 },
771 .vsync_len = { 1, 21, 203 },
772 .flags = DISPLAY_FLAGS_DE_HIGH,
775 static const struct panel_desc hannstar_hsd070pww1 = {
776 .timings = &hannstar_hsd070pww1_timing,
783 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
786 static const struct display_timing hannstar_hsd100pxn1_timing = {
787 .pixelclock = { 55000000, 65000000, 75000000 },
788 .hactive = { 1024, 1024, 1024 },
789 .hfront_porch = { 40, 40, 40 },
790 .hback_porch = { 220, 220, 220 },
791 .hsync_len = { 20, 60, 100 },
792 .vactive = { 768, 768, 768 },
793 .vfront_porch = { 7, 7, 7 },
794 .vback_porch = { 21, 21, 21 },
795 .vsync_len = { 10, 10, 10 },
796 .flags = DISPLAY_FLAGS_DE_HIGH,
799 static const struct panel_desc hannstar_hsd100pxn1 = {
800 .timings = &hannstar_hsd100pxn1_timing,
807 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
810 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
813 .hsync_start = 800 + 85,
814 .hsync_end = 800 + 85 + 86,
815 .htotal = 800 + 85 + 86 + 85,
817 .vsync_start = 480 + 16,
818 .vsync_end = 480 + 16 + 13,
819 .vtotal = 480 + 16 + 13 + 16,
823 static const struct panel_desc hitachi_tx23d38vm0caa = {
824 .modes = &hitachi_tx23d38vm0caa_mode,
833 static const struct drm_display_mode innolux_at043tn24_mode = {
836 .hsync_start = 480 + 2,
837 .hsync_end = 480 + 2 + 41,
838 .htotal = 480 + 2 + 41 + 2,
840 .vsync_start = 272 + 2,
841 .vsync_end = 272 + 2 + 11,
842 .vtotal = 272 + 2 + 11 + 2,
844 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
847 static const struct panel_desc innolux_at043tn24 = {
848 .modes = &innolux_at043tn24_mode,
855 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
858 static const struct drm_display_mode innolux_g121i1_l01_mode = {
861 .hsync_start = 1280 + 64,
862 .hsync_end = 1280 + 64 + 32,
863 .htotal = 1280 + 64 + 32 + 64,
865 .vsync_start = 800 + 9,
866 .vsync_end = 800 + 9 + 6,
867 .vtotal = 800 + 9 + 6 + 9,
871 static const struct panel_desc innolux_g121i1_l01 = {
872 .modes = &innolux_g121i1_l01_mode,
881 static const struct drm_display_mode innolux_n116bge_mode = {
884 .hsync_start = 1366 + 136,
885 .hsync_end = 1366 + 136 + 30,
886 .htotal = 1366 + 136 + 30 + 60,
888 .vsync_start = 768 + 8,
889 .vsync_end = 768 + 8 + 12,
890 .vtotal = 768 + 8 + 12 + 12,
892 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
895 static const struct panel_desc innolux_n116bge = {
896 .modes = &innolux_n116bge_mode,
905 static const struct drm_display_mode innolux_n156bge_l21_mode = {
908 .hsync_start = 1366 + 16,
909 .hsync_end = 1366 + 16 + 34,
910 .htotal = 1366 + 16 + 34 + 50,
912 .vsync_start = 768 + 2,
913 .vsync_end = 768 + 2 + 6,
914 .vtotal = 768 + 2 + 6 + 12,
918 static const struct panel_desc innolux_n156bge_l21 = {
919 .modes = &innolux_n156bge_l21_mode,
928 static const struct drm_display_mode innolux_zj070na_01p_mode = {
931 .hsync_start = 1024 + 128,
932 .hsync_end = 1024 + 128 + 64,
933 .htotal = 1024 + 128 + 64 + 128,
935 .vsync_start = 600 + 16,
936 .vsync_end = 600 + 16 + 4,
937 .vtotal = 600 + 16 + 4 + 16,
941 static const struct panel_desc innolux_zj070na_01p = {
942 .modes = &innolux_zj070na_01p_mode,
951 static const struct drm_display_mode lg_lb070wv8_mode = {
954 .hsync_start = 800 + 88,
955 .hsync_end = 800 + 88 + 80,
956 .htotal = 800 + 88 + 80 + 88,
958 .vsync_start = 480 + 10,
959 .vsync_end = 480 + 10 + 25,
960 .vtotal = 480 + 10 + 25 + 10,
964 static const struct panel_desc lg_lb070wv8 = {
965 .modes = &lg_lb070wv8_mode,
972 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
975 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
978 .hsync_start = 1536 + 12,
979 .hsync_end = 1536 + 12 + 16,
980 .htotal = 1536 + 12 + 16 + 48,
982 .vsync_start = 2048 + 8,
983 .vsync_end = 2048 + 8 + 4,
984 .vtotal = 2048 + 8 + 4 + 8,
986 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
989 static const struct panel_desc lg_lp079qx1_sp0v = {
990 .modes = &lg_lp079qx1_sp0v_mode,
998 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1001 .hsync_start = 2048 + 150,
1002 .hsync_end = 2048 + 150 + 5,
1003 .htotal = 2048 + 150 + 5 + 5,
1005 .vsync_start = 1536 + 3,
1006 .vsync_end = 1536 + 3 + 1,
1007 .vtotal = 1536 + 3 + 1 + 9,
1011 static const struct panel_desc lg_lp097qx1_spa1 = {
1012 .modes = &lg_lp097qx1_spa1_mode,
1020 static const struct drm_display_mode lg_lp129qe_mode = {
1023 .hsync_start = 2560 + 48,
1024 .hsync_end = 2560 + 48 + 32,
1025 .htotal = 2560 + 48 + 32 + 80,
1027 .vsync_start = 1700 + 3,
1028 .vsync_end = 1700 + 3 + 10,
1029 .vtotal = 1700 + 3 + 10 + 36,
1033 static const struct panel_desc lg_lp129qe = {
1034 .modes = &lg_lp129qe_mode,
1043 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1046 .hsync_start = 480 + 2,
1047 .hsync_end = 480 + 2 + 41,
1048 .htotal = 480 + 2 + 41 + 2,
1050 .vsync_start = 272 + 2,
1051 .vsync_end = 272 + 2 + 4,
1052 .vtotal = 272 + 2 + 4 + 2,
1056 static const struct panel_desc nec_nl4827hc19_05b = {
1057 .modes = &nec_nl4827hc19_05b_mode,
1064 .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1067 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1068 .pixelclock = { 30000000, 30000000, 40000000 },
1069 .hactive = { 800, 800, 800 },
1070 .hfront_porch = { 40, 40, 40 },
1071 .hback_porch = { 40, 40, 40 },
1072 .hsync_len = { 1, 48, 48 },
1073 .vactive = { 480, 480, 480 },
1074 .vfront_porch = { 13, 13, 13 },
1075 .vback_porch = { 29, 29, 29 },
1076 .vsync_len = { 3, 3, 3 },
1077 .flags = DISPLAY_FLAGS_DE_HIGH,
1080 static const struct panel_desc okaya_rs800480t_7x0gp = {
1081 .timings = &okaya_rs800480t_7x0gp_timing,
1094 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1097 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1100 .hsync_start = 480 + 10,
1101 .hsync_end = 480 + 10 + 10,
1102 .htotal = 480 + 10 + 10 + 15,
1104 .vsync_start = 800 + 3,
1105 .vsync_end = 800 + 3 + 3,
1106 .vtotal = 800 + 3 + 3 + 3,
1110 static const struct panel_desc ortustech_com43h4m85ulc = {
1111 .modes = &ortustech_com43h4m85ulc_mode,
1118 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1121 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1124 .hsync_start = 2560 + 48,
1125 .hsync_end = 2560 + 48 + 32,
1126 .htotal = 2560 + 48 + 32 + 80,
1128 .vsync_start = 1600 + 2,
1129 .vsync_end = 1600 + 2 + 5,
1130 .vtotal = 1600 + 2 + 5 + 57,
1134 static const struct panel_desc samsung_lsn122dl01_c01 = {
1135 .modes = &samsung_lsn122dl01_c01_mode,
1143 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1146 .hsync_start = 1024 + 24,
1147 .hsync_end = 1024 + 24 + 136,
1148 .htotal = 1024 + 24 + 136 + 160,
1150 .vsync_start = 600 + 3,
1151 .vsync_end = 600 + 3 + 6,
1152 .vtotal = 600 + 3 + 6 + 61,
1156 static const struct panel_desc samsung_ltn101nt05 = {
1157 .modes = &samsung_ltn101nt05_mode,
1166 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1169 .hsync_start = 1366 + 64,
1170 .hsync_end = 1366 + 64 + 48,
1171 .htotal = 1366 + 64 + 48 + 128,
1173 .vsync_start = 768 + 2,
1174 .vsync_end = 768 + 2 + 5,
1175 .vtotal = 768 + 2 + 5 + 17,
1179 static const struct panel_desc samsung_ltn140at29_301 = {
1180 .modes = &samsung_ltn140at29_301_mode,
1189 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1192 .hsync_start = 800 + 1,
1193 .hsync_end = 800 + 1 + 64,
1194 .htotal = 800 + 1 + 64 + 64,
1196 .vsync_start = 480 + 1,
1197 .vsync_end = 480 + 1 + 23,
1198 .vtotal = 480 + 1 + 23 + 22,
1202 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1203 .modes = &shelly_sca07010_bfn_lnn_mode,
1209 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1212 static const struct of_device_id platform_of_match[] = {
1214 .compatible = "ampire,am800480r3tmqwa1h",
1215 .data = &ire_am800480r3tmqwa1h,
1217 .compatible = "auo,b101aw03",
1218 .data = &auo_b101aw03,
1220 .compatible = "auo,b101ean01",
1221 .data = &auo_b101ean01,
1223 .compatible = "auo,b101ew05",
1224 .data = &auo_b101ew05,
1226 .compatible = "auo,b101xtn01",
1227 .data = &auo_b101xtn01,
1229 .compatible = "auo,b116xw03",
1230 .data = &auo_b116xw03,
1232 .compatible = "auo,b133htn01",
1233 .data = &auo_b133htn01,
1235 .compatible = "auo,b133xtn01",
1236 .data = &auo_b133xtn01,
1238 .compatible = "avic,tm070ddh03",
1239 .data = &avic_tm070ddh03,
1241 .compatible = "chunghwa,claa070wp03xg",
1242 .data = &chunghwa_claa070wp03xg,
1244 .compatible = "chunghwa,claa101wa01a",
1245 .data = &chunghwa_claa101wa01a
1247 .compatible = "chunghwa,claa101wb01",
1248 .data = &chunghwa_claa101wb01
1250 .compatible = "edt,et057090dhu",
1251 .data = &edt_et057090dhu,
1253 .compatible = "edt,et070080dh6",
1254 .data = &edt_etm0700g0dh6,
1256 .compatible = "edt,etm0700g0dh6",
1257 .data = &edt_etm0700g0dh6,
1259 .compatible = "foxlink,fl500wvr00-a0t",
1260 .data = &foxlink_fl500wvr00_a0t,
1262 .compatible = "giantplus,gpg482739qs5",
1263 .data = &giantplus_gpg482739qs5
1265 .compatible = "hannstar,hsd070pww1",
1266 .data = &hannstar_hsd070pww1,
1268 .compatible = "hannstar,hsd100pxn1",
1269 .data = &hannstar_hsd100pxn1,
1271 .compatible = "hit,tx23d38vm0caa",
1272 .data = &hitachi_tx23d38vm0caa
1274 .compatible = "innolux,at043tn24",
1275 .data = &innolux_at043tn24,
1277 .compatible ="innolux,g121i1-l01",
1278 .data = &innolux_g121i1_l01
1280 .compatible = "innolux,n116bge",
1281 .data = &innolux_n116bge,
1283 .compatible = "innolux,n156bge-l21",
1284 .data = &innolux_n156bge_l21,
1286 .compatible = "innolux,zj070na-01p",
1287 .data = &innolux_zj070na_01p,
1289 .compatible = "lg,lb070wv8",
1290 .data = &lg_lb070wv8,
1292 .compatible = "lg,lp079qx1-sp0v",
1293 .data = &lg_lp079qx1_sp0v,
1295 .compatible = "lg,lp097qx1-spa1",
1296 .data = &lg_lp097qx1_spa1,
1298 .compatible = "lg,lp129qe",
1299 .data = &lg_lp129qe,
1301 .compatible = "nec,nl4827hc19-05b",
1302 .data = &nec_nl4827hc19_05b,
1304 .compatible = "okaya,rs800480t-7x0gp",
1305 .data = &okaya_rs800480t_7x0gp,
1307 .compatible = "ortustech,com43h4m85ulc",
1308 .data = &ortustech_com43h4m85ulc,
1310 .compatible = "samsung,lsn122dl01-c01",
1311 .data = &samsung_lsn122dl01_c01,
1313 .compatible = "samsung,ltn101nt05",
1314 .data = &samsung_ltn101nt05,
1316 .compatible = "samsung,ltn140at29-301",
1317 .data = &samsung_ltn140at29_301,
1319 .compatible = "shelly,sca07010-bfn-lnn",
1320 .data = &shelly_sca07010_bfn_lnn,
1325 MODULE_DEVICE_TABLE(of, platform_of_match);
1327 static int panel_simple_platform_probe(struct platform_device *pdev)
1329 const struct of_device_id *id;
1331 id = of_match_node(platform_of_match, pdev->dev.of_node);
1335 return panel_simple_probe(&pdev->dev, id->data);
1338 static int panel_simple_platform_remove(struct platform_device *pdev)
1340 return panel_simple_remove(&pdev->dev);
1343 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1345 panel_simple_shutdown(&pdev->dev);
1348 static struct platform_driver panel_simple_platform_driver = {
1350 .name = "panel-simple",
1351 .of_match_table = platform_of_match,
1353 .probe = panel_simple_platform_probe,
1354 .remove = panel_simple_platform_remove,
1355 .shutdown = panel_simple_platform_shutdown,
1358 struct panel_desc_dsi {
1359 struct panel_desc desc;
1361 unsigned long flags;
1362 enum mipi_dsi_pixel_format format;
1366 static const struct drm_display_mode auo_b080uan01_mode = {
1369 .hsync_start = 1200 + 62,
1370 .hsync_end = 1200 + 62 + 4,
1371 .htotal = 1200 + 62 + 4 + 62,
1373 .vsync_start = 1920 + 9,
1374 .vsync_end = 1920 + 9 + 2,
1375 .vtotal = 1920 + 9 + 2 + 8,
1379 static const struct panel_desc_dsi auo_b080uan01 = {
1381 .modes = &auo_b080uan01_mode,
1389 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1390 .format = MIPI_DSI_FMT_RGB888,
1394 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1397 .hsync_start = 1200 + 120,
1398 .hsync_end = 1200 + 120 + 20,
1399 .htotal = 1200 + 120 + 20 + 21,
1401 .vsync_start = 1920 + 21,
1402 .vsync_end = 1920 + 21 + 3,
1403 .vtotal = 1920 + 21 + 3 + 18,
1405 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1408 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1410 .modes = &boe_tv080wum_nl0_mode,
1417 .flags = MIPI_DSI_MODE_VIDEO |
1418 MIPI_DSI_MODE_VIDEO_BURST |
1419 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1420 .format = MIPI_DSI_FMT_RGB888,
1424 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1427 .hsync_start = 800 + 32,
1428 .hsync_end = 800 + 32 + 1,
1429 .htotal = 800 + 32 + 1 + 57,
1431 .vsync_start = 1280 + 28,
1432 .vsync_end = 1280 + 28 + 1,
1433 .vtotal = 1280 + 28 + 1 + 14,
1437 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1439 .modes = &lg_ld070wx3_sl01_mode,
1447 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1448 .format = MIPI_DSI_FMT_RGB888,
1452 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1455 .hsync_start = 720 + 12,
1456 .hsync_end = 720 + 12 + 4,
1457 .htotal = 720 + 12 + 4 + 112,
1459 .vsync_start = 1280 + 8,
1460 .vsync_end = 1280 + 8 + 4,
1461 .vtotal = 1280 + 8 + 4 + 12,
1465 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1467 .modes = &lg_lh500wx1_sd03_mode,
1475 .flags = MIPI_DSI_MODE_VIDEO,
1476 .format = MIPI_DSI_FMT_RGB888,
1480 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1483 .hsync_start = 1920 + 154,
1484 .hsync_end = 1920 + 154 + 16,
1485 .htotal = 1920 + 154 + 16 + 32,
1487 .vsync_start = 1200 + 17,
1488 .vsync_end = 1200 + 17 + 2,
1489 .vtotal = 1200 + 17 + 2 + 16,
1493 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1495 .modes = &panasonic_vvx10f004b00_mode,
1503 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1504 MIPI_DSI_CLOCK_NON_CONTINUOUS,
1505 .format = MIPI_DSI_FMT_RGB888,
1510 static const struct of_device_id dsi_of_match[] = {
1512 .compatible = "auo,b080uan01",
1513 .data = &auo_b080uan01
1515 .compatible = "boe,tv080wum-nl0",
1516 .data = &boe_tv080wum_nl0
1518 .compatible = "lg,ld070wx3-sl01",
1519 .data = &lg_ld070wx3_sl01
1521 .compatible = "lg,lh500wx1-sd03",
1522 .data = &lg_lh500wx1_sd03
1524 .compatible = "panasonic,vvx10f004b00",
1525 .data = &panasonic_vvx10f004b00
1530 MODULE_DEVICE_TABLE(of, dsi_of_match);
1532 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1534 const struct panel_desc_dsi *desc;
1535 const struct of_device_id *id;
1538 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1544 err = panel_simple_probe(&dsi->dev, &desc->desc);
1548 dsi->mode_flags = desc->flags;
1549 dsi->format = desc->format;
1550 dsi->lanes = desc->lanes;
1552 return mipi_dsi_attach(dsi);
1555 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1559 err = mipi_dsi_detach(dsi);
1561 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1563 return panel_simple_remove(&dsi->dev);
1566 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1568 panel_simple_shutdown(&dsi->dev);
1571 static struct mipi_dsi_driver panel_simple_dsi_driver = {
1573 .name = "panel-simple-dsi",
1574 .of_match_table = dsi_of_match,
1576 .probe = panel_simple_dsi_probe,
1577 .remove = panel_simple_dsi_remove,
1578 .shutdown = panel_simple_dsi_shutdown,
1581 static int __init panel_simple_init(void)
1585 err = platform_driver_register(&panel_simple_platform_driver);
1589 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1590 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
1597 module_init(panel_simple_init);
1599 static void __exit panel_simple_exit(void)
1601 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1602 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
1604 platform_driver_unregister(&panel_simple_platform_driver);
1606 module_exit(panel_simple_exit);
1608 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1609 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
1610 MODULE_LICENSE("GPL and additional rights");