2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/backlight.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/module.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regulator/consumer.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_mipi_dsi.h>
34 #include <drm/drm_panel.h>
36 #include <video/display_timing.h>
37 #include <video/mipi_display.h>
38 #include <video/of_display_timing.h>
39 #include <video/videomode.h>
42 u8 dtype; /* data type */
44 u8 dlen; /* payload len */
48 struct dsi_ctrl_hdr dchdr;
52 struct dsi_panel_cmds {
55 struct dsi_cmd_desc *cmds;
60 const struct drm_display_mode *modes;
61 unsigned int num_modes;
62 const struct display_timing *timings;
63 unsigned int num_timings;
73 * @prepare: the time (in milliseconds) that it takes for the panel to
74 * become ready and start receiving video data
75 * @enable: the time (in milliseconds) that it takes for the panel to
76 * display the first valid frame after starting to receive
78 * @disable: the time (in milliseconds) that it takes for the panel to
79 * turn the display off (no content is visible)
80 * @unprepare: the time (in milliseconds) that it takes for the panel
81 * to power itself down completely
87 unsigned int unprepare;
94 struct drm_panel base;
95 struct mipi_dsi_device *dsi;
100 const struct panel_desc *desc;
102 struct backlight_device *backlight;
103 struct regulator *supply;
104 struct i2c_adapter *ddc;
106 struct gpio_desc *enable_gpio;
107 struct gpio_desc *reset_gpio;
108 unsigned int reset_delay;
110 struct dsi_panel_cmds *on_cmds;
111 struct dsi_panel_cmds *off_cmds;
114 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
116 return container_of(panel, struct panel_simple, base);
119 static void panel_simple_dsi_cmds_cleanup(struct panel_simple *p)
122 kfree(p->on_cmds->buf);
123 kfree(p->on_cmds->cmds);
127 kfree(p->off_cmds->buf);
128 kfree(p->off_cmds->cmds);
132 static int panel_simple_dsi_parse_dcs_cmds(struct device *dev,
133 const u8 *data, int blen,
134 struct dsi_panel_cmds *pcmds)
138 struct dsi_ctrl_hdr *dchdr;
144 buf = kmemdup(data, blen, GFP_KERNEL);
148 /* scan dcs commands */
152 while (len > sizeof(*dchdr)) {
153 dchdr = (struct dsi_ctrl_hdr *)bp;
155 if (dchdr->dlen > len) {
156 dev_err(dev, "%s: error, len=%d", __func__,
161 bp += sizeof(*dchdr);
162 len -= sizeof(*dchdr);
169 dev_err(dev, "%s: dcs_cmd=%x len=%d error!",
170 __func__, buf[0], blen);
175 pcmds->cmds = kcalloc(cnt, sizeof(struct dsi_cmd_desc), GFP_KERNEL);
181 pcmds->cmd_cnt = cnt;
187 for (i = 0; i < cnt; i++) {
188 dchdr = (struct dsi_ctrl_hdr *)bp;
189 len -= sizeof(*dchdr);
190 bp += sizeof(*dchdr);
191 pcmds->cmds[i].dchdr = *dchdr;
192 pcmds->cmds[i].payload = bp;
197 dev_info(dev, "%s: dcs_cmd=%x len=%d, cmd_cnt=%d\n", __func__,
198 pcmds->buf[0], pcmds->blen, pcmds->cmd_cnt);
202 static int panel_simple_dsi_send_cmds(struct panel_simple *panel,
203 struct dsi_panel_cmds *cmds)
205 struct mipi_dsi_device *dsi = panel->dsi;
211 for (i = 0; i < cmds->cmd_cnt; i++) {
212 struct dsi_cmd_desc *cmd = &cmds->cmds[i];
214 switch (cmd->dchdr.dtype) {
215 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
216 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
217 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
218 case MIPI_DSI_GENERIC_LONG_WRITE:
219 err = mipi_dsi_generic_write(dsi, cmd->payload,
222 case MIPI_DSI_DCS_SHORT_WRITE:
223 case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
224 case MIPI_DSI_DCS_LONG_WRITE:
225 err = mipi_dsi_dcs_write_buffer(dsi, cmd->payload,
233 dev_err(panel->dev, "failed to write dcs cmd: %d\n",
237 msleep(cmd->dchdr.wait);
243 static int panel_simple_get_fixed_modes(struct panel_simple *panel)
245 struct drm_connector *connector = panel->base.connector;
246 struct drm_device *drm = panel->base.drm;
247 struct drm_display_mode *mode;
248 unsigned int i, num = 0;
253 for (i = 0; i < panel->desc->num_timings; i++) {
254 const struct display_timing *dt = &panel->desc->timings[i];
257 videomode_from_timing(dt, &vm);
258 mode = drm_mode_create(drm);
260 dev_err(drm->dev, "failed to add mode %ux%u\n",
261 dt->hactive.typ, dt->vactive.typ);
265 drm_display_mode_from_videomode(&vm, mode);
266 drm_mode_set_name(mode);
268 drm_mode_probed_add(connector, mode);
272 for (i = 0; i < panel->desc->num_modes; i++) {
273 const struct drm_display_mode *m = &panel->desc->modes[i];
275 mode = drm_mode_duplicate(drm, m);
277 dev_err(drm->dev, "failed to add mode %ux%u@%u\n",
278 m->hdisplay, m->vdisplay, m->vrefresh);
282 drm_mode_set_name(mode);
284 drm_mode_probed_add(connector, mode);
288 connector->display_info.bpc = panel->desc->bpc;
289 connector->display_info.width_mm = panel->desc->size.width;
290 connector->display_info.height_mm = panel->desc->size.height;
291 if (panel->desc->bus_format)
292 drm_display_info_set_bus_formats(&connector->display_info,
293 &panel->desc->bus_format, 1);
298 static int panel_simple_of_get_native_mode(struct panel_simple *panel)
300 struct drm_connector *connector = panel->base.connector;
301 struct drm_device *drm = panel->base.drm;
302 struct drm_display_mode *mode;
303 struct device_node *timings_np;
306 timings_np = of_get_child_by_name(panel->dev->of_node,
309 dev_dbg(panel->dev, "failed to find display-timings node\n");
313 of_node_put(timings_np);
314 mode = drm_mode_create(drm);
318 ret = of_get_drm_display_mode(panel->dev->of_node, mode,
321 dev_dbg(panel->dev, "failed to find dts display timings\n");
322 drm_mode_destroy(drm, mode);
326 drm_mode_set_name(mode);
327 mode->type |= DRM_MODE_TYPE_PREFERRED;
328 drm_mode_probed_add(connector, mode);
333 static int panel_simple_disable(struct drm_panel *panel)
335 struct panel_simple *p = to_panel_simple(panel);
341 p->backlight->props.power = FB_BLANK_POWERDOWN;
342 backlight_update_status(p->backlight);
345 if (p->desc && p->desc->delay.disable)
346 msleep(p->desc->delay.disable);
353 static int panel_simple_unprepare(struct drm_panel *panel)
355 struct panel_simple *p = to_panel_simple(panel);
362 err = panel_simple_dsi_send_cmds(p, p->off_cmds);
364 dev_err(p->dev, "failed to send off cmds\n");
368 gpiod_direction_output(p->reset_gpio, 1);
371 gpiod_direction_output(p->enable_gpio, 0);
373 regulator_disable(p->supply);
375 if (p->desc && p->desc->delay.unprepare)
376 msleep(p->desc->delay.unprepare);
383 static int panel_simple_prepare(struct drm_panel *panel)
385 struct panel_simple *p = to_panel_simple(panel);
391 err = regulator_enable(p->supply);
393 dev_err(panel->dev, "failed to enable supply: %d\n", err);
398 gpiod_direction_output(p->enable_gpio, 1);
400 if (p->desc && p->desc->delay.prepare)
401 msleep(p->desc->delay.prepare);
404 gpiod_direction_output(p->reset_gpio, 1);
407 msleep(p->reset_delay);
410 gpiod_direction_output(p->reset_gpio, 0);
417 static int panel_simple_enable(struct drm_panel *panel)
419 struct panel_simple *p = to_panel_simple(panel);
426 err = panel_simple_dsi_send_cmds(p, p->on_cmds);
428 dev_err(p->dev, "failed to send on cmds\n");
431 if (p->desc && p->desc->delay.enable)
432 msleep(p->desc->delay.enable);
435 p->backlight->props.power = FB_BLANK_UNBLANK;
436 backlight_update_status(p->backlight);
444 static int panel_simple_get_modes(struct drm_panel *panel)
446 struct panel_simple *p = to_panel_simple(panel);
449 /* add device node plane modes */
450 num += panel_simple_of_get_native_mode(p);
452 /* add hard-coded panel modes */
453 num += panel_simple_get_fixed_modes(p);
455 /* probe EDID if a DDC bus is available */
457 struct edid *edid = drm_get_edid(panel->connector, p->ddc);
458 drm_mode_connector_update_edid_property(panel->connector, edid);
460 num += drm_add_edid_modes(panel->connector, edid);
468 static int panel_simple_get_timings(struct drm_panel *panel,
469 unsigned int num_timings,
470 struct display_timing *timings)
472 struct panel_simple *p = to_panel_simple(panel);
478 if (p->desc->num_timings < num_timings)
479 num_timings = p->desc->num_timings;
482 for (i = 0; i < num_timings; i++)
483 timings[i] = p->desc->timings[i];
485 return p->desc->num_timings;
488 static const struct drm_panel_funcs panel_simple_funcs = {
489 .disable = panel_simple_disable,
490 .unprepare = panel_simple_unprepare,
491 .prepare = panel_simple_prepare,
492 .enable = panel_simple_enable,
493 .get_modes = panel_simple_get_modes,
494 .get_timings = panel_simple_get_timings,
497 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
499 struct device_node *backlight, *ddc;
500 struct panel_simple *panel;
501 struct panel_desc *of_desc;
505 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
510 of_desc = devm_kzalloc(dev, sizeof(*of_desc), GFP_KERNEL);
512 of_desc = devm_kmemdup(dev, desc, sizeof(*of_desc), GFP_KERNEL);
514 if (!of_property_read_u32(dev->of_node, "bus-format", &val))
515 of_desc->bus_format = val;
516 if (!of_property_read_u32(dev->of_node, "delay,prepare", &val))
517 of_desc->delay.prepare = val;
518 if (!of_property_read_u32(dev->of_node, "delay,enable", &val))
519 of_desc->delay.enable = val;
520 if (!of_property_read_u32(dev->of_node, "delay,disable", &val))
521 of_desc->delay.disable = val;
522 if (!of_property_read_u32(dev->of_node, "delay,unprepare", &val))
523 of_desc->delay.unprepare = val;
525 panel->enabled = false;
526 panel->prepared = false;
527 panel->desc = of_desc;
530 panel->supply = devm_regulator_get(dev, "power");
531 if (IS_ERR(panel->supply))
532 return PTR_ERR(panel->supply);
534 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable", 0);
535 if (IS_ERR(panel->enable_gpio)) {
536 err = PTR_ERR(panel->enable_gpio);
537 dev_err(dev, "failed to request enable GPIO: %d\n", err);
541 panel->reset_gpio = devm_gpiod_get_optional(dev, "reset", 0);
542 if (IS_ERR(panel->reset_gpio)) {
543 err = PTR_ERR(panel->reset_gpio);
544 dev_err(dev, "failed to request reset GPIO: %d\n", err);
548 backlight = of_parse_phandle(dev->of_node, "backlight", 0);
550 panel->backlight = of_find_backlight_by_node(backlight);
551 of_node_put(backlight);
553 if (!panel->backlight)
554 return -EPROBE_DEFER;
557 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
559 panel->ddc = of_find_i2c_adapter_by_node(ddc);
568 drm_panel_init(&panel->base);
569 panel->base.dev = dev;
570 panel->base.funcs = &panel_simple_funcs;
572 err = drm_panel_add(&panel->base);
576 dev_set_drvdata(dev, panel);
582 put_device(&panel->ddc->dev);
584 if (panel->backlight)
585 put_device(&panel->backlight->dev);
590 static int panel_simple_remove(struct device *dev)
592 struct panel_simple *panel = dev_get_drvdata(dev);
594 drm_panel_detach(&panel->base);
595 drm_panel_remove(&panel->base);
597 panel_simple_disable(&panel->base);
600 put_device(&panel->ddc->dev);
602 if (panel->backlight)
603 put_device(&panel->backlight->dev);
605 panel_simple_dsi_cmds_cleanup(panel);
610 static void panel_simple_shutdown(struct device *dev)
612 struct panel_simple *panel = dev_get_drvdata(dev);
614 panel_simple_disable(&panel->base);
617 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
620 .hsync_start = 800 + 0,
621 .hsync_end = 800 + 0 + 255,
622 .htotal = 800 + 0 + 255 + 0,
624 .vsync_start = 480 + 2,
625 .vsync_end = 480 + 2 + 45,
626 .vtotal = 480 + 2 + 45 + 0,
628 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
631 static const struct panel_desc ampire_am800480r3tmqwa1h = {
632 .modes = &ire_am800480r3tmqwa1h_mode,
639 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
642 static const struct drm_display_mode auo_b101aw03_mode = {
645 .hsync_start = 1024 + 156,
646 .hsync_end = 1024 + 156 + 8,
647 .htotal = 1024 + 156 + 8 + 156,
649 .vsync_start = 600 + 16,
650 .vsync_end = 600 + 16 + 6,
651 .vtotal = 600 + 16 + 6 + 16,
655 static const struct panel_desc auo_b101aw03 = {
656 .modes = &auo_b101aw03_mode,
665 static const struct drm_display_mode auo_b101ean01_mode = {
668 .hsync_start = 1280 + 119,
669 .hsync_end = 1280 + 119 + 32,
670 .htotal = 1280 + 119 + 32 + 21,
672 .vsync_start = 800 + 4,
673 .vsync_end = 800 + 4 + 20,
674 .vtotal = 800 + 4 + 20 + 8,
678 static const struct panel_desc auo_b101ean01 = {
679 .modes = &auo_b101ean01_mode,
688 static const struct drm_display_mode auo_b101ew05_mode = {
691 .hsync_start = 1280 + 18,
692 .hsync_end = 1280 + 18 + 100,
693 .htotal = 1280 + 18 + 100 + 10,
695 .vsync_start = 800 + 6,
696 .vsync_end = 800 + 6 + 8,
697 .vtotal = 800 + 6 + 8 + 2,
701 static const struct panel_desc auo_b101ew05 = {
702 .modes = &auo_b101ew05_mode,
711 static const struct drm_display_mode auo_b101xtn01_mode = {
714 .hsync_start = 1366 + 20,
715 .hsync_end = 1366 + 20 + 70,
716 .htotal = 1366 + 20 + 70,
718 .vsync_start = 768 + 14,
719 .vsync_end = 768 + 14 + 42,
720 .vtotal = 768 + 14 + 42,
722 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
725 static const struct panel_desc auo_b101xtn01 = {
726 .modes = &auo_b101xtn01_mode,
735 static const struct drm_display_mode auo_b116xw03_mode = {
738 .hsync_start = 1366 + 40,
739 .hsync_end = 1366 + 40 + 40,
740 .htotal = 1366 + 40 + 40 + 32,
742 .vsync_start = 768 + 10,
743 .vsync_end = 768 + 10 + 12,
744 .vtotal = 768 + 10 + 12 + 6,
748 static const struct panel_desc auo_b116xw03 = {
749 .modes = &auo_b116xw03_mode,
758 static const struct drm_display_mode auo_b125han03_mode = {
761 .hsync_start = 1920 + 48,
762 .hsync_end = 1920 + 48 + 32,
763 .htotal = 1920 + 48 + 32 + 140,
765 .vsync_start = 1080 + 2,
766 .vsync_end = 1080 + 2 + 5,
767 .vtotal = 1080 + 2 + 5 + 57,
769 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
772 static const struct panel_desc auo_b125han03 = {
773 .modes = &auo_b125han03_mode,
780 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
783 static const struct drm_display_mode auo_b133xtn01_mode = {
786 .hsync_start = 1366 + 48,
787 .hsync_end = 1366 + 48 + 32,
788 .htotal = 1366 + 48 + 32 + 20,
790 .vsync_start = 768 + 3,
791 .vsync_end = 768 + 3 + 6,
792 .vtotal = 768 + 3 + 6 + 13,
796 static const struct panel_desc auo_b133xtn01 = {
797 .modes = &auo_b133xtn01_mode,
806 static const struct drm_display_mode auo_b133htn01_mode = {
809 .hsync_start = 1920 + 172,
810 .hsync_end = 1920 + 172 + 80,
811 .htotal = 1920 + 172 + 80 + 60,
813 .vsync_start = 1080 + 25,
814 .vsync_end = 1080 + 25 + 10,
815 .vtotal = 1080 + 25 + 10 + 10,
819 static const struct panel_desc auo_b133htn01 = {
820 .modes = &auo_b133htn01_mode,
834 static const struct drm_display_mode avic_tm070ddh03_mode = {
837 .hsync_start = 1024 + 160,
838 .hsync_end = 1024 + 160 + 4,
839 .htotal = 1024 + 160 + 4 + 156,
841 .vsync_start = 600 + 17,
842 .vsync_end = 600 + 17 + 1,
843 .vtotal = 600 + 17 + 1 + 17,
847 static const struct panel_desc avic_tm070ddh03 = {
848 .modes = &avic_tm070ddh03_mode,
862 static const struct drm_display_mode boe_nv125fhm_n73_mode = {
865 .hsync_start = 1366 + 80,
866 .hsync_end = 1366 + 80 + 20,
867 .htotal = 1366 + 80 + 20 + 60,
869 .vsync_start = 768 + 12,
870 .vsync_end = 768 + 12 + 2,
871 .vtotal = 768 + 12 + 2 + 8,
873 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
876 static const struct panel_desc boe_nv125fhm_n73 = {
877 .modes = &boe_nv125fhm_n73_mode,
887 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
890 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
893 .hsync_start = 800 + 24,
894 .hsync_end = 800 + 24 + 16,
895 .htotal = 800 + 24 + 16 + 24,
897 .vsync_start = 1280 + 2,
898 .vsync_end = 1280 + 2 + 2,
899 .vtotal = 1280 + 2 + 2 + 4,
903 static const struct panel_desc chunghwa_claa070wp03xg = {
904 .modes = &chunghwa_claa070wp03xg_mode,
913 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
916 .hsync_start = 1366 + 58,
917 .hsync_end = 1366 + 58 + 58,
918 .htotal = 1366 + 58 + 58 + 58,
920 .vsync_start = 768 + 4,
921 .vsync_end = 768 + 4 + 4,
922 .vtotal = 768 + 4 + 4 + 4,
926 static const struct panel_desc chunghwa_claa101wa01a = {
927 .modes = &chunghwa_claa101wa01a_mode,
936 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
939 .hsync_start = 1366 + 48,
940 .hsync_end = 1366 + 48 + 32,
941 .htotal = 1366 + 48 + 32 + 20,
943 .vsync_start = 768 + 16,
944 .vsync_end = 768 + 16 + 8,
945 .vtotal = 768 + 16 + 8 + 16,
949 static const struct panel_desc chunghwa_claa101wb01 = {
950 .modes = &chunghwa_claa101wb01_mode,
959 static const struct drm_display_mode edt_et057090dhu_mode = {
962 .hsync_start = 640 + 16,
963 .hsync_end = 640 + 16 + 30,
964 .htotal = 640 + 16 + 30 + 114,
966 .vsync_start = 480 + 10,
967 .vsync_end = 480 + 10 + 3,
968 .vtotal = 480 + 10 + 3 + 32,
970 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
973 static const struct panel_desc edt_et057090dhu = {
974 .modes = &edt_et057090dhu_mode,
983 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
986 .hsync_start = 800 + 40,
987 .hsync_end = 800 + 40 + 128,
988 .htotal = 800 + 40 + 128 + 88,
990 .vsync_start = 480 + 10,
991 .vsync_end = 480 + 10 + 2,
992 .vtotal = 480 + 10 + 2 + 33,
994 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
997 static const struct panel_desc edt_etm0700g0dh6 = {
998 .modes = &edt_etm0700g0dh6_mode,
1007 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1010 .hsync_start = 800 + 168,
1011 .hsync_end = 800 + 168 + 64,
1012 .htotal = 800 + 168 + 64 + 88,
1014 .vsync_start = 480 + 37,
1015 .vsync_end = 480 + 37 + 2,
1016 .vtotal = 480 + 37 + 2 + 8,
1020 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1021 .modes = &foxlink_fl500wvr00_a0t_mode,
1028 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1031 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
1034 .hsync_start = 480 + 5,
1035 .hsync_end = 480 + 5 + 1,
1036 .htotal = 480 + 5 + 1 + 40,
1038 .vsync_start = 272 + 8,
1039 .vsync_end = 272 + 8 + 1,
1040 .vtotal = 272 + 8 + 1 + 8,
1044 static const struct panel_desc giantplus_gpg482739qs5 = {
1045 .modes = &giantplus_gpg482739qs5_mode,
1052 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1055 static const struct display_timing hannstar_hsd070pww1_timing = {
1056 .pixelclock = { 64300000, 71100000, 82000000 },
1057 .hactive = { 1280, 1280, 1280 },
1058 .hfront_porch = { 1, 1, 10 },
1059 .hback_porch = { 1, 1, 10 },
1061 * According to the data sheet, the minimum horizontal blanking interval
1062 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
1063 * minimum working horizontal blanking interval to be 60 clocks.
1065 .hsync_len = { 58, 158, 661 },
1066 .vactive = { 800, 800, 800 },
1067 .vfront_porch = { 1, 1, 10 },
1068 .vback_porch = { 1, 1, 10 },
1069 .vsync_len = { 1, 21, 203 },
1070 .flags = DISPLAY_FLAGS_DE_HIGH,
1073 static const struct panel_desc hannstar_hsd070pww1 = {
1074 .timings = &hannstar_hsd070pww1_timing,
1081 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1084 static const struct display_timing hannstar_hsd100pxn1_timing = {
1085 .pixelclock = { 55000000, 65000000, 75000000 },
1086 .hactive = { 1024, 1024, 1024 },
1087 .hfront_porch = { 40, 40, 40 },
1088 .hback_porch = { 220, 220, 220 },
1089 .hsync_len = { 20, 60, 100 },
1090 .vactive = { 768, 768, 768 },
1091 .vfront_porch = { 7, 7, 7 },
1092 .vback_porch = { 21, 21, 21 },
1093 .vsync_len = { 10, 10, 10 },
1094 .flags = DISPLAY_FLAGS_DE_HIGH,
1097 static const struct panel_desc hannstar_hsd100pxn1 = {
1098 .timings = &hannstar_hsd100pxn1_timing,
1105 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1108 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
1111 .hsync_start = 800 + 85,
1112 .hsync_end = 800 + 85 + 86,
1113 .htotal = 800 + 85 + 86 + 85,
1115 .vsync_start = 480 + 16,
1116 .vsync_end = 480 + 16 + 13,
1117 .vtotal = 480 + 16 + 13 + 16,
1121 static const struct panel_desc hitachi_tx23d38vm0caa = {
1122 .modes = &hitachi_tx23d38vm0caa_mode,
1131 static const struct drm_display_mode innolux_at043tn24_mode = {
1134 .hsync_start = 480 + 2,
1135 .hsync_end = 480 + 2 + 41,
1136 .htotal = 480 + 2 + 41 + 2,
1138 .vsync_start = 272 + 2,
1139 .vsync_end = 272 + 2 + 11,
1140 .vtotal = 272 + 2 + 11 + 2,
1142 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1145 static const struct panel_desc innolux_at043tn24 = {
1146 .modes = &innolux_at043tn24_mode,
1153 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1156 static const struct drm_display_mode innolux_g121i1_l01_mode = {
1159 .hsync_start = 1280 + 64,
1160 .hsync_end = 1280 + 64 + 32,
1161 .htotal = 1280 + 64 + 32 + 64,
1163 .vsync_start = 800 + 9,
1164 .vsync_end = 800 + 9 + 6,
1165 .vtotal = 800 + 9 + 6 + 9,
1169 static const struct panel_desc innolux_g121i1_l01 = {
1170 .modes = &innolux_g121i1_l01_mode,
1179 static const struct drm_display_mode innolux_n116bge_mode = {
1182 .hsync_start = 1366 + 136,
1183 .hsync_end = 1366 + 136 + 30,
1184 .htotal = 1366 + 136 + 30 + 60,
1186 .vsync_start = 768 + 8,
1187 .vsync_end = 768 + 8 + 12,
1188 .vtotal = 768 + 8 + 12 + 12,
1190 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1193 static const struct panel_desc innolux_n116bge = {
1194 .modes = &innolux_n116bge_mode,
1203 static const struct drm_display_mode innolux_n125hce_mode = {
1206 .hsync_start = 1920 + 80,
1207 .hsync_end = 1920 + 80 + 30,
1208 .htotal = 1920 + 80 + 30 + 50,
1210 .vsync_start = 1080 + 12,
1211 .vsync_end = 1080 + 12 + 4,
1212 .vtotal = 1080 + 12 + 4 + 16,
1214 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1217 static const struct panel_desc innolux_n125hce = {
1218 .modes = &innolux_n125hce_mode,
1229 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1232 static const struct drm_display_mode innolux_n156bge_l21_mode = {
1235 .hsync_start = 1366 + 16,
1236 .hsync_end = 1366 + 16 + 34,
1237 .htotal = 1366 + 16 + 34 + 50,
1239 .vsync_start = 768 + 2,
1240 .vsync_end = 768 + 2 + 6,
1241 .vtotal = 768 + 2 + 6 + 12,
1245 static const struct panel_desc innolux_n156bge_l21 = {
1246 .modes = &innolux_n156bge_l21_mode,
1255 static const struct drm_display_mode innolux_zj070na_01p_mode = {
1258 .hsync_start = 1024 + 128,
1259 .hsync_end = 1024 + 128 + 64,
1260 .htotal = 1024 + 128 + 64 + 128,
1262 .vsync_start = 600 + 16,
1263 .vsync_end = 600 + 16 + 4,
1264 .vtotal = 600 + 16 + 4 + 16,
1268 static const struct panel_desc innolux_zj070na_01p = {
1269 .modes = &innolux_zj070na_01p_mode,
1278 static const struct drm_display_mode lg_lb070wv8_mode = {
1281 .hsync_start = 800 + 88,
1282 .hsync_end = 800 + 88 + 80,
1283 .htotal = 800 + 88 + 80 + 88,
1285 .vsync_start = 480 + 10,
1286 .vsync_end = 480 + 10 + 25,
1287 .vtotal = 480 + 10 + 25 + 10,
1291 static const struct panel_desc lg_lb070wv8 = {
1292 .modes = &lg_lb070wv8_mode,
1299 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1302 static const struct drm_display_mode sharp_lcd_f402_mode = {
1305 .hsync_start = 1536 + 12,
1306 .hsync_end = 1536 + 12 + 48,
1307 .htotal = 1536 + 12 + 48 + 16,
1309 .vsync_start = 2048 + 8,
1310 .vsync_end = 2048 + 8 + 8,
1311 .vtotal = 2048 + 8 + 8 + 4,
1313 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1316 static const struct panel_desc sharp_lcd_f402 = {
1317 .modes = &sharp_lcd_f402_mode,
1324 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1327 static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
1330 .hsync_start = 1536 + 12,
1331 .hsync_end = 1536 + 12 + 16,
1332 .htotal = 1536 + 12 + 16 + 48,
1334 .vsync_start = 2048 + 8,
1335 .vsync_end = 2048 + 8 + 4,
1336 .vtotal = 2048 + 8 + 4 + 8,
1338 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1341 static const struct panel_desc lg_lp079qx1_sp0v = {
1342 .modes = &lg_lp079qx1_sp0v_mode,
1348 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1351 static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
1354 .hsync_start = 2048 + 150,
1355 .hsync_end = 2048 + 150 + 5,
1356 .htotal = 2048 + 150 + 5 + 5,
1358 .vsync_start = 1536 + 3,
1359 .vsync_end = 1536 + 3 + 1,
1360 .vtotal = 1536 + 3 + 1 + 9,
1364 static const struct panel_desc lg_lp097qx1_spa1 = {
1365 .modes = &lg_lp097qx1_spa1_mode,
1373 static const struct drm_display_mode lg_lp129qe_mode = {
1376 .hsync_start = 2560 + 48,
1377 .hsync_end = 2560 + 48 + 32,
1378 .htotal = 2560 + 48 + 32 + 80,
1380 .vsync_start = 1700 + 3,
1381 .vsync_end = 1700 + 3 + 10,
1382 .vtotal = 1700 + 3 + 10 + 36,
1386 static const struct panel_desc lg_lp129qe = {
1387 .modes = &lg_lp129qe_mode,
1396 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
1399 .hsync_start = 480 + 2,
1400 .hsync_end = 480 + 2 + 41,
1401 .htotal = 480 + 2 + 41 + 2,
1403 .vsync_start = 272 + 2,
1404 .vsync_end = 272 + 2 + 4,
1405 .vtotal = 272 + 2 + 4 + 2,
1409 static const struct panel_desc nec_nl4827hc19_05b = {
1410 .modes = &nec_nl4827hc19_05b_mode,
1417 .bus_format = MEDIA_BUS_FMT_RGB888_1X24
1420 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
1421 .pixelclock = { 30000000, 30000000, 40000000 },
1422 .hactive = { 800, 800, 800 },
1423 .hfront_porch = { 40, 40, 40 },
1424 .hback_porch = { 40, 40, 40 },
1425 .hsync_len = { 1, 48, 48 },
1426 .vactive = { 480, 480, 480 },
1427 .vfront_porch = { 13, 13, 13 },
1428 .vback_porch = { 29, 29, 29 },
1429 .vsync_len = { 3, 3, 3 },
1430 .flags = DISPLAY_FLAGS_DE_HIGH,
1433 static const struct panel_desc okaya_rs800480t_7x0gp = {
1434 .timings = &okaya_rs800480t_7x0gp_timing,
1447 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1450 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
1453 .hsync_start = 480 + 10,
1454 .hsync_end = 480 + 10 + 10,
1455 .htotal = 480 + 10 + 10 + 15,
1457 .vsync_start = 800 + 3,
1458 .vsync_end = 800 + 3 + 3,
1459 .vtotal = 800 + 3 + 3 + 3,
1463 static const struct panel_desc ortustech_com43h4m85ulc = {
1464 .modes = &ortustech_com43h4m85ulc_mode,
1471 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1474 static const struct drm_display_mode samsung_lsn122dl01_c01_mode = {
1477 .hsync_start = 2560 + 48,
1478 .hsync_end = 2560 + 48 + 32,
1479 .htotal = 2560 + 48 + 32 + 80,
1481 .vsync_start = 1600 + 2,
1482 .vsync_end = 1600 + 2 + 5,
1483 .vtotal = 1600 + 2 + 5 + 57,
1487 static const struct panel_desc samsung_lsn122dl01_c01 = {
1488 .modes = &samsung_lsn122dl01_c01_mode,
1496 static const struct drm_display_mode samsung_ltn101nt05_mode = {
1499 .hsync_start = 1024 + 24,
1500 .hsync_end = 1024 + 24 + 136,
1501 .htotal = 1024 + 24 + 136 + 160,
1503 .vsync_start = 600 + 3,
1504 .vsync_end = 600 + 3 + 6,
1505 .vtotal = 600 + 3 + 6 + 61,
1509 static const struct panel_desc samsung_ltn101nt05 = {
1510 .modes = &samsung_ltn101nt05_mode,
1519 static const struct drm_display_mode samsung_ltn140at29_301_mode = {
1522 .hsync_start = 1366 + 64,
1523 .hsync_end = 1366 + 64 + 48,
1524 .htotal = 1366 + 64 + 48 + 128,
1526 .vsync_start = 768 + 2,
1527 .vsync_end = 768 + 2 + 5,
1528 .vtotal = 768 + 2 + 5 + 17,
1532 static const struct panel_desc samsung_ltn140at29_301 = {
1533 .modes = &samsung_ltn140at29_301_mode,
1542 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
1545 .hsync_start = 800 + 1,
1546 .hsync_end = 800 + 1 + 64,
1547 .htotal = 800 + 1 + 64 + 64,
1549 .vsync_start = 480 + 1,
1550 .vsync_end = 480 + 1 + 23,
1551 .vtotal = 480 + 1 + 23 + 22,
1555 static const struct panel_desc shelly_sca07010_bfn_lnn = {
1556 .modes = &shelly_sca07010_bfn_lnn_mode,
1562 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1565 static const struct of_device_id platform_of_match[] = {
1567 .compatible = "simple-panel",
1570 .compatible = "ampire,am800480r3tmqwa1h",
1571 .data = &ire_am800480r3tmqwa1h,
1573 .compatible = "auo,b101aw03",
1574 .data = &auo_b101aw03,
1576 .compatible = "auo,b101ean01",
1577 .data = &auo_b101ean01,
1579 .compatible = "auo,b101ew05",
1580 .data = &auo_b101ew05,
1582 .compatible = "auo,b101xtn01",
1583 .data = &auo_b101xtn01,
1585 .compatible = "auo,b116xw03",
1586 .data = &auo_b116xw03,
1588 .compatible = "auo,b125han03",
1589 .data = &auo_b125han03,
1591 .compatible = "auo,b133htn01",
1592 .data = &auo_b133htn01,
1594 .compatible = "auo,b133xtn01",
1595 .data = &auo_b133xtn01,
1597 .compatible = "avic,tm070ddh03",
1598 .data = &avic_tm070ddh03,
1600 .compatible = "boe,nv125fhm-n73",
1601 .data = &boe_nv125fhm_n73,
1603 .compatible = "chunghwa,claa070wp03xg",
1604 .data = &chunghwa_claa070wp03xg,
1606 .compatible = "chunghwa,claa101wa01a",
1607 .data = &chunghwa_claa101wa01a
1609 .compatible = "chunghwa,claa101wb01",
1610 .data = &chunghwa_claa101wb01
1612 .compatible = "edt,et057090dhu",
1613 .data = &edt_et057090dhu,
1615 .compatible = "edt,et070080dh6",
1616 .data = &edt_etm0700g0dh6,
1618 .compatible = "edt,etm0700g0dh6",
1619 .data = &edt_etm0700g0dh6,
1621 .compatible = "foxlink,fl500wvr00-a0t",
1622 .data = &foxlink_fl500wvr00_a0t,
1624 .compatible = "giantplus,gpg482739qs5",
1625 .data = &giantplus_gpg482739qs5
1627 .compatible = "hannstar,hsd070pww1",
1628 .data = &hannstar_hsd070pww1,
1630 .compatible = "hannstar,hsd100pxn1",
1631 .data = &hannstar_hsd100pxn1,
1633 .compatible = "hit,tx23d38vm0caa",
1634 .data = &hitachi_tx23d38vm0caa
1636 .compatible = "innolux,at043tn24",
1637 .data = &innolux_at043tn24,
1639 .compatible ="innolux,g121i1-l01",
1640 .data = &innolux_g121i1_l01
1642 .compatible = "innolux,n116bge",
1643 .data = &innolux_n116bge,
1645 .compatible = "innolux,n125hce",
1646 .data = &innolux_n125hce,
1648 .compatible = "innolux,n156bge-l21",
1649 .data = &innolux_n156bge_l21,
1651 .compatible = "innolux,zj070na-01p",
1652 .data = &innolux_zj070na_01p,
1654 .compatible = "lg,lb070wv8",
1655 .data = &lg_lb070wv8,
1657 .compatible = "lg,lp079qx1-sp0v",
1658 .data = &lg_lp079qx1_sp0v,
1660 .compatible = "sharp,lcd-f402",
1661 .data = &sharp_lcd_f402,
1663 .compatible = "lg,lp097qx1-spa1",
1664 .data = &lg_lp097qx1_spa1,
1666 .compatible = "lg,lp129qe",
1667 .data = &lg_lp129qe,
1669 .compatible = "nec,nl4827hc19-05b",
1670 .data = &nec_nl4827hc19_05b,
1672 .compatible = "okaya,rs800480t-7x0gp",
1673 .data = &okaya_rs800480t_7x0gp,
1675 .compatible = "ortustech,com43h4m85ulc",
1676 .data = &ortustech_com43h4m85ulc,
1678 .compatible = "samsung,lsn122dl01-c01",
1679 .data = &samsung_lsn122dl01_c01,
1681 .compatible = "samsung,ltn101nt05",
1682 .data = &samsung_ltn101nt05,
1684 .compatible = "samsung,ltn140at29-301",
1685 .data = &samsung_ltn140at29_301,
1687 .compatible = "sharp,lcd-f402",
1688 .data = &sharp_lcd_f402,
1690 .compatible = "shelly,sca07010-bfn-lnn",
1691 .data = &shelly_sca07010_bfn_lnn,
1696 MODULE_DEVICE_TABLE(of, platform_of_match);
1698 static int panel_simple_platform_probe(struct platform_device *pdev)
1700 const struct of_device_id *id;
1702 id = of_match_node(platform_of_match, pdev->dev.of_node);
1706 return panel_simple_probe(&pdev->dev, id->data);
1709 static int panel_simple_platform_remove(struct platform_device *pdev)
1711 return panel_simple_remove(&pdev->dev);
1714 static void panel_simple_platform_shutdown(struct platform_device *pdev)
1716 panel_simple_shutdown(&pdev->dev);
1719 static struct platform_driver panel_simple_platform_driver = {
1721 .name = "panel-simple",
1722 .of_match_table = platform_of_match,
1724 .probe = panel_simple_platform_probe,
1725 .remove = panel_simple_platform_remove,
1726 .shutdown = panel_simple_platform_shutdown,
1729 struct panel_desc_dsi {
1730 struct panel_desc desc;
1732 unsigned long flags;
1733 enum mipi_dsi_pixel_format format;
1737 static const struct drm_display_mode auo_b080uan01_mode = {
1740 .hsync_start = 1200 + 62,
1741 .hsync_end = 1200 + 62 + 4,
1742 .htotal = 1200 + 62 + 4 + 62,
1744 .vsync_start = 1920 + 9,
1745 .vsync_end = 1920 + 9 + 2,
1746 .vtotal = 1920 + 9 + 2 + 8,
1750 static const struct panel_desc_dsi auo_b080uan01 = {
1752 .modes = &auo_b080uan01_mode,
1760 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1761 .format = MIPI_DSI_FMT_RGB888,
1765 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
1768 .hsync_start = 1200 + 120,
1769 .hsync_end = 1200 + 120 + 20,
1770 .htotal = 1200 + 120 + 20 + 21,
1772 .vsync_start = 1920 + 21,
1773 .vsync_end = 1920 + 21 + 3,
1774 .vtotal = 1920 + 21 + 3 + 18,
1776 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1779 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
1781 .modes = &boe_tv080wum_nl0_mode,
1788 .flags = MIPI_DSI_MODE_VIDEO |
1789 MIPI_DSI_MODE_VIDEO_BURST |
1790 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
1791 .format = MIPI_DSI_FMT_RGB888,
1795 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
1798 .hsync_start = 800 + 32,
1799 .hsync_end = 800 + 32 + 1,
1800 .htotal = 800 + 32 + 1 + 57,
1802 .vsync_start = 1280 + 28,
1803 .vsync_end = 1280 + 28 + 1,
1804 .vtotal = 1280 + 28 + 1 + 14,
1808 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
1810 .modes = &lg_ld070wx3_sl01_mode,
1818 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
1819 .format = MIPI_DSI_FMT_RGB888,
1823 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
1826 .hsync_start = 720 + 12,
1827 .hsync_end = 720 + 12 + 4,
1828 .htotal = 720 + 12 + 4 + 112,
1830 .vsync_start = 1280 + 8,
1831 .vsync_end = 1280 + 8 + 4,
1832 .vtotal = 1280 + 8 + 4 + 12,
1836 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
1838 .modes = &lg_lh500wx1_sd03_mode,
1846 .flags = MIPI_DSI_MODE_VIDEO,
1847 .format = MIPI_DSI_FMT_RGB888,
1851 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
1854 .hsync_start = 1920 + 154,
1855 .hsync_end = 1920 + 154 + 16,
1856 .htotal = 1920 + 154 + 16 + 32,
1858 .vsync_start = 1200 + 17,
1859 .vsync_end = 1200 + 17 + 2,
1860 .vtotal = 1200 + 17 + 2 + 16,
1864 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
1866 .modes = &panasonic_vvx10f004b00_mode,
1874 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1875 MIPI_DSI_CLOCK_NON_CONTINUOUS,
1876 .format = MIPI_DSI_FMT_RGB888,
1881 static const struct of_device_id dsi_of_match[] = {
1883 .compatible = "simple-panel-dsi",
1886 .compatible = "auo,b080uan01",
1887 .data = &auo_b080uan01
1889 .compatible = "boe,tv080wum-nl0",
1890 .data = &boe_tv080wum_nl0
1892 .compatible = "lg,ld070wx3-sl01",
1893 .data = &lg_ld070wx3_sl01
1895 .compatible = "lg,lh500wx1-sd03",
1896 .data = &lg_lh500wx1_sd03
1898 .compatible = "panasonic,vvx10f004b00",
1899 .data = &panasonic_vvx10f004b00
1904 MODULE_DEVICE_TABLE(of, dsi_of_match);
1906 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
1908 struct panel_simple *panel;
1909 const struct panel_desc_dsi *desc;
1910 const struct of_device_id *id;
1911 const struct panel_desc *pdesc;
1917 id = of_match_node(dsi_of_match, dsi->dev.of_node);
1924 dsi->mode_flags = desc->flags;
1925 dsi->format = desc->format;
1926 dsi->lanes = desc->lanes;
1927 pdesc = &desc->desc;
1932 err = panel_simple_probe(&dsi->dev, pdesc);
1936 panel = dev_get_drvdata(&dsi->dev);
1939 if (!of_property_read_u32(dsi->dev.of_node, "dsi,flags", &val))
1940 dsi->mode_flags = val;
1942 if (!of_property_read_u32(dsi->dev.of_node, "dsi,format", &val))
1945 if (!of_property_read_u32(dsi->dev.of_node, "dsi,lanes", &val))
1948 if (!of_property_read_u32(dsi->dev.of_node, "reset-delay-ms", &val))
1949 panel->reset_delay = val;
1951 data = of_get_property(dsi->dev.of_node, "panel-init-sequence", &len);
1953 panel->on_cmds = devm_kzalloc(&dsi->dev,
1954 sizeof(*panel->on_cmds),
1956 if (!panel->on_cmds)
1959 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
1962 dev_err(&dsi->dev, "failed to parse panel init sequence\n");
1967 data = of_get_property(dsi->dev.of_node, "panel-exit-sequence", &len);
1969 panel->off_cmds = devm_kzalloc(&dsi->dev,
1970 sizeof(*panel->off_cmds),
1972 if (!panel->off_cmds)
1975 err = panel_simple_dsi_parse_dcs_cmds(&dsi->dev, data, len,
1978 dev_err(&dsi->dev, "failed to parse panel exit sequence\n");
1983 return mipi_dsi_attach(dsi);
1986 static int panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
1990 err = mipi_dsi_detach(dsi);
1992 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
1994 return panel_simple_remove(&dsi->dev);
1997 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
1999 panel_simple_shutdown(&dsi->dev);
2002 static struct mipi_dsi_driver panel_simple_dsi_driver = {
2004 .name = "panel-simple-dsi",
2005 .of_match_table = dsi_of_match,
2007 .probe = panel_simple_dsi_probe,
2008 .remove = panel_simple_dsi_remove,
2009 .shutdown = panel_simple_dsi_shutdown,
2012 static int __init panel_simple_init(void)
2016 err = platform_driver_register(&panel_simple_platform_driver);
2020 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
2021 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
2028 module_init(panel_simple_init);
2030 static void __exit panel_simple_exit(void)
2032 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
2033 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
2035 platform_driver_unregister(&panel_simple_platform_driver);
2037 module_exit(panel_simple_exit);
2039 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2040 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
2041 MODULE_LICENSE("GPL and additional rights");