2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include <drm/drm_fixed.h>
32 #include "atom-bits.h"
34 static void atombios_overscan_setup(struct drm_crtc *crtc,
35 struct drm_display_mode *mode,
36 struct drm_display_mode *adjusted_mode)
38 struct drm_device *dev = crtc->dev;
39 struct radeon_device *rdev = dev->dev_private;
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
45 memset(&args, 0, sizeof(args));
47 args.ucCRTC = radeon_crtc->crtc_id;
49 switch (radeon_crtc->rmx_type) {
51 args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
52 args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2;
53 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
54 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2;
57 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
61 args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
62 args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2;
64 args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
65 args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2;
70 args.usOverscanRight = radeon_crtc->h_border;
71 args.usOverscanLeft = radeon_crtc->h_border;
72 args.usOverscanBottom = radeon_crtc->v_border;
73 args.usOverscanTop = radeon_crtc->v_border;
76 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
79 static void atombios_scaler_setup(struct drm_crtc *crtc)
81 struct drm_device *dev = crtc->dev;
82 struct radeon_device *rdev = dev->dev_private;
83 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84 ENABLE_SCALER_PS_ALLOCATION args;
85 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
87 /* fixme - fill in enc_priv for atom dac */
88 enum radeon_tv_std tv_std = TV_STD_NTSC;
89 bool is_tv = false, is_cv = false;
90 struct drm_encoder *encoder;
92 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
95 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
97 if (encoder->crtc == crtc) {
98 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101 tv_std = tv_dac->tv_std;
107 memset(&args, 0, sizeof(args));
109 args.ucScaler = radeon_crtc->crtc_id;
115 args.ucTVStandard = ATOM_TV_NTSC;
118 args.ucTVStandard = ATOM_TV_PAL;
121 args.ucTVStandard = ATOM_TV_PALM;
124 args.ucTVStandard = ATOM_TV_PAL60;
127 args.ucTVStandard = ATOM_TV_NTSCJ;
129 case TV_STD_SCART_PAL:
130 args.ucTVStandard = ATOM_TV_PAL; /* ??? */
133 args.ucTVStandard = ATOM_TV_SECAM;
136 args.ucTVStandard = ATOM_TV_PALCN;
139 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
141 args.ucTVStandard = ATOM_TV_CV;
142 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
144 switch (radeon_crtc->rmx_type) {
146 args.ucEnable = ATOM_SCALER_EXPANSION;
149 args.ucEnable = ATOM_SCALER_CENTER;
152 args.ucEnable = ATOM_SCALER_EXPANSION;
155 if (ASIC_IS_AVIVO(rdev))
156 args.ucEnable = ATOM_SCALER_DISABLE;
158 args.ucEnable = ATOM_SCALER_CENTER;
162 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
164 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
169 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
171 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172 struct drm_device *dev = crtc->dev;
173 struct radeon_device *rdev = dev->dev_private;
175 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176 ENABLE_CRTC_PS_ALLOCATION args;
178 memset(&args, 0, sizeof(args));
180 args.ucCRTC = radeon_crtc->crtc_id;
181 args.ucEnable = lock;
183 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
186 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
188 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189 struct drm_device *dev = crtc->dev;
190 struct radeon_device *rdev = dev->dev_private;
191 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192 ENABLE_CRTC_PS_ALLOCATION args;
194 memset(&args, 0, sizeof(args));
196 args.ucCRTC = radeon_crtc->crtc_id;
197 args.ucEnable = state;
199 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
202 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
204 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205 struct drm_device *dev = crtc->dev;
206 struct radeon_device *rdev = dev->dev_private;
207 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208 ENABLE_CRTC_PS_ALLOCATION args;
210 memset(&args, 0, sizeof(args));
212 args.ucCRTC = radeon_crtc->crtc_id;
213 args.ucEnable = state;
215 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
218 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
220 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221 struct drm_device *dev = crtc->dev;
222 struct radeon_device *rdev = dev->dev_private;
223 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224 BLANK_CRTC_PS_ALLOCATION args;
226 memset(&args, 0, sizeof(args));
228 args.ucCRTC = radeon_crtc->crtc_id;
229 args.ucBlanking = state;
231 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
234 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
236 struct drm_device *dev = crtc->dev;
237 struct radeon_device *rdev = dev->dev_private;
238 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
241 case DRM_MODE_DPMS_ON:
242 radeon_crtc->enabled = true;
243 /* adjust pm to dpms changes BEFORE enabling crtcs */
244 radeon_pm_compute_clocks(rdev);
245 atombios_enable_crtc(crtc, ATOM_ENABLE);
246 if (ASIC_IS_DCE3(rdev))
247 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
248 atombios_blank_crtc(crtc, ATOM_DISABLE);
249 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
250 radeon_crtc_load_lut(crtc);
252 case DRM_MODE_DPMS_STANDBY:
253 case DRM_MODE_DPMS_SUSPEND:
254 case DRM_MODE_DPMS_OFF:
255 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
256 atombios_blank_crtc(crtc, ATOM_ENABLE);
257 if (ASIC_IS_DCE3(rdev))
258 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
259 atombios_enable_crtc(crtc, ATOM_DISABLE);
260 radeon_crtc->enabled = false;
261 /* adjust pm to dpms changes AFTER disabling crtcs */
262 radeon_pm_compute_clocks(rdev);
268 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
269 struct drm_display_mode *mode)
271 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
272 struct drm_device *dev = crtc->dev;
273 struct radeon_device *rdev = dev->dev_private;
274 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
275 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
278 memset(&args, 0, sizeof(args));
279 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
280 args.usH_Blanking_Time =
281 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
282 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
283 args.usV_Blanking_Time =
284 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
285 args.usH_SyncOffset =
286 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
288 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
289 args.usV_SyncOffset =
290 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
292 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
293 args.ucH_Border = radeon_crtc->h_border;
294 args.ucV_Border = radeon_crtc->v_border;
296 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
297 misc |= ATOM_VSYNC_POLARITY;
298 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
299 misc |= ATOM_HSYNC_POLARITY;
300 if (mode->flags & DRM_MODE_FLAG_CSYNC)
301 misc |= ATOM_COMPOSITESYNC;
302 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
303 misc |= ATOM_INTERLACE;
304 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
305 misc |= ATOM_DOUBLE_CLOCK_MODE;
307 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
308 args.ucCRTC = radeon_crtc->crtc_id;
310 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
313 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
314 struct drm_display_mode *mode)
316 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
317 struct drm_device *dev = crtc->dev;
318 struct radeon_device *rdev = dev->dev_private;
319 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
320 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
323 memset(&args, 0, sizeof(args));
324 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
325 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
326 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
328 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
329 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
330 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
331 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
333 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
335 args.ucOverscanRight = radeon_crtc->h_border;
336 args.ucOverscanLeft = radeon_crtc->h_border;
337 args.ucOverscanBottom = radeon_crtc->v_border;
338 args.ucOverscanTop = radeon_crtc->v_border;
340 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
341 misc |= ATOM_VSYNC_POLARITY;
342 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
343 misc |= ATOM_HSYNC_POLARITY;
344 if (mode->flags & DRM_MODE_FLAG_CSYNC)
345 misc |= ATOM_COMPOSITESYNC;
346 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
347 misc |= ATOM_INTERLACE;
348 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
349 misc |= ATOM_DOUBLE_CLOCK_MODE;
351 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
352 args.ucCRTC = radeon_crtc->crtc_id;
354 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
357 static void atombios_disable_ss(struct drm_crtc *crtc)
359 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
360 struct drm_device *dev = crtc->dev;
361 struct radeon_device *rdev = dev->dev_private;
364 if (ASIC_IS_DCE4(rdev)) {
365 switch (radeon_crtc->pll_id) {
367 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
368 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
369 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
372 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
373 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
374 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
377 case ATOM_PPLL_INVALID:
380 } else if (ASIC_IS_AVIVO(rdev)) {
381 switch (radeon_crtc->pll_id) {
383 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
385 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
388 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
390 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
393 case ATOM_PPLL_INVALID:
400 union atom_enable_ss {
401 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
402 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
403 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
404 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
407 static void atombios_crtc_program_ss(struct drm_crtc *crtc,
410 struct radeon_atom_ss *ss)
412 struct drm_device *dev = crtc->dev;
413 struct radeon_device *rdev = dev->dev_private;
414 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
415 union atom_enable_ss args;
417 memset(&args, 0, sizeof(args));
419 if (ASIC_IS_DCE4(rdev)) {
420 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
421 args.v2.ucSpreadSpectrumType = ss->type;
424 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
425 args.v2.usSpreadSpectrumAmount = ss->amount;
426 args.v2.usSpreadSpectrumStep = ss->step;
429 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
430 args.v2.usSpreadSpectrumAmount = ss->amount;
431 args.v2.usSpreadSpectrumStep = ss->step;
434 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
435 args.v2.usSpreadSpectrumAmount = 0;
436 args.v2.usSpreadSpectrumStep = 0;
438 case ATOM_PPLL_INVALID:
441 args.v2.ucEnable = enable;
442 } else if (ASIC_IS_DCE3(rdev)) {
443 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
444 args.v1.ucSpreadSpectrumType = ss->type;
445 args.v1.ucSpreadSpectrumStep = ss->step;
446 args.v1.ucSpreadSpectrumDelay = ss->delay;
447 args.v1.ucSpreadSpectrumRange = ss->range;
448 args.v1.ucPpll = pll_id;
449 args.v1.ucEnable = enable;
450 } else if (ASIC_IS_AVIVO(rdev)) {
451 if (enable == ATOM_DISABLE) {
452 atombios_disable_ss(crtc);
455 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
456 args.lvds_ss_2.ucSpreadSpectrumType = ss->type;
457 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
458 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
459 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
460 args.lvds_ss_2.ucEnable = enable;
462 if (enable == ATOM_DISABLE) {
463 atombios_disable_ss(crtc);
466 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
467 args.lvds_ss.ucSpreadSpectrumType = ss->type;
468 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
469 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
470 args.lvds_ss.ucEnable = enable;
472 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
475 union adjust_pixel_clock {
476 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
477 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
480 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
481 struct drm_display_mode *mode,
482 struct radeon_pll *pll,
484 struct radeon_atom_ss *ss)
486 struct drm_device *dev = crtc->dev;
487 struct radeon_device *rdev = dev->dev_private;
488 struct drm_encoder *encoder = NULL;
489 struct radeon_encoder *radeon_encoder = NULL;
490 u32 adjusted_clock = mode->clock;
491 int encoder_mode = 0;
492 u32 dp_clock = mode->clock;
495 /* reset the pll flags */
498 if (ASIC_IS_AVIVO(rdev)) {
499 if ((rdev->family == CHIP_RS600) ||
500 (rdev->family == CHIP_RS690) ||
501 (rdev->family == CHIP_RS740))
502 pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
503 RADEON_PLL_PREFER_CLOSEST_LOWER);
505 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
506 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
508 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
510 pll->flags |= RADEON_PLL_LEGACY;
512 if (mode->clock > 200000) /* range limits??? */
513 pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
515 pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
519 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
520 if (encoder->crtc == crtc) {
521 radeon_encoder = to_radeon_encoder(encoder);
522 encoder_mode = atombios_get_encoder_mode(encoder);
523 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
524 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
526 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
527 struct radeon_connector_atom_dig *dig_connector =
528 radeon_connector->con_priv;
530 dp_clock = dig_connector->dp_clock;
534 /* use recommended ref_div for ss */
535 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
538 pll->flags |= RADEON_PLL_USE_REF_DIV;
539 pll->reference_div = ss->refdiv;
544 if (ASIC_IS_AVIVO(rdev)) {
545 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
546 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
547 adjusted_clock = mode->clock * 2;
548 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
549 pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
551 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
552 pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
553 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
554 pll->flags |= RADEON_PLL_USE_REF_DIV;
560 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
561 * accordingly based on the encoder/transmitter to work around
562 * special hw requirements.
564 if (ASIC_IS_DCE3(rdev)) {
565 union adjust_pixel_clock args;
569 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
570 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
572 return adjusted_clock;
574 memset(&args, 0, sizeof(args));
581 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
582 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
583 args.v1.ucEncodeMode = encoder_mode;
584 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
587 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
588 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
590 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
593 atom_execute_table(rdev->mode_info.atom_context,
594 index, (uint32_t *)&args);
595 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
598 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
599 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
600 args.v3.sInput.ucEncodeMode = encoder_mode;
601 args.v3.sInput.ucDispPllConfig = 0;
602 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
603 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
604 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
606 args.v3.sInput.ucDispPllConfig |=
607 DISPPLL_CONFIG_SS_ENABLE;
608 args.v3.sInput.ucDispPllConfig |=
609 DISPPLL_CONFIG_COHERENT_MODE;
611 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
613 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
614 /* deep color support */
615 args.v3.sInput.usPixelClock =
616 cpu_to_le16((mode->clock * bpc / 8) / 10);
618 if (dig->coherent_mode)
619 args.v3.sInput.ucDispPllConfig |=
620 DISPPLL_CONFIG_COHERENT_MODE;
621 if (mode->clock > 165000)
622 args.v3.sInput.ucDispPllConfig |=
623 DISPPLL_CONFIG_DUAL_LINK;
625 } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
626 if (encoder_mode == ATOM_ENCODER_MODE_DP) {
628 args.v3.sInput.ucDispPllConfig |=
629 DISPPLL_CONFIG_SS_ENABLE;
630 args.v3.sInput.ucDispPllConfig |=
631 DISPPLL_CONFIG_COHERENT_MODE;
633 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
634 } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) {
636 args.v3.sInput.ucDispPllConfig |=
637 DISPPLL_CONFIG_SS_ENABLE;
639 if (mode->clock > 165000)
640 args.v3.sInput.ucDispPllConfig |=
641 DISPPLL_CONFIG_DUAL_LINK;
644 atom_execute_table(rdev->mode_info.atom_context,
645 index, (uint32_t *)&args);
646 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
647 if (args.v3.sOutput.ucRefDiv) {
648 pll->flags |= RADEON_PLL_USE_REF_DIV;
649 pll->reference_div = args.v3.sOutput.ucRefDiv;
651 if (args.v3.sOutput.ucPostDiv) {
652 pll->flags |= RADEON_PLL_USE_POST_DIV;
653 pll->post_div = args.v3.sOutput.ucPostDiv;
657 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
658 return adjusted_clock;
662 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
663 return adjusted_clock;
666 return adjusted_clock;
669 union set_pixel_clock {
670 SET_PIXEL_CLOCK_PS_ALLOCATION base;
671 PIXEL_CLOCK_PARAMETERS v1;
672 PIXEL_CLOCK_PARAMETERS_V2 v2;
673 PIXEL_CLOCK_PARAMETERS_V3 v3;
674 PIXEL_CLOCK_PARAMETERS_V5 v5;
677 static void atombios_crtc_set_dcpll(struct drm_crtc *crtc)
679 struct drm_device *dev = crtc->dev;
680 struct radeon_device *rdev = dev->dev_private;
683 union set_pixel_clock args;
685 memset(&args, 0, sizeof(args));
687 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
688 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
696 /* if the default dcpll clock is specified,
697 * SetPixelClock provides the dividers
699 args.v5.ucCRTC = ATOM_CRTC_INVALID;
700 args.v5.usPixelClock = rdev->clock.default_dispclk;
701 args.v5.ucPpll = ATOM_DCPLL;
704 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
709 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
712 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
715 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
726 struct drm_device *dev = crtc->dev;
727 struct radeon_device *rdev = dev->dev_private;
729 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
730 union set_pixel_clock args;
732 memset(&args, 0, sizeof(args));
734 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
742 if (clock == ATOM_DISABLE)
744 args.v1.usPixelClock = cpu_to_le16(clock / 10);
745 args.v1.usRefDiv = cpu_to_le16(ref_div);
746 args.v1.usFbDiv = cpu_to_le16(fb_div);
747 args.v1.ucFracFbDiv = frac_fb_div;
748 args.v1.ucPostDiv = post_div;
749 args.v1.ucPpll = pll_id;
750 args.v1.ucCRTC = crtc_id;
751 args.v1.ucRefDivSrc = 1;
754 args.v2.usPixelClock = cpu_to_le16(clock / 10);
755 args.v2.usRefDiv = cpu_to_le16(ref_div);
756 args.v2.usFbDiv = cpu_to_le16(fb_div);
757 args.v2.ucFracFbDiv = frac_fb_div;
758 args.v2.ucPostDiv = post_div;
759 args.v2.ucPpll = pll_id;
760 args.v2.ucCRTC = crtc_id;
761 args.v2.ucRefDivSrc = 1;
764 args.v3.usPixelClock = cpu_to_le16(clock / 10);
765 args.v3.usRefDiv = cpu_to_le16(ref_div);
766 args.v3.usFbDiv = cpu_to_le16(fb_div);
767 args.v3.ucFracFbDiv = frac_fb_div;
768 args.v3.ucPostDiv = post_div;
769 args.v3.ucPpll = pll_id;
770 args.v3.ucMiscInfo = (pll_id << 2);
771 args.v3.ucTransmitterId = encoder_id;
772 args.v3.ucEncoderMode = encoder_mode;
775 args.v5.ucCRTC = crtc_id;
776 args.v5.usPixelClock = cpu_to_le16(clock / 10);
777 args.v5.ucRefDiv = ref_div;
778 args.v5.usFbDiv = cpu_to_le16(fb_div);
779 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
780 args.v5.ucPostDiv = post_div;
781 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
782 args.v5.ucTransmitterID = encoder_id;
783 args.v5.ucEncoderMode = encoder_mode;
784 args.v5.ucPpll = pll_id;
787 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
792 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
796 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
799 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
801 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
802 struct drm_device *dev = crtc->dev;
803 struct radeon_device *rdev = dev->dev_private;
804 struct drm_encoder *encoder = NULL;
805 struct radeon_encoder *radeon_encoder = NULL;
806 u32 pll_clock = mode->clock;
807 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
808 struct radeon_pll *pll;
810 int encoder_mode = 0;
811 struct radeon_atom_ss ss;
812 bool ss_enabled = false;
814 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
815 if (encoder->crtc == crtc) {
816 radeon_encoder = to_radeon_encoder(encoder);
817 encoder_mode = atombios_get_encoder_mode(encoder);
825 switch (radeon_crtc->pll_id) {
827 pll = &rdev->clock.p1pll;
830 pll = &rdev->clock.p2pll;
833 case ATOM_PPLL_INVALID:
835 pll = &rdev->clock.dcpll;
839 if (radeon_encoder->active_device &
840 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
841 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
842 struct drm_connector *connector =
843 radeon_get_connector_for_encoder(encoder);
844 struct radeon_connector *radeon_connector =
845 to_radeon_connector(connector);
846 struct radeon_connector_atom_dig *dig_connector =
847 radeon_connector->con_priv;
850 switch (encoder_mode) {
851 case ATOM_ENCODER_MODE_DP:
853 dp_clock = dig_connector->dp_clock / 10;
854 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
855 if (ASIC_IS_DCE4(rdev))
857 radeon_atombios_get_asic_ss_info(rdev, &ss,
862 radeon_atombios_get_ppll_ss_info(rdev, &ss,
865 if (ASIC_IS_DCE4(rdev))
867 radeon_atombios_get_asic_ss_info(rdev, &ss,
868 ASIC_INTERNAL_SS_ON_DP,
871 if (dp_clock == 16200) {
873 radeon_atombios_get_ppll_ss_info(rdev, &ss,
877 radeon_atombios_get_ppll_ss_info(rdev, &ss,
881 radeon_atombios_get_ppll_ss_info(rdev, &ss,
886 case ATOM_ENCODER_MODE_LVDS:
887 if (ASIC_IS_DCE4(rdev))
888 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
892 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
895 case ATOM_ENCODER_MODE_DVI:
896 if (ASIC_IS_DCE4(rdev))
898 radeon_atombios_get_asic_ss_info(rdev, &ss,
899 ASIC_INTERNAL_SS_ON_TMDS,
902 case ATOM_ENCODER_MODE_HDMI:
903 if (ASIC_IS_DCE4(rdev))
905 radeon_atombios_get_asic_ss_info(rdev, &ss,
906 ASIC_INTERNAL_SS_ON_HDMI,
914 /* adjust pixel clock as needed */
915 adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
917 radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
918 &ref_div, &post_div);
920 atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
922 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
923 encoder_mode, radeon_encoder->encoder_id, mode->clock,
924 ref_div, fb_div, frac_fb_div, post_div);
927 /* calculate ss amount and step size */
928 if (ASIC_IS_DCE4(rdev)) {
930 u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
931 ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
932 ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
933 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
934 if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
935 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
936 (125 * 25 * pll->reference_freq / 100);
938 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
939 (125 * 25 * pll->reference_freq / 100);
943 atombios_crtc_program_ss(crtc, ATOM_ENABLE, radeon_crtc->pll_id, &ss);
947 static int evergreen_crtc_do_set_base(struct drm_crtc *crtc,
948 struct drm_framebuffer *fb,
949 int x, int y, int atomic)
951 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
952 struct drm_device *dev = crtc->dev;
953 struct radeon_device *rdev = dev->dev_private;
954 struct radeon_framebuffer *radeon_fb;
955 struct drm_framebuffer *target_fb;
956 struct drm_gem_object *obj;
957 struct radeon_bo *rbo;
958 uint64_t fb_location;
959 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
963 if (!atomic && !crtc->fb) {
964 DRM_DEBUG_KMS("No FB bound\n");
969 radeon_fb = to_radeon_framebuffer(fb);
973 radeon_fb = to_radeon_framebuffer(crtc->fb);
974 target_fb = crtc->fb;
977 /* If atomic, assume fb object is pinned & idle & fenced and
978 * just update base pointers
980 obj = radeon_fb->obj;
981 rbo = obj->driver_private;
982 r = radeon_bo_reserve(rbo, false);
983 if (unlikely(r != 0))
987 fb_location = radeon_bo_gpu_offset(rbo);
989 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
990 if (unlikely(r != 0)) {
991 radeon_bo_unreserve(rbo);
996 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
997 radeon_bo_unreserve(rbo);
999 switch (target_fb->bits_per_pixel) {
1001 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1002 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1005 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1006 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1009 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1010 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1014 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1015 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1018 DRM_ERROR("Unsupported screen depth %d\n",
1019 target_fb->bits_per_pixel);
1023 if (tiling_flags & RADEON_TILING_MACRO)
1024 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1025 else if (tiling_flags & RADEON_TILING_MICRO)
1026 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1028 switch (radeon_crtc->crtc_id) {
1030 WREG32(AVIVO_D1VGA_CONTROL, 0);
1033 WREG32(AVIVO_D2VGA_CONTROL, 0);
1036 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1039 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1042 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1045 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1051 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1052 upper_32_bits(fb_location));
1053 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1054 upper_32_bits(fb_location));
1055 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1056 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1057 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1058 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1059 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1061 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1062 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1063 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1064 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1065 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1066 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1068 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1069 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1070 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1072 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1073 crtc->mode.vdisplay);
1076 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1078 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1079 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1081 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1082 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1083 EVERGREEN_INTERLEAVE_EN);
1085 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1087 if (!atomic && fb && fb != crtc->fb) {
1088 radeon_fb = to_radeon_framebuffer(fb);
1089 rbo = radeon_fb->obj->driver_private;
1090 r = radeon_bo_reserve(rbo, false);
1091 if (unlikely(r != 0))
1093 radeon_bo_unpin(rbo);
1094 radeon_bo_unreserve(rbo);
1097 /* Bytes per pixel may have changed */
1098 radeon_bandwidth_update(rdev);
1103 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1104 struct drm_framebuffer *fb,
1105 int x, int y, int atomic)
1107 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1108 struct drm_device *dev = crtc->dev;
1109 struct radeon_device *rdev = dev->dev_private;
1110 struct radeon_framebuffer *radeon_fb;
1111 struct drm_gem_object *obj;
1112 struct radeon_bo *rbo;
1113 struct drm_framebuffer *target_fb;
1114 uint64_t fb_location;
1115 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1119 if (!atomic && !crtc->fb) {
1120 DRM_DEBUG_KMS("No FB bound\n");
1125 radeon_fb = to_radeon_framebuffer(fb);
1129 radeon_fb = to_radeon_framebuffer(crtc->fb);
1130 target_fb = crtc->fb;
1133 obj = radeon_fb->obj;
1134 rbo = obj->driver_private;
1135 r = radeon_bo_reserve(rbo, false);
1136 if (unlikely(r != 0))
1139 /* If atomic, assume fb object is pinned & idle & fenced and
1140 * just update base pointers
1143 fb_location = radeon_bo_gpu_offset(rbo);
1145 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1146 if (unlikely(r != 0)) {
1147 radeon_bo_unreserve(rbo);
1151 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1152 radeon_bo_unreserve(rbo);
1154 switch (target_fb->bits_per_pixel) {
1157 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1158 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1162 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1163 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1167 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1168 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1173 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1174 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1177 DRM_ERROR("Unsupported screen depth %d\n",
1178 target_fb->bits_per_pixel);
1182 if (rdev->family >= CHIP_R600) {
1183 if (tiling_flags & RADEON_TILING_MACRO)
1184 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1185 else if (tiling_flags & RADEON_TILING_MICRO)
1186 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1188 if (tiling_flags & RADEON_TILING_MACRO)
1189 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1191 if (tiling_flags & RADEON_TILING_MICRO)
1192 fb_format |= AVIVO_D1GRPH_TILED;
1195 if (radeon_crtc->crtc_id == 0)
1196 WREG32(AVIVO_D1VGA_CONTROL, 0);
1198 WREG32(AVIVO_D2VGA_CONTROL, 0);
1200 if (rdev->family >= CHIP_RV770) {
1201 if (radeon_crtc->crtc_id) {
1202 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1203 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1205 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1206 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1209 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1211 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1212 radeon_crtc->crtc_offset, (u32) fb_location);
1213 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1215 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1216 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1217 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1218 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1219 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1220 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1222 fb_pitch_pixels = target_fb->pitch / (target_fb->bits_per_pixel / 8);
1223 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1224 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1226 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1227 crtc->mode.vdisplay);
1230 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1232 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1233 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
1235 if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
1236 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1237 AVIVO_D1MODE_INTERLEAVE_EN);
1239 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1241 if (!atomic && fb && fb != crtc->fb) {
1242 radeon_fb = to_radeon_framebuffer(fb);
1243 rbo = radeon_fb->obj->driver_private;
1244 r = radeon_bo_reserve(rbo, false);
1245 if (unlikely(r != 0))
1247 radeon_bo_unpin(rbo);
1248 radeon_bo_unreserve(rbo);
1251 /* Bytes per pixel may have changed */
1252 radeon_bandwidth_update(rdev);
1257 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1258 struct drm_framebuffer *old_fb)
1260 struct drm_device *dev = crtc->dev;
1261 struct radeon_device *rdev = dev->dev_private;
1263 if (ASIC_IS_DCE4(rdev))
1264 return evergreen_crtc_do_set_base(crtc, old_fb, x, y, 0);
1265 else if (ASIC_IS_AVIVO(rdev))
1266 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1268 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1271 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1272 struct drm_framebuffer *fb,
1273 int x, int y, enum mode_set_atomic state)
1275 struct drm_device *dev = crtc->dev;
1276 struct radeon_device *rdev = dev->dev_private;
1278 if (ASIC_IS_DCE4(rdev))
1279 return evergreen_crtc_do_set_base(crtc, fb, x, y, 1);
1280 else if (ASIC_IS_AVIVO(rdev))
1281 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1283 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1286 /* properly set additional regs when using atombios */
1287 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1289 struct drm_device *dev = crtc->dev;
1290 struct radeon_device *rdev = dev->dev_private;
1291 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1292 u32 disp_merge_cntl;
1294 switch (radeon_crtc->crtc_id) {
1296 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1297 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1298 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1301 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1302 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1303 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1304 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1305 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1310 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1312 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1313 struct drm_device *dev = crtc->dev;
1314 struct radeon_device *rdev = dev->dev_private;
1315 struct drm_encoder *test_encoder;
1316 struct drm_crtc *test_crtc;
1317 uint32_t pll_in_use = 0;
1319 if (ASIC_IS_DCE4(rdev)) {
1320 /* if crtc is driving DP and we have an ext clock, use that */
1321 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1322 if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1323 if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
1324 if (rdev->clock.dp_extclk)
1325 return ATOM_PPLL_INVALID;
1330 /* otherwise, pick one of the plls */
1331 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1332 struct radeon_crtc *radeon_test_crtc;
1334 if (crtc == test_crtc)
1337 radeon_test_crtc = to_radeon_crtc(test_crtc);
1338 if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1339 (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1340 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1342 if (!(pll_in_use & 1))
1346 return radeon_crtc->crtc_id;
1350 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1351 struct drm_display_mode *mode,
1352 struct drm_display_mode *adjusted_mode,
1353 int x, int y, struct drm_framebuffer *old_fb)
1355 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1356 struct drm_device *dev = crtc->dev;
1357 struct radeon_device *rdev = dev->dev_private;
1358 struct drm_encoder *encoder;
1359 bool is_tvcv = false;
1361 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1363 if (encoder->crtc == crtc) {
1364 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1365 if (radeon_encoder->active_device &
1366 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1371 /* always set DCPLL */
1372 if (ASIC_IS_DCE4(rdev)) {
1373 struct radeon_atom_ss ss;
1374 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1375 ASIC_INTERNAL_SS_ON_DCPLL,
1376 rdev->clock.default_dispclk);
1378 atombios_crtc_program_ss(crtc, ATOM_DISABLE, ATOM_DCPLL, &ss);
1379 atombios_crtc_set_dcpll(crtc);
1381 atombios_crtc_program_ss(crtc, ATOM_ENABLE, ATOM_DCPLL, &ss);
1383 atombios_crtc_set_pll(crtc, adjusted_mode);
1385 if (ASIC_IS_DCE4(rdev))
1386 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1387 else if (ASIC_IS_AVIVO(rdev)) {
1389 atombios_crtc_set_timing(crtc, adjusted_mode);
1391 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1393 atombios_crtc_set_timing(crtc, adjusted_mode);
1394 if (radeon_crtc->crtc_id == 0)
1395 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1396 radeon_legacy_atom_fixup(crtc);
1398 atombios_crtc_set_base(crtc, x, y, old_fb);
1399 atombios_overscan_setup(crtc, mode, adjusted_mode);
1400 atombios_scaler_setup(crtc);
1404 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1405 struct drm_display_mode *mode,
1406 struct drm_display_mode *adjusted_mode)
1408 struct drm_device *dev = crtc->dev;
1409 struct radeon_device *rdev = dev->dev_private;
1411 /* adjust pm to upcoming mode change */
1412 radeon_pm_compute_clocks(rdev);
1414 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1419 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1421 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1424 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1426 atombios_lock_crtc(crtc, ATOM_ENABLE);
1427 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1430 static void atombios_crtc_commit(struct drm_crtc *crtc)
1432 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1433 atombios_lock_crtc(crtc, ATOM_DISABLE);
1436 static void atombios_crtc_disable(struct drm_crtc *crtc)
1438 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1439 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1441 switch (radeon_crtc->pll_id) {
1444 /* disable the ppll */
1445 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1446 0, 0, ATOM_DISABLE, 0, 0, 0, 0);
1451 radeon_crtc->pll_id = -1;
1454 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1455 .dpms = atombios_crtc_dpms,
1456 .mode_fixup = atombios_crtc_mode_fixup,
1457 .mode_set = atombios_crtc_mode_set,
1458 .mode_set_base = atombios_crtc_set_base,
1459 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1460 .prepare = atombios_crtc_prepare,
1461 .commit = atombios_crtc_commit,
1462 .load_lut = radeon_crtc_load_lut,
1463 .disable = atombios_crtc_disable,
1466 void radeon_atombios_init_crtc(struct drm_device *dev,
1467 struct radeon_crtc *radeon_crtc)
1469 struct radeon_device *rdev = dev->dev_private;
1471 if (ASIC_IS_DCE4(rdev)) {
1472 switch (radeon_crtc->crtc_id) {
1475 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1478 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1481 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1484 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1487 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1490 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1494 if (radeon_crtc->crtc_id == 1)
1495 radeon_crtc->crtc_offset =
1496 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1498 radeon_crtc->crtc_offset = 0;
1500 radeon_crtc->pll_id = -1;
1501 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);