drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26 #include <drm/drmP.h>
  27 #include <drm/drm_crtc_helper.h>
  28 #include <drm/radeon_drm.h>
  29 #include "radeon.h"
  30 #include "atom.h"
  31 #include <linux/backlight.h>
  32
  33 extern int atom_debug;
  34
  35 static u8
  36 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  37 {
  38         u8 backlight_level;
  39         u32 bios_2_scratch;
  40
  41         if (rdev->family >= CHIP_R600)
  42                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  43         else
  44                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  45
  46         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  47                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  48
  49         return backlight_level;
  50 }
  51
  52 static void
  53 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  54                                        u8 backlight_level)
  55 {
  56         u32 bios_2_scratch;
  57
  58         if (rdev->family >= CHIP_R600)
  59                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  60         else
  61                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  62
  63         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  64         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  65                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
  66
  67         if (rdev->family >= CHIP_R600)
  68                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  69         else
  70                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  71 }
  72
  73 u8
  74 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  75 {
  76         struct drm_device *dev = radeon_encoder->base.dev;
  77         struct radeon_device *rdev = dev->dev_private;
  78
  79         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  80                 return 0;
  81
  82         return radeon_atom_get_backlight_level_from_reg(rdev);
  83 }
  84
  85 void
  86 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  87 {
  88         struct drm_encoder *encoder = &radeon_encoder->base;
  89         struct drm_device *dev = radeon_encoder->base.dev;
  90         struct radeon_device *rdev = dev->dev_private;
  91         struct radeon_encoder_atom_dig *dig;
  92         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
  93         int index;
  94
  95         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  96                 return;
  97
  98         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
  99             radeon_encoder->enc_priv) {
 100                 dig = radeon_encoder->enc_priv;
 101                 dig->backlight_level = level;
 102                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 103
 104                 switch (radeon_encoder->encoder_id) {
 105                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 106                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 107                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 108                         if (dig->backlight_level == 0) {
 109                                 args.ucAction = ATOM_LCD_BLOFF;
 110                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 111                         } else {
 112                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 113                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 114                                 args.ucAction = ATOM_LCD_BLON;
 115                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 116                         }
 117                         break;
 118                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 119                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 120                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 121                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 122                         if (dig->backlight_level == 0)
 123                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 124                         else {
 125                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 126                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 127                         }
 128                         break;
 129                 default:
 130                         break;
 131                 }
 132         }
 133 }
 134
 135 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 136
 137 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 138 {
 139         u8 level;
 140
 141         /* Convert brightness to hardware level */
 142         if (bd->props.brightness < 0)
 143                 level = 0;
 144         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 145                 level = RADEON_MAX_BL_LEVEL;
 146         else
 147                 level = bd->props.brightness;
 148
 149         return level;
 150 }
 151
 152 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 153 {
 154         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 155         struct radeon_encoder *radeon_encoder = pdata->encoder;
 156
 157         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 158
 159         return 0;
 160 }
 161
 162 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 163 {
 164         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 165         struct radeon_encoder *radeon_encoder = pdata->encoder;
 166         struct drm_device *dev = radeon_encoder->base.dev;
 167         struct radeon_device *rdev = dev->dev_private;
 168
 169         return radeon_atom_get_backlight_level_from_reg(rdev);
 170 }
 171
 172 static const struct backlight_ops radeon_atom_backlight_ops = {
 173         .get_brightness = radeon_atom_backlight_get_brightness,
 174         .update_status  = radeon_atom_backlight_update_status,
 175 };
 176
 177 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 178                                 struct drm_connector *drm_connector)
 179 {
 180         struct drm_device *dev = radeon_encoder->base.dev;
 181         struct radeon_device *rdev = dev->dev_private;
 182         struct backlight_device *bd;
 183         struct backlight_properties props;
 184         struct radeon_backlight_privdata *pdata;
 185         struct radeon_encoder_atom_dig *dig;
 186         u8 backlight_level;
 187         char bl_name[16];
 188
 189         /* Mac laptops with multiple GPUs use the gmux driver for backlight
 190          * so don't register a backlight device
 191          */
 192         if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 193             (rdev->pdev->device == 0x6741))
 194                 return;
 195
 196         if (!radeon_encoder->enc_priv)
 197                 return;
 198
 199         if (!rdev->is_atom_bios)
 200                 return;
 201
 202         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 203                 return;
 204
 205         pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 206         if (!pdata) {
 207                 DRM_ERROR("Memory allocation failed\n");
 208                 goto error;
 209         }
 210
 211         memset(&props, 0, sizeof(props));
 212         props.max_brightness = RADEON_MAX_BL_LEVEL;
 213         props.type = BACKLIGHT_RAW;
 214         snprintf(bl_name, sizeof(bl_name),
 215                  "radeon_bl%d", dev->primary->index);
 216         bd = backlight_device_register(bl_name, drm_connector->kdev,
 217                                        pdata, &radeon_atom_backlight_ops, &props);
 218         if (IS_ERR(bd)) {
 219                 DRM_ERROR("Backlight registration failed\n");
 220                 goto error;
 221         }
 222
 223         pdata->encoder = radeon_encoder;
 224
 225         backlight_level = radeon_atom_get_backlight_level_from_reg(rdev);
 226
 227         dig = radeon_encoder->enc_priv;
 228         dig->bl_dev = bd;
 229
 230         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 231         bd->props.power = FB_BLANK_UNBLANK;
 232         backlight_update_status(bd);
 233
 234         DRM_INFO("radeon atom DIG backlight initialized\n");
 235
 236         return;
 237
 238 error:
 239         kfree(pdata);
 240         return;
 241 }
 242
 243 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 244 {
 245         struct drm_device *dev = radeon_encoder->base.dev;
 246         struct radeon_device *rdev = dev->dev_private;
 247         struct backlight_device *bd = NULL;
 248         struct radeon_encoder_atom_dig *dig;
 249
 250         if (!radeon_encoder->enc_priv)
 251                 return;
 252
 253         if (!rdev->is_atom_bios)
 254                 return;
 255
 256         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 257                 return;
 258
 259         dig = radeon_encoder->enc_priv;
 260         bd = dig->bl_dev;
 261         dig->bl_dev = NULL;
 262
 263         if (bd) {
 264                 struct radeon_legacy_backlight_privdata *pdata;
 265
 266                 pdata = bl_get_data(bd);
 267                 backlight_device_unregister(bd);
 268                 kfree(pdata);
 269
 270                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
 271         }
 272 }
 273
 274 #else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 275
 276 void radeon_atom_backlight_init(struct radeon_encoder *encoder)
 277 {
 278 }
 279
 280 static void radeon_atom_backlight_exit(struct radeon_encoder *encoder)
 281 {
 282 }
 283
 284 #endif
 285
 286 /* evil but including atombios.h is much worse */
 287 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
 288                                 struct drm_display_mode *mode);
 289
 290
 291 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
 292 {
 293         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 294         switch (radeon_encoder->encoder_id) {
 295         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 296         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 297         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 298         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 299         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
 300         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
 301         case ENCODER_OBJECT_ID_INTERNAL_DDI:
 302         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 303         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 304         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 305         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 306         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
 307                 return true;
 308         default:
 309                 return false;
 310         }
 311 }
 312
 313 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 314                                    const struct drm_display_mode *mode,
 315                                    struct drm_display_mode *adjusted_mode)
 316 {
 317         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 318         struct drm_device *dev = encoder->dev;
 319         struct radeon_device *rdev = dev->dev_private;
 320
 321         /* set the active encoder to connector routing */
 322         radeon_encoder_set_active_device(encoder);
 323         drm_mode_set_crtcinfo(adjusted_mode, 0);
 324
 325         /* hw bug */
 326         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 327             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 328                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 329
 330         /* get the native mode for LVDS */
 331         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 332                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 333
 334         /* get the native mode for TV */
 335         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 336                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 337                 if (tv_dac) {
 338                         if (tv_dac->tv_std == TV_STD_NTSC ||
 339                             tv_dac->tv_std == TV_STD_NTSC_J ||
 340                             tv_dac->tv_std == TV_STD_PAL_M)
 341                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 342                         else
 343                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 344                 }
 345         }
 346
 347         if (ASIC_IS_DCE3(rdev) &&
 348             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 349              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 350                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 351                 radeon_dp_set_link_config(connector, adjusted_mode);
 352         }
 353
 354         return true;
 355 }
 356
 357 static void
 358 atombios_dac_setup(struct drm_encoder *encoder, int action)
 359 {
 360         struct drm_device *dev = encoder->dev;
 361         struct radeon_device *rdev = dev->dev_private;
 362         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 363         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 364         int index = 0;
 365         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 366
 367         memset(&args, 0, sizeof(args));
 368
 369         switch (radeon_encoder->encoder_id) {
 370         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 371         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 372                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 373                 break;
 374         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 375         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 376                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 377                 break;
 378         }
 379
 380         args.ucAction = action;
 381
 382         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 383                 args.ucDacStandard = ATOM_DAC1_PS2;
 384         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 385                 args.ucDacStandard = ATOM_DAC1_CV;
 386         else {
 387                 switch (dac_info->tv_std) {
 388                 case TV_STD_PAL:
 389                 case TV_STD_PAL_M:
 390                 case TV_STD_SCART_PAL:
 391                 case TV_STD_SECAM:
 392                 case TV_STD_PAL_CN:
 393                         args.ucDacStandard = ATOM_DAC1_PAL;
 394                         break;
 395                 case TV_STD_NTSC:
 396                 case TV_STD_NTSC_J:
 397                 case TV_STD_PAL_60:
 398                 default:
 399                         args.ucDacStandard = ATOM_DAC1_NTSC;
 400                         break;
 401                 }
 402         }
 403         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 404
 405         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 406
 407 }
 408
 409 static void
 410 atombios_tv_setup(struct drm_encoder *encoder, int action)
 411 {
 412         struct drm_device *dev = encoder->dev;
 413         struct radeon_device *rdev = dev->dev_private;
 414         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 415         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 416         int index = 0;
 417         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 418
 419         memset(&args, 0, sizeof(args));
 420
 421         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 422
 423         args.sTVEncoder.ucAction = action;
 424
 425         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 426                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 427         else {
 428                 switch (dac_info->tv_std) {
 429                 case TV_STD_NTSC:
 430                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 431                         break;
 432                 case TV_STD_PAL:
 433                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 434                         break;
 435                 case TV_STD_PAL_M:
 436                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 437                         break;
 438                 case TV_STD_PAL_60:
 439                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 440                         break;
 441                 case TV_STD_NTSC_J:
 442                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 443                         break;
 444                 case TV_STD_SCART_PAL:
 445                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 446                         break;
 447                 case TV_STD_SECAM:
 448                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 449                         break;
 450                 case TV_STD_PAL_CN:
 451                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 452                         break;
 453                 default:
 454                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 455                         break;
 456                 }
 457         }
 458
 459         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 460
 461         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 462
 463 }
 464
 465 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 466 {
 467         int bpc = 8;
 468
 469         if (encoder->crtc) {
 470                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 471                 bpc = radeon_crtc->bpc;
 472         }
 473
 474         switch (bpc) {
 475         case 0:
 476                 return PANEL_BPC_UNDEFINE;
 477         case 6:
 478                 return PANEL_6BIT_PER_COLOR;
 479         case 8:
 480         default:
 481                 return PANEL_8BIT_PER_COLOR;
 482         case 10:
 483                 return PANEL_10BIT_PER_COLOR;
 484         case 12:
 485                 return PANEL_12BIT_PER_COLOR;
 486         case 16:
 487                 return PANEL_16BIT_PER_COLOR;
 488         }
 489 }
 490
 491 union dvo_encoder_control {
 492         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 493         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 494         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 495         DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
 496 };
 497
 498 void
 499 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 500 {
 501         struct drm_device *dev = encoder->dev;
 502         struct radeon_device *rdev = dev->dev_private;
 503         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 504         union dvo_encoder_control args;
 505         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 506         uint8_t frev, crev;
 507
 508         memset(&args, 0, sizeof(args));
 509
 510         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 511                 return;
 512
 513         /* some R4xx chips have the wrong frev */
 514         if (rdev->family <= CHIP_RV410)
 515                 frev = 1;
 516
 517         switch (frev) {
 518         case 1:
 519                 switch (crev) {
 520                 case 1:
 521                         /* R4xx, R5xx */
 522                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 523
 524                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 525                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 526
 527                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 528                         break;
 529                 case 2:
 530                         /* RS600/690/740 */
 531                         args.dvo.sDVOEncoder.ucAction = action;
 532                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 533                         /* DFP1, CRT1, TV1 depending on the type of port */
 534                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 535
 536                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 537                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 538                         break;
 539                 case 3:
 540                         /* R6xx */
 541                         args.dvo_v3.ucAction = action;
 542                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 543                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 544                         break;
 545                 case 4:
 546                         /* DCE8 */
 547                         args.dvo_v4.ucAction = action;
 548                         args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 549                         args.dvo_v4.ucDVOConfig = 0; /* XXX */
 550                         args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 551                         break;
 552                 default:
 553                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 554                         break;
 555                 }
 556                 break;
 557         default:
 558                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 559                 break;
 560         }
 561
 562         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 563 }
 564
 565 union lvds_encoder_control {
 566         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 567         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 568 };
 569
 570 void
 571 atombios_digital_setup(struct drm_encoder *encoder, int action)
 572 {
 573         struct drm_device *dev = encoder->dev;
 574         struct radeon_device *rdev = dev->dev_private;
 575         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 576         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 577         union lvds_encoder_control args;
 578         int index = 0;
 579         int hdmi_detected = 0;
 580         uint8_t frev, crev;
 581
 582         if (!dig)
 583                 return;
 584
 585         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 586                 hdmi_detected = 1;
 587
 588         memset(&args, 0, sizeof(args));
 589
 590         switch (radeon_encoder->encoder_id) {
 591         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 592                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 593                 break;
 594         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 595         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 596                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 597                 break;
 598         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 599                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 600                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 601                 else
 602                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 603                 break;
 604         }
 605
 606         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 607                 return;
 608
 609         switch (frev) {
 610         case 1:
 611         case 2:
 612                 switch (crev) {
 613                 case 1:
 614                         args.v1.ucMisc = 0;
 615                         args.v1.ucAction = action;
 616                         if (hdmi_detected)
 617                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 618                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 619                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 620                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 621                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 622                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 623                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 624                         } else {
 625                                 if (dig->linkb)
 626                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 627                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 628                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 629                                 /*if (pScrn->rgbBits == 8) */
 630                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 631                         }
 632                         break;
 633                 case 2:
 634                 case 3:
 635                         args.v2.ucMisc = 0;
 636                         args.v2.ucAction = action;
 637                         if (crev == 3) {
 638                                 if (dig->coherent_mode)
 639                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 640                         }
 641                         if (hdmi_detected)
 642                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 643                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 644                         args.v2.ucTruncate = 0;
 645                         args.v2.ucSpatial = 0;
 646                         args.v2.ucTemporal = 0;
 647                         args.v2.ucFRC = 0;
 648                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 649                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 650                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 651                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 652                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 653                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 654                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 655                                 }
 656                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 657                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 658                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 659                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 660                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 661                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 662                                 }
 663                         } else {
 664                                 if (dig->linkb)
 665                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 666                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 667                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 668                         }
 669                         break;
 670                 default:
 671                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 672                         break;
 673                 }
 674                 break;
 675         default:
 676                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 677                 break;
 678         }
 679
 680         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 681 }
 682
 683 int
 684 atombios_get_encoder_mode(struct drm_encoder *encoder)
 685 {
 686         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 687         struct drm_connector *connector;
 688         struct radeon_connector *radeon_connector;
 689         struct radeon_connector_atom_dig *dig_connector;
 690
 691         /* dp bridges are always DP */
 692         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 693                 return ATOM_ENCODER_MODE_DP;
 694
 695         /* DVO is always DVO */
 696         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 697             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 698                 return ATOM_ENCODER_MODE_DVO;
 699
 700         connector = radeon_get_connector_for_encoder(encoder);
 701         /* if we don't have an active device yet, just use one of
 702          * the connectors tied to the encoder.
 703          */
 704         if (!connector)
 705                 connector = radeon_get_connector_for_encoder_init(encoder);
 706         radeon_connector = to_radeon_connector(connector);
 707
 708         switch (connector->connector_type) {
 709         case DRM_MODE_CONNECTOR_DVII:
 710         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 711                 if (radeon_audio != 0) {
 712                         if (radeon_connector->use_digital &&
 713                             (radeon_connector->audio == RADEON_AUDIO_ENABLE))
 714                                 return ATOM_ENCODER_MODE_HDMI;
 715                         else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 716                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 717                                 return ATOM_ENCODER_MODE_HDMI;
 718                         else if (radeon_connector->use_digital)
 719                                 return ATOM_ENCODER_MODE_DVI;
 720                         else
 721                                 return ATOM_ENCODER_MODE_CRT;
 722                 } else if (radeon_connector->use_digital) {
 723                         return ATOM_ENCODER_MODE_DVI;
 724                 } else {
 725                         return ATOM_ENCODER_MODE_CRT;
 726                 }
 727                 break;
 728         case DRM_MODE_CONNECTOR_DVID:
 729         case DRM_MODE_CONNECTOR_HDMIA:
 730         default:
 731                 if (radeon_audio != 0) {
 732                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 733                                 return ATOM_ENCODER_MODE_HDMI;
 734                         else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 735                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 736                                 return ATOM_ENCODER_MODE_HDMI;
 737                         else
 738                                 return ATOM_ENCODER_MODE_DVI;
 739                 } else {
 740                         return ATOM_ENCODER_MODE_DVI;
 741                 }
 742                 break;
 743         case DRM_MODE_CONNECTOR_LVDS:
 744                 return ATOM_ENCODER_MODE_LVDS;
 745                 break;
 746         case DRM_MODE_CONNECTOR_DisplayPort:
 747                 dig_connector = radeon_connector->con_priv;
 748                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 749                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 750                         return ATOM_ENCODER_MODE_DP;
 751                 } else if (radeon_audio != 0) {
 752                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 753                                 return ATOM_ENCODER_MODE_HDMI;
 754                         else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
 755                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 756                                 return ATOM_ENCODER_MODE_HDMI;
 757                         else
 758                                 return ATOM_ENCODER_MODE_DVI;
 759                 } else {
 760                         return ATOM_ENCODER_MODE_DVI;
 761                 }
 762                 break;
 763         case DRM_MODE_CONNECTOR_eDP:
 764                 return ATOM_ENCODER_MODE_DP;
 765         case DRM_MODE_CONNECTOR_DVIA:
 766         case DRM_MODE_CONNECTOR_VGA:
 767                 return ATOM_ENCODER_MODE_CRT;
 768                 break;
 769         case DRM_MODE_CONNECTOR_Composite:
 770         case DRM_MODE_CONNECTOR_SVIDEO:
 771         case DRM_MODE_CONNECTOR_9PinDIN:
 772                 /* fix me */
 773                 return ATOM_ENCODER_MODE_TV;
 774                 /*return ATOM_ENCODER_MODE_CV;*/
 775                 break;
 776         }
 777 }
 778
 779 /*
 780  * DIG Encoder/Transmitter Setup
 781  *
 782  * DCE 3.0/3.1
 783  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 784  * Supports up to 3 digital outputs
 785  * - 2 DIG encoder blocks.
 786  * DIG1 can drive UNIPHY link A or link B
 787  * DIG2 can drive UNIPHY link B or LVTMA
 788  *
 789  * DCE 3.2
 790  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 791  * Supports up to 5 digital outputs
 792  * - 2 DIG encoder blocks.
 793  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 794  *
 795  * DCE 4.0/5.0/6.0
 796  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 797  * Supports up to 6 digital outputs
 798  * - 6 DIG encoder blocks.
 799  * - DIG to PHY mapping is hardcoded
 800  * DIG1 drives UNIPHY0 link A, A+B
 801  * DIG2 drives UNIPHY0 link B
 802  * DIG3 drives UNIPHY1 link A, A+B
 803  * DIG4 drives UNIPHY1 link B
 804  * DIG5 drives UNIPHY2 link A, A+B
 805  * DIG6 drives UNIPHY2 link B
 806  *
 807  * DCE 4.1
 808  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 809  * Supports up to 6 digital outputs
 810  * - 2 DIG encoder blocks.
 811  * llano
 812  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 813  * ontario
 814  * DIG1 drives UNIPHY0/1/2 link A
 815  * DIG2 drives UNIPHY0/1/2 link B
 816  *
 817  * Routing
 818  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 819  * Examples:
 820  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 821  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 822  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 823  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 824  */
 825
 826 union dig_encoder_control {
 827         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 828         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 829         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 830         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 831 };
 832
 833 void
 834 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 835 {
 836         struct drm_device *dev = encoder->dev;
 837         struct radeon_device *rdev = dev->dev_private;
 838         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 839         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 840         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 841         union dig_encoder_control args;
 842         int index = 0;
 843         uint8_t frev, crev;
 844         int dp_clock = 0;
 845         int dp_lane_count = 0;
 846         int hpd_id = RADEON_HPD_NONE;
 847
 848         if (connector) {
 849                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 850                 struct radeon_connector_atom_dig *dig_connector =
 851                         radeon_connector->con_priv;
 852
 853                 dp_clock = dig_connector->dp_clock;
 854                 dp_lane_count = dig_connector->dp_lane_count;
 855                 hpd_id = radeon_connector->hpd.hpd;
 856         }
 857
 858         /* no dig encoder assigned */
 859         if (dig->dig_encoder == -1)
 860                 return;
 861
 862         memset(&args, 0, sizeof(args));
 863
 864         if (ASIC_IS_DCE4(rdev))
 865                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 866         else {
 867                 if (dig->dig_encoder)
 868                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 869                 else
 870                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 871         }
 872
 873         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 874                 return;
 875
 876         switch (frev) {
 877         case 1:
 878                 switch (crev) {
 879                 case 1:
 880                         args.v1.ucAction = action;
 881                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 882                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 883                                 args.v3.ucPanelMode = panel_mode;
 884                         else
 885                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 886
 887                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 888                                 args.v1.ucLaneNum = dp_lane_count;
 889                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 890                                 args.v1.ucLaneNum = 8;
 891                         else
 892                                 args.v1.ucLaneNum = 4;
 893
 894                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 895                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 896                         switch (radeon_encoder->encoder_id) {
 897                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 898                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 899                                 break;
 900                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 901                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 902                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 903                                 break;
 904                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 905                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 906                                 break;
 907                         }
 908                         if (dig->linkb)
 909                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 910                         else
 911                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 912                         break;
 913                 case 2:
 914                 case 3:
 915                         args.v3.ucAction = action;
 916                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 917                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 918                                 args.v3.ucPanelMode = panel_mode;
 919                         else
 920                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 921
 922                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 923                                 args.v3.ucLaneNum = dp_lane_count;
 924                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 925                                 args.v3.ucLaneNum = 8;
 926                         else
 927                                 args.v3.ucLaneNum = 4;
 928
 929                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 930                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 931                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
 932                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 933                         break;
 934                 case 4:
 935                         args.v4.ucAction = action;
 936                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 937                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 938                                 args.v4.ucPanelMode = panel_mode;
 939                         else
 940                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 941
 942                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 943                                 args.v4.ucLaneNum = dp_lane_count;
 944                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 945                                 args.v4.ucLaneNum = 8;
 946                         else
 947                                 args.v4.ucLaneNum = 4;
 948
 949                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 950                                 if (dp_clock == 540000)
 951                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 952                                 else if (dp_clock == 324000)
 953                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
 954                                 else if (dp_clock == 270000)
 955                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 956                                 else
 957                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
 958                         }
 959                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
 960                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 961                         if (hpd_id == RADEON_HPD_NONE)
 962                                 args.v4.ucHPD_ID = 0;
 963                         else
 964                                 args.v4.ucHPD_ID = hpd_id + 1;
 965                         break;
 966                 default:
 967                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 968                         break;
 969                 }
 970                 break;
 971         default:
 972                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 973                 break;
 974         }
 975
 976         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 977
 978 }
 979
 980 union dig_transmitter_control {
 981         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 982         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 983         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 984         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 985         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
 986 };
 987
 988 void
 989 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
 990 {
 991         struct drm_device *dev = encoder->dev;
 992         struct radeon_device *rdev = dev->dev_private;
 993         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 994         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 995         struct drm_connector *connector;
 996         union dig_transmitter_control args;
 997         int index = 0;
 998         uint8_t frev, crev;
 999         bool is_dp = false;
1000         int pll_id = 0;
1001         int dp_clock = 0;
1002         int dp_lane_count = 0;
1003         int connector_object_id = 0;
1004         int igp_lane_info = 0;
1005         int dig_encoder = dig->dig_encoder;
1006         int hpd_id = RADEON_HPD_NONE;
1007
1008         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1009                 connector = radeon_get_connector_for_encoder_init(encoder);
1010                 /* just needed to avoid bailing in the encoder check.  the encoder
1011                  * isn't used for init
1012                  */
1013                 dig_encoder = 0;
1014         } else
1015                 connector = radeon_get_connector_for_encoder(encoder);
1016
1017         if (connector) {
1018                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1019                 struct radeon_connector_atom_dig *dig_connector =
1020                         radeon_connector->con_priv;
1021
1022                 hpd_id = radeon_connector->hpd.hpd;
1023                 dp_clock = dig_connector->dp_clock;
1024                 dp_lane_count = dig_connector->dp_lane_count;
1025                 connector_object_id =
1026                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1027                 igp_lane_info = dig_connector->igp_lane_info;
1028         }
1029
1030         if (encoder->crtc) {
1031                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1032                 pll_id = radeon_crtc->pll_id;
1033         }
1034
1035         /* no dig encoder assigned */
1036         if (dig_encoder == -1)
1037                 return;
1038
1039         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1040                 is_dp = true;
1041
1042         memset(&args, 0, sizeof(args));
1043
1044         switch (radeon_encoder->encoder_id) {
1045         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1046                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1047                 break;
1048         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1049         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1050         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1051         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1052                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1053                 break;
1054         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1055                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1056                 break;
1057         }
1058
1059         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1060                 return;
1061
1062         switch (frev) {
1063         case 1:
1064                 switch (crev) {
1065                 case 1:
1066                         args.v1.ucAction = action;
1067                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1068                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1069                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1070                                 args.v1.asMode.ucLaneSel = lane_num;
1071                                 args.v1.asMode.ucLaneSet = lane_set;
1072                         } else {
1073                                 if (is_dp)
1074                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1075                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1076                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1077                                 else
1078                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1079                         }
1080
1081                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1082
1083                         if (dig_encoder)
1084                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1085                         else
1086                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1087
1088                         if ((rdev->flags & RADEON_IS_IGP) &&
1089                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1090                                 if (is_dp ||
1091                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1092                                         if (igp_lane_info & 0x1)
1093                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1094                                         else if (igp_lane_info & 0x2)
1095                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1096                                         else if (igp_lane_info & 0x4)
1097                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1098                                         else if (igp_lane_info & 0x8)
1099                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1100                                 } else {
1101                                         if (igp_lane_info & 0x3)
1102                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1103                                         else if (igp_lane_info & 0xc)
1104                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1105                                 }
1106                         }
1107
1108                         if (dig->linkb)
1109                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1110                         else
1111                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1112
1113                         if (is_dp)
1114                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1115                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1116                                 if (dig->coherent_mode)
1117                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1118                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1119                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1120                         }
1121                         break;
1122                 case 2:
1123                         args.v2.ucAction = action;
1124                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1125                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1126                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1127                                 args.v2.asMode.ucLaneSel = lane_num;
1128                                 args.v2.asMode.ucLaneSet = lane_set;
1129                         } else {
1130                                 if (is_dp)
1131                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1132                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1133                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1134                                 else
1135                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1136                         }
1137
1138                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1139                         if (dig->linkb)
1140                                 args.v2.acConfig.ucLinkSel = 1;
1141
1142                         switch (radeon_encoder->encoder_id) {
1143                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1144                                 args.v2.acConfig.ucTransmitterSel = 0;
1145                                 break;
1146                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1147                                 args.v2.acConfig.ucTransmitterSel = 1;
1148                                 break;
1149                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1150                                 args.v2.acConfig.ucTransmitterSel = 2;
1151                                 break;
1152                         }
1153
1154                         if (is_dp) {
1155                                 args.v2.acConfig.fCoherentMode = 1;
1156                                 args.v2.acConfig.fDPConnector = 1;
1157                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1158                                 if (dig->coherent_mode)
1159                                         args.v2.acConfig.fCoherentMode = 1;
1160                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1161                                         args.v2.acConfig.fDualLinkConnector = 1;
1162                         }
1163                         break;
1164                 case 3:
1165                         args.v3.ucAction = action;
1166                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1167                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1168                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1169                                 args.v3.asMode.ucLaneSel = lane_num;
1170                                 args.v3.asMode.ucLaneSet = lane_set;
1171                         } else {
1172                                 if (is_dp)
1173                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1174                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1175                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1176                                 else
1177                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1178                         }
1179
1180                         if (is_dp)
1181                                 args.v3.ucLaneNum = dp_lane_count;
1182                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1183                                 args.v3.ucLaneNum = 8;
1184                         else
1185                                 args.v3.ucLaneNum = 4;
1186
1187                         if (dig->linkb)
1188                                 args.v3.acConfig.ucLinkSel = 1;
1189                         if (dig_encoder & 1)
1190                                 args.v3.acConfig.ucEncoderSel = 1;
1191
1192                         /* Select the PLL for the PHY
1193                          * DP PHY should be clocked from external src if there is
1194                          * one.
1195                          */
1196                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1197                         if (is_dp && rdev->clock.dp_extclk)
1198                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1199                         else
1200                                 args.v3.acConfig.ucRefClkSource = pll_id;
1201
1202                         switch (radeon_encoder->encoder_id) {
1203                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1204                                 args.v3.acConfig.ucTransmitterSel = 0;
1205                                 break;
1206                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1207                                 args.v3.acConfig.ucTransmitterSel = 1;
1208                                 break;
1209                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1210                                 args.v3.acConfig.ucTransmitterSel = 2;
1211                                 break;
1212                         }
1213
1214                         if (is_dp)
1215                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1216                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1217                                 if (dig->coherent_mode)
1218                                         args.v3.acConfig.fCoherentMode = 1;
1219                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1220                                         args.v3.acConfig.fDualLinkConnector = 1;
1221                         }
1222                         break;
1223                 case 4:
1224                         args.v4.ucAction = action;
1225                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1226                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1227                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1228                                 args.v4.asMode.ucLaneSel = lane_num;
1229                                 args.v4.asMode.ucLaneSet = lane_set;
1230                         } else {
1231                                 if (is_dp)
1232                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1233                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1234                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1235                                 else
1236                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1237                         }
1238
1239                         if (is_dp)
1240                                 args.v4.ucLaneNum = dp_lane_count;
1241                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1242                                 args.v4.ucLaneNum = 8;
1243                         else
1244                                 args.v4.ucLaneNum = 4;
1245
1246                         if (dig->linkb)
1247                                 args.v4.acConfig.ucLinkSel = 1;
1248                         if (dig_encoder & 1)
1249                                 args.v4.acConfig.ucEncoderSel = 1;
1250
1251                         /* Select the PLL for the PHY
1252                          * DP PHY should be clocked from external src if there is
1253                          * one.
1254                          */
1255                         /* On DCE5 DCPLL usually generates the DP ref clock */
1256                         if (is_dp) {
1257                                 if (rdev->clock.dp_extclk)
1258                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1259                                 else
1260                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1261                         } else
1262                                 args.v4.acConfig.ucRefClkSource = pll_id;
1263
1264                         switch (radeon_encoder->encoder_id) {
1265                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1266                                 args.v4.acConfig.ucTransmitterSel = 0;
1267                                 break;
1268                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1269                                 args.v4.acConfig.ucTransmitterSel = 1;
1270                                 break;
1271                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1272                                 args.v4.acConfig.ucTransmitterSel = 2;
1273                                 break;
1274                         }
1275
1276                         if (is_dp)
1277                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1278                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1279                                 if (dig->coherent_mode)
1280                                         args.v4.acConfig.fCoherentMode = 1;
1281                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1282                                         args.v4.acConfig.fDualLinkConnector = 1;
1283                         }
1284                         break;
1285                 case 5:
1286                         args.v5.ucAction = action;
1287                         if (is_dp)
1288                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1289                         else
1290                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1291
1292                         switch (radeon_encoder->encoder_id) {
1293                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1294                                 if (dig->linkb)
1295                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1296                                 else
1297                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1298                                 break;
1299                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1300                                 if (dig->linkb)
1301                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1302                                 else
1303                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1304                                 break;
1305                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1306                                 if (dig->linkb)
1307                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1308                                 else
1309                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1310                                 break;
1311                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1312                                 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1313                                 break;
1314                         }
1315                         if (is_dp)
1316                                 args.v5.ucLaneNum = dp_lane_count;
1317                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1318                                 args.v5.ucLaneNum = 8;
1319                         else
1320                                 args.v5.ucLaneNum = 4;
1321                         args.v5.ucConnObjId = connector_object_id;
1322                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1323
1324                         if (is_dp && rdev->clock.dp_extclk)
1325                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1326                         else
1327                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1328
1329                         if (is_dp)
1330                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1331                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1332                                 if (dig->coherent_mode)
1333                                         args.v5.asConfig.ucCoherentMode = 1;
1334                         }
1335                         if (hpd_id == RADEON_HPD_NONE)
1336                                 args.v5.asConfig.ucHPDSel = 0;
1337                         else
1338                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1339                         args.v5.ucDigEncoderSel = 1 << dig_encoder;
1340                         args.v5.ucDPLaneSet = lane_set;
1341                         break;
1342                 default:
1343                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1344                         break;
1345                 }
1346                 break;
1347         default:
1348                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1349                 break;
1350         }
1351
1352         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1353 }
1354
1355 bool
1356 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1357 {
1358         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1359         struct drm_device *dev = radeon_connector->base.dev;
1360         struct radeon_device *rdev = dev->dev_private;
1361         union dig_transmitter_control args;
1362         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1363         uint8_t frev, crev;
1364
1365         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1366                 goto done;
1367
1368         if (!ASIC_IS_DCE4(rdev))
1369                 goto done;
1370
1371         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1372             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1373                 goto done;
1374
1375         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1376                 goto done;
1377
1378         memset(&args, 0, sizeof(args));
1379
1380         args.v1.ucAction = action;
1381
1382         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1383
1384         /* wait for the panel to power up */
1385         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1386                 int i;
1387
1388                 for (i = 0; i < 300; i++) {
1389                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1390                                 return true;
1391                         mdelay(1);
1392                 }
1393                 return false;
1394         }
1395 done:
1396         return true;
1397 }
1398
1399 union external_encoder_control {
1400         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1401         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1402 };
1403
1404 static void
1405 atombios_external_encoder_setup(struct drm_encoder *encoder,
1406                                 struct drm_encoder *ext_encoder,
1407                                 int action)
1408 {
1409         struct drm_device *dev = encoder->dev;
1410         struct radeon_device *rdev = dev->dev_private;
1411         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1412         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1413         union external_encoder_control args;
1414         struct drm_connector *connector;
1415         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1416         u8 frev, crev;
1417         int dp_clock = 0;
1418         int dp_lane_count = 0;
1419         int connector_object_id = 0;
1420         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1421
1422         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1423                 connector = radeon_get_connector_for_encoder_init(encoder);
1424         else
1425                 connector = radeon_get_connector_for_encoder(encoder);
1426
1427         if (connector) {
1428                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1429                 struct radeon_connector_atom_dig *dig_connector =
1430                         radeon_connector->con_priv;
1431
1432                 dp_clock = dig_connector->dp_clock;
1433                 dp_lane_count = dig_connector->dp_lane_count;
1434                 connector_object_id =
1435                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1436         }
1437
1438         memset(&args, 0, sizeof(args));
1439
1440         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1441                 return;
1442
1443         switch (frev) {
1444         case 1:
1445                 /* no params on frev 1 */
1446                 break;
1447         case 2:
1448                 switch (crev) {
1449                 case 1:
1450                 case 2:
1451                         args.v1.sDigEncoder.ucAction = action;
1452                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1453                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1454
1455                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1456                                 if (dp_clock == 270000)
1457                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1458                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1459                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1460                                 args.v1.sDigEncoder.ucLaneNum = 8;
1461                         else
1462                                 args.v1.sDigEncoder.ucLaneNum = 4;
1463                         break;
1464                 case 3:
1465                         args.v3.sExtEncoder.ucAction = action;
1466                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1467                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1468                         else
1469                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1470                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1471
1472                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1473                                 if (dp_clock == 270000)
1474                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1475                                 else if (dp_clock == 540000)
1476                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1477                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1478                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1479                                 args.v3.sExtEncoder.ucLaneNum = 8;
1480                         else
1481                                 args.v3.sExtEncoder.ucLaneNum = 4;
1482                         switch (ext_enum) {
1483                         case GRAPH_OBJECT_ENUM_ID1:
1484                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1485                                 break;
1486                         case GRAPH_OBJECT_ENUM_ID2:
1487                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1488                                 break;
1489                         case GRAPH_OBJECT_ENUM_ID3:
1490                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1491                                 break;
1492                         }
1493                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1494                         break;
1495                 default:
1496                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1497                         return;
1498                 }
1499                 break;
1500         default:
1501                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1502                 return;
1503         }
1504         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1505 }
1506
1507 static void
1508 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1509 {
1510         struct drm_device *dev = encoder->dev;
1511         struct radeon_device *rdev = dev->dev_private;
1512         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1513         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1514         ENABLE_YUV_PS_ALLOCATION args;
1515         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1516         uint32_t temp, reg;
1517
1518         memset(&args, 0, sizeof(args));
1519
1520         if (rdev->family >= CHIP_R600)
1521                 reg = R600_BIOS_3_SCRATCH;
1522         else
1523                 reg = RADEON_BIOS_3_SCRATCH;
1524
1525         /* XXX: fix up scratch reg handling */
1526         temp = RREG32(reg);
1527         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1528                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1529                              (radeon_crtc->crtc_id << 18)));
1530         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1531                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1532         else
1533                 WREG32(reg, 0);
1534
1535         if (enable)
1536                 args.ucEnable = ATOM_ENABLE;
1537         args.ucCRTC = radeon_crtc->crtc_id;
1538
1539         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1540
1541         WREG32(reg, temp);
1542 }
1543
1544 static void
1545 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1546 {
1547         struct drm_device *dev = encoder->dev;
1548         struct radeon_device *rdev = dev->dev_private;
1549         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1550         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1551         int index = 0;
1552
1553         memset(&args, 0, sizeof(args));
1554
1555         switch (radeon_encoder->encoder_id) {
1556         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1557         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1558                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1559                 break;
1560         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1561         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1562         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1563                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1564                 break;
1565         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1566                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1567                 break;
1568         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1569                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1570                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1571                 else
1572                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1573                 break;
1574         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1575         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1576                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1577                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1578                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1579                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1580                 else
1581                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1582                 break;
1583         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1584         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1585                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1586                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1587                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1588                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1589                 else
1590                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1591                 break;
1592         default:
1593                 return;
1594         }
1595
1596         switch (mode) {
1597         case DRM_MODE_DPMS_ON:
1598                 args.ucAction = ATOM_ENABLE;
1599                 /* workaround for DVOOutputControl on some RS690 systems */
1600                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1601                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1602                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1603                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1604                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1605                 } else
1606                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1607                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1608                         args.ucAction = ATOM_LCD_BLON;
1609                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1610                 }
1611                 break;
1612         case DRM_MODE_DPMS_STANDBY:
1613         case DRM_MODE_DPMS_SUSPEND:
1614         case DRM_MODE_DPMS_OFF:
1615                 args.ucAction = ATOM_DISABLE;
1616                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1617                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1618                         args.ucAction = ATOM_LCD_BLOFF;
1619                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1620                 }
1621                 break;
1622         }
1623 }
1624
1625 static void
1626 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1627 {
1628         struct drm_device *dev = encoder->dev;
1629         struct radeon_device *rdev = dev->dev_private;
1630         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1631         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1632         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1633         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1634         struct radeon_connector *radeon_connector = NULL;
1635         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1636         bool travis_quirk = false;
1637
1638         if (connector) {
1639                 radeon_connector = to_radeon_connector(connector);
1640                 radeon_dig_connector = radeon_connector->con_priv;
1641                 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1642                      ENCODER_OBJECT_ID_TRAVIS) &&
1643                     (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1644                     !ASIC_IS_DCE5(rdev))
1645                         travis_quirk = true;
1646         }
1647
1648         switch (mode) {
1649         case DRM_MODE_DPMS_ON:
1650                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1651                         if (!connector)
1652                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1653                         else
1654                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1655
1656                         /* setup and enable the encoder */
1657                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1658                         atombios_dig_encoder_setup(encoder,
1659                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1660                                                    dig->panel_mode);
1661                         if (ext_encoder) {
1662                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1663                                         atombios_external_encoder_setup(encoder, ext_encoder,
1664                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1665                         }
1666                 } else if (ASIC_IS_DCE4(rdev)) {
1667                         /* setup and enable the encoder */
1668                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1669                 } else {
1670                         /* setup and enable the encoder and transmitter */
1671                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1672                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1673                 }
1674                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1675                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1676                                 atombios_set_edp_panel_power(connector,
1677                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1678                                 radeon_dig_connector->edp_on = true;
1679                         }
1680                 }
1681                 /* enable the transmitter */
1682                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1683                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1684                         /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1685                         radeon_dp_link_train(encoder, connector);
1686                         if (ASIC_IS_DCE4(rdev))
1687                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1688                 }
1689                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1690                         atombios_dig_transmitter_setup(encoder,
1691                                                        ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1692                 if (ext_encoder)
1693                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1694                 break;
1695         case DRM_MODE_DPMS_STANDBY:
1696         case DRM_MODE_DPMS_SUSPEND:
1697         case DRM_MODE_DPMS_OFF:
1698                 if (ASIC_IS_DCE4(rdev)) {
1699                         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1700                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1701                 }
1702                 if (ext_encoder)
1703                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1704                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1705                         atombios_dig_transmitter_setup(encoder,
1706                                                        ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1707
1708                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1709                     connector && !travis_quirk)
1710                         radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1711                 if (ASIC_IS_DCE4(rdev)) {
1712                         /* disable the transmitter */
1713                         atombios_dig_transmitter_setup(encoder,
1714                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1715                 } else {
1716                         /* disable the encoder and transmitter */
1717                         atombios_dig_transmitter_setup(encoder,
1718                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1719                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1720                 }
1721                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1722                         if (travis_quirk)
1723                                 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1724                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1725                                 atombios_set_edp_panel_power(connector,
1726                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1727                                 radeon_dig_connector->edp_on = false;
1728                         }
1729                 }
1730                 break;
1731         }
1732 }
1733
1734 static void
1735 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1736 {
1737         struct drm_device *dev = encoder->dev;
1738         struct radeon_device *rdev = dev->dev_private;
1739         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1740
1741         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1742                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1743                   radeon_encoder->active_device);
1744         switch (radeon_encoder->encoder_id) {
1745         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1746         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1747         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1748         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1749         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1750         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1751         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1752         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1753                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1754                 break;
1755         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1756         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1757         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1758         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1759         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1760                 radeon_atom_encoder_dpms_dig(encoder, mode);
1761                 break;
1762         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1763                 if (ASIC_IS_DCE5(rdev)) {
1764                         switch (mode) {
1765                         case DRM_MODE_DPMS_ON:
1766                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1767                                 break;
1768                         case DRM_MODE_DPMS_STANDBY:
1769                         case DRM_MODE_DPMS_SUSPEND:
1770                         case DRM_MODE_DPMS_OFF:
1771                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1772                                 break;
1773                         }
1774                 } else if (ASIC_IS_DCE3(rdev))
1775                         radeon_atom_encoder_dpms_dig(encoder, mode);
1776                 else
1777                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1778                 break;
1779         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1780         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1781                 if (ASIC_IS_DCE5(rdev)) {
1782                         switch (mode) {
1783                         case DRM_MODE_DPMS_ON:
1784                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1785                                 break;
1786                         case DRM_MODE_DPMS_STANDBY:
1787                         case DRM_MODE_DPMS_SUSPEND:
1788                         case DRM_MODE_DPMS_OFF:
1789                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1790                                 break;
1791                         }
1792                 } else
1793                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1794                 break;
1795         default:
1796                 return;
1797         }
1798
1799         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1800
1801 }
1802
1803 union crtc_source_param {
1804         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1805         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1806 };
1807
1808 static void
1809 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1810 {
1811         struct drm_device *dev = encoder->dev;
1812         struct radeon_device *rdev = dev->dev_private;
1813         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1814         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1815         union crtc_source_param args;
1816         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1817         uint8_t frev, crev;
1818         struct radeon_encoder_atom_dig *dig;
1819
1820         memset(&args, 0, sizeof(args));
1821
1822         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1823                 return;
1824
1825         switch (frev) {
1826         case 1:
1827                 switch (crev) {
1828                 case 1:
1829                 default:
1830                         if (ASIC_IS_AVIVO(rdev))
1831                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1832                         else {
1833                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1834                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1835                                 } else {
1836                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1837                                 }
1838                         }
1839                         switch (radeon_encoder->encoder_id) {
1840                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1841                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1842                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1843                                 break;
1844                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1845                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1846                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1847                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1848                                 else
1849                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1850                                 break;
1851                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1852                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1853                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1854                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1855                                 break;
1856                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1857                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1858                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1859                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1860                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1861                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1862                                 else
1863                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1864                                 break;
1865                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1866                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1867                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1868                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1869                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1870                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1871                                 else
1872                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1873                                 break;
1874                         }
1875                         break;
1876                 case 2:
1877                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1878                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1879                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1880
1881                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1882                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1883                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1884                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1885                                 else
1886                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1887                         } else
1888                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1889                         switch (radeon_encoder->encoder_id) {
1890                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1891                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1892                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1893                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1894                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1895                                 dig = radeon_encoder->enc_priv;
1896                                 switch (dig->dig_encoder) {
1897                                 case 0:
1898                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1899                                         break;
1900                                 case 1:
1901                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1902                                         break;
1903                                 case 2:
1904                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1905                                         break;
1906                                 case 3:
1907                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1908                                         break;
1909                                 case 4:
1910                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1911                                         break;
1912                                 case 5:
1913                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1914                                         break;
1915                                 case 6:
1916                                         args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1917                                         break;
1918                                 }
1919                                 break;
1920                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1921                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1922                                 break;
1923                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1924                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1925                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1926                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1927                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1928                                 else
1929                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1930                                 break;
1931                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1932                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1933                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1934                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1935                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1936                                 else
1937                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1938                                 break;
1939                         }
1940                         break;
1941                 }
1942                 break;
1943         default:
1944                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1945                 return;
1946         }
1947
1948         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1949
1950         /* update scratch regs with new routing */
1951         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1952 }
1953
1954 static void
1955 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1956                               struct drm_display_mode *mode)
1957 {
1958         struct drm_device *dev = encoder->dev;
1959         struct radeon_device *rdev = dev->dev_private;
1960         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1961         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1962
1963         /* Funky macbooks */
1964         if ((dev->pdev->device == 0x71C5) &&
1965             (dev->pdev->subsystem_vendor == 0x106b) &&
1966             (dev->pdev->subsystem_device == 0x0080)) {
1967                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1968                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1969
1970                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1971                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1972
1973                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1974                 }
1975         }
1976
1977         /* set scaler clears this on some chips */
1978         if (ASIC_IS_AVIVO(rdev) &&
1979             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1980                 if (ASIC_IS_DCE8(rdev)) {
1981                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1982                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
1983                                        CIK_INTERLEAVE_EN);
1984                         else
1985                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1986                 } else if (ASIC_IS_DCE4(rdev)) {
1987                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1988                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1989                                        EVERGREEN_INTERLEAVE_EN);
1990                         else
1991                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1992                 } else {
1993                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1994                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1995                                        AVIVO_D1MODE_INTERLEAVE_EN);
1996                         else
1997                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1998                 }
1999         }
2000 }
2001
2002 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
2003 {
2004         struct drm_device *dev = encoder->dev;
2005         struct radeon_device *rdev = dev->dev_private;
2006         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2007         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2008         struct drm_encoder *test_encoder;
2009         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2010         uint32_t dig_enc_in_use = 0;
2011
2012         if (ASIC_IS_DCE6(rdev)) {
2013                 /* DCE6 */
2014                 switch (radeon_encoder->encoder_id) {
2015                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2016                         if (dig->linkb)
2017                                 return 1;
2018                         else
2019                                 return 0;
2020                         break;
2021                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2022                         if (dig->linkb)
2023                                 return 3;
2024                         else
2025                                 return 2;
2026                         break;
2027                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2028                         if (dig->linkb)
2029                                 return 5;
2030                         else
2031                                 return 4;
2032                         break;
2033                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2034                         return 6;
2035                         break;
2036                 }
2037         } else if (ASIC_IS_DCE4(rdev)) {
2038                 /* DCE4/5 */
2039                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2040                         /* ontario follows DCE4 */
2041                         if (rdev->family == CHIP_PALM) {
2042                                 if (dig->linkb)
2043                                         return 1;
2044                                 else
2045                                         return 0;
2046                         } else
2047                                 /* llano follows DCE3.2 */
2048                                 return radeon_crtc->crtc_id;
2049                 } else {
2050                         switch (radeon_encoder->encoder_id) {
2051                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2052                                 if (dig->linkb)
2053                                         return 1;
2054                                 else
2055                                         return 0;
2056                                 break;
2057                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2058                                 if (dig->linkb)
2059                                         return 3;
2060                                 else
2061                                         return 2;
2062                                 break;
2063                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2064                                 if (dig->linkb)
2065                                         return 5;
2066                                 else
2067                                         return 4;
2068                                 break;
2069                         }
2070                 }
2071         }
2072
2073         /* on DCE32 and encoder can driver any block so just crtc id */
2074         if (ASIC_IS_DCE32(rdev)) {
2075                 return radeon_crtc->crtc_id;
2076         }
2077
2078         /* on DCE3 - LVTMA can only be driven by DIGB */
2079         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2080                 struct radeon_encoder *radeon_test_encoder;
2081
2082                 if (encoder == test_encoder)
2083                         continue;
2084
2085                 if (!radeon_encoder_is_digital(test_encoder))
2086                         continue;
2087
2088                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2089                 dig = radeon_test_encoder->enc_priv;
2090
2091                 if (dig->dig_encoder >= 0)
2092                         dig_enc_in_use |= (1 << dig->dig_encoder);
2093         }
2094
2095         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2096                 if (dig_enc_in_use & 0x2)
2097                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2098                 return 1;
2099         }
2100         if (!(dig_enc_in_use & 1))
2101                 return 0;
2102         return 1;
2103 }
2104
2105 /* This only needs to be called once at startup */
2106 void
2107 radeon_atom_encoder_init(struct radeon_device *rdev)
2108 {
2109         struct drm_device *dev = rdev->ddev;
2110         struct drm_encoder *encoder;
2111
2112         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2113                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2114                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2115
2116                 switch (radeon_encoder->encoder_id) {
2117                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2118                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2119                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2120                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2121                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2122                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2123                         break;
2124                 default:
2125                         break;
2126                 }
2127
2128                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2129                         atombios_external_encoder_setup(encoder, ext_encoder,
2130                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2131         }
2132 }
2133
2134 static void
2135 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2136                              struct drm_display_mode *mode,
2137                              struct drm_display_mode *adjusted_mode)
2138 {
2139         struct drm_device *dev = encoder->dev;
2140         struct radeon_device *rdev = dev->dev_private;
2141         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2142
2143         radeon_encoder->pixel_clock = adjusted_mode->clock;
2144
2145         /* need to call this here rather than in prepare() since we need some crtc info */
2146         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2147
2148         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2149                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2150                         atombios_yuv_setup(encoder, true);
2151                 else
2152                         atombios_yuv_setup(encoder, false);
2153         }
2154
2155         switch (radeon_encoder->encoder_id) {
2156         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2157         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2158         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2159         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2160                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2161                 break;
2162         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2163         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2164         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2165         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2166         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2167                 /* handled in dpms */
2168                 break;
2169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2170         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2172                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2173                 break;
2174         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2175         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2176         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2177         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2178                 atombios_dac_setup(encoder, ATOM_ENABLE);
2179                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2180                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2181                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2182                         else
2183                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2184                 }
2185                 break;
2186         }
2187
2188         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2189
2190         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2191                 if (rdev->asic->display.hdmi_enable)
2192                         radeon_hdmi_enable(rdev, encoder, true);
2193                 if (rdev->asic->display.hdmi_setmode)
2194                         radeon_hdmi_setmode(rdev, encoder, adjusted_mode);
2195         }
2196 }
2197
2198 static bool
2199 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2200 {
2201         struct drm_device *dev = encoder->dev;
2202         struct radeon_device *rdev = dev->dev_private;
2203         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2204         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2205
2206         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2207                                        ATOM_DEVICE_CV_SUPPORT |
2208                                        ATOM_DEVICE_CRT_SUPPORT)) {
2209                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2210                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2211                 uint8_t frev, crev;
2212
2213                 memset(&args, 0, sizeof(args));
2214
2215                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2216                         return false;
2217
2218                 args.sDacload.ucMisc = 0;
2219
2220                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2221                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2222                         args.sDacload.ucDacType = ATOM_DAC_A;
2223                 else
2224                         args.sDacload.ucDacType = ATOM_DAC_B;
2225
2226                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2227                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2228                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2229                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2230                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2231                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2232                         if (crev >= 3)
2233                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2234                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2235                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2236                         if (crev >= 3)
2237                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2238                 }
2239
2240                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2241
2242                 return true;
2243         } else
2244                 return false;
2245 }
2246
2247 static enum drm_connector_status
2248 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2249 {
2250         struct drm_device *dev = encoder->dev;
2251         struct radeon_device *rdev = dev->dev_private;
2252         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2253         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2254         uint32_t bios_0_scratch;
2255
2256         if (!atombios_dac_load_detect(encoder, connector)) {
2257                 DRM_DEBUG_KMS("detect returned false \n");
2258                 return connector_status_unknown;
2259         }
2260
2261         if (rdev->family >= CHIP_R600)
2262                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2263         else
2264                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2265
2266         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2267         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2268                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2269                         return connector_status_connected;
2270         }
2271         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2272                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2273                         return connector_status_connected;
2274         }
2275         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2276                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2277                         return connector_status_connected;
2278         }
2279         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2280                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2281                         return connector_status_connected; /* CTV */
2282                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2283                         return connector_status_connected; /* STV */
2284         }
2285         return connector_status_disconnected;
2286 }
2287
2288 static enum drm_connector_status
2289 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2290 {
2291         struct drm_device *dev = encoder->dev;
2292         struct radeon_device *rdev = dev->dev_private;
2293         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2294         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2295         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2296         u32 bios_0_scratch;
2297
2298         if (!ASIC_IS_DCE4(rdev))
2299                 return connector_status_unknown;
2300
2301         if (!ext_encoder)
2302                 return connector_status_unknown;
2303
2304         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2305                 return connector_status_unknown;
2306
2307         /* load detect on the dp bridge */
2308         atombios_external_encoder_setup(encoder, ext_encoder,
2309                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2310
2311         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2312
2313         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2314         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2315                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2316                         return connector_status_connected;
2317         }
2318         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2319                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2320                         return connector_status_connected;
2321         }
2322         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2323                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2324                         return connector_status_connected;
2325         }
2326         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2327                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2328                         return connector_status_connected; /* CTV */
2329                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2330                         return connector_status_connected; /* STV */
2331         }
2332         return connector_status_disconnected;
2333 }
2334
2335 void
2336 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2337 {
2338         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2339
2340         if (ext_encoder)
2341                 /* ddc_setup on the dp bridge */
2342                 atombios_external_encoder_setup(encoder, ext_encoder,
2343                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2344
2345 }
2346
2347 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2348 {
2349         struct radeon_device *rdev = encoder->dev->dev_private;
2350         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2351         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2352
2353         if ((radeon_encoder->active_device &
2354              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2355             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2356              ENCODER_OBJECT_ID_NONE)) {
2357                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2358                 if (dig) {
2359                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2360                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2361                                 if (rdev->family >= CHIP_R600)
2362                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2363                                 else
2364                                         /* RS600/690/740 have only 1 afmt block */
2365                                         dig->afmt = rdev->mode_info.afmt[0];
2366                         }
2367                 }
2368         }
2369
2370         radeon_atom_output_lock(encoder, true);
2371
2372         if (connector) {
2373                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2374
2375                 /* select the clock/data port if it uses a router */
2376                 if (radeon_connector->router.cd_valid)
2377                         radeon_router_select_cd_port(radeon_connector);
2378
2379                 /* turn eDP panel on for mode set */
2380                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2381                         atombios_set_edp_panel_power(connector,
2382                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2383         }
2384
2385         /* this is needed for the pll/ss setup to work correctly in some cases */
2386         atombios_set_encoder_crtc_source(encoder);
2387         /* set up the FMT blocks */
2388         if (ASIC_IS_DCE8(rdev))
2389                 dce8_program_fmt(encoder);
2390         else if (ASIC_IS_DCE4(rdev))
2391                 dce4_program_fmt(encoder);
2392         else if (ASIC_IS_DCE3(rdev))
2393                 dce3_program_fmt(encoder);
2394         else if (ASIC_IS_AVIVO(rdev))
2395                 avivo_program_fmt(encoder);
2396 }
2397
2398 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2399 {
2400         /* need to call this here as we need the crtc set up */
2401         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2402         radeon_atom_output_lock(encoder, false);
2403 }
2404
2405 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2406 {
2407         struct drm_device *dev = encoder->dev;
2408         struct radeon_device *rdev = dev->dev_private;
2409         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2410         struct radeon_encoder_atom_dig *dig;
2411
2412         /* check for pre-DCE3 cards with shared encoders;
2413          * can't really use the links individually, so don't disable
2414          * the encoder if it's in use by another connector
2415          */
2416         if (!ASIC_IS_DCE3(rdev)) {
2417                 struct drm_encoder *other_encoder;
2418                 struct radeon_encoder *other_radeon_encoder;
2419
2420                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2421                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2422                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2423                             drm_helper_encoder_in_use(other_encoder))
2424                                 goto disable_done;
2425                 }
2426         }
2427
2428         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2429
2430         switch (radeon_encoder->encoder_id) {
2431         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2432         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2433         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2434         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2435                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2436                 break;
2437         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2438         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2439         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2440         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2441         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2442                 /* handled in dpms */
2443                 break;
2444         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2445         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2446         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2447                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2448                 break;
2449         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2450         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2451         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2452         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2453                 atombios_dac_setup(encoder, ATOM_DISABLE);
2454                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2455                         atombios_tv_setup(encoder, ATOM_DISABLE);
2456                 break;
2457         }
2458
2459 disable_done:
2460         if (radeon_encoder_is_digital(encoder)) {
2461                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2462                         if (rdev->asic->display.hdmi_enable)
2463                                 radeon_hdmi_enable(rdev, encoder, false);
2464                 }
2465                 dig = radeon_encoder->enc_priv;
2466                 dig->dig_encoder = -1;
2467         }
2468         radeon_encoder->active_device = 0;
2469 }
2470
2471 /* these are handled by the primary encoders */
2472 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2473 {
2474
2475 }
2476
2477 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2478 {
2479
2480 }
2481
2482 static void
2483 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2484                          struct drm_display_mode *mode,
2485                          struct drm_display_mode *adjusted_mode)
2486 {
2487
2488 }
2489
2490 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2491 {
2492
2493 }
2494
2495 static void
2496 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2497 {
2498
2499 }
2500
2501 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2502                                        const struct drm_display_mode *mode,
2503                                        struct drm_display_mode *adjusted_mode)
2504 {
2505         return true;
2506 }
2507
2508 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2509         .dpms = radeon_atom_ext_dpms,
2510         .mode_fixup = radeon_atom_ext_mode_fixup,
2511         .prepare = radeon_atom_ext_prepare,
2512         .mode_set = radeon_atom_ext_mode_set,
2513         .commit = radeon_atom_ext_commit,
2514         .disable = radeon_atom_ext_disable,
2515         /* no detect for TMDS/LVDS yet */
2516 };
2517
2518 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2519         .dpms = radeon_atom_encoder_dpms,
2520         .mode_fixup = radeon_atom_mode_fixup,
2521         .prepare = radeon_atom_encoder_prepare,
2522         .mode_set = radeon_atom_encoder_mode_set,
2523         .commit = radeon_atom_encoder_commit,
2524         .disable = radeon_atom_encoder_disable,
2525         .detect = radeon_atom_dig_detect,
2526 };
2527
2528 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2529         .dpms = radeon_atom_encoder_dpms,
2530         .mode_fixup = radeon_atom_mode_fixup,
2531         .prepare = radeon_atom_encoder_prepare,
2532         .mode_set = radeon_atom_encoder_mode_set,
2533         .commit = radeon_atom_encoder_commit,
2534         .detect = radeon_atom_dac_detect,
2535 };
2536
2537 void radeon_enc_destroy(struct drm_encoder *encoder)
2538 {
2539         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2540         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2541                 radeon_atom_backlight_exit(radeon_encoder);
2542         kfree(radeon_encoder->enc_priv);
2543         drm_encoder_cleanup(encoder);
2544         kfree(radeon_encoder);
2545 }
2546
2547 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2548         .destroy = radeon_enc_destroy,
2549 };
2550
2551 static struct radeon_encoder_atom_dac *
2552 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2553 {
2554         struct drm_device *dev = radeon_encoder->base.dev;
2555         struct radeon_device *rdev = dev->dev_private;
2556         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2557
2558         if (!dac)
2559                 return NULL;
2560
2561         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2562         return dac;
2563 }
2564
2565 static struct radeon_encoder_atom_dig *
2566 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2567 {
2568         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2569         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2570
2571         if (!dig)
2572                 return NULL;
2573
2574         /* coherent mode by default */
2575         dig->coherent_mode = true;
2576         dig->dig_encoder = -1;
2577
2578         if (encoder_enum == 2)
2579                 dig->linkb = true;
2580         else
2581                 dig->linkb = false;
2582
2583         return dig;
2584 }
2585
2586 void
2587 radeon_add_atom_encoder(struct drm_device *dev,
2588                         uint32_t encoder_enum,
2589                         uint32_t supported_device,
2590                         u16 caps)
2591 {
2592         struct radeon_device *rdev = dev->dev_private;
2593         struct drm_encoder *encoder;
2594         struct radeon_encoder *radeon_encoder;
2595
2596         /* see if we already added it */
2597         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2598                 radeon_encoder = to_radeon_encoder(encoder);
2599                 if (radeon_encoder->encoder_enum == encoder_enum) {
2600                         radeon_encoder->devices |= supported_device;
2601                         return;
2602                 }
2603
2604         }
2605
2606         /* add a new one */
2607         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2608         if (!radeon_encoder)
2609                 return;
2610
2611         encoder = &radeon_encoder->base;
2612         switch (rdev->num_crtc) {
2613         case 1:
2614                 encoder->possible_crtcs = 0x1;
2615                 break;
2616         case 2:
2617         default:
2618                 encoder->possible_crtcs = 0x3;
2619                 break;
2620         case 4:
2621                 encoder->possible_crtcs = 0xf;
2622                 break;
2623         case 6:
2624                 encoder->possible_crtcs = 0x3f;
2625                 break;
2626         }
2627
2628         radeon_encoder->enc_priv = NULL;
2629
2630         radeon_encoder->encoder_enum = encoder_enum;
2631         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2632         radeon_encoder->devices = supported_device;
2633         radeon_encoder->rmx_type = RMX_OFF;
2634         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2635         radeon_encoder->is_ext_encoder = false;
2636         radeon_encoder->caps = caps;
2637
2638         switch (radeon_encoder->encoder_id) {
2639         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2640         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2641         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2642         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2643                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2644                         radeon_encoder->rmx_type = RMX_FULL;
2645                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2646                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2647                 } else {
2648                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2649                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2650                 }
2651                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2652                 break;
2653         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2654                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2655                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2656                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2657                 break;
2658         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2659         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2660         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2661                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2662                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2663                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2664                 break;
2665         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2666         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2667         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2668         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2669         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2670         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2671         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2672         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2673                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2674                         radeon_encoder->rmx_type = RMX_FULL;
2675                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2676                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2677                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2678                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2679                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2680                 } else {
2681                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2682                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2683                 }
2684                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2685                 break;
2686         case ENCODER_OBJECT_ID_SI170B:
2687         case ENCODER_OBJECT_ID_CH7303:
2688         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2689         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2690         case ENCODER_OBJECT_ID_TITFP513:
2691         case ENCODER_OBJECT_ID_VT1623:
2692         case ENCODER_OBJECT_ID_HDMI_SI1930:
2693         case ENCODER_OBJECT_ID_TRAVIS:
2694         case ENCODER_OBJECT_ID_NUTMEG:
2695                 /* these are handled by the primary encoders */
2696                 radeon_encoder->is_ext_encoder = true;
2697                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2698                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2699                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2700                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2701                 else
2702                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2703                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2704                 break;
2705         }
2706 }