drivers/gpu/drm/radeon/ci_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include "drmP.h"
  26 #include "radeon.h"
  27 #include "radeon_ucode.h"
  28 #include "cikd.h"
  29 #include "r600_dpm.h"
  30 #include "ci_dpm.h"
  31 #include "atom.h"
  32 #include <linux/seq_file.h>
  33
  34 #define MC_CG_ARB_FREQ_F0           0x0a
  35 #define MC_CG_ARB_FREQ_F1           0x0b
  36 #define MC_CG_ARB_FREQ_F2           0x0c
  37 #define MC_CG_ARB_FREQ_F3           0x0d
  38
  39 #define SMC_RAM_END 0x40000
  40
  41 #define VOLTAGE_SCALE               4
  42 #define VOLTAGE_VID_OFFSET_SCALE1    625
  43 #define VOLTAGE_VID_OFFSET_SCALE2    100
  44
  45 static const struct ci_pt_defaults defaults_hawaii_xt =
  46 {
  47         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
  48         { 0x84,  0x0,   0x0,   0x7F,  0x0,   0x0,   0x5A,  0x60,  0x51,  0x8E,  0x79,  0x6B,  0x5F,  0x90,  0x79  },
  49         { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
  50 };
  51
  52 static const struct ci_pt_defaults defaults_hawaii_pro =
  53 {
  54         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
  55         { 0x93,  0x0,   0x0,   0x97,  0x0,   0x0,   0x6B,  0x60,  0x51,  0x95,  0x79,  0x6B,  0x5F,  0x90,  0x79  },
  56         { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
  57 };
  58
  59 static const struct ci_pt_defaults defaults_bonaire_xt =
  60 {
  61         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  62         { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
  63         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
  64 };
  65
  66 static const struct ci_pt_defaults defaults_bonaire_pro =
  67 {
  68         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
  69         { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
  70         { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
  71 };
  72
  73 static const struct ci_pt_defaults defaults_saturn_xt =
  74 {
  75         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
  76         { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
  77         { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
  78 };
  79
  80 static const struct ci_pt_defaults defaults_saturn_pro =
  81 {
  82         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
  83         { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
  84         { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
  85 };
  86
  87 static const struct ci_pt_config_reg didt_config_ci[] =
  88 {
  89         { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  90         { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  91         { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  92         { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  93         { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  94         { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  95         { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  96         { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  97         { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  98         { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  99         { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 100         { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 101         { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 102         { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 103         { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 104         { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 105         { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 106         { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 107         { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 108         { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 109         { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 110         { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 111         { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 112         { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 113         { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 114         { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 115         { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 116         { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 117         { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 118         { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 119         { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 120         { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 121         { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 122         { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 123         { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 124         { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 125         { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 126         { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 127         { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 128         { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 129         { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 130         { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 131         { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 132         { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 133         { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 134         { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 135         { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 136         { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 137         { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 138         { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 139         { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 140         { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 141         { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 142         { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 143         { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 144         { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 145         { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 146         { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 147         { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 148         { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 149         { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 150         { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 151         { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 152         { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 153         { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 154         { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 155         { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 156         { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 157         { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 158         { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 159         { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 160         { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 161         { 0xFFFFFFFF }
 162 };
 163
 164 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
 165 extern void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
 166                                                             u32 *max_clock);
 167 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
 168                                        u32 arb_freq_src, u32 arb_freq_dest);
 169 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
 170 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
 171 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
 172                                                      u32 max_voltage_steps,
 173                                                      struct atom_voltage_table *voltage_table);
 174 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
 175 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
 176 extern int ci_mc_load_microcode(struct radeon_device *rdev);
 177 extern void cik_update_cg(struct radeon_device *rdev,
 178                           u32 block, bool enable);
 179
 180 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
 181                                          struct atom_voltage_table_entry *voltage_table,
 182                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
 183 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
 184 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
 185                                        u32 target_tdp);
 186 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
 187
 188 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
 189 {
 190         struct ci_power_info *pi = rdev->pm.dpm.priv;
 191
 192         return pi;
 193 }
 194
 195 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
 196 {
 197         struct ci_ps *ps = rps->ps_priv;
 198
 199         return ps;
 200 }
 201
 202 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
 203 {
 204         struct ci_power_info *pi = ci_get_pi(rdev);
 205
 206         switch (rdev->pdev->device) {
 207         case 0x6649:
 208         case 0x6650:
 209         case 0x6651:
 210         case 0x6658:
 211         case 0x665C:
 212         case 0x665D:
 213         default:
 214                 pi->powertune_defaults = &defaults_bonaire_xt;
 215                 break;
 216         case 0x6640:
 217         case 0x6641:
 218         case 0x6646:
 219         case 0x6647:
 220                 pi->powertune_defaults = &defaults_saturn_xt;
 221                 break;
 222         case 0x67B8:
 223         case 0x67B0:
 224                 pi->powertune_defaults = &defaults_hawaii_xt;
 225                 break;
 226         case 0x67BA:
 227         case 0x67B1:
 228                 pi->powertune_defaults = &defaults_hawaii_pro;
 229                 break;
 230         case 0x67A0:
 231         case 0x67A1:
 232         case 0x67A2:
 233         case 0x67A8:
 234         case 0x67A9:
 235         case 0x67AA:
 236         case 0x67B9:
 237         case 0x67BE:
 238                 pi->powertune_defaults = &defaults_bonaire_xt;
 239                 break;
 240         }
 241
 242         pi->dte_tj_offset = 0;
 243
 244         pi->caps_power_containment = true;
 245         pi->caps_cac = false;
 246         pi->caps_sq_ramping = false;
 247         pi->caps_db_ramping = false;
 248         pi->caps_td_ramping = false;
 249         pi->caps_tcp_ramping = false;
 250
 251         if (pi->caps_power_containment) {
 252                 pi->caps_cac = true;
 253                 pi->enable_bapm_feature = true;
 254                 pi->enable_tdc_limit_feature = true;
 255                 pi->enable_pkg_pwr_tracking_feature = true;
 256         }
 257 }
 258
 259 static u8 ci_convert_to_vid(u16 vddc)
 260 {
 261         return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
 262 }
 263
 264 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
 265 {
 266         struct ci_power_info *pi = ci_get_pi(rdev);
 267         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 268         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 269         u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
 270         u32 i;
 271
 272         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
 273                 return -EINVAL;
 274         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
 275                 return -EINVAL;
 276         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
 277             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
 278                 return -EINVAL;
 279
 280         for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
 281                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 282                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
 283                         hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
 284                         hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
 285                 } else {
 286                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
 287                         hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
 288                 }
 289         }
 290         return 0;
 291 }
 292
 293 static int ci_populate_vddc_vid(struct radeon_device *rdev)
 294 {
 295         struct ci_power_info *pi = ci_get_pi(rdev);
 296         u8 *vid = pi->smc_powertune_table.VddCVid;
 297         u32 i;
 298
 299         if (pi->vddc_voltage_table.count > 8)
 300                 return -EINVAL;
 301
 302         for (i = 0; i < pi->vddc_voltage_table.count; i++)
 303                 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
 304
 305         return 0;
 306 }
 307
 308 static int ci_populate_svi_load_line(struct radeon_device *rdev)
 309 {
 310         struct ci_power_info *pi = ci_get_pi(rdev);
 311         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 312
 313         pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
 314         pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
 315         pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
 316         pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
 317
 318         return 0;
 319 }
 320
 321 static int ci_populate_tdc_limit(struct radeon_device *rdev)
 322 {
 323         struct ci_power_info *pi = ci_get_pi(rdev);
 324         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 325         u16 tdc_limit;
 326
 327         tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
 328         pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
 329         pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 330                 pt_defaults->tdc_vddc_throttle_release_limit_perc;
 331         pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
 332
 333         return 0;
 334 }
 335
 336 static int ci_populate_dw8(struct radeon_device *rdev)
 337 {
 338         struct ci_power_info *pi = ci_get_pi(rdev);
 339         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 340         int ret;
 341
 342         ret = ci_read_smc_sram_dword(rdev,
 343                                      SMU7_FIRMWARE_HEADER_LOCATION +
 344                                      offsetof(SMU7_Firmware_Header, PmFuseTable) +
 345                                      offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
 346                                      (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
 347                                      pi->sram_end);
 348         if (ret)
 349                 return -EINVAL;
 350         else
 351                 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
 352
 353         return 0;
 354 }
 355
 356 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
 357 {
 358         struct ci_power_info *pi = ci_get_pi(rdev);
 359         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 360         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 361         int i, min, max;
 362
 363         min = max = hi_vid[0];
 364         for (i = 0; i < 8; i++) {
 365                 if (0 != hi_vid[i]) {
 366                         if (min > hi_vid[i])
 367                                 min = hi_vid[i];
 368                         if (max < hi_vid[i])
 369                                 max = hi_vid[i];
 370                 }
 371
 372                 if (0 != lo_vid[i]) {
 373                         if (min > lo_vid[i])
 374                                 min = lo_vid[i];
 375                         if (max < lo_vid[i])
 376                                 max = lo_vid[i];
 377                 }
 378         }
 379
 380         if ((min == 0) || (max == 0))
 381                 return -EINVAL;
 382         pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
 383         pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
 384
 385         return 0;
 386 }
 387
 388 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
 389 {
 390         struct ci_power_info *pi = ci_get_pi(rdev);
 391         u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
 392         u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
 393         struct radeon_cac_tdp_table *cac_tdp_table =
 394                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 395
 396         hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
 397         lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
 398
 399         pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
 400         pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
 401
 402         return 0;
 403 }
 404
 405 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
 406 {
 407         struct ci_power_info *pi = ci_get_pi(rdev);
 408         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 409         SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
 410         struct radeon_cac_tdp_table *cac_tdp_table =
 411                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 412         struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
 413         int i, j, k;
 414         const u16 *def1;
 415         const u16 *def2;
 416
 417         dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
 418         dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
 419
 420         dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
 421         dpm_table->GpuTjMax =
 422                 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
 423         dpm_table->GpuTjHyst = 8;
 424
 425         dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
 426
 427         if (ppm) {
 428                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
 429                 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
 430         } else {
 431                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
 432                 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
 433         }
 434
 435         dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
 436         def1 = pt_defaults->bapmti_r;
 437         def2 = pt_defaults->bapmti_rc;
 438
 439         for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
 440                 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
 441                         for (k = 0; k < SMU7_DTE_SINKS; k++) {
 442                                 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
 443                                 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
 444                                 def1++;
 445                                 def2++;
 446                         }
 447                 }
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int ci_populate_pm_base(struct radeon_device *rdev)
 454 {
 455         struct ci_power_info *pi = ci_get_pi(rdev);
 456         u32 pm_fuse_table_offset;
 457         int ret;
 458
 459         if (pi->caps_power_containment) {
 460                 ret = ci_read_smc_sram_dword(rdev,
 461                                              SMU7_FIRMWARE_HEADER_LOCATION +
 462                                              offsetof(SMU7_Firmware_Header, PmFuseTable),
 463                                              &pm_fuse_table_offset, pi->sram_end);
 464                 if (ret)
 465                         return ret;
 466                 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
 467                 if (ret)
 468                         return ret;
 469                 ret = ci_populate_vddc_vid(rdev);
 470                 if (ret)
 471                         return ret;
 472                 ret = ci_populate_svi_load_line(rdev);
 473                 if (ret)
 474                         return ret;
 475                 ret = ci_populate_tdc_limit(rdev);
 476                 if (ret)
 477                         return ret;
 478                 ret = ci_populate_dw8(rdev);
 479                 if (ret)
 480                         return ret;
 481                 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
 482                 if (ret)
 483                         return ret;
 484                 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
 485                 if (ret)
 486                         return ret;
 487                 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
 488                                            (u8 *)&pi->smc_powertune_table,
 489                                            sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
 490                 if (ret)
 491                         return ret;
 492         }
 493
 494         return 0;
 495 }
 496
 497 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
 498 {
 499         struct ci_power_info *pi = ci_get_pi(rdev);
 500         u32 data;
 501
 502         if (pi->caps_sq_ramping) {
 503                 data = RREG32_DIDT(DIDT_SQ_CTRL0);
 504                 if (enable)
 505                         data |= DIDT_CTRL_EN;
 506                 else
 507                         data &= ~DIDT_CTRL_EN;
 508                 WREG32_DIDT(DIDT_SQ_CTRL0, data);
 509         }
 510
 511         if (pi->caps_db_ramping) {
 512                 data = RREG32_DIDT(DIDT_DB_CTRL0);
 513                 if (enable)
 514                         data |= DIDT_CTRL_EN;
 515                 else
 516                         data &= ~DIDT_CTRL_EN;
 517                 WREG32_DIDT(DIDT_DB_CTRL0, data);
 518         }
 519
 520         if (pi->caps_td_ramping) {
 521                 data = RREG32_DIDT(DIDT_TD_CTRL0);
 522                 if (enable)
 523                         data |= DIDT_CTRL_EN;
 524                 else
 525                         data &= ~DIDT_CTRL_EN;
 526                 WREG32_DIDT(DIDT_TD_CTRL0, data);
 527         }
 528
 529         if (pi->caps_tcp_ramping) {
 530                 data = RREG32_DIDT(DIDT_TCP_CTRL0);
 531                 if (enable)
 532                         data |= DIDT_CTRL_EN;
 533                 else
 534                         data &= ~DIDT_CTRL_EN;
 535                 WREG32_DIDT(DIDT_TCP_CTRL0, data);
 536         }
 537 }
 538
 539 static int ci_program_pt_config_registers(struct radeon_device *rdev,
 540                                           const struct ci_pt_config_reg *cac_config_regs)
 541 {
 542         const struct ci_pt_config_reg *config_regs = cac_config_regs;
 543         u32 data;
 544         u32 cache = 0;
 545
 546         if (config_regs == NULL)
 547                 return -EINVAL;
 548
 549         while (config_regs->offset != 0xFFFFFFFF) {
 550                 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
 551                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 552                 } else {
 553                         switch (config_regs->type) {
 554                         case CISLANDS_CONFIGREG_SMC_IND:
 555                                 data = RREG32_SMC(config_regs->offset);
 556                                 break;
 557                         case CISLANDS_CONFIGREG_DIDT_IND:
 558                                 data = RREG32_DIDT(config_regs->offset);
 559                                 break;
 560                         default:
 561                                 data = RREG32(config_regs->offset << 2);
 562                                 break;
 563                         }
 564
 565                         data &= ~config_regs->mask;
 566                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 567                         data |= cache;
 568
 569                         switch (config_regs->type) {
 570                         case CISLANDS_CONFIGREG_SMC_IND:
 571                                 WREG32_SMC(config_regs->offset, data);
 572                                 break;
 573                         case CISLANDS_CONFIGREG_DIDT_IND:
 574                                 WREG32_DIDT(config_regs->offset, data);
 575                                 break;
 576                         default:
 577                                 WREG32(config_regs->offset << 2, data);
 578                                 break;
 579                         }
 580                         cache = 0;
 581                 }
 582                 config_regs++;
 583         }
 584         return 0;
 585 }
 586
 587 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
 588 {
 589         struct ci_power_info *pi = ci_get_pi(rdev);
 590         int ret;
 591
 592         if (pi->caps_sq_ramping || pi->caps_db_ramping ||
 593             pi->caps_td_ramping || pi->caps_tcp_ramping) {
 594                 cik_enter_rlc_safe_mode(rdev);
 595
 596                 if (enable) {
 597                         ret = ci_program_pt_config_registers(rdev, didt_config_ci);
 598                         if (ret) {
 599                                 cik_exit_rlc_safe_mode(rdev);
 600                                 return ret;
 601                         }
 602                 }
 603
 604                 ci_do_enable_didt(rdev, enable);
 605
 606                 cik_exit_rlc_safe_mode(rdev);
 607         }
 608
 609         return 0;
 610 }
 611
 612 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
 613 {
 614         struct ci_power_info *pi = ci_get_pi(rdev);
 615         PPSMC_Result smc_result;
 616         int ret = 0;
 617
 618         if (enable) {
 619                 pi->power_containment_features = 0;
 620                 if (pi->caps_power_containment) {
 621                         if (pi->enable_bapm_feature) {
 622                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
 623                                 if (smc_result != PPSMC_Result_OK)
 624                                         ret = -EINVAL;
 625                                 else
 626                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
 627                         }
 628
 629                         if (pi->enable_tdc_limit_feature) {
 630                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
 631                                 if (smc_result != PPSMC_Result_OK)
 632                                         ret = -EINVAL;
 633                                 else
 634                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
 635                         }
 636
 637                         if (pi->enable_pkg_pwr_tracking_feature) {
 638                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
 639                                 if (smc_result != PPSMC_Result_OK) {
 640                                         ret = -EINVAL;
 641                                 } else {
 642                                         struct radeon_cac_tdp_table *cac_tdp_table =
 643                                                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 644                                         u32 default_pwr_limit =
 645                                                 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
 646
 647                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
 648
 649                                         ci_set_power_limit(rdev, default_pwr_limit);
 650                                 }
 651                         }
 652                 }
 653         } else {
 654                 if (pi->caps_power_containment && pi->power_containment_features) {
 655                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
 656                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
 657
 658                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
 659                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
 660
 661                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
 662                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
 663                         pi->power_containment_features = 0;
 664                 }
 665         }
 666
 667         return ret;
 668 }
 669
 670 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
 671 {
 672         struct ci_power_info *pi = ci_get_pi(rdev);
 673         PPSMC_Result smc_result;
 674         int ret = 0;
 675
 676         if (pi->caps_cac) {
 677                 if (enable) {
 678                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
 679                         if (smc_result != PPSMC_Result_OK) {
 680                                 ret = -EINVAL;
 681                                 pi->cac_enabled = false;
 682                         } else {
 683                                 pi->cac_enabled = true;
 684                         }
 685                 } else if (pi->cac_enabled) {
 686                         ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
 687                         pi->cac_enabled = false;
 688                 }
 689         }
 690
 691         return ret;
 692 }
 693
 694 static int ci_power_control_set_level(struct radeon_device *rdev)
 695 {
 696         struct ci_power_info *pi = ci_get_pi(rdev);
 697         struct radeon_cac_tdp_table *cac_tdp_table =
 698                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 699         s32 adjust_percent;
 700         s32 target_tdp;
 701         int ret = 0;
 702         bool adjust_polarity = false; /* ??? */
 703
 704         if (pi->caps_power_containment &&
 705             (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) {
 706                 adjust_percent = adjust_polarity ?
 707                         rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
 708                 target_tdp = ((100 + adjust_percent) *
 709                               (s32)cac_tdp_table->configurable_tdp) / 100;
 710                 target_tdp *= 256;
 711
 712                 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
 713         }
 714
 715         return ret;
 716 }
 717
 718 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
 719 {
 720         struct ci_power_info *pi = ci_get_pi(rdev);
 721
 722         if (pi->uvd_power_gated == gate)
 723                 return;
 724
 725         pi->uvd_power_gated = gate;
 726
 727         ci_update_uvd_dpm(rdev, gate);
 728 }
 729
 730 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
 731 {
 732         struct ci_power_info *pi = ci_get_pi(rdev);
 733         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
 734         u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
 735
 736         if (vblank_time < switch_limit)
 737                 return true;
 738         else
 739                 return false;
 740
 741 }
 742
 743 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
 744                                         struct radeon_ps *rps)
 745 {
 746         struct ci_ps *ps = ci_get_ps(rps);
 747         struct ci_power_info *pi = ci_get_pi(rdev);
 748         struct radeon_clock_and_voltage_limits *max_limits;
 749         bool disable_mclk_switching;
 750         u32 sclk, mclk;
 751         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
 752         int i;
 753
 754         if (rps->vce_active) {
 755                 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
 756                 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
 757         } else {
 758                 rps->evclk = 0;
 759                 rps->ecclk = 0;
 760         }
 761
 762         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
 763             ci_dpm_vblank_too_short(rdev))
 764                 disable_mclk_switching = true;
 765         else
 766                 disable_mclk_switching = false;
 767
 768         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
 769                 pi->battery_state = true;
 770         else
 771                 pi->battery_state = false;
 772
 773         if (rdev->pm.dpm.ac_power)
 774                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
 775         else
 776                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
 777
 778         if (rdev->pm.dpm.ac_power == false) {
 779                 for (i = 0; i < ps->performance_level_count; i++) {
 780                         if (ps->performance_levels[i].mclk > max_limits->mclk)
 781                                 ps->performance_levels[i].mclk = max_limits->mclk;
 782                         if (ps->performance_levels[i].sclk > max_limits->sclk)
 783                                 ps->performance_levels[i].sclk = max_limits->sclk;
 784                 }
 785         }
 786
 787         /* limit clocks to max supported clocks based on voltage dependency tables */
 788         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
 789                                                         &max_sclk_vddc);
 790         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
 791                                                         &max_mclk_vddci);
 792         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
 793                                                         &max_mclk_vddc);
 794
 795         for (i = 0; i < ps->performance_level_count; i++) {
 796                 if (max_sclk_vddc) {
 797                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
 798                                 ps->performance_levels[i].sclk = max_sclk_vddc;
 799                 }
 800                 if (max_mclk_vddci) {
 801                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
 802                                 ps->performance_levels[i].mclk = max_mclk_vddci;
 803                 }
 804                 if (max_mclk_vddc) {
 805                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
 806                                 ps->performance_levels[i].mclk = max_mclk_vddc;
 807                 }
 808         }
 809
 810         /* XXX validate the min clocks required for display */
 811
 812         if (disable_mclk_switching) {
 813                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
 814                 sclk = ps->performance_levels[0].sclk;
 815         } else {
 816                 mclk = ps->performance_levels[0].mclk;
 817                 sclk = ps->performance_levels[0].sclk;
 818         }
 819
 820         if (rps->vce_active) {
 821                 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
 822                         sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
 823                 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
 824                         mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
 825         }
 826
 827         ps->performance_levels[0].sclk = sclk;
 828         ps->performance_levels[0].mclk = mclk;
 829
 830         if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
 831                 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
 832
 833         if (disable_mclk_switching) {
 834                 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
 835                         ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
 836         } else {
 837                 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
 838                         ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
 839         }
 840 }
 841
 842 static int ci_set_thermal_temperature_range(struct radeon_device *rdev,
 843                                             int min_temp, int max_temp)
 844 {
 845         int low_temp = 0 * 1000;
 846         int high_temp = 255 * 1000;
 847         u32 tmp;
 848
 849         if (low_temp < min_temp)
 850                 low_temp = min_temp;
 851         if (high_temp > max_temp)
 852                 high_temp = max_temp;
 853         if (high_temp < low_temp) {
 854                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
 855                 return -EINVAL;
 856         }
 857
 858         tmp = RREG32_SMC(CG_THERMAL_INT);
 859         tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
 860         tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
 861                 CI_DIG_THERM_INTL(low_temp / 1000);
 862         WREG32_SMC(CG_THERMAL_INT, tmp);
 863
 864 #if 0
 865         /* XXX: need to figure out how to handle this properly */
 866         tmp = RREG32_SMC(CG_THERMAL_CTRL);
 867         tmp &= DIG_THERM_DPM_MASK;
 868         tmp |= DIG_THERM_DPM(high_temp / 1000);
 869         WREG32_SMC(CG_THERMAL_CTRL, tmp);
 870 #endif
 871
 872         return 0;
 873 }
 874
 875 #if 0
 876 static int ci_read_smc_soft_register(struct radeon_device *rdev,
 877                                      u16 reg_offset, u32 *value)
 878 {
 879         struct ci_power_info *pi = ci_get_pi(rdev);
 880
 881         return ci_read_smc_sram_dword(rdev,
 882                                       pi->soft_regs_start + reg_offset,
 883                                       value, pi->sram_end);
 884 }
 885 #endif
 886
 887 static int ci_write_smc_soft_register(struct radeon_device *rdev,
 888                                       u16 reg_offset, u32 value)
 889 {
 890         struct ci_power_info *pi = ci_get_pi(rdev);
 891
 892         return ci_write_smc_sram_dword(rdev,
 893                                        pi->soft_regs_start + reg_offset,
 894                                        value, pi->sram_end);
 895 }
 896
 897 static void ci_init_fps_limits(struct radeon_device *rdev)
 898 {
 899         struct ci_power_info *pi = ci_get_pi(rdev);
 900         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
 901
 902         if (pi->caps_fps) {
 903                 u16 tmp;
 904
 905                 tmp = 45;
 906                 table->FpsHighT = cpu_to_be16(tmp);
 907
 908                 tmp = 30;
 909                 table->FpsLowT = cpu_to_be16(tmp);
 910         }
 911 }
 912
 913 static int ci_update_sclk_t(struct radeon_device *rdev)
 914 {
 915         struct ci_power_info *pi = ci_get_pi(rdev);
 916         int ret = 0;
 917         u32 low_sclk_interrupt_t = 0;
 918
 919         if (pi->caps_sclk_throttle_low_notification) {
 920                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 921
 922                 ret = ci_copy_bytes_to_smc(rdev,
 923                                            pi->dpm_table_start +
 924                                            offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
 925                                            (u8 *)&low_sclk_interrupt_t,
 926                                            sizeof(u32), pi->sram_end);
 927
 928         }
 929
 930         return ret;
 931 }
 932
 933 static void ci_get_leakage_voltages(struct radeon_device *rdev)
 934 {
 935         struct ci_power_info *pi = ci_get_pi(rdev);
 936         u16 leakage_id, virtual_voltage_id;
 937         u16 vddc, vddci;
 938         int i;
 939
 940         pi->vddc_leakage.count = 0;
 941         pi->vddci_leakage.count = 0;
 942
 943         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 944                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
 945                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 946                         if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
 947                                 continue;
 948                         if (vddc != 0 && vddc != virtual_voltage_id) {
 949                                 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
 950                                 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
 951                                 pi->vddc_leakage.count++;
 952                         }
 953                 }
 954         } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
 955                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
 956                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 957                         if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
 958                                                                                  virtual_voltage_id,
 959                                                                                  leakage_id) == 0) {
 960                                 if (vddc != 0 && vddc != virtual_voltage_id) {
 961                                         pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
 962                                         pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
 963                                         pi->vddc_leakage.count++;
 964                                 }
 965                                 if (vddci != 0 && vddci != virtual_voltage_id) {
 966                                         pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
 967                                         pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
 968                                         pi->vddci_leakage.count++;
 969                                 }
 970                         }
 971                 }
 972         }
 973 }
 974
 975 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
 976 {
 977         struct ci_power_info *pi = ci_get_pi(rdev);
 978         bool want_thermal_protection;
 979         enum radeon_dpm_event_src dpm_event_src;
 980         u32 tmp;
 981
 982         switch (sources) {
 983         case 0:
 984         default:
 985                 want_thermal_protection = false;
 986                 break;
 987         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
 988                 want_thermal_protection = true;
 989                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
 990                 break;
 991         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
 992                 want_thermal_protection = true;
 993                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
 994                 break;
 995         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
 996               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
 997                 want_thermal_protection = true;
 998                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
 999                 break;
1000         }
1001
1002         if (want_thermal_protection) {
1003 #if 0
1004                 /* XXX: need to figure out how to handle this properly */
1005                 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1006                 tmp &= DPM_EVENT_SRC_MASK;
1007                 tmp |= DPM_EVENT_SRC(dpm_event_src);
1008                 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1009 #endif
1010
1011                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1012                 if (pi->thermal_protection)
1013                         tmp &= ~THERMAL_PROTECTION_DIS;
1014                 else
1015                         tmp |= THERMAL_PROTECTION_DIS;
1016                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1017         } else {
1018                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1019                 tmp |= THERMAL_PROTECTION_DIS;
1020                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1021         }
1022 }
1023
1024 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1025                                            enum radeon_dpm_auto_throttle_src source,
1026                                            bool enable)
1027 {
1028         struct ci_power_info *pi = ci_get_pi(rdev);
1029
1030         if (enable) {
1031                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1032                         pi->active_auto_throttle_sources |= 1 << source;
1033                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1034                 }
1035         } else {
1036                 if (pi->active_auto_throttle_sources & (1 << source)) {
1037                         pi->active_auto_throttle_sources &= ~(1 << source);
1038                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1039                 }
1040         }
1041 }
1042
1043 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1044 {
1045         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1046                 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1047 }
1048
1049 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1050 {
1051         struct ci_power_info *pi = ci_get_pi(rdev);
1052         PPSMC_Result smc_result;
1053
1054         if (!pi->need_update_smu7_dpm_table)
1055                 return 0;
1056
1057         if ((!pi->sclk_dpm_key_disabled) &&
1058             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1059                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1060                 if (smc_result != PPSMC_Result_OK)
1061                         return -EINVAL;
1062         }
1063
1064         if ((!pi->mclk_dpm_key_disabled) &&
1065             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1066                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1067                 if (smc_result != PPSMC_Result_OK)
1068                         return -EINVAL;
1069         }
1070
1071         pi->need_update_smu7_dpm_table = 0;
1072         return 0;
1073 }
1074
1075 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1076 {
1077         struct ci_power_info *pi = ci_get_pi(rdev);
1078         PPSMC_Result smc_result;
1079
1080         if (enable) {
1081                 if (!pi->sclk_dpm_key_disabled) {
1082                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1083                         if (smc_result != PPSMC_Result_OK)
1084                                 return -EINVAL;
1085                 }
1086
1087                 if (!pi->mclk_dpm_key_disabled) {
1088                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1089                         if (smc_result != PPSMC_Result_OK)
1090                                 return -EINVAL;
1091
1092                         WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1093
1094                         WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1095                         WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1096                         WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1097
1098                         udelay(10);
1099
1100                         WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1101                         WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1102                         WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1103                 }
1104         } else {
1105                 if (!pi->sclk_dpm_key_disabled) {
1106                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1107                         if (smc_result != PPSMC_Result_OK)
1108                                 return -EINVAL;
1109                 }
1110
1111                 if (!pi->mclk_dpm_key_disabled) {
1112                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1113                         if (smc_result != PPSMC_Result_OK)
1114                                 return -EINVAL;
1115                 }
1116         }
1117
1118         return 0;
1119 }
1120
1121 static int ci_start_dpm(struct radeon_device *rdev)
1122 {
1123         struct ci_power_info *pi = ci_get_pi(rdev);
1124         PPSMC_Result smc_result;
1125         int ret;
1126         u32 tmp;
1127
1128         tmp = RREG32_SMC(GENERAL_PWRMGT);
1129         tmp |= GLOBAL_PWRMGT_EN;
1130         WREG32_SMC(GENERAL_PWRMGT, tmp);
1131
1132         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1133         tmp |= DYNAMIC_PM_EN;
1134         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1135
1136         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1137
1138         WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1139
1140         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1141         if (smc_result != PPSMC_Result_OK)
1142                 return -EINVAL;
1143
1144         ret = ci_enable_sclk_mclk_dpm(rdev, true);
1145         if (ret)
1146                 return ret;
1147
1148         if (!pi->pcie_dpm_key_disabled) {
1149                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1150                 if (smc_result != PPSMC_Result_OK)
1151                         return -EINVAL;
1152         }
1153
1154         return 0;
1155 }
1156
1157 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1158 {
1159         struct ci_power_info *pi = ci_get_pi(rdev);
1160         PPSMC_Result smc_result;
1161
1162         if (!pi->need_update_smu7_dpm_table)
1163                 return 0;
1164
1165         if ((!pi->sclk_dpm_key_disabled) &&
1166             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1167                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1168                 if (smc_result != PPSMC_Result_OK)
1169                         return -EINVAL;
1170         }
1171
1172         if ((!pi->mclk_dpm_key_disabled) &&
1173             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1174                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1175                 if (smc_result != PPSMC_Result_OK)
1176                         return -EINVAL;
1177         }
1178
1179         return 0;
1180 }
1181
1182 static int ci_stop_dpm(struct radeon_device *rdev)
1183 {
1184         struct ci_power_info *pi = ci_get_pi(rdev);
1185         PPSMC_Result smc_result;
1186         int ret;
1187         u32 tmp;
1188
1189         tmp = RREG32_SMC(GENERAL_PWRMGT);
1190         tmp &= ~GLOBAL_PWRMGT_EN;
1191         WREG32_SMC(GENERAL_PWRMGT, tmp);
1192
1193         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1194         tmp &= ~DYNAMIC_PM_EN;
1195         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1196
1197         if (!pi->pcie_dpm_key_disabled) {
1198                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1199                 if (smc_result != PPSMC_Result_OK)
1200                         return -EINVAL;
1201         }
1202
1203         ret = ci_enable_sclk_mclk_dpm(rdev, false);
1204         if (ret)
1205                 return ret;
1206
1207         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1208         if (smc_result != PPSMC_Result_OK)
1209                 return -EINVAL;
1210
1211         return 0;
1212 }
1213
1214 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1215 {
1216         u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1217
1218         if (enable)
1219                 tmp &= ~SCLK_PWRMGT_OFF;
1220         else
1221                 tmp |= SCLK_PWRMGT_OFF;
1222         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1223 }
1224
1225 #if 0
1226 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1227                                         bool ac_power)
1228 {
1229         struct ci_power_info *pi = ci_get_pi(rdev);
1230         struct radeon_cac_tdp_table *cac_tdp_table =
1231                 rdev->pm.dpm.dyn_state.cac_tdp_table;
1232         u32 power_limit;
1233
1234         if (ac_power)
1235                 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1236         else
1237                 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1238
1239         ci_set_power_limit(rdev, power_limit);
1240
1241         if (pi->caps_automatic_dc_transition) {
1242                 if (ac_power)
1243                         ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1244                 else
1245                         ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1246         }
1247
1248         return 0;
1249 }
1250 #endif
1251
1252 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1253                                                       PPSMC_Msg msg, u32 parameter)
1254 {
1255         WREG32(SMC_MSG_ARG_0, parameter);
1256         return ci_send_msg_to_smc(rdev, msg);
1257 }
1258
1259 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1260                                                         PPSMC_Msg msg, u32 *parameter)
1261 {
1262         PPSMC_Result smc_result;
1263
1264         smc_result = ci_send_msg_to_smc(rdev, msg);
1265
1266         if ((smc_result == PPSMC_Result_OK) && parameter)
1267                 *parameter = RREG32(SMC_MSG_ARG_0);
1268
1269         return smc_result;
1270 }
1271
1272 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1273 {
1274         struct ci_power_info *pi = ci_get_pi(rdev);
1275
1276         if (!pi->sclk_dpm_key_disabled) {
1277                 PPSMC_Result smc_result =
1278                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, n);
1279                 if (smc_result != PPSMC_Result_OK)
1280                         return -EINVAL;
1281         }
1282
1283         return 0;
1284 }
1285
1286 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1287 {
1288         struct ci_power_info *pi = ci_get_pi(rdev);
1289
1290         if (!pi->mclk_dpm_key_disabled) {
1291                 PPSMC_Result smc_result =
1292                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_ForceState, n);
1293                 if (smc_result != PPSMC_Result_OK)
1294                         return -EINVAL;
1295         }
1296
1297         return 0;
1298 }
1299
1300 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1301 {
1302         struct ci_power_info *pi = ci_get_pi(rdev);
1303
1304         if (!pi->pcie_dpm_key_disabled) {
1305                 PPSMC_Result smc_result =
1306                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1307                 if (smc_result != PPSMC_Result_OK)
1308                         return -EINVAL;
1309         }
1310
1311         return 0;
1312 }
1313
1314 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1315 {
1316         struct ci_power_info *pi = ci_get_pi(rdev);
1317
1318         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1319                 PPSMC_Result smc_result =
1320                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1321                 if (smc_result != PPSMC_Result_OK)
1322                         return -EINVAL;
1323         }
1324
1325         return 0;
1326 }
1327
1328 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1329                                        u32 target_tdp)
1330 {
1331         PPSMC_Result smc_result =
1332                 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1333         if (smc_result != PPSMC_Result_OK)
1334                 return -EINVAL;
1335         return 0;
1336 }
1337
1338 static int ci_set_boot_state(struct radeon_device *rdev)
1339 {
1340         return ci_enable_sclk_mclk_dpm(rdev, false);
1341 }
1342
1343 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1344 {
1345         u32 sclk_freq;
1346         PPSMC_Result smc_result =
1347                 ci_send_msg_to_smc_return_parameter(rdev,
1348                                                     PPSMC_MSG_API_GetSclkFrequency,
1349                                                     &sclk_freq);
1350         if (smc_result != PPSMC_Result_OK)
1351                 sclk_freq = 0;
1352
1353         return sclk_freq;
1354 }
1355
1356 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1357 {
1358         u32 mclk_freq;
1359         PPSMC_Result smc_result =
1360                 ci_send_msg_to_smc_return_parameter(rdev,
1361                                                     PPSMC_MSG_API_GetMclkFrequency,
1362                                                     &mclk_freq);
1363         if (smc_result != PPSMC_Result_OK)
1364                 mclk_freq = 0;
1365
1366         return mclk_freq;
1367 }
1368
1369 static void ci_dpm_start_smc(struct radeon_device *rdev)
1370 {
1371         int i;
1372
1373         ci_program_jump_on_start(rdev);
1374         ci_start_smc_clock(rdev);
1375         ci_start_smc(rdev);
1376         for (i = 0; i < rdev->usec_timeout; i++) {
1377                 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1378                         break;
1379         }
1380 }
1381
1382 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1383 {
1384         ci_reset_smc(rdev);
1385         ci_stop_smc_clock(rdev);
1386 }
1387
1388 static int ci_process_firmware_header(struct radeon_device *rdev)
1389 {
1390         struct ci_power_info *pi = ci_get_pi(rdev);
1391         u32 tmp;
1392         int ret;
1393
1394         ret = ci_read_smc_sram_dword(rdev,
1395                                      SMU7_FIRMWARE_HEADER_LOCATION +
1396                                      offsetof(SMU7_Firmware_Header, DpmTable),
1397                                      &tmp, pi->sram_end);
1398         if (ret)
1399                 return ret;
1400
1401         pi->dpm_table_start = tmp;
1402
1403         ret = ci_read_smc_sram_dword(rdev,
1404                                      SMU7_FIRMWARE_HEADER_LOCATION +
1405                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
1406                                      &tmp, pi->sram_end);
1407         if (ret)
1408                 return ret;
1409
1410         pi->soft_regs_start = tmp;
1411
1412         ret = ci_read_smc_sram_dword(rdev,
1413                                      SMU7_FIRMWARE_HEADER_LOCATION +
1414                                      offsetof(SMU7_Firmware_Header, mcRegisterTable),
1415                                      &tmp, pi->sram_end);
1416         if (ret)
1417                 return ret;
1418
1419         pi->mc_reg_table_start = tmp;
1420
1421         ret = ci_read_smc_sram_dword(rdev,
1422                                      SMU7_FIRMWARE_HEADER_LOCATION +
1423                                      offsetof(SMU7_Firmware_Header, FanTable),
1424                                      &tmp, pi->sram_end);
1425         if (ret)
1426                 return ret;
1427
1428         pi->fan_table_start = tmp;
1429
1430         ret = ci_read_smc_sram_dword(rdev,
1431                                      SMU7_FIRMWARE_HEADER_LOCATION +
1432                                      offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1433                                      &tmp, pi->sram_end);
1434         if (ret)
1435                 return ret;
1436
1437         pi->arb_table_start = tmp;
1438
1439         return 0;
1440 }
1441
1442 static void ci_read_clock_registers(struct radeon_device *rdev)
1443 {
1444         struct ci_power_info *pi = ci_get_pi(rdev);
1445
1446         pi->clock_registers.cg_spll_func_cntl =
1447                 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1448         pi->clock_registers.cg_spll_func_cntl_2 =
1449                 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1450         pi->clock_registers.cg_spll_func_cntl_3 =
1451                 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1452         pi->clock_registers.cg_spll_func_cntl_4 =
1453                 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1454         pi->clock_registers.cg_spll_spread_spectrum =
1455                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1456         pi->clock_registers.cg_spll_spread_spectrum_2 =
1457                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1458         pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1459         pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1460         pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1461         pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1462         pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1463         pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1464         pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1465         pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1466         pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1467 }
1468
1469 static void ci_init_sclk_t(struct radeon_device *rdev)
1470 {
1471         struct ci_power_info *pi = ci_get_pi(rdev);
1472
1473         pi->low_sclk_interrupt_t = 0;
1474 }
1475
1476 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1477                                          bool enable)
1478 {
1479         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1480
1481         if (enable)
1482                 tmp &= ~THERMAL_PROTECTION_DIS;
1483         else
1484                 tmp |= THERMAL_PROTECTION_DIS;
1485         WREG32_SMC(GENERAL_PWRMGT, tmp);
1486 }
1487
1488 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1489 {
1490         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1491
1492         tmp |= STATIC_PM_EN;
1493
1494         WREG32_SMC(GENERAL_PWRMGT, tmp);
1495 }
1496
1497 #if 0
1498 static int ci_enter_ulp_state(struct radeon_device *rdev)
1499 {
1500
1501         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1502
1503         udelay(25000);
1504
1505         return 0;
1506 }
1507
1508 static int ci_exit_ulp_state(struct radeon_device *rdev)
1509 {
1510         int i;
1511
1512         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1513
1514         udelay(7000);
1515
1516         for (i = 0; i < rdev->usec_timeout; i++) {
1517                 if (RREG32(SMC_RESP_0) == 1)
1518                         break;
1519                 udelay(1000);
1520         }
1521
1522         return 0;
1523 }
1524 #endif
1525
1526 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1527                                         bool has_display)
1528 {
1529         PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1530
1531         return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
1532 }
1533
1534 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1535                                       bool enable)
1536 {
1537         struct ci_power_info *pi = ci_get_pi(rdev);
1538
1539         if (enable) {
1540                 if (pi->caps_sclk_ds) {
1541                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1542                                 return -EINVAL;
1543                 } else {
1544                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1545                                 return -EINVAL;
1546                 }
1547         } else {
1548                 if (pi->caps_sclk_ds) {
1549                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1550                                 return -EINVAL;
1551                 }
1552         }
1553
1554         return 0;
1555 }
1556
1557 static void ci_program_display_gap(struct radeon_device *rdev)
1558 {
1559         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1560         u32 pre_vbi_time_in_us;
1561         u32 frame_time_in_us;
1562         u32 ref_clock = rdev->clock.spll.reference_freq;
1563         u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1564         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1565
1566         tmp &= ~DISP_GAP_MASK;
1567         if (rdev->pm.dpm.new_active_crtc_count > 0)
1568                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1569         else
1570                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1571         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1572
1573         if (refresh_rate == 0)
1574                 refresh_rate = 60;
1575         if (vblank_time == 0xffffffff)
1576                 vblank_time = 500;
1577         frame_time_in_us = 1000000 / refresh_rate;
1578         pre_vbi_time_in_us =
1579                 frame_time_in_us - 200 - vblank_time;
1580         tmp = pre_vbi_time_in_us * (ref_clock / 100);
1581
1582         WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1583         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1584         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1585
1586
1587         ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1588
1589 }
1590
1591 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1592 {
1593         struct ci_power_info *pi = ci_get_pi(rdev);
1594         u32 tmp;
1595
1596         if (enable) {
1597                 if (pi->caps_sclk_ss_support) {
1598                         tmp = RREG32_SMC(GENERAL_PWRMGT);
1599                         tmp |= DYN_SPREAD_SPECTRUM_EN;
1600                         WREG32_SMC(GENERAL_PWRMGT, tmp);
1601                 }
1602         } else {
1603                 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1604                 tmp &= ~SSEN;
1605                 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
1606
1607                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1608                 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
1609                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1610         }
1611 }
1612
1613 static void ci_program_sstp(struct radeon_device *rdev)
1614 {
1615         WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
1616 }
1617
1618 static void ci_enable_display_gap(struct radeon_device *rdev)
1619 {
1620         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1621
1622         tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
1623         tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1624                 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
1625
1626         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1627 }
1628
1629 static void ci_program_vc(struct radeon_device *rdev)
1630 {
1631         u32 tmp;
1632
1633         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1634         tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
1635         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1636
1637         WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
1638         WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
1639         WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
1640         WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
1641         WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
1642         WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
1643         WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
1644         WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
1645 }
1646
1647 static void ci_clear_vc(struct radeon_device *rdev)
1648 {
1649         u32 tmp;
1650
1651         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1652         tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
1653         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1654
1655         WREG32_SMC(CG_FTV_0, 0);
1656         WREG32_SMC(CG_FTV_1, 0);
1657         WREG32_SMC(CG_FTV_2, 0);
1658         WREG32_SMC(CG_FTV_3, 0);
1659         WREG32_SMC(CG_FTV_4, 0);
1660         WREG32_SMC(CG_FTV_5, 0);
1661         WREG32_SMC(CG_FTV_6, 0);
1662         WREG32_SMC(CG_FTV_7, 0);
1663 }
1664
1665 static int ci_upload_firmware(struct radeon_device *rdev)
1666 {
1667         struct ci_power_info *pi = ci_get_pi(rdev);
1668         int i, ret;
1669
1670         for (i = 0; i < rdev->usec_timeout; i++) {
1671                 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
1672                         break;
1673         }
1674         WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
1675
1676         ci_stop_smc_clock(rdev);
1677         ci_reset_smc(rdev);
1678
1679         ret = ci_load_smc_ucode(rdev, pi->sram_end);
1680
1681         return ret;
1682
1683 }
1684
1685 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
1686                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
1687                                      struct atom_voltage_table *voltage_table)
1688 {
1689         u32 i;
1690
1691         if (voltage_dependency_table == NULL)
1692                 return -EINVAL;
1693
1694         voltage_table->mask_low = 0;
1695         voltage_table->phase_delay = 0;
1696
1697         voltage_table->count = voltage_dependency_table->count;
1698         for (i = 0; i < voltage_table->count; i++) {
1699                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
1700                 voltage_table->entries[i].smio_low = 0;
1701         }
1702
1703         return 0;
1704 }
1705
1706 static int ci_construct_voltage_tables(struct radeon_device *rdev)
1707 {
1708         struct ci_power_info *pi = ci_get_pi(rdev);
1709         int ret;
1710
1711         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1712                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
1713                                                     VOLTAGE_OBJ_GPIO_LUT,
1714                                                     &pi->vddc_voltage_table);
1715                 if (ret)
1716                         return ret;
1717         } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1718                 ret = ci_get_svi2_voltage_table(rdev,
1719                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
1720                                                 &pi->vddc_voltage_table);
1721                 if (ret)
1722                         return ret;
1723         }
1724
1725         if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
1726                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
1727                                                          &pi->vddc_voltage_table);
1728
1729         if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1730                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
1731                                                     VOLTAGE_OBJ_GPIO_LUT,
1732                                                     &pi->vddci_voltage_table);
1733                 if (ret)
1734                         return ret;
1735         } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1736                 ret = ci_get_svi2_voltage_table(rdev,
1737                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
1738                                                 &pi->vddci_voltage_table);
1739                 if (ret)
1740                         return ret;
1741         }
1742
1743         if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
1744                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
1745                                                          &pi->vddci_voltage_table);
1746
1747         if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1748                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
1749                                                     VOLTAGE_OBJ_GPIO_LUT,
1750                                                     &pi->mvdd_voltage_table);
1751                 if (ret)
1752                         return ret;
1753         } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1754                 ret = ci_get_svi2_voltage_table(rdev,
1755                                                 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
1756                                                 &pi->mvdd_voltage_table);
1757                 if (ret)
1758                         return ret;
1759         }
1760
1761         if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
1762                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
1763                                                          &pi->mvdd_voltage_table);
1764
1765         return 0;
1766 }
1767
1768 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
1769                                           struct atom_voltage_table_entry *voltage_table,
1770                                           SMU7_Discrete_VoltageLevel *smc_voltage_table)
1771 {
1772         int ret;
1773
1774         ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
1775                                             &smc_voltage_table->StdVoltageHiSidd,
1776                                             &smc_voltage_table->StdVoltageLoSidd);
1777
1778         if (ret) {
1779                 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
1780                 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
1781         }
1782
1783         smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
1784         smc_voltage_table->StdVoltageHiSidd =
1785                 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
1786         smc_voltage_table->StdVoltageLoSidd =
1787                 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
1788 }
1789
1790 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
1791                                       SMU7_Discrete_DpmTable *table)
1792 {
1793         struct ci_power_info *pi = ci_get_pi(rdev);
1794         unsigned int count;
1795
1796         table->VddcLevelCount = pi->vddc_voltage_table.count;
1797         for (count = 0; count < table->VddcLevelCount; count++) {
1798                 ci_populate_smc_voltage_table(rdev,
1799                                               &pi->vddc_voltage_table.entries[count],
1800                                               &table->VddcLevel[count]);
1801
1802                 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1803                         table->VddcLevel[count].Smio |=
1804                                 pi->vddc_voltage_table.entries[count].smio_low;
1805                 else
1806                         table->VddcLevel[count].Smio = 0;
1807         }
1808         table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
1809
1810         return 0;
1811 }
1812
1813 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
1814                                        SMU7_Discrete_DpmTable *table)
1815 {
1816         unsigned int count;
1817         struct ci_power_info *pi = ci_get_pi(rdev);
1818
1819         table->VddciLevelCount = pi->vddci_voltage_table.count;
1820         for (count = 0; count < table->VddciLevelCount; count++) {
1821                 ci_populate_smc_voltage_table(rdev,
1822                                               &pi->vddci_voltage_table.entries[count],
1823                                               &table->VddciLevel[count]);
1824
1825                 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1826                         table->VddciLevel[count].Smio |=
1827                                 pi->vddci_voltage_table.entries[count].smio_low;
1828                 else
1829                         table->VddciLevel[count].Smio = 0;
1830         }
1831         table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
1832
1833         return 0;
1834 }
1835
1836 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
1837                                       SMU7_Discrete_DpmTable *table)
1838 {
1839         struct ci_power_info *pi = ci_get_pi(rdev);
1840         unsigned int count;
1841
1842         table->MvddLevelCount = pi->mvdd_voltage_table.count;
1843         for (count = 0; count < table->MvddLevelCount; count++) {
1844                 ci_populate_smc_voltage_table(rdev,
1845                                               &pi->mvdd_voltage_table.entries[count],
1846                                               &table->MvddLevel[count]);
1847
1848                 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1849                         table->MvddLevel[count].Smio |=
1850                                 pi->mvdd_voltage_table.entries[count].smio_low;
1851                 else
1852                         table->MvddLevel[count].Smio = 0;
1853         }
1854         table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
1855
1856         return 0;
1857 }
1858
1859 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
1860                                           SMU7_Discrete_DpmTable *table)
1861 {
1862         int ret;
1863
1864         ret = ci_populate_smc_vddc_table(rdev, table);
1865         if (ret)
1866                 return ret;
1867
1868         ret = ci_populate_smc_vddci_table(rdev, table);
1869         if (ret)
1870                 return ret;
1871
1872         ret = ci_populate_smc_mvdd_table(rdev, table);
1873         if (ret)
1874                 return ret;
1875
1876         return 0;
1877 }
1878
1879 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
1880                                   SMU7_Discrete_VoltageLevel *voltage)
1881 {
1882         struct ci_power_info *pi = ci_get_pi(rdev);
1883         u32 i = 0;
1884
1885         if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
1886                 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
1887                         if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
1888                                 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
1889                                 break;
1890                         }
1891                 }
1892
1893                 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
1894                         return -EINVAL;
1895         }
1896
1897         return -EINVAL;
1898 }
1899
1900 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
1901                                          struct atom_voltage_table_entry *voltage_table,
1902                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
1903 {
1904         u16 v_index, idx;
1905         bool voltage_found = false;
1906         *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
1907         *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
1908
1909         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
1910                 return -EINVAL;
1911
1912         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
1913                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1914                         if (voltage_table->value ==
1915                             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1916                                 voltage_found = true;
1917                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1918                                         idx = v_index;
1919                                 else
1920                                         idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1921                                 *std_voltage_lo_sidd =
1922                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1923                                 *std_voltage_hi_sidd =
1924                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1925                                 break;
1926                         }
1927                 }
1928
1929                 if (!voltage_found) {
1930                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1931                                 if (voltage_table->value <=
1932                                     rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1933                                         voltage_found = true;
1934                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1935                                                 idx = v_index;
1936                                         else
1937                                                 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1938                                         *std_voltage_lo_sidd =
1939                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1940                                         *std_voltage_hi_sidd =
1941                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1942                                         break;
1943                                 }
1944                         }
1945                 }
1946         }
1947
1948         return 0;
1949 }
1950
1951 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
1952                                                   const struct radeon_phase_shedding_limits_table *limits,
1953                                                   u32 sclk,
1954                                                   u32 *phase_shedding)
1955 {
1956         unsigned int i;
1957
1958         *phase_shedding = 1;
1959
1960         for (i = 0; i < limits->count; i++) {
1961                 if (sclk < limits->entries[i].sclk) {
1962                         *phase_shedding = i;
1963                         break;
1964                 }
1965         }
1966 }
1967
1968 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
1969                                                   const struct radeon_phase_shedding_limits_table *limits,
1970                                                   u32 mclk,
1971                                                   u32 *phase_shedding)
1972 {
1973         unsigned int i;
1974
1975         *phase_shedding = 1;
1976
1977         for (i = 0; i < limits->count; i++) {
1978                 if (mclk < limits->entries[i].mclk) {
1979                         *phase_shedding = i;
1980                         break;
1981                 }
1982         }
1983 }
1984
1985 static int ci_init_arb_table_index(struct radeon_device *rdev)
1986 {
1987         struct ci_power_info *pi = ci_get_pi(rdev);
1988         u32 tmp;
1989         int ret;
1990
1991         ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
1992                                      &tmp, pi->sram_end);
1993         if (ret)
1994                 return ret;
1995
1996         tmp &= 0x00FFFFFF;
1997         tmp |= MC_CG_ARB_FREQ_F1 << 24;
1998
1999         return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2000                                        tmp, pi->sram_end);
2001 }
2002
2003 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2004                                          struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2005                                          u32 clock, u32 *voltage)
2006 {
2007         u32 i = 0;
2008
2009         if (allowed_clock_voltage_table->count == 0)
2010                 return -EINVAL;
2011
2012         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2013                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2014                         *voltage = allowed_clock_voltage_table->entries[i].v;
2015                         return 0;
2016                 }
2017         }
2018
2019         *voltage = allowed_clock_voltage_table->entries[i-1].v;
2020
2021         return 0;
2022 }
2023
2024 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2025                                              u32 sclk, u32 min_sclk_in_sr)
2026 {
2027         u32 i;
2028         u32 tmp;
2029         u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2030                 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2031
2032         if (sclk < min)
2033                 return 0;
2034
2035         for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
2036                 tmp = sclk / (1 << i);
2037                 if (tmp >= min || i == 0)
2038                         break;
2039         }
2040
2041         return (u8)i;
2042 }
2043
2044 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2045 {
2046         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2047 }
2048
2049 static int ci_reset_to_default(struct radeon_device *rdev)
2050 {
2051         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2052                 0 : -EINVAL;
2053 }
2054
2055 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2056 {
2057         u32 tmp;
2058
2059         tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2060
2061         if (tmp == MC_CG_ARB_FREQ_F0)
2062                 return 0;
2063
2064         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2065 }
2066
2067 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2068                                                 u32 sclk,
2069                                                 u32 mclk,
2070                                                 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2071 {
2072         u32 dram_timing;
2073         u32 dram_timing2;
2074         u32 burst_time;
2075
2076         radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2077
2078         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
2079         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2080         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2081
2082         arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
2083         arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2084         arb_regs->McArbBurstTime = (u8)burst_time;
2085
2086         return 0;
2087 }
2088
2089 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2090 {
2091         struct ci_power_info *pi = ci_get_pi(rdev);
2092         SMU7_Discrete_MCArbDramTimingTable arb_regs;
2093         u32 i, j;
2094         int ret =  0;
2095
2096         memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2097
2098         for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2099                 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2100                         ret = ci_populate_memory_timing_parameters(rdev,
2101                                                                    pi->dpm_table.sclk_table.dpm_levels[i].value,
2102                                                                    pi->dpm_table.mclk_table.dpm_levels[j].value,
2103                                                                    &arb_regs.entries[i][j]);
2104                         if (ret)
2105                                 break;
2106                 }
2107         }
2108
2109         if (ret == 0)
2110                 ret = ci_copy_bytes_to_smc(rdev,
2111                                            pi->arb_table_start,
2112                                            (u8 *)&arb_regs,
2113                                            sizeof(SMU7_Discrete_MCArbDramTimingTable),
2114                                            pi->sram_end);
2115
2116         return ret;
2117 }
2118
2119 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2120 {
2121         struct ci_power_info *pi = ci_get_pi(rdev);
2122
2123         if (pi->need_update_smu7_dpm_table == 0)
2124                 return 0;
2125
2126         return ci_do_program_memory_timing_parameters(rdev);
2127 }
2128
2129 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2130                                           struct radeon_ps *radeon_boot_state)
2131 {
2132         struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2133         struct ci_power_info *pi = ci_get_pi(rdev);
2134         u32 level = 0;
2135
2136         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2137                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2138                     boot_state->performance_levels[0].sclk) {
2139                         pi->smc_state_table.GraphicsBootLevel = level;
2140                         break;
2141                 }
2142         }
2143
2144         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2145                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2146                     boot_state->performance_levels[0].mclk) {
2147                         pi->smc_state_table.MemoryBootLevel = level;
2148                         break;
2149                 }
2150         }
2151 }
2152
2153 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2154 {
2155         u32 i;
2156         u32 mask_value = 0;
2157
2158         for (i = dpm_table->count; i > 0; i--) {
2159                 mask_value = mask_value << 1;
2160                 if (dpm_table->dpm_levels[i-1].enabled)
2161                         mask_value |= 0x1;
2162                 else
2163                         mask_value &= 0xFFFFFFFE;
2164         }
2165
2166         return mask_value;
2167 }
2168
2169 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2170                                        SMU7_Discrete_DpmTable *table)
2171 {
2172         struct ci_power_info *pi = ci_get_pi(rdev);
2173         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2174         u32 i;
2175
2176         for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2177                 table->LinkLevel[i].PcieGenSpeed =
2178                         (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2179                 table->LinkLevel[i].PcieLaneCount =
2180                         r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2181                 table->LinkLevel[i].EnabledForActivity = 1;
2182                 table->LinkLevel[i].DownT = cpu_to_be32(5);
2183                 table->LinkLevel[i].UpT = cpu_to_be32(30);
2184         }
2185
2186         pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2187         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2188                 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2189 }
2190
2191 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2192                                      SMU7_Discrete_DpmTable *table)
2193 {
2194         u32 count;
2195         struct atom_clock_dividers dividers;
2196         int ret = -EINVAL;
2197
2198         table->UvdLevelCount =
2199                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2200
2201         for (count = 0; count < table->UvdLevelCount; count++) {
2202                 table->UvdLevel[count].VclkFrequency =
2203                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2204                 table->UvdLevel[count].DclkFrequency =
2205                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2206                 table->UvdLevel[count].MinVddc =
2207                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2208                 table->UvdLevel[count].MinVddcPhases = 1;
2209
2210                 ret = radeon_atom_get_clock_dividers(rdev,
2211                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2212                                                      table->UvdLevel[count].VclkFrequency, false, &dividers);
2213                 if (ret)
2214                         return ret;
2215
2216                 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2217
2218                 ret = radeon_atom_get_clock_dividers(rdev,
2219                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2220                                                      table->UvdLevel[count].DclkFrequency, false, &dividers);
2221                 if (ret)
2222                         return ret;
2223
2224                 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2225
2226                 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2227                 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2228                 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2229         }
2230
2231         return ret;
2232 }
2233
2234 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2235                                      SMU7_Discrete_DpmTable *table)
2236 {
2237         u32 count;
2238         struct atom_clock_dividers dividers;
2239         int ret = -EINVAL;
2240
2241         table->VceLevelCount =
2242                 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2243
2244         for (count = 0; count < table->VceLevelCount; count++) {
2245                 table->VceLevel[count].Frequency =
2246                         rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2247                 table->VceLevel[count].MinVoltage =
2248                         (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2249                 table->VceLevel[count].MinPhases = 1;
2250
2251                 ret = radeon_atom_get_clock_dividers(rdev,
2252                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2253                                                      table->VceLevel[count].Frequency, false, &dividers);
2254                 if (ret)
2255                         return ret;
2256
2257                 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2258
2259                 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2260                 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2261         }
2262
2263         return ret;
2264
2265 }
2266
2267 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2268                                      SMU7_Discrete_DpmTable *table)
2269 {
2270         u32 count;
2271         struct atom_clock_dividers dividers;
2272         int ret = -EINVAL;
2273
2274         table->AcpLevelCount = (u8)
2275                 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2276
2277         for (count = 0; count < table->AcpLevelCount; count++) {
2278                 table->AcpLevel[count].Frequency =
2279                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2280                 table->AcpLevel[count].MinVoltage =
2281                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2282                 table->AcpLevel[count].MinPhases = 1;
2283
2284                 ret = radeon_atom_get_clock_dividers(rdev,
2285                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2286                                                      table->AcpLevel[count].Frequency, false, &dividers);
2287                 if (ret)
2288                         return ret;
2289
2290                 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2291
2292                 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2293                 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2294         }
2295
2296         return ret;
2297 }
2298
2299 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2300                                       SMU7_Discrete_DpmTable *table)
2301 {
2302         u32 count;
2303         struct atom_clock_dividers dividers;
2304         int ret = -EINVAL;
2305
2306         table->SamuLevelCount =
2307                 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2308
2309         for (count = 0; count < table->SamuLevelCount; count++) {
2310                 table->SamuLevel[count].Frequency =
2311                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2312                 table->SamuLevel[count].MinVoltage =
2313                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2314                 table->SamuLevel[count].MinPhases = 1;
2315
2316                 ret = radeon_atom_get_clock_dividers(rdev,
2317                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2318                                                      table->SamuLevel[count].Frequency, false, &dividers);
2319                 if (ret)
2320                         return ret;
2321
2322                 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2323
2324                 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2325                 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2326         }
2327
2328         return ret;
2329 }
2330
2331 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2332                                     u32 memory_clock,
2333                                     SMU7_Discrete_MemoryLevel *mclk,
2334                                     bool strobe_mode,
2335                                     bool dll_state_on)
2336 {
2337         struct ci_power_info *pi = ci_get_pi(rdev);
2338         u32  dll_cntl = pi->clock_registers.dll_cntl;
2339         u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2340         u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2341         u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2342         u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2343         u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2344         u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2345         u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
2346         u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
2347         struct atom_mpll_param mpll_param;
2348         int ret;
2349
2350         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2351         if (ret)
2352                 return ret;
2353
2354         mpll_func_cntl &= ~BWCTRL_MASK;
2355         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2356
2357         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2358         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2359                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2360
2361         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2362         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2363
2364         if (pi->mem_gddr5) {
2365                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2366                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2367                         YCLK_POST_DIV(mpll_param.post_div);
2368         }
2369
2370         if (pi->caps_mclk_ss_support) {
2371                 struct radeon_atom_ss ss;
2372                 u32 freq_nom;
2373                 u32 tmp;
2374                 u32 reference_clock = rdev->clock.mpll.reference_freq;
2375
2376                 if (pi->mem_gddr5)
2377                         freq_nom = memory_clock * 4;
2378                 else
2379                         freq_nom = memory_clock * 2;
2380
2381                 tmp = (freq_nom / reference_clock);
2382                 tmp = tmp * tmp;
2383                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2384                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2385                         u32 clks = reference_clock * 5 / ss.rate;
2386                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2387
2388                         mpll_ss1 &= ~CLKV_MASK;
2389                         mpll_ss1 |= CLKV(clkv);
2390
2391                         mpll_ss2 &= ~CLKS_MASK;
2392                         mpll_ss2 |= CLKS(clks);
2393                 }
2394         }
2395
2396         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2397         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2398
2399         if (dll_state_on)
2400                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2401         else
2402                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2403
2404         mclk->MclkFrequency = memory_clock;
2405         mclk->MpllFuncCntl = mpll_func_cntl;
2406         mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2407         mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2408         mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2409         mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2410         mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2411         mclk->DllCntl = dll_cntl;
2412         mclk->MpllSs1 = mpll_ss1;
2413         mclk->MpllSs2 = mpll_ss2;
2414
2415         return 0;
2416 }
2417
2418 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2419                                            u32 memory_clock,
2420                                            SMU7_Discrete_MemoryLevel *memory_level)
2421 {
2422         struct ci_power_info *pi = ci_get_pi(rdev);
2423         int ret;
2424         bool dll_state_on;
2425
2426         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2427                 ret = ci_get_dependency_volt_by_clk(rdev,
2428                                                     &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2429                                                     memory_clock, &memory_level->MinVddc);
2430                 if (ret)
2431                         return ret;
2432         }
2433
2434         if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2435                 ret = ci_get_dependency_volt_by_clk(rdev,
2436                                                     &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2437                                                     memory_clock, &memory_level->MinVddci);
2438                 if (ret)
2439                         return ret;
2440         }
2441
2442         if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2443                 ret = ci_get_dependency_volt_by_clk(rdev,
2444                                                     &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2445                                                     memory_clock, &memory_level->MinMvdd);
2446                 if (ret)
2447                         return ret;
2448         }
2449
2450         memory_level->MinVddcPhases = 1;
2451
2452         if (pi->vddc_phase_shed_control)
2453                 ci_populate_phase_value_based_on_mclk(rdev,
2454                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2455                                                       memory_clock,
2456                                                       &memory_level->MinVddcPhases);
2457
2458         memory_level->EnabledForThrottle = 1;
2459         memory_level->EnabledForActivity = 1;
2460         memory_level->UpH = 0;
2461         memory_level->DownH = 100;
2462         memory_level->VoltageDownH = 0;
2463         memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2464
2465         memory_level->StutterEnable = false;
2466         memory_level->StrobeEnable = false;
2467         memory_level->EdcReadEnable = false;
2468         memory_level->EdcWriteEnable = false;
2469         memory_level->RttEnable = false;
2470
2471         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2472
2473         if (pi->mclk_stutter_mode_threshold &&
2474             (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2475             (pi->uvd_enabled == false) &&
2476             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2477             (rdev->pm.dpm.new_active_crtc_count <= 2))
2478                 memory_level->StutterEnable = true;
2479
2480         if (pi->mclk_strobe_mode_threshold &&
2481             (memory_clock <= pi->mclk_strobe_mode_threshold))
2482                 memory_level->StrobeEnable = 1;
2483
2484         if (pi->mem_gddr5) {
2485                 memory_level->StrobeRatio =
2486                         si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2487                 if (pi->mclk_edc_enable_threshold &&
2488                     (memory_clock > pi->mclk_edc_enable_threshold))
2489                         memory_level->EdcReadEnable = true;
2490
2491                 if (pi->mclk_edc_wr_enable_threshold &&
2492                     (memory_clock > pi->mclk_edc_wr_enable_threshold))
2493                         memory_level->EdcWriteEnable = true;
2494
2495                 if (memory_level->StrobeEnable) {
2496                         if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2497                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2498                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2499                         else
2500                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2501                 } else {
2502                         dll_state_on = pi->dll_default_on;
2503                 }
2504         } else {
2505                 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2506                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2507         }
2508
2509         ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2510         if (ret)
2511                 return ret;
2512
2513         memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2514         memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2515         memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2516         memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2517
2518         memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2519         memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2520         memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2521         memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2522         memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2523         memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2524         memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2525         memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2526         memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2527         memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2528         memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2529
2530         return 0;
2531 }
2532
2533 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2534                                       SMU7_Discrete_DpmTable *table)
2535 {
2536         struct ci_power_info *pi = ci_get_pi(rdev);
2537         struct atom_clock_dividers dividers;
2538         SMU7_Discrete_VoltageLevel voltage_level;
2539         u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2540         u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2541         u32 dll_cntl = pi->clock_registers.dll_cntl;
2542         u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2543         int ret;
2544
2545         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2546
2547         if (pi->acpi_vddc)
2548                 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2549         else
2550                 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2551
2552         table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2553
2554         table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2555
2556         ret = radeon_atom_get_clock_dividers(rdev,
2557                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2558                                              table->ACPILevel.SclkFrequency, false, &dividers);
2559         if (ret)
2560                 return ret;
2561
2562         table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2563         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2564         table->ACPILevel.DeepSleepDivId = 0;
2565
2566         spll_func_cntl &= ~SPLL_PWRON;
2567         spll_func_cntl |= SPLL_RESET;
2568
2569         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2570         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
2571
2572         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2573         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2574         table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2575         table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
2576         table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
2577         table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2578         table->ACPILevel.CcPwrDynRm = 0;
2579         table->ACPILevel.CcPwrDynRm1 = 0;
2580
2581         table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
2582         table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
2583         table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
2584         table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
2585         table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
2586         table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
2587         table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
2588         table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
2589         table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
2590         table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
2591         table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
2592
2593         table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
2594         table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
2595
2596         if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2597                 if (pi->acpi_vddci)
2598                         table->MemoryACPILevel.MinVddci =
2599                                 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
2600                 else
2601                         table->MemoryACPILevel.MinVddci =
2602                                 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
2603         }
2604
2605         if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
2606                 table->MemoryACPILevel.MinMvdd = 0;
2607         else
2608                 table->MemoryACPILevel.MinMvdd =
2609                         cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
2610
2611         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
2612         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2613
2614         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
2615
2616         table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
2617         table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
2618         table->MemoryACPILevel.MpllAdFuncCntl =
2619                 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
2620         table->MemoryACPILevel.MpllDqFuncCntl =
2621                 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
2622         table->MemoryACPILevel.MpllFuncCntl =
2623                 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
2624         table->MemoryACPILevel.MpllFuncCntl_1 =
2625                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
2626         table->MemoryACPILevel.MpllFuncCntl_2 =
2627                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
2628         table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
2629         table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
2630
2631         table->MemoryACPILevel.EnabledForThrottle = 0;
2632         table->MemoryACPILevel.EnabledForActivity = 0;
2633         table->MemoryACPILevel.UpH = 0;
2634         table->MemoryACPILevel.DownH = 100;
2635         table->MemoryACPILevel.VoltageDownH = 0;
2636         table->MemoryACPILevel.ActivityLevel =
2637                 cpu_to_be16((u16)pi->mclk_activity_target);
2638
2639         table->MemoryACPILevel.StutterEnable = false;
2640         table->MemoryACPILevel.StrobeEnable = false;
2641         table->MemoryACPILevel.EdcReadEnable = false;
2642         table->MemoryACPILevel.EdcWriteEnable = false;
2643         table->MemoryACPILevel.RttEnable = false;
2644
2645         return 0;
2646 }
2647
2648
2649 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
2650 {
2651         struct ci_power_info *pi = ci_get_pi(rdev);
2652         struct ci_ulv_parm *ulv = &pi->ulv;
2653
2654         if (ulv->supported) {
2655                 if (enable)
2656                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
2657                                 0 : -EINVAL;
2658                 else
2659                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
2660                                 0 : -EINVAL;
2661         }
2662
2663         return 0;
2664 }
2665
2666 static int ci_populate_ulv_level(struct radeon_device *rdev,
2667                                  SMU7_Discrete_Ulv *state)
2668 {
2669         struct ci_power_info *pi = ci_get_pi(rdev);
2670         u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
2671
2672         state->CcPwrDynRm = 0;
2673         state->CcPwrDynRm1 = 0;
2674
2675         if (ulv_voltage == 0) {
2676                 pi->ulv.supported = false;
2677                 return 0;
2678         }
2679
2680         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2681                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2682                         state->VddcOffset = 0;
2683                 else
2684                         state->VddcOffset =
2685                                 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
2686         } else {
2687                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2688                         state->VddcOffsetVid = 0;
2689                 else
2690                         state->VddcOffsetVid = (u8)
2691                                 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
2692                                  VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2693         }
2694         state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
2695
2696         state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
2697         state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
2698         state->VddcOffset = cpu_to_be16(state->VddcOffset);
2699
2700         return 0;
2701 }
2702
2703 static int ci_calculate_sclk_params(struct radeon_device *rdev,
2704                                     u32 engine_clock,
2705                                     SMU7_Discrete_GraphicsLevel *sclk)
2706 {
2707         struct ci_power_info *pi = ci_get_pi(rdev);
2708         struct atom_clock_dividers dividers;
2709         u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
2710         u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
2711         u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
2712         u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2713         u32 reference_clock = rdev->clock.spll.reference_freq;
2714         u32 reference_divider;
2715         u32 fbdiv;
2716         int ret;
2717
2718         ret = radeon_atom_get_clock_dividers(rdev,
2719                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2720                                              engine_clock, false, &dividers);
2721         if (ret)
2722                 return ret;
2723
2724         reference_divider = 1 + dividers.ref_div;
2725         fbdiv = dividers.fb_div & 0x3FFFFFF;
2726
2727         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2728         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2729         spll_func_cntl_3 |= SPLL_DITHEN;
2730
2731         if (pi->caps_sclk_ss_support) {
2732                 struct radeon_atom_ss ss;
2733                 u32 vco_freq = engine_clock * dividers.post_div;
2734
2735                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2736                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2737                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2738                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2739
2740                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
2741                         cg_spll_spread_spectrum |= CLK_S(clk_s);
2742                         cg_spll_spread_spectrum |= SSEN;
2743
2744                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2745                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2746                 }
2747         }
2748
2749         sclk->SclkFrequency = engine_clock;
2750         sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2751         sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2752         sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2753         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
2754         sclk->SclkDid = (u8)dividers.post_divider;
2755
2756         return 0;
2757 }
2758
2759 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
2760                                             u32 engine_clock,
2761                                             u16 sclk_activity_level_t,
2762                                             SMU7_Discrete_GraphicsLevel *graphic_level)
2763 {
2764         struct ci_power_info *pi = ci_get_pi(rdev);
2765         int ret;
2766
2767         ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
2768         if (ret)
2769                 return ret;
2770
2771         ret = ci_get_dependency_volt_by_clk(rdev,
2772                                             &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2773                                             engine_clock, &graphic_level->MinVddc);
2774         if (ret)
2775                 return ret;
2776
2777         graphic_level->SclkFrequency = engine_clock;
2778
2779         graphic_level->Flags =  0;
2780         graphic_level->MinVddcPhases = 1;
2781
2782         if (pi->vddc_phase_shed_control)
2783                 ci_populate_phase_value_based_on_sclk(rdev,
2784                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2785                                                       engine_clock,
2786                                                       &graphic_level->MinVddcPhases);
2787
2788         graphic_level->ActivityLevel = sclk_activity_level_t;
2789
2790         graphic_level->CcPwrDynRm = 0;
2791         graphic_level->CcPwrDynRm1 = 0;
2792         graphic_level->EnabledForActivity = 1;
2793         graphic_level->EnabledForThrottle = 1;
2794         graphic_level->UpH = 0;
2795         graphic_level->DownH = 0;
2796         graphic_level->VoltageDownH = 0;
2797         graphic_level->PowerThrottle = 0;
2798
2799         if (pi->caps_sclk_ds)
2800                 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
2801                                                                                    engine_clock,
2802                                                                                    CISLAND_MINIMUM_ENGINE_CLOCK);
2803
2804         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2805
2806         graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
2807         graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
2808         graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
2809         graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
2810         graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
2811         graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
2812         graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
2813         graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
2814         graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
2815         graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
2816         graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
2817
2818         return 0;
2819 }
2820
2821 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
2822 {
2823         struct ci_power_info *pi = ci_get_pi(rdev);
2824         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2825         u32 level_array_address = pi->dpm_table_start +
2826                 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
2827         u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
2828                 SMU7_MAX_LEVELS_GRAPHICS;
2829         SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
2830         u32 i, ret;
2831
2832         memset(levels, 0, level_array_size);
2833
2834         for (i = 0; i < dpm_table->sclk_table.count; i++) {
2835                 ret = ci_populate_single_graphic_level(rdev,
2836                                                        dpm_table->sclk_table.dpm_levels[i].value,
2837                                                        (u16)pi->activity_target[i],
2838                                                        &pi->smc_state_table.GraphicsLevel[i]);
2839                 if (ret)
2840                         return ret;
2841                 if (i == (dpm_table->sclk_table.count - 1))
2842                         pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
2843                                 PPSMC_DISPLAY_WATERMARK_HIGH;
2844         }
2845
2846         pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
2847         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
2848                 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2849
2850         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2851                                    (u8 *)levels, level_array_size,
2852                                    pi->sram_end);
2853         if (ret)
2854                 return ret;
2855
2856         return 0;
2857 }
2858
2859 static int ci_populate_ulv_state(struct radeon_device *rdev,
2860                                  SMU7_Discrete_Ulv *ulv_level)
2861 {
2862         return ci_populate_ulv_level(rdev, ulv_level);
2863 }
2864
2865 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
2866 {
2867         struct ci_power_info *pi = ci_get_pi(rdev);
2868         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2869         u32 level_array_address = pi->dpm_table_start +
2870                 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
2871         u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
2872                 SMU7_MAX_LEVELS_MEMORY;
2873         SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
2874         u32 i, ret;
2875
2876         memset(levels, 0, level_array_size);
2877
2878         for (i = 0; i < dpm_table->mclk_table.count; i++) {
2879                 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
2880                         return -EINVAL;
2881                 ret = ci_populate_single_memory_level(rdev,
2882                                                       dpm_table->mclk_table.dpm_levels[i].value,
2883                                                       &pi->smc_state_table.MemoryLevel[i]);
2884                 if (ret)
2885                         return ret;
2886         }
2887
2888         pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
2889
2890         pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
2891         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
2892                 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2893
2894         pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
2895                 PPSMC_DISPLAY_WATERMARK_HIGH;
2896
2897         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2898                                    (u8 *)levels, level_array_size,
2899                                    pi->sram_end);
2900         if (ret)
2901                 return ret;
2902
2903         return 0;
2904 }
2905
2906 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
2907                                       struct ci_single_dpm_table* dpm_table,
2908                                       u32 count)
2909 {
2910         u32 i;
2911
2912         dpm_table->count = count;
2913         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
2914                 dpm_table->dpm_levels[i].enabled = false;
2915 }
2916
2917 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
2918                                       u32 index, u32 pcie_gen, u32 pcie_lanes)
2919 {
2920         dpm_table->dpm_levels[index].value = pcie_gen;
2921         dpm_table->dpm_levels[index].param1 = pcie_lanes;
2922         dpm_table->dpm_levels[index].enabled = true;
2923 }
2924
2925 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
2926 {
2927         struct ci_power_info *pi = ci_get_pi(rdev);
2928
2929         if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
2930                 return -EINVAL;
2931
2932         if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
2933                 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
2934                 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
2935         } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
2936                 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
2937                 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
2938         }
2939
2940         ci_reset_single_dpm_table(rdev,
2941                                   &pi->dpm_table.pcie_speed_table,
2942                                   SMU7_MAX_LEVELS_LINK);
2943
2944         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
2945                                   pi->pcie_gen_powersaving.min,
2946                                   pi->pcie_lane_powersaving.min);
2947         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
2948                                   pi->pcie_gen_performance.min,
2949                                   pi->pcie_lane_performance.min);
2950         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
2951                                   pi->pcie_gen_powersaving.min,
2952                                   pi->pcie_lane_powersaving.max);
2953         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
2954                                   pi->pcie_gen_performance.min,
2955                                   pi->pcie_lane_performance.max);
2956         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
2957                                   pi->pcie_gen_powersaving.max,
2958                                   pi->pcie_lane_powersaving.max);
2959         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
2960                                   pi->pcie_gen_performance.max,
2961                                   pi->pcie_lane_performance.max);
2962
2963         pi->dpm_table.pcie_speed_table.count = 6;
2964
2965         return 0;
2966 }
2967
2968 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
2969 {
2970         struct ci_power_info *pi = ci_get_pi(rdev);
2971         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
2972                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2973         struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
2974                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
2975         struct radeon_cac_leakage_table *std_voltage_table =
2976                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2977         u32 i;
2978
2979         if (allowed_sclk_vddc_table == NULL)
2980                 return -EINVAL;
2981         if (allowed_sclk_vddc_table->count < 1)
2982                 return -EINVAL;
2983         if (allowed_mclk_table == NULL)
2984                 return -EINVAL;
2985         if (allowed_mclk_table->count < 1)
2986                 return -EINVAL;
2987
2988         memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
2989
2990         ci_reset_single_dpm_table(rdev,
2991                                   &pi->dpm_table.sclk_table,
2992                                   SMU7_MAX_LEVELS_GRAPHICS);
2993         ci_reset_single_dpm_table(rdev,
2994                                   &pi->dpm_table.mclk_table,
2995                                   SMU7_MAX_LEVELS_MEMORY);
2996         ci_reset_single_dpm_table(rdev,
2997                                   &pi->dpm_table.vddc_table,
2998                                   SMU7_MAX_LEVELS_VDDC);
2999         ci_reset_single_dpm_table(rdev,
3000                                   &pi->dpm_table.vddci_table,
3001                                   SMU7_MAX_LEVELS_VDDCI);
3002         ci_reset_single_dpm_table(rdev,
3003                                   &pi->dpm_table.mvdd_table,
3004                                   SMU7_MAX_LEVELS_MVDD);
3005
3006         pi->dpm_table.sclk_table.count = 0;
3007         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3008                 if ((i == 0) ||
3009                     (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3010                      allowed_sclk_vddc_table->entries[i].clk)) {
3011                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3012                                 allowed_sclk_vddc_table->entries[i].clk;
3013                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true;
3014                         pi->dpm_table.sclk_table.count++;
3015                 }
3016         }
3017
3018         pi->dpm_table.mclk_table.count = 0;
3019         for (i = 0; i < allowed_mclk_table->count; i++) {
3020                 if ((i==0) ||
3021                     (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3022                      allowed_mclk_table->entries[i].clk)) {
3023                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3024                                 allowed_mclk_table->entries[i].clk;
3025                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true;
3026                         pi->dpm_table.mclk_table.count++;
3027                 }
3028         }
3029
3030         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3031                 pi->dpm_table.vddc_table.dpm_levels[i].value =
3032                         allowed_sclk_vddc_table->entries[i].v;
3033                 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3034                         std_voltage_table->entries[i].leakage;
3035                 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3036         }
3037         pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3038
3039         allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3040         if (allowed_mclk_table) {
3041                 for (i = 0; i < allowed_mclk_table->count; i++) {
3042                         pi->dpm_table.vddci_table.dpm_levels[i].value =
3043                                 allowed_mclk_table->entries[i].v;
3044                         pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3045                 }
3046                 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3047         }
3048
3049         allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3050         if (allowed_mclk_table) {
3051                 for (i = 0; i < allowed_mclk_table->count; i++) {
3052                         pi->dpm_table.mvdd_table.dpm_levels[i].value =
3053                                 allowed_mclk_table->entries[i].v;
3054                         pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3055                 }
3056                 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3057         }
3058
3059         ci_setup_default_pcie_tables(rdev);
3060
3061         return 0;
3062 }
3063
3064 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3065                               u32 value, u32 *boot_level)
3066 {
3067         u32 i;
3068         int ret = -EINVAL;
3069
3070         for(i = 0; i < table->count; i++) {
3071                 if (value == table->dpm_levels[i].value) {
3072                         *boot_level = i;
3073                         ret = 0;
3074                 }
3075         }
3076
3077         return ret;
3078 }
3079
3080 static int ci_init_smc_table(struct radeon_device *rdev)
3081 {
3082         struct ci_power_info *pi = ci_get_pi(rdev);
3083         struct ci_ulv_parm *ulv = &pi->ulv;
3084         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3085         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3086         int ret;
3087
3088         ret = ci_setup_default_dpm_tables(rdev);
3089         if (ret)
3090                 return ret;
3091
3092         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3093                 ci_populate_smc_voltage_tables(rdev, table);
3094
3095         ci_init_fps_limits(rdev);
3096
3097         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3098                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3099
3100         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3101                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3102
3103         if (pi->mem_gddr5)
3104                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3105
3106         if (ulv->supported) {
3107                 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3108                 if (ret)
3109                         return ret;
3110                 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3111         }
3112
3113         ret = ci_populate_all_graphic_levels(rdev);
3114         if (ret)
3115                 return ret;
3116
3117         ret = ci_populate_all_memory_levels(rdev);
3118         if (ret)
3119                 return ret;
3120
3121         ci_populate_smc_link_level(rdev, table);
3122
3123         ret = ci_populate_smc_acpi_level(rdev, table);
3124         if (ret)
3125                 return ret;
3126
3127         ret = ci_populate_smc_vce_level(rdev, table);
3128         if (ret)
3129                 return ret;
3130
3131         ret = ci_populate_smc_acp_level(rdev, table);
3132         if (ret)
3133                 return ret;
3134
3135         ret = ci_populate_smc_samu_level(rdev, table);
3136         if (ret)
3137                 return ret;
3138
3139         ret = ci_do_program_memory_timing_parameters(rdev);
3140         if (ret)
3141                 return ret;
3142
3143         ret = ci_populate_smc_uvd_level(rdev, table);
3144         if (ret)
3145                 return ret;
3146
3147         table->UvdBootLevel  = 0;
3148         table->VceBootLevel  = 0;
3149         table->AcpBootLevel  = 0;
3150         table->SamuBootLevel  = 0;
3151         table->GraphicsBootLevel  = 0;
3152         table->MemoryBootLevel  = 0;
3153
3154         ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3155                                  pi->vbios_boot_state.sclk_bootup_value,
3156                                  (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3157
3158         ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3159                                  pi->vbios_boot_state.mclk_bootup_value,
3160                                  (u32 *)&pi->smc_state_table.MemoryBootLevel);
3161
3162         table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3163         table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3164         table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3165
3166         ci_populate_smc_initial_state(rdev, radeon_boot_state);
3167
3168         ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3169         if (ret)
3170                 return ret;
3171
3172         table->UVDInterval = 1;
3173         table->VCEInterval = 1;
3174         table->ACPInterval = 1;
3175         table->SAMUInterval = 1;
3176         table->GraphicsVoltageChangeEnable = 1;
3177         table->GraphicsThermThrottleEnable = 1;
3178         table->GraphicsInterval = 1;
3179         table->VoltageInterval = 1;
3180         table->ThermalInterval = 1;
3181         table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3182                                              CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3183         table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3184                                             CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3185         table->MemoryVoltageChangeEnable = 1;
3186         table->MemoryInterval = 1;
3187         table->VoltageResponseTime = 0;
3188         table->VddcVddciDelta = 4000;
3189         table->PhaseResponseTime = 0;
3190         table->MemoryThermThrottleEnable = 1;
3191         table->PCIeBootLinkLevel = 0;
3192         table->PCIeGenInterval = 1;
3193         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3194                 table->SVI2Enable  = 1;
3195         else
3196                 table->SVI2Enable  = 0;
3197
3198         table->ThermGpio = 17;
3199         table->SclkStepSize = 0x4000;
3200
3201         table->SystemFlags = cpu_to_be32(table->SystemFlags);
3202         table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3203         table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3204         table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3205         table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3206         table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3207         table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3208         table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3209         table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3210         table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3211         table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3212         table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3213         table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3214         table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3215
3216         ret = ci_copy_bytes_to_smc(rdev,
3217                                    pi->dpm_table_start +
3218                                    offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3219                                    (u8 *)&table->SystemFlags,
3220                                    sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3221                                    pi->sram_end);
3222         if (ret)
3223                 return ret;
3224
3225         return 0;
3226 }
3227
3228 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3229                                       struct ci_single_dpm_table *dpm_table,
3230                                       u32 low_limit, u32 high_limit)
3231 {
3232         u32 i;
3233
3234         for (i = 0; i < dpm_table->count; i++) {
3235                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3236                     (dpm_table->dpm_levels[i].value > high_limit))
3237                         dpm_table->dpm_levels[i].enabled = false;
3238                 else
3239                         dpm_table->dpm_levels[i].enabled = true;
3240         }
3241 }
3242
3243 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3244                                     u32 speed_low, u32 lanes_low,
3245                                     u32 speed_high, u32 lanes_high)
3246 {
3247         struct ci_power_info *pi = ci_get_pi(rdev);
3248         struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3249         u32 i, j;
3250
3251         for (i = 0; i < pcie_table->count; i++) {
3252                 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3253                     (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3254                     (pcie_table->dpm_levels[i].value > speed_high) ||
3255                     (pcie_table->dpm_levels[i].param1 > lanes_high))
3256                         pcie_table->dpm_levels[i].enabled = false;
3257                 else
3258                         pcie_table->dpm_levels[i].enabled = true;
3259         }
3260
3261         for (i = 0; i < pcie_table->count; i++) {
3262                 if (pcie_table->dpm_levels[i].enabled) {
3263                         for (j = i + 1; j < pcie_table->count; j++) {
3264                                 if (pcie_table->dpm_levels[j].enabled) {
3265                                         if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3266                                             (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3267                                                 pcie_table->dpm_levels[j].enabled = false;
3268                                 }
3269                         }
3270                 }
3271         }
3272 }
3273
3274 static int ci_trim_dpm_states(struct radeon_device *rdev,
3275                               struct radeon_ps *radeon_state)
3276 {
3277         struct ci_ps *state = ci_get_ps(radeon_state);
3278         struct ci_power_info *pi = ci_get_pi(rdev);
3279         u32 high_limit_count;
3280
3281         if (state->performance_level_count < 1)
3282                 return -EINVAL;
3283
3284         if (state->performance_level_count == 1)
3285                 high_limit_count = 0;
3286         else
3287                 high_limit_count = 1;
3288
3289         ci_trim_single_dpm_states(rdev,
3290                                   &pi->dpm_table.sclk_table,
3291                                   state->performance_levels[0].sclk,
3292                                   state->performance_levels[high_limit_count].sclk);
3293
3294         ci_trim_single_dpm_states(rdev,
3295                                   &pi->dpm_table.mclk_table,
3296                                   state->performance_levels[0].mclk,
3297                                   state->performance_levels[high_limit_count].mclk);
3298
3299         ci_trim_pcie_dpm_states(rdev,
3300                                 state->performance_levels[0].pcie_gen,
3301                                 state->performance_levels[0].pcie_lane,
3302                                 state->performance_levels[high_limit_count].pcie_gen,
3303                                 state->performance_levels[high_limit_count].pcie_lane);
3304
3305         return 0;
3306 }
3307
3308 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3309 {
3310         struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3311                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3312         struct radeon_clock_voltage_dependency_table *vddc_table =
3313                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3314         u32 requested_voltage = 0;
3315         u32 i;
3316
3317         if (disp_voltage_table == NULL)
3318                 return -EINVAL;
3319         if (!disp_voltage_table->count)
3320                 return -EINVAL;
3321
3322         for (i = 0; i < disp_voltage_table->count; i++) {
3323                 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3324                         requested_voltage = disp_voltage_table->entries[i].v;
3325         }
3326
3327         for (i = 0; i < vddc_table->count; i++) {
3328                 if (requested_voltage <= vddc_table->entries[i].v) {
3329                         requested_voltage = vddc_table->entries[i].v;
3330                         return (ci_send_msg_to_smc_with_parameter(rdev,
3331                                                                   PPSMC_MSG_VddC_Request,
3332                                                                   requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3333                                 0 : -EINVAL;
3334                 }
3335         }
3336
3337         return -EINVAL;
3338 }
3339
3340 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3341 {
3342         struct ci_power_info *pi = ci_get_pi(rdev);
3343         PPSMC_Result result;
3344
3345         if (!pi->sclk_dpm_key_disabled) {
3346                 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3347                         result = ci_send_msg_to_smc_with_parameter(rdev,
3348                                                                    PPSMC_MSG_SCLKDPM_SetEnabledMask,
3349                                                                    pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3350                         if (result != PPSMC_Result_OK)
3351                                 return -EINVAL;
3352                 }
3353         }
3354
3355         if (!pi->mclk_dpm_key_disabled) {
3356                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3357                         result = ci_send_msg_to_smc_with_parameter(rdev,
3358                                                                    PPSMC_MSG_MCLKDPM_SetEnabledMask,
3359                                                                    pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3360                         if (result != PPSMC_Result_OK)
3361                                 return -EINVAL;
3362                 }
3363         }
3364
3365         if (!pi->pcie_dpm_key_disabled) {
3366                 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3367                         result = ci_send_msg_to_smc_with_parameter(rdev,
3368                                                                    PPSMC_MSG_PCIeDPM_SetEnabledMask,
3369                                                                    pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3370                         if (result != PPSMC_Result_OK)
3371                                 return -EINVAL;
3372                 }
3373         }
3374
3375         ci_apply_disp_minimum_voltage_request(rdev);
3376
3377         return 0;
3378 }
3379
3380 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3381                                                    struct radeon_ps *radeon_state)
3382 {
3383         struct ci_power_info *pi = ci_get_pi(rdev);
3384         struct ci_ps *state = ci_get_ps(radeon_state);
3385         struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3386         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3387         struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3388         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3389         u32 i;
3390
3391         pi->need_update_smu7_dpm_table = 0;
3392
3393         for (i = 0; i < sclk_table->count; i++) {
3394                 if (sclk == sclk_table->dpm_levels[i].value)
3395                         break;
3396         }
3397
3398         if (i >= sclk_table->count) {
3399                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3400         } else {
3401                 /* XXX check display min clock requirements */
3402                 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK)
3403                         pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3404         }
3405
3406         for (i = 0; i < mclk_table->count; i++) {
3407                 if (mclk == mclk_table->dpm_levels[i].value)
3408                         break;
3409         }
3410
3411         if (i >= mclk_table->count)
3412                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3413
3414         if (rdev->pm.dpm.current_active_crtc_count !=
3415             rdev->pm.dpm.new_active_crtc_count)
3416                 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3417 }
3418
3419 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3420                                                        struct radeon_ps *radeon_state)
3421 {
3422         struct ci_power_info *pi = ci_get_pi(rdev);
3423         struct ci_ps *state = ci_get_ps(radeon_state);
3424         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3425         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3426         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3427         int ret;
3428
3429         if (!pi->need_update_smu7_dpm_table)
3430                 return 0;
3431
3432         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3433                 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3434
3435         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3436                 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3437
3438         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3439                 ret = ci_populate_all_graphic_levels(rdev);
3440                 if (ret)
3441                         return ret;
3442         }
3443
3444         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3445                 ret = ci_populate_all_memory_levels(rdev);
3446                 if (ret)
3447                         return ret;
3448         }
3449
3450         return 0;
3451 }
3452
3453 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3454 {
3455         struct ci_power_info *pi = ci_get_pi(rdev);
3456         const struct radeon_clock_and_voltage_limits *max_limits;
3457         int i;
3458
3459         if (rdev->pm.dpm.ac_power)
3460                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3461         else
3462                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3463
3464         if (enable) {
3465                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3466
3467                 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3468                         if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3469                                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3470
3471                                 if (!pi->caps_uvd_dpm)
3472                                         break;
3473                         }
3474                 }
3475
3476                 ci_send_msg_to_smc_with_parameter(rdev,
3477                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
3478                                                   pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3479
3480                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3481                         pi->uvd_enabled = true;
3482                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3483                         ci_send_msg_to_smc_with_parameter(rdev,
3484                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3485                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3486                 }
3487         } else {
3488                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3489                         pi->uvd_enabled = false;
3490                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3491                         ci_send_msg_to_smc_with_parameter(rdev,
3492                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3493                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3494                 }
3495         }
3496
3497         return (ci_send_msg_to_smc(rdev, enable ?
3498                                    PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3499                 0 : -EINVAL;
3500 }
3501
3502 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3503 {
3504         struct ci_power_info *pi = ci_get_pi(rdev);
3505         const struct radeon_clock_and_voltage_limits *max_limits;
3506         int i;
3507
3508         if (rdev->pm.dpm.ac_power)
3509                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3510         else
3511                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3512
3513         if (enable) {
3514                 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3515                 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3516                         if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3517                                 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3518
3519                                 if (!pi->caps_vce_dpm)
3520                                         break;
3521                         }
3522                 }
3523
3524                 ci_send_msg_to_smc_with_parameter(rdev,
3525                                                   PPSMC_MSG_VCEDPM_SetEnabledMask,
3526                                                   pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3527         }
3528
3529         return (ci_send_msg_to_smc(rdev, enable ?
3530                                    PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3531                 0 : -EINVAL;
3532 }
3533
3534 #if 0
3535 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3536 {
3537         struct ci_power_info *pi = ci_get_pi(rdev);
3538         const struct radeon_clock_and_voltage_limits *max_limits;
3539         int i;
3540
3541         if (rdev->pm.dpm.ac_power)
3542                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3543         else
3544                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3545
3546         if (enable) {
3547                 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3548                 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3549                         if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3550                                 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3551
3552                                 if (!pi->caps_samu_dpm)
3553                                         break;
3554                         }
3555                 }
3556
3557                 ci_send_msg_to_smc_with_parameter(rdev,
3558                                                   PPSMC_MSG_SAMUDPM_SetEnabledMask,
3559                                                   pi->dpm_level_enable_mask.samu_dpm_enable_mask);
3560         }
3561         return (ci_send_msg_to_smc(rdev, enable ?
3562                                    PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
3563                 0 : -EINVAL;
3564 }
3565
3566 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
3567 {
3568         struct ci_power_info *pi = ci_get_pi(rdev);
3569         const struct radeon_clock_and_voltage_limits *max_limits;
3570         int i;
3571
3572         if (rdev->pm.dpm.ac_power)
3573                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3574         else
3575                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3576
3577         if (enable) {
3578                 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
3579                 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3580                         if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3581                                 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
3582
3583                                 if (!pi->caps_acp_dpm)
3584                                         break;
3585                         }
3586                 }
3587
3588                 ci_send_msg_to_smc_with_parameter(rdev,
3589                                                   PPSMC_MSG_ACPDPM_SetEnabledMask,
3590                                                   pi->dpm_level_enable_mask.acp_dpm_enable_mask);
3591         }
3592
3593         return (ci_send_msg_to_smc(rdev, enable ?
3594                                    PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
3595                 0 : -EINVAL;
3596 }
3597 #endif
3598
3599 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
3600 {
3601         struct ci_power_info *pi = ci_get_pi(rdev);
3602         u32 tmp;
3603
3604         if (!gate) {
3605                 if (pi->caps_uvd_dpm ||
3606                     (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
3607                         pi->smc_state_table.UvdBootLevel = 0;
3608                 else
3609                         pi->smc_state_table.UvdBootLevel =
3610                                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
3611
3612                 tmp = RREG32_SMC(DPM_TABLE_475);
3613                 tmp &= ~UvdBootLevel_MASK;
3614                 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
3615                 WREG32_SMC(DPM_TABLE_475, tmp);
3616         }
3617
3618         return ci_enable_uvd_dpm(rdev, !gate);
3619 }
3620
3621 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
3622 {
3623         u8 i;
3624         u32 min_evclk = 30000; /* ??? */
3625         struct radeon_vce_clock_voltage_dependency_table *table =
3626                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3627
3628         for (i = 0; i < table->count; i++) {
3629                 if (table->entries[i].evclk >= min_evclk)
3630                         return i;
3631         }
3632
3633         return table->count - 1;
3634 }
3635
3636 static int ci_update_vce_dpm(struct radeon_device *rdev,
3637                              struct radeon_ps *radeon_new_state,
3638                              struct radeon_ps *radeon_current_state)
3639 {
3640         struct ci_power_info *pi = ci_get_pi(rdev);
3641         int ret = 0;
3642         u32 tmp;
3643
3644         if (radeon_current_state->evclk != radeon_new_state->evclk) {
3645                 if (radeon_new_state->evclk) {
3646                         /* turn the clocks on when encoding */
3647                         cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
3648
3649                         pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
3650                         tmp = RREG32_SMC(DPM_TABLE_475);
3651                         tmp &= ~VceBootLevel_MASK;
3652                         tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
3653                         WREG32_SMC(DPM_TABLE_475, tmp);
3654
3655                         ret = ci_enable_vce_dpm(rdev, true);
3656                 } else {
3657                         /* turn the clocks off when not encoding */
3658                         cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
3659
3660                         ret = ci_enable_vce_dpm(rdev, false);
3661                 }
3662         }
3663         return ret;
3664 }
3665
3666 #if 0
3667 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
3668 {
3669         return ci_enable_samu_dpm(rdev, gate);
3670 }
3671
3672 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
3673 {
3674         struct ci_power_info *pi = ci_get_pi(rdev);
3675         u32 tmp;
3676
3677         if (!gate) {
3678                 pi->smc_state_table.AcpBootLevel = 0;
3679
3680                 tmp = RREG32_SMC(DPM_TABLE_475);
3681                 tmp &= ~AcpBootLevel_MASK;
3682                 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
3683                 WREG32_SMC(DPM_TABLE_475, tmp);
3684         }
3685
3686         return ci_enable_acp_dpm(rdev, !gate);
3687 }
3688 #endif
3689
3690 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
3691                                              struct radeon_ps *radeon_state)
3692 {
3693         struct ci_power_info *pi = ci_get_pi(rdev);
3694         int ret;
3695
3696         ret = ci_trim_dpm_states(rdev, radeon_state);
3697         if (ret)
3698                 return ret;
3699
3700         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3701                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
3702         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3703                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
3704         pi->last_mclk_dpm_enable_mask =
3705                 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3706         if (pi->uvd_enabled) {
3707                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
3708                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3709         }
3710         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
3711                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
3712
3713         return 0;
3714 }
3715
3716 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
3717                                        u32 level_mask)
3718 {
3719         u32 level = 0;
3720
3721         while ((level_mask & (1 << level)) == 0)
3722                 level++;
3723
3724         return level;
3725 }
3726
3727
3728 int ci_dpm_force_performance_level(struct radeon_device *rdev,
3729                                    enum radeon_dpm_forced_level level)
3730 {
3731         struct ci_power_info *pi = ci_get_pi(rdev);
3732         PPSMC_Result smc_result;
3733         u32 tmp, levels, i;
3734         int ret;
3735
3736         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3737                 if ((!pi->sclk_dpm_key_disabled) &&
3738                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3739                         levels = 0;
3740                         tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
3741                         while (tmp >>= 1)
3742                                 levels++;
3743                         if (levels) {
3744                                 ret = ci_dpm_force_state_sclk(rdev, levels);
3745                                 if (ret)
3746                                         return ret;
3747                                 for (i = 0; i < rdev->usec_timeout; i++) {
3748                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3749                                                CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3750                                         if (tmp == levels)
3751                                                 break;
3752                                         udelay(1);
3753                                 }
3754                         }
3755                 }
3756                 if ((!pi->mclk_dpm_key_disabled) &&
3757                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3758                         levels = 0;
3759                         tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3760                         while (tmp >>= 1)
3761                                 levels++;
3762                         if (levels) {
3763                                 ret = ci_dpm_force_state_mclk(rdev, levels);
3764                                 if (ret)
3765                                         return ret;
3766                                 for (i = 0; i < rdev->usec_timeout; i++) {
3767                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3768                                                CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3769                                         if (tmp == levels)
3770                                                 break;
3771                                         udelay(1);
3772                                 }
3773                         }
3774                 }
3775                 if ((!pi->pcie_dpm_key_disabled) &&
3776                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3777                         levels = 0;
3778                         tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
3779                         while (tmp >>= 1)
3780                                 levels++;
3781                         if (levels) {
3782                                 ret = ci_dpm_force_state_pcie(rdev, level);
3783                                 if (ret)
3784                                         return ret;
3785                                 for (i = 0; i < rdev->usec_timeout; i++) {
3786                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3787                                                CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3788                                         if (tmp == levels)
3789                                                 break;
3790                                         udelay(1);
3791                                 }
3792                         }
3793                 }
3794         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3795                 if ((!pi->sclk_dpm_key_disabled) &&
3796                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3797                         levels = ci_get_lowest_enabled_level(rdev,
3798                                                              pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3799                         ret = ci_dpm_force_state_sclk(rdev, levels);
3800                         if (ret)
3801                                 return ret;
3802                         for (i = 0; i < rdev->usec_timeout; i++) {
3803                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3804                                        CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3805                                 if (tmp == levels)
3806                                         break;
3807                                 udelay(1);
3808                         }
3809                 }
3810                 if ((!pi->mclk_dpm_key_disabled) &&
3811                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3812                         levels = ci_get_lowest_enabled_level(rdev,
3813                                                              pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3814                         ret = ci_dpm_force_state_mclk(rdev, levels);
3815                         if (ret)
3816                                 return ret;
3817                         for (i = 0; i < rdev->usec_timeout; i++) {
3818                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3819                                        CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3820                                 if (tmp == levels)
3821                                         break;
3822                                 udelay(1);
3823                         }
3824                 }
3825                 if ((!pi->pcie_dpm_key_disabled) &&
3826                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3827                         levels = ci_get_lowest_enabled_level(rdev,
3828                                                              pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3829                         ret = ci_dpm_force_state_pcie(rdev, levels);
3830                         if (ret)
3831                                 return ret;
3832                         for (i = 0; i < rdev->usec_timeout; i++) {
3833                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3834                                        CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3835                                 if (tmp == levels)
3836                                         break;
3837                                 udelay(1);
3838                         }
3839                 }
3840         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3841                 if (!pi->sclk_dpm_key_disabled) {
3842                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel);
3843                         if (smc_result != PPSMC_Result_OK)
3844                                 return -EINVAL;
3845                 }
3846                 if (!pi->mclk_dpm_key_disabled) {
3847                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_NoForcedLevel);
3848                         if (smc_result != PPSMC_Result_OK)
3849                                 return -EINVAL;
3850                 }
3851                 if (!pi->pcie_dpm_key_disabled) {
3852                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_UnForceLevel);
3853                         if (smc_result != PPSMC_Result_OK)
3854                                 return -EINVAL;
3855                 }
3856         }
3857
3858         rdev->pm.dpm.forced_level = level;
3859
3860         return 0;
3861 }
3862
3863 static int ci_set_mc_special_registers(struct radeon_device *rdev,
3864                                        struct ci_mc_reg_table *table)
3865 {
3866         struct ci_power_info *pi = ci_get_pi(rdev);
3867         u8 i, j, k;
3868         u32 temp_reg;
3869
3870         for (i = 0, j = table->last; i < table->last; i++) {
3871                 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3872                         return -EINVAL;
3873                 switch(table->mc_reg_address[i].s1 << 2) {
3874                 case MC_SEQ_MISC1:
3875                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
3876                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
3877                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3878                         for (k = 0; k < table->num_entries; k++) {
3879                                 table->mc_reg_table_entry[k].mc_data[j] =
3880                                         ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3881                         }
3882                         j++;
3883                         if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3884                                 return -EINVAL;
3885
3886                         temp_reg = RREG32(MC_PMG_CMD_MRS);
3887                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
3888                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3889                         for (k = 0; k < table->num_entries; k++) {
3890                                 table->mc_reg_table_entry[k].mc_data[j] =
3891                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3892                                 if (!pi->mem_gddr5)
3893                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3894                         }
3895                         j++;
3896                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3897                                 return -EINVAL;
3898
3899                         if (!pi->mem_gddr5) {
3900                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
3901                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
3902                                 for (k = 0; k < table->num_entries; k++) {
3903                                         table->mc_reg_table_entry[k].mc_data[j] =
3904                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3905                                 }
3906                                 j++;
3907                                 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3908                                         return -EINVAL;
3909                         }
3910                         break;
3911                 case MC_SEQ_RESERVE_M:
3912                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
3913                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
3914                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3915                         for (k = 0; k < table->num_entries; k++) {
3916                                 table->mc_reg_table_entry[k].mc_data[j] =
3917                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3918                         }
3919                         j++;
3920                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3921                                 return -EINVAL;
3922                         break;
3923                 default:
3924                         break;
3925                 }
3926
3927         }
3928
3929         table->last = j;
3930
3931         return 0;
3932 }
3933
3934 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
3935 {
3936         bool result = true;
3937
3938         switch(in_reg) {
3939         case MC_SEQ_RAS_TIMING >> 2:
3940                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
3941                 break;
3942         case MC_SEQ_DLL_STBY >> 2:
3943                 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
3944                 break;
3945         case MC_SEQ_G5PDX_CMD0 >> 2:
3946                 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
3947                 break;
3948         case MC_SEQ_G5PDX_CMD1 >> 2:
3949                 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
3950                 break;
3951         case MC_SEQ_G5PDX_CTRL >> 2:
3952                 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
3953                 break;
3954         case MC_SEQ_CAS_TIMING >> 2:
3955                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
3956             break;
3957         case MC_SEQ_MISC_TIMING >> 2:
3958                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
3959                 break;
3960         case MC_SEQ_MISC_TIMING2 >> 2:
3961                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
3962                 break;
3963         case MC_SEQ_PMG_DVS_CMD >> 2:
3964                 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
3965                 break;
3966         case MC_SEQ_PMG_DVS_CTL >> 2:
3967                 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
3968                 break;
3969         case MC_SEQ_RD_CTL_D0 >> 2:
3970                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
3971                 break;
3972         case MC_SEQ_RD_CTL_D1 >> 2:
3973                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
3974                 break;
3975         case MC_SEQ_WR_CTL_D0 >> 2:
3976                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
3977                 break;
3978         case MC_SEQ_WR_CTL_D1 >> 2:
3979                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
3980                 break;
3981         case MC_PMG_CMD_EMRS >> 2:
3982                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3983                 break;
3984         case MC_PMG_CMD_MRS >> 2:
3985                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3986                 break;
3987         case MC_PMG_CMD_MRS1 >> 2:
3988                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3989                 break;
3990         case MC_SEQ_PMG_TIMING >> 2:
3991                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
3992                 break;
3993         case MC_PMG_CMD_MRS2 >> 2:
3994                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
3995                 break;
3996         case MC_SEQ_WR_CTL_2 >> 2:
3997                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
3998                 break;
3999         default:
4000                 result = false;
4001                 break;
4002         }
4003
4004         return result;
4005 }
4006
4007 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4008 {
4009         u8 i, j;
4010
4011         for (i = 0; i < table->last; i++) {
4012                 for (j = 1; j < table->num_entries; j++) {
4013                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4014                             table->mc_reg_table_entry[j].mc_data[i]) {
4015                                 table->valid_flag |= 1 << i;
4016                                 break;
4017                         }
4018                 }
4019         }
4020 }
4021
4022 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4023 {
4024         u32 i;
4025         u16 address;
4026
4027         for (i = 0; i < table->last; i++) {
4028                 table->mc_reg_address[i].s0 =
4029                         ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4030                         address : table->mc_reg_address[i].s1;
4031         }
4032 }
4033
4034 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4035                                       struct ci_mc_reg_table *ci_table)
4036 {
4037         u8 i, j;
4038
4039         if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4040                 return -EINVAL;
4041         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4042                 return -EINVAL;
4043
4044         for (i = 0; i < table->last; i++)
4045                 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4046
4047         ci_table->last = table->last;
4048
4049         for (i = 0; i < table->num_entries; i++) {
4050                 ci_table->mc_reg_table_entry[i].mclk_max =
4051                         table->mc_reg_table_entry[i].mclk_max;
4052                 for (j = 0; j < table->last; j++)
4053                         ci_table->mc_reg_table_entry[i].mc_data[j] =
4054                                 table->mc_reg_table_entry[i].mc_data[j];
4055         }
4056         ci_table->num_entries = table->num_entries;
4057
4058         return 0;
4059 }
4060
4061 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4062 {
4063         struct ci_power_info *pi = ci_get_pi(rdev);
4064         struct atom_mc_reg_table *table;
4065         struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4066         u8 module_index = rv770_get_memory_module_index(rdev);
4067         int ret;
4068
4069         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4070         if (!table)
4071                 return -ENOMEM;
4072
4073         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4074         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4075         WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4076         WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4077         WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4078         WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4079         WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4080         WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4081         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4082         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4083         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4084         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4085         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4086         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4087         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4088         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4089         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4090         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4091         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4092         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4093
4094         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4095         if (ret)
4096                 goto init_mc_done;
4097
4098         ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4099         if (ret)
4100                 goto init_mc_done;
4101
4102         ci_set_s0_mc_reg_index(ci_table);
4103
4104         ret = ci_set_mc_special_registers(rdev, ci_table);
4105         if (ret)
4106                 goto init_mc_done;
4107
4108         ci_set_valid_flag(ci_table);
4109
4110 init_mc_done:
4111         kfree(table);
4112
4113         return ret;
4114 }
4115
4116 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4117                                         SMU7_Discrete_MCRegisters *mc_reg_table)
4118 {
4119         struct ci_power_info *pi = ci_get_pi(rdev);
4120         u32 i, j;
4121
4122         for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4123                 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4124                         if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4125                                 return -EINVAL;
4126                         mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4127                         mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4128                         i++;
4129                 }
4130         }
4131
4132         mc_reg_table->last = (u8)i;
4133
4134         return 0;
4135 }
4136
4137 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4138                                     SMU7_Discrete_MCRegisterSet *data,
4139                                     u32 num_entries, u32 valid_flag)
4140 {
4141         u32 i, j;
4142
4143         for (i = 0, j = 0; j < num_entries; j++) {
4144                 if (valid_flag & (1 << j)) {
4145                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
4146                         i++;
4147                 }
4148         }
4149 }
4150
4151 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4152                                                  const u32 memory_clock,
4153                                                  SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4154 {
4155         struct ci_power_info *pi = ci_get_pi(rdev);
4156         u32 i = 0;
4157
4158         for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4159                 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4160                         break;
4161         }
4162
4163         if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4164                 --i;
4165
4166         ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4167                                 mc_reg_table_data, pi->mc_reg_table.last,
4168                                 pi->mc_reg_table.valid_flag);
4169 }
4170
4171 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4172                                            SMU7_Discrete_MCRegisters *mc_reg_table)
4173 {
4174         struct ci_power_info *pi = ci_get_pi(rdev);
4175         u32 i;
4176
4177         for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4178                 ci_convert_mc_reg_table_entry_to_smc(rdev,
4179                                                      pi->dpm_table.mclk_table.dpm_levels[i].value,
4180                                                      &mc_reg_table->data[i]);
4181 }
4182
4183 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4184 {
4185         struct ci_power_info *pi = ci_get_pi(rdev);
4186         int ret;
4187
4188         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4189
4190         ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4191         if (ret)
4192                 return ret;
4193         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4194
4195         return ci_copy_bytes_to_smc(rdev,
4196                                     pi->mc_reg_table_start,
4197                                     (u8 *)&pi->smc_mc_reg_table,
4198                                     sizeof(SMU7_Discrete_MCRegisters),
4199                                     pi->sram_end);
4200 }
4201
4202 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4203 {
4204         struct ci_power_info *pi = ci_get_pi(rdev);
4205
4206         if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4207                 return 0;
4208
4209         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4210
4211         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4212
4213         return ci_copy_bytes_to_smc(rdev,
4214                                     pi->mc_reg_table_start +
4215                                     offsetof(SMU7_Discrete_MCRegisters, data[0]),
4216                                     (u8 *)&pi->smc_mc_reg_table.data[0],
4217                                     sizeof(SMU7_Discrete_MCRegisterSet) *
4218                                     pi->dpm_table.mclk_table.count,
4219                                     pi->sram_end);
4220 }
4221
4222 static void ci_enable_voltage_control(struct radeon_device *rdev)
4223 {
4224         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4225
4226         tmp |= VOLT_PWRMGT_EN;
4227         WREG32_SMC(GENERAL_PWRMGT, tmp);
4228 }
4229
4230 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4231                                                       struct radeon_ps *radeon_state)
4232 {
4233         struct ci_ps *state = ci_get_ps(radeon_state);
4234         int i;
4235         u16 pcie_speed, max_speed = 0;
4236
4237         for (i = 0; i < state->performance_level_count; i++) {
4238                 pcie_speed = state->performance_levels[i].pcie_gen;
4239                 if (max_speed < pcie_speed)
4240                         max_speed = pcie_speed;
4241         }
4242
4243         return max_speed;
4244 }
4245
4246 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4247 {
4248         u32 speed_cntl = 0;
4249
4250         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4251         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4252
4253         return (u16)speed_cntl;
4254 }
4255
4256 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4257 {
4258         u32 link_width = 0;
4259
4260         link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4261         link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4262
4263         switch (link_width) {
4264         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4265                 return 1;
4266         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4267                 return 2;
4268         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4269                 return 4;
4270         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4271                 return 8;
4272         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4273                 /* not actually supported */
4274                 return 12;
4275         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4276         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4277         default:
4278                 return 16;
4279         }
4280 }
4281
4282 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4283                                                              struct radeon_ps *radeon_new_state,
4284                                                              struct radeon_ps *radeon_current_state)
4285 {
4286         struct ci_power_info *pi = ci_get_pi(rdev);
4287         enum radeon_pcie_gen target_link_speed =
4288                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4289         enum radeon_pcie_gen current_link_speed;
4290
4291         if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4292                 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4293         else
4294                 current_link_speed = pi->force_pcie_gen;
4295
4296         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4297         pi->pspp_notify_required = false;
4298         if (target_link_speed > current_link_speed) {
4299                 switch (target_link_speed) {
4300 #ifdef CONFIG_ACPI
4301                 case RADEON_PCIE_GEN3:
4302                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4303                                 break;
4304                         pi->force_pcie_gen = RADEON_PCIE_GEN2;
4305                         if (current_link_speed == RADEON_PCIE_GEN2)
4306                                 break;
4307                 case RADEON_PCIE_GEN2:
4308                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4309                                 break;
4310 #endif
4311                 default:
4312                         pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4313                         break;
4314                 }
4315         } else {
4316                 if (target_link_speed < current_link_speed)
4317                         pi->pspp_notify_required = true;
4318         }
4319 }
4320
4321 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4322                                                            struct radeon_ps *radeon_new_state,
4323                                                            struct radeon_ps *radeon_current_state)
4324 {
4325         struct ci_power_info *pi = ci_get_pi(rdev);
4326         enum radeon_pcie_gen target_link_speed =
4327                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4328         u8 request;
4329
4330         if (pi->pspp_notify_required) {
4331                 if (target_link_speed == RADEON_PCIE_GEN3)
4332                         request = PCIE_PERF_REQ_PECI_GEN3;
4333                 else if (target_link_speed == RADEON_PCIE_GEN2)
4334                         request = PCIE_PERF_REQ_PECI_GEN2;
4335                 else
4336                         request = PCIE_PERF_REQ_PECI_GEN1;
4337
4338                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4339                     (ci_get_current_pcie_speed(rdev) > 0))
4340                         return;
4341
4342 #ifdef CONFIG_ACPI
4343                 radeon_acpi_pcie_performance_request(rdev, request, false);
4344 #endif
4345         }
4346 }
4347
4348 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4349 {
4350         struct ci_power_info *pi = ci_get_pi(rdev);
4351         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4352                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4353         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4354                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4355         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4356                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4357
4358         if (allowed_sclk_vddc_table == NULL)
4359                 return -EINVAL;
4360         if (allowed_sclk_vddc_table->count < 1)
4361                 return -EINVAL;
4362         if (allowed_mclk_vddc_table == NULL)
4363                 return -EINVAL;
4364         if (allowed_mclk_vddc_table->count < 1)
4365                 return -EINVAL;
4366         if (allowed_mclk_vddci_table == NULL)
4367                 return -EINVAL;
4368         if (allowed_mclk_vddci_table->count < 1)
4369                 return -EINVAL;
4370
4371         pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4372         pi->max_vddc_in_pp_table =
4373                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4374
4375         pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4376         pi->max_vddci_in_pp_table =
4377                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4378
4379         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4380                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4381         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4382                 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4383         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4384                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4385         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4386                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4387
4388         return 0;
4389 }
4390
4391 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4392 {
4393         struct ci_power_info *pi = ci_get_pi(rdev);
4394         struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4395         u32 leakage_index;
4396
4397         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4398                 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4399                         *vddc = leakage_table->actual_voltage[leakage_index];
4400                         break;
4401                 }
4402         }
4403 }
4404
4405 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4406 {
4407         struct ci_power_info *pi = ci_get_pi(rdev);
4408         struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4409         u32 leakage_index;
4410
4411         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4412                 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4413                         *vddci = leakage_table->actual_voltage[leakage_index];
4414                         break;
4415                 }
4416         }
4417 }
4418
4419 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4420                                                                       struct radeon_clock_voltage_dependency_table *table)
4421 {
4422         u32 i;
4423
4424         if (table) {
4425                 for (i = 0; i < table->count; i++)
4426                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4427         }
4428 }
4429
4430 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4431                                                                        struct radeon_clock_voltage_dependency_table *table)
4432 {
4433         u32 i;
4434
4435         if (table) {
4436                 for (i = 0; i < table->count; i++)
4437                         ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4438         }
4439 }
4440
4441 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4442                                                                           struct radeon_vce_clock_voltage_dependency_table *table)
4443 {
4444         u32 i;
4445
4446         if (table) {
4447                 for (i = 0; i < table->count; i++)
4448                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4449         }
4450 }
4451
4452 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4453                                                                           struct radeon_uvd_clock_voltage_dependency_table *table)
4454 {
4455         u32 i;
4456
4457         if (table) {
4458                 for (i = 0; i < table->count; i++)
4459                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4460         }
4461 }
4462
4463 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
4464                                                                    struct radeon_phase_shedding_limits_table *table)
4465 {
4466         u32 i;
4467
4468         if (table) {
4469                 for (i = 0; i < table->count; i++)
4470                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
4471         }
4472 }
4473
4474 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
4475                                                             struct radeon_clock_and_voltage_limits *table)
4476 {
4477         if (table) {
4478                 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
4479                 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
4480         }
4481 }
4482
4483 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
4484                                                          struct radeon_cac_leakage_table *table)
4485 {
4486         u32 i;
4487
4488         if (table) {
4489                 for (i = 0; i < table->count; i++)
4490                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
4491         }
4492 }
4493
4494 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
4495 {
4496
4497         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4498                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
4499         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4500                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
4501         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4502                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
4503         ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
4504                                                                    &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
4505         ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4506                                                                       &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
4507         ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4508                                                                       &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
4509         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4510                                                                   &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
4511         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4512                                                                   &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
4513         ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
4514                                                                &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
4515         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4516                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
4517         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4518                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
4519         ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
4520                                                      &rdev->pm.dpm.dyn_state.cac_leakage_table);
4521
4522 }
4523
4524 static void ci_get_memory_type(struct radeon_device *rdev)
4525 {
4526         struct ci_power_info *pi = ci_get_pi(rdev);
4527         u32 tmp;
4528
4529         tmp = RREG32(MC_SEQ_MISC0);
4530
4531         if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
4532             MC_SEQ_MISC0_GDDR5_VALUE)
4533                 pi->mem_gddr5 = true;
4534         else
4535                 pi->mem_gddr5 = false;
4536
4537 }
4538
4539 static void ci_update_current_ps(struct radeon_device *rdev,
4540                                  struct radeon_ps *rps)
4541 {
4542         struct ci_ps *new_ps = ci_get_ps(rps);
4543         struct ci_power_info *pi = ci_get_pi(rdev);
4544
4545         pi->current_rps = *rps;
4546         pi->current_ps = *new_ps;
4547         pi->current_rps.ps_priv = &pi->current_ps;
4548 }
4549
4550 static void ci_update_requested_ps(struct radeon_device *rdev,
4551                                    struct radeon_ps *rps)
4552 {
4553         struct ci_ps *new_ps = ci_get_ps(rps);
4554         struct ci_power_info *pi = ci_get_pi(rdev);
4555
4556         pi->requested_rps = *rps;
4557         pi->requested_ps = *new_ps;
4558         pi->requested_rps.ps_priv = &pi->requested_ps;
4559 }
4560
4561 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
4562 {
4563         struct ci_power_info *pi = ci_get_pi(rdev);
4564         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
4565         struct radeon_ps *new_ps = &requested_ps;
4566
4567         ci_update_requested_ps(rdev, new_ps);
4568
4569         ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
4570
4571         return 0;
4572 }
4573
4574 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
4575 {
4576         struct ci_power_info *pi = ci_get_pi(rdev);
4577         struct radeon_ps *new_ps = &pi->requested_rps;
4578
4579         ci_update_current_ps(rdev, new_ps);
4580 }
4581
4582
4583 void ci_dpm_setup_asic(struct radeon_device *rdev)
4584 {
4585         int r;
4586
4587         r = ci_mc_load_microcode(rdev);
4588         if (r)
4589                 DRM_ERROR("Failed to load MC firmware!\n");
4590         ci_read_clock_registers(rdev);
4591         ci_get_memory_type(rdev);
4592         ci_enable_acpi_power_management(rdev);
4593         ci_init_sclk_t(rdev);
4594 }
4595
4596 int ci_dpm_enable(struct radeon_device *rdev)
4597 {
4598         struct ci_power_info *pi = ci_get_pi(rdev);
4599         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4600         int ret;
4601
4602         if (ci_is_smc_running(rdev))
4603                 return -EINVAL;
4604         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
4605                 ci_enable_voltage_control(rdev);
4606                 ret = ci_construct_voltage_tables(rdev);
4607                 if (ret) {
4608                         DRM_ERROR("ci_construct_voltage_tables failed\n");
4609                         return ret;
4610                 }
4611         }
4612         if (pi->caps_dynamic_ac_timing) {
4613                 ret = ci_initialize_mc_reg_table(rdev);
4614                 if (ret)
4615                         pi->caps_dynamic_ac_timing = false;
4616         }
4617         if (pi->dynamic_ss)
4618                 ci_enable_spread_spectrum(rdev, true);
4619         if (pi->thermal_protection)
4620                 ci_enable_thermal_protection(rdev, true);
4621         ci_program_sstp(rdev);
4622         ci_enable_display_gap(rdev);
4623         ci_program_vc(rdev);
4624         ret = ci_upload_firmware(rdev);
4625         if (ret) {
4626                 DRM_ERROR("ci_upload_firmware failed\n");
4627                 return ret;
4628         }
4629         ret = ci_process_firmware_header(rdev);
4630         if (ret) {
4631                 DRM_ERROR("ci_process_firmware_header failed\n");
4632                 return ret;
4633         }
4634         ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
4635         if (ret) {
4636                 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
4637                 return ret;
4638         }
4639         ret = ci_init_smc_table(rdev);
4640         if (ret) {
4641                 DRM_ERROR("ci_init_smc_table failed\n");
4642                 return ret;
4643         }
4644         ret = ci_init_arb_table_index(rdev);
4645         if (ret) {
4646                 DRM_ERROR("ci_init_arb_table_index failed\n");
4647                 return ret;
4648         }
4649         if (pi->caps_dynamic_ac_timing) {
4650                 ret = ci_populate_initial_mc_reg_table(rdev);
4651                 if (ret) {
4652                         DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
4653                         return ret;
4654                 }
4655         }
4656         ret = ci_populate_pm_base(rdev);
4657         if (ret) {
4658                 DRM_ERROR("ci_populate_pm_base failed\n");
4659                 return ret;
4660         }
4661         ci_dpm_start_smc(rdev);
4662         ci_enable_vr_hot_gpio_interrupt(rdev);
4663         ret = ci_notify_smc_display_change(rdev, false);
4664         if (ret) {
4665                 DRM_ERROR("ci_notify_smc_display_change failed\n");
4666                 return ret;
4667         }
4668         ci_enable_sclk_control(rdev, true);
4669         ret = ci_enable_ulv(rdev, true);
4670         if (ret) {
4671                 DRM_ERROR("ci_enable_ulv failed\n");
4672                 return ret;
4673         }
4674         ret = ci_enable_ds_master_switch(rdev, true);
4675         if (ret) {
4676                 DRM_ERROR("ci_enable_ds_master_switch failed\n");
4677                 return ret;
4678         }
4679         ret = ci_start_dpm(rdev);
4680         if (ret) {
4681                 DRM_ERROR("ci_start_dpm failed\n");
4682                 return ret;
4683         }
4684         ret = ci_enable_didt(rdev, true);
4685         if (ret) {
4686                 DRM_ERROR("ci_enable_didt failed\n");
4687                 return ret;
4688         }
4689         ret = ci_enable_smc_cac(rdev, true);
4690         if (ret) {
4691                 DRM_ERROR("ci_enable_smc_cac failed\n");
4692                 return ret;
4693         }
4694         ret = ci_enable_power_containment(rdev, true);
4695         if (ret) {
4696                 DRM_ERROR("ci_enable_power_containment failed\n");
4697                 return ret;
4698         }
4699
4700         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
4701
4702         ci_update_current_ps(rdev, boot_ps);
4703
4704         return 0;
4705 }
4706
4707 int ci_dpm_late_enable(struct radeon_device *rdev)
4708 {
4709         int ret;
4710
4711         if (rdev->irq.installed &&
4712             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
4713 #if 0
4714                 PPSMC_Result result;
4715 #endif
4716                 ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
4717                 if (ret) {
4718                         DRM_ERROR("ci_set_thermal_temperature_range failed\n");
4719                         return ret;
4720                 }
4721                 rdev->irq.dpm_thermal = true;
4722                 radeon_irq_set(rdev);
4723 #if 0
4724                 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
4725
4726                 if (result != PPSMC_Result_OK)
4727                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
4728 #endif
4729         }
4730
4731         ci_dpm_powergate_uvd(rdev, true);
4732
4733         return 0;
4734 }
4735
4736 void ci_dpm_disable(struct radeon_device *rdev)
4737 {
4738         struct ci_power_info *pi = ci_get_pi(rdev);
4739         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4740
4741         ci_dpm_powergate_uvd(rdev, false);
4742
4743         if (!ci_is_smc_running(rdev))
4744                 return;
4745
4746         if (pi->thermal_protection)
4747                 ci_enable_thermal_protection(rdev, false);
4748         ci_enable_power_containment(rdev, false);
4749         ci_enable_smc_cac(rdev, false);
4750         ci_enable_didt(rdev, false);
4751         ci_enable_spread_spectrum(rdev, false);
4752         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
4753         ci_stop_dpm(rdev);
4754         ci_enable_ds_master_switch(rdev, true);
4755         ci_enable_ulv(rdev, false);
4756         ci_clear_vc(rdev);
4757         ci_reset_to_default(rdev);
4758         ci_dpm_stop_smc(rdev);
4759         ci_force_switch_to_arb_f0(rdev);
4760
4761         ci_update_current_ps(rdev, boot_ps);
4762 }
4763
4764 int ci_dpm_set_power_state(struct radeon_device *rdev)
4765 {
4766         struct ci_power_info *pi = ci_get_pi(rdev);
4767         struct radeon_ps *new_ps = &pi->requested_rps;
4768         struct radeon_ps *old_ps = &pi->current_rps;
4769         int ret;
4770
4771         ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
4772         if (pi->pcie_performance_request)
4773                 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
4774         ret = ci_freeze_sclk_mclk_dpm(rdev);
4775         if (ret) {
4776                 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
4777                 return ret;
4778         }
4779         ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
4780         if (ret) {
4781                 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
4782                 return ret;
4783         }
4784         ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
4785         if (ret) {
4786                 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
4787                 return ret;
4788         }
4789
4790         ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
4791         if (ret) {
4792                 DRM_ERROR("ci_update_vce_dpm failed\n");
4793                 return ret;
4794         }
4795
4796         ret = ci_update_sclk_t(rdev);
4797         if (ret) {
4798                 DRM_ERROR("ci_update_sclk_t failed\n");
4799                 return ret;
4800         }
4801         if (pi->caps_dynamic_ac_timing) {
4802                 ret = ci_update_and_upload_mc_reg_table(rdev);
4803                 if (ret) {
4804                         DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
4805                         return ret;
4806                 }
4807         }
4808         ret = ci_program_memory_timing_parameters(rdev);
4809         if (ret) {
4810                 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
4811                 return ret;
4812         }
4813         ret = ci_unfreeze_sclk_mclk_dpm(rdev);
4814         if (ret) {
4815                 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
4816                 return ret;
4817         }
4818         ret = ci_upload_dpm_level_enable_mask(rdev);
4819         if (ret) {
4820                 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
4821                 return ret;
4822         }
4823         if (pi->pcie_performance_request)
4824                 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
4825
4826         return 0;
4827 }
4828
4829 int ci_dpm_power_control_set_level(struct radeon_device *rdev)
4830 {
4831         return ci_power_control_set_level(rdev);
4832 }
4833
4834 void ci_dpm_reset_asic(struct radeon_device *rdev)
4835 {
4836         ci_set_boot_state(rdev);
4837 }
4838
4839 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
4840 {
4841         ci_program_display_gap(rdev);
4842 }
4843
4844 union power_info {
4845         struct _ATOM_POWERPLAY_INFO info;
4846         struct _ATOM_POWERPLAY_INFO_V2 info_2;
4847         struct _ATOM_POWERPLAY_INFO_V3 info_3;
4848         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
4849         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
4850         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
4851 };
4852
4853 union pplib_clock_info {
4854         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
4855         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
4856         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
4857         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
4858         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
4859         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
4860 };
4861
4862 union pplib_power_state {
4863         struct _ATOM_PPLIB_STATE v1;
4864         struct _ATOM_PPLIB_STATE_V2 v2;
4865 };
4866
4867 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
4868                                           struct radeon_ps *rps,
4869                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
4870                                           u8 table_rev)
4871 {
4872         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
4873         rps->class = le16_to_cpu(non_clock_info->usClassification);
4874         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
4875
4876         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
4877                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
4878                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
4879         } else {
4880                 rps->vclk = 0;
4881                 rps->dclk = 0;
4882         }
4883
4884         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
4885                 rdev->pm.dpm.boot_ps = rps;
4886         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
4887                 rdev->pm.dpm.uvd_ps = rps;
4888 }
4889
4890 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
4891                                       struct radeon_ps *rps, int index,
4892                                       union pplib_clock_info *clock_info)
4893 {
4894         struct ci_power_info *pi = ci_get_pi(rdev);
4895         struct ci_ps *ps = ci_get_ps(rps);
4896         struct ci_pl *pl = &ps->performance_levels[index];
4897
4898         ps->performance_level_count = index + 1;
4899
4900         pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
4901         pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
4902         pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
4903         pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
4904
4905         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
4906                                                  pi->sys_pcie_mask,
4907                                                  pi->vbios_boot_state.pcie_gen_bootup_value,
4908                                                  clock_info->ci.ucPCIEGen);
4909         pl->pcie_lane = r600_get_pcie_lane_support(rdev,
4910                                                    pi->vbios_boot_state.pcie_lane_bootup_value,
4911                                                    le16_to_cpu(clock_info->ci.usPCIELane));
4912
4913         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
4914                 pi->acpi_pcie_gen = pl->pcie_gen;
4915         }
4916
4917         if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
4918                 pi->ulv.supported = true;
4919                 pi->ulv.pl = *pl;
4920                 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
4921         }
4922
4923         /* patch up boot state */
4924         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
4925                 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
4926                 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
4927                 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
4928                 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
4929         }
4930
4931         switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
4932         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
4933                 pi->use_pcie_powersaving_levels = true;
4934                 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
4935                         pi->pcie_gen_powersaving.max = pl->pcie_gen;
4936                 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
4937                         pi->pcie_gen_powersaving.min = pl->pcie_gen;
4938                 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
4939                         pi->pcie_lane_powersaving.max = pl->pcie_lane;
4940                 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
4941                         pi->pcie_lane_powersaving.min = pl->pcie_lane;
4942                 break;
4943         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
4944                 pi->use_pcie_performance_levels = true;
4945                 if (pi->pcie_gen_performance.max < pl->pcie_gen)
4946                         pi->pcie_gen_performance.max = pl->pcie_gen;
4947                 if (pi->pcie_gen_performance.min > pl->pcie_gen)
4948                         pi->pcie_gen_performance.min = pl->pcie_gen;
4949                 if (pi->pcie_lane_performance.max < pl->pcie_lane)
4950                         pi->pcie_lane_performance.max = pl->pcie_lane;
4951                 if (pi->pcie_lane_performance.min > pl->pcie_lane)
4952                         pi->pcie_lane_performance.min = pl->pcie_lane;
4953                 break;
4954         default:
4955                 break;
4956         }
4957 }
4958
4959 static int ci_parse_power_table(struct radeon_device *rdev)
4960 {
4961         struct radeon_mode_info *mode_info = &rdev->mode_info;
4962         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
4963         union pplib_power_state *power_state;
4964         int i, j, k, non_clock_array_index, clock_array_index;
4965         union pplib_clock_info *clock_info;
4966         struct _StateArray *state_array;
4967         struct _ClockInfoArray *clock_info_array;
4968         struct _NonClockInfoArray *non_clock_info_array;
4969         union power_info *power_info;
4970         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
4971         u16 data_offset;
4972         u8 frev, crev;
4973         u8 *power_state_offset;
4974         struct ci_ps *ps;
4975
4976         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
4977                                    &frev, &crev, &data_offset))
4978                 return -EINVAL;
4979         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
4980
4981         state_array = (struct _StateArray *)
4982                 (mode_info->atom_context->bios + data_offset +
4983                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
4984         clock_info_array = (struct _ClockInfoArray *)
4985                 (mode_info->atom_context->bios + data_offset +
4986                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
4987         non_clock_info_array = (struct _NonClockInfoArray *)
4988                 (mode_info->atom_context->bios + data_offset +
4989                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
4990
4991         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
4992                                   state_array->ucNumEntries, GFP_KERNEL);
4993         if (!rdev->pm.dpm.ps)
4994                 return -ENOMEM;
4995         power_state_offset = (u8 *)state_array->states;
4996         for (i = 0; i < state_array->ucNumEntries; i++) {
4997                 u8 *idx;
4998                 power_state = (union pplib_power_state *)power_state_offset;
4999                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5000                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5001                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
5002                 if (!rdev->pm.power_state[i].clock_info)
5003                         return -EINVAL;
5004                 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5005                 if (ps == NULL) {
5006                         kfree(rdev->pm.dpm.ps);
5007                         return -ENOMEM;
5008                 }
5009                 rdev->pm.dpm.ps[i].ps_priv = ps;
5010                 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5011                                               non_clock_info,
5012                                               non_clock_info_array->ucEntrySize);
5013                 k = 0;
5014                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5015                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5016                         clock_array_index = idx[j];
5017                         if (clock_array_index >= clock_info_array->ucNumEntries)
5018                                 continue;
5019                         if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5020                                 break;
5021                         clock_info = (union pplib_clock_info *)
5022                                 ((u8 *)&clock_info_array->clockInfo[0] +
5023                                  (clock_array_index * clock_info_array->ucEntrySize));
5024                         ci_parse_pplib_clock_info(rdev,
5025                                                   &rdev->pm.dpm.ps[i], k,
5026                                                   clock_info);
5027                         k++;
5028                 }
5029                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5030         }
5031         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5032
5033         /* fill in the vce power states */
5034         for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5035                 u32 sclk, mclk;
5036                 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5037                 clock_info = (union pplib_clock_info *)
5038                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5039                 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5040                 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5041                 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5042                 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5043                 rdev->pm.dpm.vce_states[i].sclk = sclk;
5044                 rdev->pm.dpm.vce_states[i].mclk = mclk;
5045         }
5046
5047         return 0;
5048 }
5049
5050 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5051                                     struct ci_vbios_boot_state *boot_state)
5052 {
5053         struct radeon_mode_info *mode_info = &rdev->mode_info;
5054         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5055         ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5056         u8 frev, crev;
5057         u16 data_offset;
5058
5059         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5060                                    &frev, &crev, &data_offset)) {
5061                 firmware_info =
5062                         (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5063                                                     data_offset);
5064                 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5065                 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5066                 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5067                 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5068                 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5069                 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5070                 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5071
5072                 return 0;
5073         }
5074         return -EINVAL;
5075 }
5076
5077 void ci_dpm_fini(struct radeon_device *rdev)
5078 {
5079         int i;
5080
5081         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5082                 kfree(rdev->pm.dpm.ps[i].ps_priv);
5083         }
5084         kfree(rdev->pm.dpm.ps);
5085         kfree(rdev->pm.dpm.priv);
5086         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5087         r600_free_extended_power_table(rdev);
5088 }
5089
5090 int ci_dpm_init(struct radeon_device *rdev)
5091 {
5092         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5093         u16 data_offset, size;
5094         u8 frev, crev;
5095         struct ci_power_info *pi;
5096         int ret;
5097         u32 mask;
5098
5099         pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5100         if (pi == NULL)
5101                 return -ENOMEM;
5102         rdev->pm.dpm.priv = pi;
5103
5104         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5105         if (ret)
5106                 pi->sys_pcie_mask = 0;
5107         else
5108                 pi->sys_pcie_mask = mask;
5109         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5110
5111         pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5112         pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5113         pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5114         pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5115
5116         pi->pcie_lane_performance.max = 0;
5117         pi->pcie_lane_performance.min = 16;
5118         pi->pcie_lane_powersaving.max = 0;
5119         pi->pcie_lane_powersaving.min = 16;
5120
5121         ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5122         if (ret) {
5123                 ci_dpm_fini(rdev);
5124                 return ret;
5125         }
5126
5127         ret = r600_get_platform_caps(rdev);
5128         if (ret) {
5129                 ci_dpm_fini(rdev);
5130                 return ret;
5131         }
5132
5133         ret = r600_parse_extended_power_table(rdev);
5134         if (ret) {
5135                 ci_dpm_fini(rdev);
5136                 return ret;
5137         }
5138
5139         ret = ci_parse_power_table(rdev);
5140         if (ret) {
5141                 ci_dpm_fini(rdev);
5142                 return ret;
5143         }
5144
5145         pi->dll_default_on = false;
5146         pi->sram_end = SMC_RAM_END;
5147
5148         pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5149         pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5150         pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5151         pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5152         pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5153         pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5154         pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5155         pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5156
5157         pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5158
5159         pi->sclk_dpm_key_disabled = 0;
5160         pi->mclk_dpm_key_disabled = 0;
5161         pi->pcie_dpm_key_disabled = 0;
5162
5163         /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5164         if ((rdev->pdev->device == 0x6658) &&
5165             (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5166                 pi->mclk_dpm_key_disabled = 1;
5167         }
5168
5169         pi->caps_sclk_ds = true;
5170
5171         pi->mclk_strobe_mode_threshold = 40000;
5172         pi->mclk_stutter_mode_threshold = 40000;
5173         pi->mclk_edc_enable_threshold = 40000;
5174         pi->mclk_edc_wr_enable_threshold = 40000;
5175
5176         ci_initialize_powertune_defaults(rdev);
5177
5178         pi->caps_fps = false;
5179
5180         pi->caps_sclk_throttle_low_notification = false;
5181
5182         pi->caps_uvd_dpm = true;
5183         pi->caps_vce_dpm = true;
5184
5185         ci_get_leakage_voltages(rdev);
5186         ci_patch_dependency_tables_with_leakage(rdev);
5187         ci_set_private_data_variables_based_on_pptable(rdev);
5188
5189         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5190                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5191         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5192                 ci_dpm_fini(rdev);
5193                 return -ENOMEM;
5194         }
5195         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5196         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5197         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5198         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5199         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5200         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5201         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5202         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5203         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5204
5205         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5206         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5207         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5208
5209         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5210         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5211         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5212         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5213
5214         if (rdev->family == CHIP_HAWAII) {
5215                 pi->thermal_temp_setting.temperature_low = 94500;
5216                 pi->thermal_temp_setting.temperature_high = 95000;
5217                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5218         } else {
5219                 pi->thermal_temp_setting.temperature_low = 99500;
5220                 pi->thermal_temp_setting.temperature_high = 100000;
5221                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5222         }
5223
5224         pi->uvd_enabled = false;
5225
5226         pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5227         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5228         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5229         if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5230                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5231         else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5232                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5233
5234         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5235                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5236                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5237                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5238                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5239                 else
5240                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5241         }
5242
5243         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5244                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5245                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5246                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5247                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5248                 else
5249                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5250         }
5251
5252         pi->vddc_phase_shed_control = true;
5253
5254 #if defined(CONFIG_ACPI)
5255         pi->pcie_performance_request =
5256                 radeon_acpi_is_pcie_performance_request_supported(rdev);
5257 #else
5258         pi->pcie_performance_request = false;
5259 #endif
5260
5261         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5262                                    &frev, &crev, &data_offset)) {
5263                 pi->caps_sclk_ss_support = true;
5264                 pi->caps_mclk_ss_support = true;
5265                 pi->dynamic_ss = true;
5266         } else {
5267                 pi->caps_sclk_ss_support = false;
5268                 pi->caps_mclk_ss_support = false;
5269                 pi->dynamic_ss = true;
5270         }
5271
5272         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5273                 pi->thermal_protection = true;
5274         else
5275                 pi->thermal_protection = false;
5276
5277         pi->caps_dynamic_ac_timing = true;
5278
5279         pi->uvd_power_gated = false;
5280
5281         /* make sure dc limits are valid */
5282         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5283             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5284                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5285                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5286
5287         return 0;
5288 }
5289
5290 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5291                                                     struct seq_file *m)
5292 {
5293         u32 sclk = ci_get_average_sclk_freq(rdev);
5294         u32 mclk = ci_get_average_mclk_freq(rdev);
5295
5296         seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
5297                    sclk, mclk);
5298 }
5299
5300 void ci_dpm_print_power_state(struct radeon_device *rdev,
5301                               struct radeon_ps *rps)
5302 {
5303         struct ci_ps *ps = ci_get_ps(rps);
5304         struct ci_pl *pl;
5305         int i;
5306
5307         r600_dpm_print_class_info(rps->class, rps->class2);
5308         r600_dpm_print_cap_info(rps->caps);
5309         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5310         for (i = 0; i < ps->performance_level_count; i++) {
5311                 pl = &ps->performance_levels[i];
5312                 printk("\t\tpower level %d    sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5313                        i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5314         }
5315         r600_dpm_print_ps_status(rdev, rps);
5316 }
5317
5318 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5319 {
5320         struct ci_power_info *pi = ci_get_pi(rdev);
5321         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5322
5323         if (low)
5324                 return requested_state->performance_levels[0].sclk;
5325         else
5326                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5327 }
5328
5329 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5330 {
5331         struct ci_power_info *pi = ci_get_pi(rdev);
5332         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5333
5334         if (low)
5335                 return requested_state->performance_levels[0].mclk;
5336         else
5337                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
5338 }