2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/seq_file.h>
32 #define MC_CG_ARB_FREQ_F0 0x0a
33 #define MC_CG_ARB_FREQ_F1 0x0b
34 #define MC_CG_ARB_FREQ_F2 0x0c
35 #define MC_CG_ARB_FREQ_F3 0x0d
37 #define SMC_RAM_END 0x40000
39 #define VOLTAGE_SCALE 4
40 #define VOLTAGE_VID_OFFSET_SCALE1 625
41 #define VOLTAGE_VID_OFFSET_SCALE2 100
43 static const struct ci_pt_defaults defaults_hawaii_xt =
45 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
46 { 0x84, 0x0, 0x0, 0x7F, 0x0, 0x0, 0x5A, 0x60, 0x51, 0x8E, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
47 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
50 static const struct ci_pt_defaults defaults_hawaii_pro =
52 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
53 { 0x93, 0x0, 0x0, 0x97, 0x0, 0x0, 0x6B, 0x60, 0x51, 0x95, 0x79, 0x6B, 0x5F, 0x90, 0x79 },
54 { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
57 static const struct ci_pt_defaults defaults_bonaire_xt =
59 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
60 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
61 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
64 static const struct ci_pt_defaults defaults_bonaire_pro =
66 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
67 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
68 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
71 static const struct ci_pt_defaults defaults_saturn_xt =
73 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
74 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
75 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
78 static const struct ci_pt_defaults defaults_saturn_pro =
80 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
81 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
82 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
85 static const struct ci_pt_config_reg didt_config_ci[] =
87 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
88 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
89 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
90 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
91 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
92 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
93 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
94 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
95 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
96 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
97 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
98 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
99 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
100 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
101 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
102 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
103 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
104 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
105 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
106 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
107 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
108 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
109 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
110 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
162 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
163 extern void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
165 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
166 u32 arb_freq_src, u32 arb_freq_dest);
167 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
168 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
169 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
170 u32 max_voltage_steps,
171 struct atom_voltage_table *voltage_table);
172 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
173 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
175 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
176 struct atom_voltage_table_entry *voltage_table,
177 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
178 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
179 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
181 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
183 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
185 struct ci_power_info *pi = rdev->pm.dpm.priv;
190 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
192 struct ci_ps *ps = rps->ps_priv;
197 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
199 struct ci_power_info *pi = ci_get_pi(rdev);
201 switch (rdev->pdev->device) {
206 pi->powertune_defaults = &defaults_bonaire_xt;
210 pi->powertune_defaults = &defaults_bonaire_pro;
213 pi->powertune_defaults = &defaults_saturn_xt;
216 pi->powertune_defaults = &defaults_saturn_pro;
228 pi->powertune_defaults = &defaults_hawaii_xt;
232 pi->powertune_defaults = &defaults_hawaii_pro;
236 pi->dte_tj_offset = 0;
238 pi->caps_power_containment = true;
239 pi->caps_cac = false;
240 pi->caps_sq_ramping = false;
241 pi->caps_db_ramping = false;
242 pi->caps_td_ramping = false;
243 pi->caps_tcp_ramping = false;
245 if (pi->caps_power_containment) {
247 pi->enable_bapm_feature = true;
248 pi->enable_tdc_limit_feature = true;
249 pi->enable_pkg_pwr_tracking_feature = true;
253 static u8 ci_convert_to_vid(u16 vddc)
255 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
258 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
260 struct ci_power_info *pi = ci_get_pi(rdev);
261 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
262 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
263 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
266 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
268 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
270 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
271 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
274 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
275 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
276 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
277 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
278 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
280 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
281 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
287 static int ci_populate_vddc_vid(struct radeon_device *rdev)
289 struct ci_power_info *pi = ci_get_pi(rdev);
290 u8 *vid = pi->smc_powertune_table.VddCVid;
293 if (pi->vddc_voltage_table.count > 8)
296 for (i = 0; i < pi->vddc_voltage_table.count; i++)
297 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
302 static int ci_populate_svi_load_line(struct radeon_device *rdev)
304 struct ci_power_info *pi = ci_get_pi(rdev);
305 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
307 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
308 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
309 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
310 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
315 static int ci_populate_tdc_limit(struct radeon_device *rdev)
317 struct ci_power_info *pi = ci_get_pi(rdev);
318 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
321 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
322 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
323 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
324 pt_defaults->tdc_vddc_throttle_release_limit_perc;
325 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
330 static int ci_populate_dw8(struct radeon_device *rdev)
332 struct ci_power_info *pi = ci_get_pi(rdev);
333 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
336 ret = ci_read_smc_sram_dword(rdev,
337 SMU7_FIRMWARE_HEADER_LOCATION +
338 offsetof(SMU7_Firmware_Header, PmFuseTable) +
339 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
340 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
345 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
350 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
352 struct ci_power_info *pi = ci_get_pi(rdev);
353 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
354 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
357 min = max = hi_vid[0];
358 for (i = 0; i < 8; i++) {
359 if (0 != hi_vid[i]) {
366 if (0 != lo_vid[i]) {
374 if ((min == 0) || (max == 0))
376 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
377 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
382 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
384 struct ci_power_info *pi = ci_get_pi(rdev);
385 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
386 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
387 struct radeon_cac_tdp_table *cac_tdp_table =
388 rdev->pm.dpm.dyn_state.cac_tdp_table;
390 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
391 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
393 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
394 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
399 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
401 struct ci_power_info *pi = ci_get_pi(rdev);
402 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
403 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
404 struct radeon_cac_tdp_table *cac_tdp_table =
405 rdev->pm.dpm.dyn_state.cac_tdp_table;
406 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
411 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
412 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
414 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
415 dpm_table->GpuTjMax =
416 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
417 dpm_table->GpuTjHyst = 8;
419 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
422 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
423 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
425 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
426 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
429 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
430 def1 = pt_defaults->bapmti_r;
431 def2 = pt_defaults->bapmti_rc;
433 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
434 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
435 for (k = 0; k < SMU7_DTE_SINKS; k++) {
436 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
437 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
447 static int ci_populate_pm_base(struct radeon_device *rdev)
449 struct ci_power_info *pi = ci_get_pi(rdev);
450 u32 pm_fuse_table_offset;
453 if (pi->caps_power_containment) {
454 ret = ci_read_smc_sram_dword(rdev,
455 SMU7_FIRMWARE_HEADER_LOCATION +
456 offsetof(SMU7_Firmware_Header, PmFuseTable),
457 &pm_fuse_table_offset, pi->sram_end);
460 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
463 ret = ci_populate_vddc_vid(rdev);
466 ret = ci_populate_svi_load_line(rdev);
469 ret = ci_populate_tdc_limit(rdev);
472 ret = ci_populate_dw8(rdev);
475 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
478 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
481 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
482 (u8 *)&pi->smc_powertune_table,
483 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
491 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
493 struct ci_power_info *pi = ci_get_pi(rdev);
496 if (pi->caps_sq_ramping) {
497 data = RREG32_DIDT(DIDT_SQ_CTRL0);
499 data |= DIDT_CTRL_EN;
501 data &= ~DIDT_CTRL_EN;
502 WREG32_DIDT(DIDT_SQ_CTRL0, data);
505 if (pi->caps_db_ramping) {
506 data = RREG32_DIDT(DIDT_DB_CTRL0);
508 data |= DIDT_CTRL_EN;
510 data &= ~DIDT_CTRL_EN;
511 WREG32_DIDT(DIDT_DB_CTRL0, data);
514 if (pi->caps_td_ramping) {
515 data = RREG32_DIDT(DIDT_TD_CTRL0);
517 data |= DIDT_CTRL_EN;
519 data &= ~DIDT_CTRL_EN;
520 WREG32_DIDT(DIDT_TD_CTRL0, data);
523 if (pi->caps_tcp_ramping) {
524 data = RREG32_DIDT(DIDT_TCP_CTRL0);
526 data |= DIDT_CTRL_EN;
528 data &= ~DIDT_CTRL_EN;
529 WREG32_DIDT(DIDT_TCP_CTRL0, data);
533 static int ci_program_pt_config_registers(struct radeon_device *rdev,
534 const struct ci_pt_config_reg *cac_config_regs)
536 const struct ci_pt_config_reg *config_regs = cac_config_regs;
540 if (config_regs == NULL)
543 while (config_regs->offset != 0xFFFFFFFF) {
544 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
545 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
547 switch (config_regs->type) {
548 case CISLANDS_CONFIGREG_SMC_IND:
549 data = RREG32_SMC(config_regs->offset);
551 case CISLANDS_CONFIGREG_DIDT_IND:
552 data = RREG32_DIDT(config_regs->offset);
555 data = RREG32(config_regs->offset << 2);
559 data &= ~config_regs->mask;
560 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
563 switch (config_regs->type) {
564 case CISLANDS_CONFIGREG_SMC_IND:
565 WREG32_SMC(config_regs->offset, data);
567 case CISLANDS_CONFIGREG_DIDT_IND:
568 WREG32_DIDT(config_regs->offset, data);
571 WREG32(config_regs->offset << 2, data);
581 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
583 struct ci_power_info *pi = ci_get_pi(rdev);
586 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
587 pi->caps_td_ramping || pi->caps_tcp_ramping) {
588 cik_enter_rlc_safe_mode(rdev);
591 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
593 cik_exit_rlc_safe_mode(rdev);
598 ci_do_enable_didt(rdev, enable);
600 cik_exit_rlc_safe_mode(rdev);
606 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
608 struct ci_power_info *pi = ci_get_pi(rdev);
609 PPSMC_Result smc_result;
613 pi->power_containment_features = 0;
614 if (pi->caps_power_containment) {
615 if (pi->enable_bapm_feature) {
616 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
617 if (smc_result != PPSMC_Result_OK)
620 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
623 if (pi->enable_tdc_limit_feature) {
624 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
625 if (smc_result != PPSMC_Result_OK)
628 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
631 if (pi->enable_pkg_pwr_tracking_feature) {
632 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
633 if (smc_result != PPSMC_Result_OK) {
636 struct radeon_cac_tdp_table *cac_tdp_table =
637 rdev->pm.dpm.dyn_state.cac_tdp_table;
638 u32 default_pwr_limit =
639 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
641 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
643 ci_set_power_limit(rdev, default_pwr_limit);
648 if (pi->caps_power_containment && pi->power_containment_features) {
649 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
650 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
652 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
653 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
655 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
656 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
657 pi->power_containment_features = 0;
664 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
666 struct ci_power_info *pi = ci_get_pi(rdev);
667 PPSMC_Result smc_result;
672 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
673 if (smc_result != PPSMC_Result_OK) {
675 pi->cac_enabled = false;
677 pi->cac_enabled = true;
679 } else if (pi->cac_enabled) {
680 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
681 pi->cac_enabled = false;
688 static int ci_power_control_set_level(struct radeon_device *rdev)
690 struct ci_power_info *pi = ci_get_pi(rdev);
691 struct radeon_cac_tdp_table *cac_tdp_table =
692 rdev->pm.dpm.dyn_state.cac_tdp_table;
696 bool adjust_polarity = false; /* ??? */
698 if (pi->caps_power_containment &&
699 (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) {
700 adjust_percent = adjust_polarity ?
701 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
702 target_tdp = ((100 + adjust_percent) *
703 (s32)cac_tdp_table->configurable_tdp) / 100;
706 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
712 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
714 struct ci_power_info *pi = ci_get_pi(rdev);
716 if (pi->uvd_power_gated == gate)
719 pi->uvd_power_gated = gate;
721 ci_update_uvd_dpm(rdev, gate);
724 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
726 struct ci_power_info *pi = ci_get_pi(rdev);
727 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
728 u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
730 if (vblank_time < switch_limit)
737 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
738 struct radeon_ps *rps)
740 struct ci_ps *ps = ci_get_ps(rps);
741 struct ci_power_info *pi = ci_get_pi(rdev);
742 struct radeon_clock_and_voltage_limits *max_limits;
743 bool disable_mclk_switching;
745 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
748 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
749 ci_dpm_vblank_too_short(rdev))
750 disable_mclk_switching = true;
752 disable_mclk_switching = false;
754 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
755 pi->battery_state = true;
757 pi->battery_state = false;
759 if (rdev->pm.dpm.ac_power)
760 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
762 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
764 if (rdev->pm.dpm.ac_power == false) {
765 for (i = 0; i < ps->performance_level_count; i++) {
766 if (ps->performance_levels[i].mclk > max_limits->mclk)
767 ps->performance_levels[i].mclk = max_limits->mclk;
768 if (ps->performance_levels[i].sclk > max_limits->sclk)
769 ps->performance_levels[i].sclk = max_limits->sclk;
773 /* limit clocks to max supported clocks based on voltage dependency tables */
774 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
776 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
778 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
781 for (i = 0; i < ps->performance_level_count; i++) {
783 if (ps->performance_levels[i].sclk > max_sclk_vddc)
784 ps->performance_levels[i].sclk = max_sclk_vddc;
786 if (max_mclk_vddci) {
787 if (ps->performance_levels[i].mclk > max_mclk_vddci)
788 ps->performance_levels[i].mclk = max_mclk_vddci;
791 if (ps->performance_levels[i].mclk > max_mclk_vddc)
792 ps->performance_levels[i].mclk = max_mclk_vddc;
796 /* XXX validate the min clocks required for display */
798 if (disable_mclk_switching) {
799 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
800 sclk = ps->performance_levels[0].sclk;
802 mclk = ps->performance_levels[0].mclk;
803 sclk = ps->performance_levels[0].sclk;
806 ps->performance_levels[0].sclk = sclk;
807 ps->performance_levels[0].mclk = mclk;
809 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
810 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
812 if (disable_mclk_switching) {
813 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
814 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
816 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
817 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
821 static int ci_set_thermal_temperature_range(struct radeon_device *rdev,
822 int min_temp, int max_temp)
824 int low_temp = 0 * 1000;
825 int high_temp = 255 * 1000;
828 if (low_temp < min_temp)
830 if (high_temp > max_temp)
831 high_temp = max_temp;
832 if (high_temp < low_temp) {
833 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
837 tmp = RREG32_SMC(CG_THERMAL_INT);
838 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
839 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
840 CI_DIG_THERM_INTL(low_temp / 1000);
841 WREG32_SMC(CG_THERMAL_INT, tmp);
844 /* XXX: need to figure out how to handle this properly */
845 tmp = RREG32_SMC(CG_THERMAL_CTRL);
846 tmp &= DIG_THERM_DPM_MASK;
847 tmp |= DIG_THERM_DPM(high_temp / 1000);
848 WREG32_SMC(CG_THERMAL_CTRL, tmp);
855 static int ci_read_smc_soft_register(struct radeon_device *rdev,
856 u16 reg_offset, u32 *value)
858 struct ci_power_info *pi = ci_get_pi(rdev);
860 return ci_read_smc_sram_dword(rdev,
861 pi->soft_regs_start + reg_offset,
862 value, pi->sram_end);
866 static int ci_write_smc_soft_register(struct radeon_device *rdev,
867 u16 reg_offset, u32 value)
869 struct ci_power_info *pi = ci_get_pi(rdev);
871 return ci_write_smc_sram_dword(rdev,
872 pi->soft_regs_start + reg_offset,
873 value, pi->sram_end);
876 static void ci_init_fps_limits(struct radeon_device *rdev)
878 struct ci_power_info *pi = ci_get_pi(rdev);
879 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
885 table->FpsHighT = cpu_to_be16(tmp);
888 table->FpsLowT = cpu_to_be16(tmp);
892 static int ci_update_sclk_t(struct radeon_device *rdev)
894 struct ci_power_info *pi = ci_get_pi(rdev);
896 u32 low_sclk_interrupt_t = 0;
898 if (pi->caps_sclk_throttle_low_notification) {
899 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
901 ret = ci_copy_bytes_to_smc(rdev,
902 pi->dpm_table_start +
903 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
904 (u8 *)&low_sclk_interrupt_t,
905 sizeof(u32), pi->sram_end);
912 static void ci_get_leakage_voltages(struct radeon_device *rdev)
914 struct ci_power_info *pi = ci_get_pi(rdev);
915 u16 leakage_id, virtual_voltage_id;
919 pi->vddc_leakage.count = 0;
920 pi->vddci_leakage.count = 0;
922 if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
923 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
924 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
925 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
928 if (vddc != 0 && vddc != virtual_voltage_id) {
929 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
930 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
931 pi->vddc_leakage.count++;
933 if (vddci != 0 && vddci != virtual_voltage_id) {
934 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
935 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
936 pi->vddci_leakage.count++;
943 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
945 struct ci_power_info *pi = ci_get_pi(rdev);
946 bool want_thermal_protection;
947 enum radeon_dpm_event_src dpm_event_src;
953 want_thermal_protection = false;
955 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
956 want_thermal_protection = true;
957 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
959 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
960 want_thermal_protection = true;
961 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
963 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
964 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
965 want_thermal_protection = true;
966 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
970 if (want_thermal_protection) {
972 /* XXX: need to figure out how to handle this properly */
973 tmp = RREG32_SMC(CG_THERMAL_CTRL);
974 tmp &= DPM_EVENT_SRC_MASK;
975 tmp |= DPM_EVENT_SRC(dpm_event_src);
976 WREG32_SMC(CG_THERMAL_CTRL, tmp);
979 tmp = RREG32_SMC(GENERAL_PWRMGT);
980 if (pi->thermal_protection)
981 tmp &= ~THERMAL_PROTECTION_DIS;
983 tmp |= THERMAL_PROTECTION_DIS;
984 WREG32_SMC(GENERAL_PWRMGT, tmp);
986 tmp = RREG32_SMC(GENERAL_PWRMGT);
987 tmp |= THERMAL_PROTECTION_DIS;
988 WREG32_SMC(GENERAL_PWRMGT, tmp);
992 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
993 enum radeon_dpm_auto_throttle_src source,
996 struct ci_power_info *pi = ci_get_pi(rdev);
999 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1000 pi->active_auto_throttle_sources |= 1 << source;
1001 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1004 if (pi->active_auto_throttle_sources & (1 << source)) {
1005 pi->active_auto_throttle_sources &= ~(1 << source);
1006 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1011 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1013 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1014 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1017 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1019 struct ci_power_info *pi = ci_get_pi(rdev);
1020 PPSMC_Result smc_result;
1022 if (!pi->need_update_smu7_dpm_table)
1025 if ((!pi->sclk_dpm_key_disabled) &&
1026 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1027 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1028 if (smc_result != PPSMC_Result_OK)
1032 if ((!pi->mclk_dpm_key_disabled) &&
1033 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1034 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1035 if (smc_result != PPSMC_Result_OK)
1039 pi->need_update_smu7_dpm_table = 0;
1043 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1045 struct ci_power_info *pi = ci_get_pi(rdev);
1046 PPSMC_Result smc_result;
1049 if (!pi->sclk_dpm_key_disabled) {
1050 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1051 if (smc_result != PPSMC_Result_OK)
1055 if (!pi->mclk_dpm_key_disabled) {
1056 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1057 if (smc_result != PPSMC_Result_OK)
1060 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1062 WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1063 WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1064 WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1068 WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1069 WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1070 WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1073 if (!pi->sclk_dpm_key_disabled) {
1074 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1075 if (smc_result != PPSMC_Result_OK)
1079 if (!pi->mclk_dpm_key_disabled) {
1080 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1081 if (smc_result != PPSMC_Result_OK)
1089 static int ci_start_dpm(struct radeon_device *rdev)
1091 struct ci_power_info *pi = ci_get_pi(rdev);
1092 PPSMC_Result smc_result;
1096 tmp = RREG32_SMC(GENERAL_PWRMGT);
1097 tmp |= GLOBAL_PWRMGT_EN;
1098 WREG32_SMC(GENERAL_PWRMGT, tmp);
1100 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1101 tmp |= DYNAMIC_PM_EN;
1102 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1104 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1106 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1108 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1109 if (smc_result != PPSMC_Result_OK)
1112 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1116 if (!pi->pcie_dpm_key_disabled) {
1117 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1118 if (smc_result != PPSMC_Result_OK)
1125 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1127 struct ci_power_info *pi = ci_get_pi(rdev);
1128 PPSMC_Result smc_result;
1130 if (!pi->need_update_smu7_dpm_table)
1133 if ((!pi->sclk_dpm_key_disabled) &&
1134 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1135 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1136 if (smc_result != PPSMC_Result_OK)
1140 if ((!pi->mclk_dpm_key_disabled) &&
1141 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1142 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1143 if (smc_result != PPSMC_Result_OK)
1150 static int ci_stop_dpm(struct radeon_device *rdev)
1152 struct ci_power_info *pi = ci_get_pi(rdev);
1153 PPSMC_Result smc_result;
1157 tmp = RREG32_SMC(GENERAL_PWRMGT);
1158 tmp &= ~GLOBAL_PWRMGT_EN;
1159 WREG32_SMC(GENERAL_PWRMGT, tmp);
1161 tmp = RREG32(SCLK_PWRMGT_CNTL);
1162 tmp &= ~DYNAMIC_PM_EN;
1163 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1165 if (!pi->pcie_dpm_key_disabled) {
1166 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1167 if (smc_result != PPSMC_Result_OK)
1171 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1175 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1176 if (smc_result != PPSMC_Result_OK)
1182 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1184 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1187 tmp &= ~SCLK_PWRMGT_OFF;
1189 tmp |= SCLK_PWRMGT_OFF;
1190 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1194 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1197 struct ci_power_info *pi = ci_get_pi(rdev);
1198 struct radeon_cac_tdp_table *cac_tdp_table =
1199 rdev->pm.dpm.dyn_state.cac_tdp_table;
1203 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1205 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1207 ci_set_power_limit(rdev, power_limit);
1209 if (pi->caps_automatic_dc_transition) {
1211 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1213 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1220 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1221 PPSMC_Msg msg, u32 parameter)
1223 WREG32(SMC_MSG_ARG_0, parameter);
1224 return ci_send_msg_to_smc(rdev, msg);
1227 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1228 PPSMC_Msg msg, u32 *parameter)
1230 PPSMC_Result smc_result;
1232 smc_result = ci_send_msg_to_smc(rdev, msg);
1234 if ((smc_result == PPSMC_Result_OK) && parameter)
1235 *parameter = RREG32(SMC_MSG_ARG_0);
1240 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1242 struct ci_power_info *pi = ci_get_pi(rdev);
1244 if (!pi->sclk_dpm_key_disabled) {
1245 PPSMC_Result smc_result =
1246 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, n);
1247 if (smc_result != PPSMC_Result_OK)
1254 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1256 struct ci_power_info *pi = ci_get_pi(rdev);
1258 if (!pi->mclk_dpm_key_disabled) {
1259 PPSMC_Result smc_result =
1260 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_ForceState, n);
1261 if (smc_result != PPSMC_Result_OK)
1268 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1270 struct ci_power_info *pi = ci_get_pi(rdev);
1272 if (!pi->pcie_dpm_key_disabled) {
1273 PPSMC_Result smc_result =
1274 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1275 if (smc_result != PPSMC_Result_OK)
1282 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1284 struct ci_power_info *pi = ci_get_pi(rdev);
1286 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1287 PPSMC_Result smc_result =
1288 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1289 if (smc_result != PPSMC_Result_OK)
1296 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1299 PPSMC_Result smc_result =
1300 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1301 if (smc_result != PPSMC_Result_OK)
1306 static int ci_set_boot_state(struct radeon_device *rdev)
1308 return ci_enable_sclk_mclk_dpm(rdev, false);
1311 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1314 PPSMC_Result smc_result =
1315 ci_send_msg_to_smc_return_parameter(rdev,
1316 PPSMC_MSG_API_GetSclkFrequency,
1318 if (smc_result != PPSMC_Result_OK)
1324 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1327 PPSMC_Result smc_result =
1328 ci_send_msg_to_smc_return_parameter(rdev,
1329 PPSMC_MSG_API_GetMclkFrequency,
1331 if (smc_result != PPSMC_Result_OK)
1337 static void ci_dpm_start_smc(struct radeon_device *rdev)
1341 ci_program_jump_on_start(rdev);
1342 ci_start_smc_clock(rdev);
1344 for (i = 0; i < rdev->usec_timeout; i++) {
1345 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1350 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1353 ci_stop_smc_clock(rdev);
1356 static int ci_process_firmware_header(struct radeon_device *rdev)
1358 struct ci_power_info *pi = ci_get_pi(rdev);
1362 ret = ci_read_smc_sram_dword(rdev,
1363 SMU7_FIRMWARE_HEADER_LOCATION +
1364 offsetof(SMU7_Firmware_Header, DpmTable),
1365 &tmp, pi->sram_end);
1369 pi->dpm_table_start = tmp;
1371 ret = ci_read_smc_sram_dword(rdev,
1372 SMU7_FIRMWARE_HEADER_LOCATION +
1373 offsetof(SMU7_Firmware_Header, SoftRegisters),
1374 &tmp, pi->sram_end);
1378 pi->soft_regs_start = tmp;
1380 ret = ci_read_smc_sram_dword(rdev,
1381 SMU7_FIRMWARE_HEADER_LOCATION +
1382 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1383 &tmp, pi->sram_end);
1387 pi->mc_reg_table_start = tmp;
1389 ret = ci_read_smc_sram_dword(rdev,
1390 SMU7_FIRMWARE_HEADER_LOCATION +
1391 offsetof(SMU7_Firmware_Header, FanTable),
1392 &tmp, pi->sram_end);
1396 pi->fan_table_start = tmp;
1398 ret = ci_read_smc_sram_dword(rdev,
1399 SMU7_FIRMWARE_HEADER_LOCATION +
1400 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1401 &tmp, pi->sram_end);
1405 pi->arb_table_start = tmp;
1410 static void ci_read_clock_registers(struct radeon_device *rdev)
1412 struct ci_power_info *pi = ci_get_pi(rdev);
1414 pi->clock_registers.cg_spll_func_cntl =
1415 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1416 pi->clock_registers.cg_spll_func_cntl_2 =
1417 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1418 pi->clock_registers.cg_spll_func_cntl_3 =
1419 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1420 pi->clock_registers.cg_spll_func_cntl_4 =
1421 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1422 pi->clock_registers.cg_spll_spread_spectrum =
1423 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1424 pi->clock_registers.cg_spll_spread_spectrum_2 =
1425 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1426 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1427 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1428 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1429 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1430 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1431 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1432 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1433 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1434 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1437 static void ci_init_sclk_t(struct radeon_device *rdev)
1439 struct ci_power_info *pi = ci_get_pi(rdev);
1441 pi->low_sclk_interrupt_t = 0;
1444 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1447 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1450 tmp &= ~THERMAL_PROTECTION_DIS;
1452 tmp |= THERMAL_PROTECTION_DIS;
1453 WREG32_SMC(GENERAL_PWRMGT, tmp);
1456 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1458 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1460 tmp |= STATIC_PM_EN;
1462 WREG32_SMC(GENERAL_PWRMGT, tmp);
1466 static int ci_enter_ulp_state(struct radeon_device *rdev)
1469 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1476 static int ci_exit_ulp_state(struct radeon_device *rdev)
1480 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1484 for (i = 0; i < rdev->usec_timeout; i++) {
1485 if (RREG32(SMC_RESP_0) == 1)
1494 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1497 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1499 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1502 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1505 struct ci_power_info *pi = ci_get_pi(rdev);
1508 if (pi->caps_sclk_ds) {
1509 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1512 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1516 if (pi->caps_sclk_ds) {
1517 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1525 static void ci_program_display_gap(struct radeon_device *rdev)
1527 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1528 u32 pre_vbi_time_in_us;
1529 u32 frame_time_in_us;
1530 u32 ref_clock = rdev->clock.spll.reference_freq;
1531 u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1532 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1534 tmp &= ~DISP_GAP_MASK;
1535 if (rdev->pm.dpm.new_active_crtc_count > 0)
1536 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1538 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1539 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1541 if (refresh_rate == 0)
1543 if (vblank_time == 0xffffffff)
1545 frame_time_in_us = 1000000 / refresh_rate;
1546 pre_vbi_time_in_us =
1547 frame_time_in_us - 200 - vblank_time;
1548 tmp = pre_vbi_time_in_us * (ref_clock / 100);
1550 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1551 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1552 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1555 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1559 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1561 struct ci_power_info *pi = ci_get_pi(rdev);
1565 if (pi->caps_sclk_ss_support) {
1566 tmp = RREG32_SMC(GENERAL_PWRMGT);
1567 tmp |= DYN_SPREAD_SPECTRUM_EN;
1568 WREG32_SMC(GENERAL_PWRMGT, tmp);
1571 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1573 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
1575 tmp = RREG32_SMC(GENERAL_PWRMGT);
1576 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
1577 WREG32_SMC(GENERAL_PWRMGT, tmp);
1581 static void ci_program_sstp(struct radeon_device *rdev)
1583 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
1586 static void ci_enable_display_gap(struct radeon_device *rdev)
1588 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1590 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
1591 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1592 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
1594 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1597 static void ci_program_vc(struct radeon_device *rdev)
1601 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1602 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
1603 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1605 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
1606 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
1607 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
1608 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
1609 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
1610 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
1611 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
1612 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
1615 static void ci_clear_vc(struct radeon_device *rdev)
1619 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1620 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
1621 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1623 WREG32_SMC(CG_FTV_0, 0);
1624 WREG32_SMC(CG_FTV_1, 0);
1625 WREG32_SMC(CG_FTV_2, 0);
1626 WREG32_SMC(CG_FTV_3, 0);
1627 WREG32_SMC(CG_FTV_4, 0);
1628 WREG32_SMC(CG_FTV_5, 0);
1629 WREG32_SMC(CG_FTV_6, 0);
1630 WREG32_SMC(CG_FTV_7, 0);
1633 static int ci_upload_firmware(struct radeon_device *rdev)
1635 struct ci_power_info *pi = ci_get_pi(rdev);
1638 for (i = 0; i < rdev->usec_timeout; i++) {
1639 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
1642 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
1644 ci_stop_smc_clock(rdev);
1647 ret = ci_load_smc_ucode(rdev, pi->sram_end);
1653 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
1654 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
1655 struct atom_voltage_table *voltage_table)
1659 if (voltage_dependency_table == NULL)
1662 voltage_table->mask_low = 0;
1663 voltage_table->phase_delay = 0;
1665 voltage_table->count = voltage_dependency_table->count;
1666 for (i = 0; i < voltage_table->count; i++) {
1667 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
1668 voltage_table->entries[i].smio_low = 0;
1674 static int ci_construct_voltage_tables(struct radeon_device *rdev)
1676 struct ci_power_info *pi = ci_get_pi(rdev);
1679 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1680 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
1681 VOLTAGE_OBJ_GPIO_LUT,
1682 &pi->vddc_voltage_table);
1685 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1686 ret = ci_get_svi2_voltage_table(rdev,
1687 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
1688 &pi->vddc_voltage_table);
1693 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
1694 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
1695 &pi->vddc_voltage_table);
1697 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1698 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
1699 VOLTAGE_OBJ_GPIO_LUT,
1700 &pi->vddci_voltage_table);
1703 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1704 ret = ci_get_svi2_voltage_table(rdev,
1705 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
1706 &pi->vddci_voltage_table);
1711 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
1712 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
1713 &pi->vddci_voltage_table);
1715 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1716 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
1717 VOLTAGE_OBJ_GPIO_LUT,
1718 &pi->mvdd_voltage_table);
1721 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1722 ret = ci_get_svi2_voltage_table(rdev,
1723 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
1724 &pi->mvdd_voltage_table);
1729 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
1730 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
1731 &pi->mvdd_voltage_table);
1736 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
1737 struct atom_voltage_table_entry *voltage_table,
1738 SMU7_Discrete_VoltageLevel *smc_voltage_table)
1742 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
1743 &smc_voltage_table->StdVoltageHiSidd,
1744 &smc_voltage_table->StdVoltageLoSidd);
1747 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
1748 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
1751 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
1752 smc_voltage_table->StdVoltageHiSidd =
1753 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
1754 smc_voltage_table->StdVoltageLoSidd =
1755 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
1758 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
1759 SMU7_Discrete_DpmTable *table)
1761 struct ci_power_info *pi = ci_get_pi(rdev);
1764 table->VddcLevelCount = pi->vddc_voltage_table.count;
1765 for (count = 0; count < table->VddcLevelCount; count++) {
1766 ci_populate_smc_voltage_table(rdev,
1767 &pi->vddc_voltage_table.entries[count],
1768 &table->VddcLevel[count]);
1770 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1771 table->VddcLevel[count].Smio |=
1772 pi->vddc_voltage_table.entries[count].smio_low;
1774 table->VddcLevel[count].Smio = 0;
1776 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
1781 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
1782 SMU7_Discrete_DpmTable *table)
1785 struct ci_power_info *pi = ci_get_pi(rdev);
1787 table->VddciLevelCount = pi->vddci_voltage_table.count;
1788 for (count = 0; count < table->VddciLevelCount; count++) {
1789 ci_populate_smc_voltage_table(rdev,
1790 &pi->vddci_voltage_table.entries[count],
1791 &table->VddciLevel[count]);
1793 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1794 table->VddciLevel[count].Smio |=
1795 pi->vddci_voltage_table.entries[count].smio_low;
1797 table->VddciLevel[count].Smio = 0;
1799 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
1804 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
1805 SMU7_Discrete_DpmTable *table)
1807 struct ci_power_info *pi = ci_get_pi(rdev);
1810 table->MvddLevelCount = pi->mvdd_voltage_table.count;
1811 for (count = 0; count < table->MvddLevelCount; count++) {
1812 ci_populate_smc_voltage_table(rdev,
1813 &pi->mvdd_voltage_table.entries[count],
1814 &table->MvddLevel[count]);
1816 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1817 table->MvddLevel[count].Smio |=
1818 pi->mvdd_voltage_table.entries[count].smio_low;
1820 table->MvddLevel[count].Smio = 0;
1822 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
1827 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
1828 SMU7_Discrete_DpmTable *table)
1832 ret = ci_populate_smc_vddc_table(rdev, table);
1836 ret = ci_populate_smc_vddci_table(rdev, table);
1840 ret = ci_populate_smc_mvdd_table(rdev, table);
1847 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
1848 SMU7_Discrete_VoltageLevel *voltage)
1850 struct ci_power_info *pi = ci_get_pi(rdev);
1853 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
1854 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
1855 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
1856 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
1861 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
1868 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
1869 struct atom_voltage_table_entry *voltage_table,
1870 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
1873 bool voltage_found = false;
1874 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
1875 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
1877 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
1880 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
1881 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1882 if (voltage_table->value ==
1883 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1884 voltage_found = true;
1885 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1888 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1889 *std_voltage_lo_sidd =
1890 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1891 *std_voltage_hi_sidd =
1892 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1897 if (!voltage_found) {
1898 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1899 if (voltage_table->value <=
1900 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1901 voltage_found = true;
1902 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1905 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1906 *std_voltage_lo_sidd =
1907 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1908 *std_voltage_hi_sidd =
1909 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1919 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
1920 const struct radeon_phase_shedding_limits_table *limits,
1922 u32 *phase_shedding)
1926 *phase_shedding = 1;
1928 for (i = 0; i < limits->count; i++) {
1929 if (sclk < limits->entries[i].sclk) {
1930 *phase_shedding = i;
1936 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
1937 const struct radeon_phase_shedding_limits_table *limits,
1939 u32 *phase_shedding)
1943 *phase_shedding = 1;
1945 for (i = 0; i < limits->count; i++) {
1946 if (mclk < limits->entries[i].mclk) {
1947 *phase_shedding = i;
1953 static int ci_init_arb_table_index(struct radeon_device *rdev)
1955 struct ci_power_info *pi = ci_get_pi(rdev);
1959 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
1960 &tmp, pi->sram_end);
1965 tmp |= MC_CG_ARB_FREQ_F1 << 24;
1967 return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
1971 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
1972 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
1973 u32 clock, u32 *voltage)
1977 if (allowed_clock_voltage_table->count == 0)
1980 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
1981 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
1982 *voltage = allowed_clock_voltage_table->entries[i].v;
1987 *voltage = allowed_clock_voltage_table->entries[i-1].v;
1992 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1993 u32 sclk, u32 min_sclk_in_sr)
1997 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
1998 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2003 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2004 tmp = sclk / (1 << i);
2005 if (tmp >= min || i == 0)
2012 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2014 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2017 static int ci_reset_to_default(struct radeon_device *rdev)
2019 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2023 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2027 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2029 if (tmp == MC_CG_ARB_FREQ_F0)
2032 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2035 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2038 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2044 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2046 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
2047 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2048 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2050 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2051 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2052 arb_regs->McArbBurstTime = (u8)burst_time;
2057 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2059 struct ci_power_info *pi = ci_get_pi(rdev);
2060 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2064 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2066 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2067 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2068 ret = ci_populate_memory_timing_parameters(rdev,
2069 pi->dpm_table.sclk_table.dpm_levels[i].value,
2070 pi->dpm_table.mclk_table.dpm_levels[j].value,
2071 &arb_regs.entries[i][j]);
2078 ret = ci_copy_bytes_to_smc(rdev,
2079 pi->arb_table_start,
2081 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2087 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2089 struct ci_power_info *pi = ci_get_pi(rdev);
2091 if (pi->need_update_smu7_dpm_table == 0)
2094 return ci_do_program_memory_timing_parameters(rdev);
2097 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2098 struct radeon_ps *radeon_boot_state)
2100 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2101 struct ci_power_info *pi = ci_get_pi(rdev);
2104 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2105 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2106 boot_state->performance_levels[0].sclk) {
2107 pi->smc_state_table.GraphicsBootLevel = level;
2112 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2113 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2114 boot_state->performance_levels[0].mclk) {
2115 pi->smc_state_table.MemoryBootLevel = level;
2121 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2126 for (i = dpm_table->count; i > 0; i--) {
2127 mask_value = mask_value << 1;
2128 if (dpm_table->dpm_levels[i-1].enabled)
2131 mask_value &= 0xFFFFFFFE;
2137 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2138 SMU7_Discrete_DpmTable *table)
2140 struct ci_power_info *pi = ci_get_pi(rdev);
2141 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2144 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2145 table->LinkLevel[i].PcieGenSpeed =
2146 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2147 table->LinkLevel[i].PcieLaneCount =
2148 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2149 table->LinkLevel[i].EnabledForActivity = 1;
2150 table->LinkLevel[i].DownT = cpu_to_be32(5);
2151 table->LinkLevel[i].UpT = cpu_to_be32(30);
2154 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2155 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2156 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2159 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2160 SMU7_Discrete_DpmTable *table)
2163 struct atom_clock_dividers dividers;
2166 table->UvdLevelCount =
2167 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2169 for (count = 0; count < table->UvdLevelCount; count++) {
2170 table->UvdLevel[count].VclkFrequency =
2171 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2172 table->UvdLevel[count].DclkFrequency =
2173 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2174 table->UvdLevel[count].MinVddc =
2175 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2176 table->UvdLevel[count].MinVddcPhases = 1;
2178 ret = radeon_atom_get_clock_dividers(rdev,
2179 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2180 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2184 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2186 ret = radeon_atom_get_clock_dividers(rdev,
2187 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2188 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2192 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2194 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2195 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2196 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2202 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2203 SMU7_Discrete_DpmTable *table)
2206 struct atom_clock_dividers dividers;
2209 table->VceLevelCount =
2210 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2212 for (count = 0; count < table->VceLevelCount; count++) {
2213 table->VceLevel[count].Frequency =
2214 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2215 table->VceLevel[count].MinVoltage =
2216 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2217 table->VceLevel[count].MinPhases = 1;
2219 ret = radeon_atom_get_clock_dividers(rdev,
2220 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2221 table->VceLevel[count].Frequency, false, ÷rs);
2225 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2227 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2228 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2235 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2236 SMU7_Discrete_DpmTable *table)
2239 struct atom_clock_dividers dividers;
2242 table->AcpLevelCount = (u8)
2243 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2245 for (count = 0; count < table->AcpLevelCount; count++) {
2246 table->AcpLevel[count].Frequency =
2247 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2248 table->AcpLevel[count].MinVoltage =
2249 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2250 table->AcpLevel[count].MinPhases = 1;
2252 ret = radeon_atom_get_clock_dividers(rdev,
2253 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2254 table->AcpLevel[count].Frequency, false, ÷rs);
2258 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2260 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2261 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2267 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2268 SMU7_Discrete_DpmTable *table)
2271 struct atom_clock_dividers dividers;
2274 table->SamuLevelCount =
2275 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2277 for (count = 0; count < table->SamuLevelCount; count++) {
2278 table->SamuLevel[count].Frequency =
2279 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2280 table->SamuLevel[count].MinVoltage =
2281 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2282 table->SamuLevel[count].MinPhases = 1;
2284 ret = radeon_atom_get_clock_dividers(rdev,
2285 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2286 table->SamuLevel[count].Frequency, false, ÷rs);
2290 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2292 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2293 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2299 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2301 SMU7_Discrete_MemoryLevel *mclk,
2305 struct ci_power_info *pi = ci_get_pi(rdev);
2306 u32 dll_cntl = pi->clock_registers.dll_cntl;
2307 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2308 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2309 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2310 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2311 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2312 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2313 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2314 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2315 struct atom_mpll_param mpll_param;
2318 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2322 mpll_func_cntl &= ~BWCTRL_MASK;
2323 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2325 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2326 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2327 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2329 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2330 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2332 if (pi->mem_gddr5) {
2333 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2334 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2335 YCLK_POST_DIV(mpll_param.post_div);
2338 if (pi->caps_mclk_ss_support) {
2339 struct radeon_atom_ss ss;
2342 u32 reference_clock = rdev->clock.mpll.reference_freq;
2345 freq_nom = memory_clock * 4;
2347 freq_nom = memory_clock * 2;
2349 tmp = (freq_nom / reference_clock);
2351 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2352 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2353 u32 clks = reference_clock * 5 / ss.rate;
2354 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2356 mpll_ss1 &= ~CLKV_MASK;
2357 mpll_ss1 |= CLKV(clkv);
2359 mpll_ss2 &= ~CLKS_MASK;
2360 mpll_ss2 |= CLKS(clks);
2364 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2365 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2368 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2370 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2372 mclk->MclkFrequency = memory_clock;
2373 mclk->MpllFuncCntl = mpll_func_cntl;
2374 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2375 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2376 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2377 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2378 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2379 mclk->DllCntl = dll_cntl;
2380 mclk->MpllSs1 = mpll_ss1;
2381 mclk->MpllSs2 = mpll_ss2;
2386 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2388 SMU7_Discrete_MemoryLevel *memory_level)
2390 struct ci_power_info *pi = ci_get_pi(rdev);
2394 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2395 ret = ci_get_dependency_volt_by_clk(rdev,
2396 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2397 memory_clock, &memory_level->MinVddc);
2402 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2403 ret = ci_get_dependency_volt_by_clk(rdev,
2404 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2405 memory_clock, &memory_level->MinVddci);
2410 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2411 ret = ci_get_dependency_volt_by_clk(rdev,
2412 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2413 memory_clock, &memory_level->MinMvdd);
2418 memory_level->MinVddcPhases = 1;
2420 if (pi->vddc_phase_shed_control)
2421 ci_populate_phase_value_based_on_mclk(rdev,
2422 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2424 &memory_level->MinVddcPhases);
2426 memory_level->EnabledForThrottle = 1;
2427 memory_level->EnabledForActivity = 1;
2428 memory_level->UpH = 0;
2429 memory_level->DownH = 100;
2430 memory_level->VoltageDownH = 0;
2431 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2433 memory_level->StutterEnable = false;
2434 memory_level->StrobeEnable = false;
2435 memory_level->EdcReadEnable = false;
2436 memory_level->EdcWriteEnable = false;
2437 memory_level->RttEnable = false;
2439 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2441 if (pi->mclk_stutter_mode_threshold &&
2442 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2443 (pi->uvd_enabled == false) &&
2444 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2445 (rdev->pm.dpm.new_active_crtc_count <= 2))
2446 memory_level->StutterEnable = true;
2448 if (pi->mclk_strobe_mode_threshold &&
2449 (memory_clock <= pi->mclk_strobe_mode_threshold))
2450 memory_level->StrobeEnable = 1;
2452 if (pi->mem_gddr5) {
2453 memory_level->StrobeRatio =
2454 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2455 if (pi->mclk_edc_enable_threshold &&
2456 (memory_clock > pi->mclk_edc_enable_threshold))
2457 memory_level->EdcReadEnable = true;
2459 if (pi->mclk_edc_wr_enable_threshold &&
2460 (memory_clock > pi->mclk_edc_wr_enable_threshold))
2461 memory_level->EdcWriteEnable = true;
2463 if (memory_level->StrobeEnable) {
2464 if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2465 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2466 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2468 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2470 dll_state_on = pi->dll_default_on;
2473 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2474 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2477 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2481 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2482 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2483 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2484 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2486 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2487 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2488 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2489 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2490 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2491 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2492 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2493 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2494 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2495 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2496 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2501 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2502 SMU7_Discrete_DpmTable *table)
2504 struct ci_power_info *pi = ci_get_pi(rdev);
2505 struct atom_clock_dividers dividers;
2506 SMU7_Discrete_VoltageLevel voltage_level;
2507 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2508 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2509 u32 dll_cntl = pi->clock_registers.dll_cntl;
2510 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2513 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2516 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2518 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2520 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2522 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2524 ret = radeon_atom_get_clock_dividers(rdev,
2525 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2526 table->ACPILevel.SclkFrequency, false, ÷rs);
2530 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2531 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2532 table->ACPILevel.DeepSleepDivId = 0;
2534 spll_func_cntl &= ~SPLL_PWRON;
2535 spll_func_cntl |= SPLL_RESET;
2537 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2538 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
2540 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2541 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2542 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2543 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
2544 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
2545 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2546 table->ACPILevel.CcPwrDynRm = 0;
2547 table->ACPILevel.CcPwrDynRm1 = 0;
2549 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
2550 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
2551 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
2552 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
2553 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
2554 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
2555 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
2556 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
2557 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
2558 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
2559 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
2561 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
2562 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
2564 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2566 table->MemoryACPILevel.MinVddci =
2567 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
2569 table->MemoryACPILevel.MinVddci =
2570 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
2573 if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
2574 table->MemoryACPILevel.MinMvdd = 0;
2576 table->MemoryACPILevel.MinMvdd =
2577 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
2579 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
2580 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2582 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
2584 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
2585 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
2586 table->MemoryACPILevel.MpllAdFuncCntl =
2587 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
2588 table->MemoryACPILevel.MpllDqFuncCntl =
2589 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
2590 table->MemoryACPILevel.MpllFuncCntl =
2591 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
2592 table->MemoryACPILevel.MpllFuncCntl_1 =
2593 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
2594 table->MemoryACPILevel.MpllFuncCntl_2 =
2595 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
2596 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
2597 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
2599 table->MemoryACPILevel.EnabledForThrottle = 0;
2600 table->MemoryACPILevel.EnabledForActivity = 0;
2601 table->MemoryACPILevel.UpH = 0;
2602 table->MemoryACPILevel.DownH = 100;
2603 table->MemoryACPILevel.VoltageDownH = 0;
2604 table->MemoryACPILevel.ActivityLevel =
2605 cpu_to_be16((u16)pi->mclk_activity_target);
2607 table->MemoryACPILevel.StutterEnable = false;
2608 table->MemoryACPILevel.StrobeEnable = false;
2609 table->MemoryACPILevel.EdcReadEnable = false;
2610 table->MemoryACPILevel.EdcWriteEnable = false;
2611 table->MemoryACPILevel.RttEnable = false;
2617 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
2619 struct ci_power_info *pi = ci_get_pi(rdev);
2620 struct ci_ulv_parm *ulv = &pi->ulv;
2622 if (ulv->supported) {
2624 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
2627 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
2634 static int ci_populate_ulv_level(struct radeon_device *rdev,
2635 SMU7_Discrete_Ulv *state)
2637 struct ci_power_info *pi = ci_get_pi(rdev);
2638 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
2640 state->CcPwrDynRm = 0;
2641 state->CcPwrDynRm1 = 0;
2643 if (ulv_voltage == 0) {
2644 pi->ulv.supported = false;
2648 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2649 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2650 state->VddcOffset = 0;
2653 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
2655 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2656 state->VddcOffsetVid = 0;
2658 state->VddcOffsetVid = (u8)
2659 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
2660 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2662 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
2664 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
2665 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
2666 state->VddcOffset = cpu_to_be16(state->VddcOffset);
2671 static int ci_calculate_sclk_params(struct radeon_device *rdev,
2673 SMU7_Discrete_GraphicsLevel *sclk)
2675 struct ci_power_info *pi = ci_get_pi(rdev);
2676 struct atom_clock_dividers dividers;
2677 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
2678 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
2679 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
2680 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2681 u32 reference_clock = rdev->clock.spll.reference_freq;
2682 u32 reference_divider;
2686 ret = radeon_atom_get_clock_dividers(rdev,
2687 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2688 engine_clock, false, ÷rs);
2692 reference_divider = 1 + dividers.ref_div;
2693 fbdiv = dividers.fb_div & 0x3FFFFFF;
2695 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2696 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2697 spll_func_cntl_3 |= SPLL_DITHEN;
2699 if (pi->caps_sclk_ss_support) {
2700 struct radeon_atom_ss ss;
2701 u32 vco_freq = engine_clock * dividers.post_div;
2703 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2704 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2705 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2706 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2708 cg_spll_spread_spectrum &= ~CLK_S_MASK;
2709 cg_spll_spread_spectrum |= CLK_S(clk_s);
2710 cg_spll_spread_spectrum |= SSEN;
2712 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2713 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2717 sclk->SclkFrequency = engine_clock;
2718 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2719 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2720 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2721 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
2722 sclk->SclkDid = (u8)dividers.post_divider;
2727 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
2729 u16 sclk_activity_level_t,
2730 SMU7_Discrete_GraphicsLevel *graphic_level)
2732 struct ci_power_info *pi = ci_get_pi(rdev);
2735 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
2739 ret = ci_get_dependency_volt_by_clk(rdev,
2740 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2741 engine_clock, &graphic_level->MinVddc);
2745 graphic_level->SclkFrequency = engine_clock;
2747 graphic_level->Flags = 0;
2748 graphic_level->MinVddcPhases = 1;
2750 if (pi->vddc_phase_shed_control)
2751 ci_populate_phase_value_based_on_sclk(rdev,
2752 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2754 &graphic_level->MinVddcPhases);
2756 graphic_level->ActivityLevel = sclk_activity_level_t;
2758 graphic_level->CcPwrDynRm = 0;
2759 graphic_level->CcPwrDynRm1 = 0;
2760 graphic_level->EnabledForActivity = 1;
2761 graphic_level->EnabledForThrottle = 1;
2762 graphic_level->UpH = 0;
2763 graphic_level->DownH = 0;
2764 graphic_level->VoltageDownH = 0;
2765 graphic_level->PowerThrottle = 0;
2767 if (pi->caps_sclk_ds)
2768 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
2770 CISLAND_MINIMUM_ENGINE_CLOCK);
2772 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2774 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
2775 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
2776 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
2777 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
2778 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
2779 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
2780 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
2781 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
2782 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
2783 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
2784 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
2789 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
2791 struct ci_power_info *pi = ci_get_pi(rdev);
2792 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2793 u32 level_array_address = pi->dpm_table_start +
2794 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
2795 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
2796 SMU7_MAX_LEVELS_GRAPHICS;
2797 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
2800 memset(levels, 0, level_array_size);
2802 for (i = 0; i < dpm_table->sclk_table.count; i++) {
2803 ret = ci_populate_single_graphic_level(rdev,
2804 dpm_table->sclk_table.dpm_levels[i].value,
2805 (u16)pi->activity_target[i],
2806 &pi->smc_state_table.GraphicsLevel[i]);
2809 if (i == (dpm_table->sclk_table.count - 1))
2810 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
2811 PPSMC_DISPLAY_WATERMARK_HIGH;
2814 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
2815 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
2816 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2818 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2819 (u8 *)levels, level_array_size,
2827 static int ci_populate_ulv_state(struct radeon_device *rdev,
2828 SMU7_Discrete_Ulv *ulv_level)
2830 return ci_populate_ulv_level(rdev, ulv_level);
2833 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
2835 struct ci_power_info *pi = ci_get_pi(rdev);
2836 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2837 u32 level_array_address = pi->dpm_table_start +
2838 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
2839 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
2840 SMU7_MAX_LEVELS_MEMORY;
2841 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
2844 memset(levels, 0, level_array_size);
2846 for (i = 0; i < dpm_table->mclk_table.count; i++) {
2847 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
2849 ret = ci_populate_single_memory_level(rdev,
2850 dpm_table->mclk_table.dpm_levels[i].value,
2851 &pi->smc_state_table.MemoryLevel[i]);
2856 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
2858 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
2859 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
2860 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2862 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
2863 PPSMC_DISPLAY_WATERMARK_HIGH;
2865 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2866 (u8 *)levels, level_array_size,
2874 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
2875 struct ci_single_dpm_table* dpm_table,
2880 dpm_table->count = count;
2881 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
2882 dpm_table->dpm_levels[i].enabled = false;
2885 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
2886 u32 index, u32 pcie_gen, u32 pcie_lanes)
2888 dpm_table->dpm_levels[index].value = pcie_gen;
2889 dpm_table->dpm_levels[index].param1 = pcie_lanes;
2890 dpm_table->dpm_levels[index].enabled = true;
2893 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
2895 struct ci_power_info *pi = ci_get_pi(rdev);
2897 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
2900 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
2901 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
2902 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
2903 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
2904 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
2905 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
2908 ci_reset_single_dpm_table(rdev,
2909 &pi->dpm_table.pcie_speed_table,
2910 SMU7_MAX_LEVELS_LINK);
2912 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
2913 pi->pcie_gen_powersaving.min,
2914 pi->pcie_lane_powersaving.min);
2915 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
2916 pi->pcie_gen_performance.min,
2917 pi->pcie_lane_performance.min);
2918 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
2919 pi->pcie_gen_powersaving.min,
2920 pi->pcie_lane_powersaving.max);
2921 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
2922 pi->pcie_gen_performance.min,
2923 pi->pcie_lane_performance.max);
2924 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
2925 pi->pcie_gen_powersaving.max,
2926 pi->pcie_lane_powersaving.max);
2927 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
2928 pi->pcie_gen_performance.max,
2929 pi->pcie_lane_performance.max);
2931 pi->dpm_table.pcie_speed_table.count = 6;
2936 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
2938 struct ci_power_info *pi = ci_get_pi(rdev);
2939 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
2940 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2941 struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
2942 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
2943 struct radeon_cac_leakage_table *std_voltage_table =
2944 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2947 if (allowed_sclk_vddc_table == NULL)
2949 if (allowed_sclk_vddc_table->count < 1)
2951 if (allowed_mclk_table == NULL)
2953 if (allowed_mclk_table->count < 1)
2956 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
2958 ci_reset_single_dpm_table(rdev,
2959 &pi->dpm_table.sclk_table,
2960 SMU7_MAX_LEVELS_GRAPHICS);
2961 ci_reset_single_dpm_table(rdev,
2962 &pi->dpm_table.mclk_table,
2963 SMU7_MAX_LEVELS_MEMORY);
2964 ci_reset_single_dpm_table(rdev,
2965 &pi->dpm_table.vddc_table,
2966 SMU7_MAX_LEVELS_VDDC);
2967 ci_reset_single_dpm_table(rdev,
2968 &pi->dpm_table.vddci_table,
2969 SMU7_MAX_LEVELS_VDDCI);
2970 ci_reset_single_dpm_table(rdev,
2971 &pi->dpm_table.mvdd_table,
2972 SMU7_MAX_LEVELS_MVDD);
2974 pi->dpm_table.sclk_table.count = 0;
2975 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
2977 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
2978 allowed_sclk_vddc_table->entries[i].clk)) {
2979 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
2980 allowed_sclk_vddc_table->entries[i].clk;
2981 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true;
2982 pi->dpm_table.sclk_table.count++;
2986 pi->dpm_table.mclk_table.count = 0;
2987 for (i = 0; i < allowed_mclk_table->count; i++) {
2989 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
2990 allowed_mclk_table->entries[i].clk)) {
2991 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
2992 allowed_mclk_table->entries[i].clk;
2993 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true;
2994 pi->dpm_table.mclk_table.count++;
2998 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
2999 pi->dpm_table.vddc_table.dpm_levels[i].value =
3000 allowed_sclk_vddc_table->entries[i].v;
3001 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3002 std_voltage_table->entries[i].leakage;
3003 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3005 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3007 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3008 if (allowed_mclk_table) {
3009 for (i = 0; i < allowed_mclk_table->count; i++) {
3010 pi->dpm_table.vddci_table.dpm_levels[i].value =
3011 allowed_mclk_table->entries[i].v;
3012 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3014 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3017 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3018 if (allowed_mclk_table) {
3019 for (i = 0; i < allowed_mclk_table->count; i++) {
3020 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3021 allowed_mclk_table->entries[i].v;
3022 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3024 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3027 ci_setup_default_pcie_tables(rdev);
3032 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3033 u32 value, u32 *boot_level)
3038 for(i = 0; i < table->count; i++) {
3039 if (value == table->dpm_levels[i].value) {
3048 static int ci_init_smc_table(struct radeon_device *rdev)
3050 struct ci_power_info *pi = ci_get_pi(rdev);
3051 struct ci_ulv_parm *ulv = &pi->ulv;
3052 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3053 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3056 ret = ci_setup_default_dpm_tables(rdev);
3060 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3061 ci_populate_smc_voltage_tables(rdev, table);
3063 ci_init_fps_limits(rdev);
3065 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3066 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3068 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3069 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3072 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3074 if (ulv->supported) {
3075 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3078 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3081 ret = ci_populate_all_graphic_levels(rdev);
3085 ret = ci_populate_all_memory_levels(rdev);
3089 ci_populate_smc_link_level(rdev, table);
3091 ret = ci_populate_smc_acpi_level(rdev, table);
3095 ret = ci_populate_smc_vce_level(rdev, table);
3099 ret = ci_populate_smc_acp_level(rdev, table);
3103 ret = ci_populate_smc_samu_level(rdev, table);
3107 ret = ci_do_program_memory_timing_parameters(rdev);
3111 ret = ci_populate_smc_uvd_level(rdev, table);
3115 table->UvdBootLevel = 0;
3116 table->VceBootLevel = 0;
3117 table->AcpBootLevel = 0;
3118 table->SamuBootLevel = 0;
3119 table->GraphicsBootLevel = 0;
3120 table->MemoryBootLevel = 0;
3122 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3123 pi->vbios_boot_state.sclk_bootup_value,
3124 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3126 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3127 pi->vbios_boot_state.mclk_bootup_value,
3128 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3130 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3131 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3132 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3134 ci_populate_smc_initial_state(rdev, radeon_boot_state);
3136 ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3140 table->UVDInterval = 1;
3141 table->VCEInterval = 1;
3142 table->ACPInterval = 1;
3143 table->SAMUInterval = 1;
3144 table->GraphicsVoltageChangeEnable = 1;
3145 table->GraphicsThermThrottleEnable = 1;
3146 table->GraphicsInterval = 1;
3147 table->VoltageInterval = 1;
3148 table->ThermalInterval = 1;
3149 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3150 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3151 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3152 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3153 table->MemoryVoltageChangeEnable = 1;
3154 table->MemoryInterval = 1;
3155 table->VoltageResponseTime = 0;
3156 table->VddcVddciDelta = 4000;
3157 table->PhaseResponseTime = 0;
3158 table->MemoryThermThrottleEnable = 1;
3159 table->PCIeBootLinkLevel = 0;
3160 table->PCIeGenInterval = 1;
3161 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3162 table->SVI2Enable = 1;
3164 table->SVI2Enable = 0;
3166 table->ThermGpio = 17;
3167 table->SclkStepSize = 0x4000;
3169 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3170 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3171 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3172 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3173 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3174 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3175 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3176 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3177 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3178 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3179 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3180 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3181 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3182 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3184 ret = ci_copy_bytes_to_smc(rdev,
3185 pi->dpm_table_start +
3186 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3187 (u8 *)&table->SystemFlags,
3188 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3196 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3197 struct ci_single_dpm_table *dpm_table,
3198 u32 low_limit, u32 high_limit)
3202 for (i = 0; i < dpm_table->count; i++) {
3203 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3204 (dpm_table->dpm_levels[i].value > high_limit))
3205 dpm_table->dpm_levels[i].enabled = false;
3207 dpm_table->dpm_levels[i].enabled = true;
3211 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3212 u32 speed_low, u32 lanes_low,
3213 u32 speed_high, u32 lanes_high)
3215 struct ci_power_info *pi = ci_get_pi(rdev);
3216 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3219 for (i = 0; i < pcie_table->count; i++) {
3220 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3221 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3222 (pcie_table->dpm_levels[i].value > speed_high) ||
3223 (pcie_table->dpm_levels[i].param1 > lanes_high))
3224 pcie_table->dpm_levels[i].enabled = false;
3226 pcie_table->dpm_levels[i].enabled = true;
3229 for (i = 0; i < pcie_table->count; i++) {
3230 if (pcie_table->dpm_levels[i].enabled) {
3231 for (j = i + 1; j < pcie_table->count; j++) {
3232 if (pcie_table->dpm_levels[j].enabled) {
3233 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3234 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3235 pcie_table->dpm_levels[j].enabled = false;
3242 static int ci_trim_dpm_states(struct radeon_device *rdev,
3243 struct radeon_ps *radeon_state)
3245 struct ci_ps *state = ci_get_ps(radeon_state);
3246 struct ci_power_info *pi = ci_get_pi(rdev);
3247 u32 high_limit_count;
3249 if (state->performance_level_count < 1)
3252 if (state->performance_level_count == 1)
3253 high_limit_count = 0;
3255 high_limit_count = 1;
3257 ci_trim_single_dpm_states(rdev,
3258 &pi->dpm_table.sclk_table,
3259 state->performance_levels[0].sclk,
3260 state->performance_levels[high_limit_count].sclk);
3262 ci_trim_single_dpm_states(rdev,
3263 &pi->dpm_table.mclk_table,
3264 state->performance_levels[0].mclk,
3265 state->performance_levels[high_limit_count].mclk);
3267 ci_trim_pcie_dpm_states(rdev,
3268 state->performance_levels[0].pcie_gen,
3269 state->performance_levels[0].pcie_lane,
3270 state->performance_levels[high_limit_count].pcie_gen,
3271 state->performance_levels[high_limit_count].pcie_lane);
3276 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3278 struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3279 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3280 struct radeon_clock_voltage_dependency_table *vddc_table =
3281 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3282 u32 requested_voltage = 0;
3285 if (disp_voltage_table == NULL)
3287 if (!disp_voltage_table->count)
3290 for (i = 0; i < disp_voltage_table->count; i++) {
3291 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3292 requested_voltage = disp_voltage_table->entries[i].v;
3295 for (i = 0; i < vddc_table->count; i++) {
3296 if (requested_voltage <= vddc_table->entries[i].v) {
3297 requested_voltage = vddc_table->entries[i].v;
3298 return (ci_send_msg_to_smc_with_parameter(rdev,
3299 PPSMC_MSG_VddC_Request,
3300 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3308 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3310 struct ci_power_info *pi = ci_get_pi(rdev);
3311 PPSMC_Result result;
3313 if (!pi->sclk_dpm_key_disabled) {
3314 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3315 result = ci_send_msg_to_smc_with_parameter(rdev,
3316 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3317 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3318 if (result != PPSMC_Result_OK)
3323 if (!pi->mclk_dpm_key_disabled) {
3324 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3325 result = ci_send_msg_to_smc_with_parameter(rdev,
3326 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3327 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3328 if (result != PPSMC_Result_OK)
3333 if (!pi->pcie_dpm_key_disabled) {
3334 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3335 result = ci_send_msg_to_smc_with_parameter(rdev,
3336 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3337 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3338 if (result != PPSMC_Result_OK)
3343 ci_apply_disp_minimum_voltage_request(rdev);
3348 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3349 struct radeon_ps *radeon_state)
3351 struct ci_power_info *pi = ci_get_pi(rdev);
3352 struct ci_ps *state = ci_get_ps(radeon_state);
3353 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3354 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3355 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3356 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3359 pi->need_update_smu7_dpm_table = 0;
3361 for (i = 0; i < sclk_table->count; i++) {
3362 if (sclk == sclk_table->dpm_levels[i].value)
3366 if (i >= sclk_table->count) {
3367 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3369 /* XXX check display min clock requirements */
3370 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK)
3371 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3374 for (i = 0; i < mclk_table->count; i++) {
3375 if (mclk == mclk_table->dpm_levels[i].value)
3379 if (i >= mclk_table->count)
3380 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3382 if (rdev->pm.dpm.current_active_crtc_count !=
3383 rdev->pm.dpm.new_active_crtc_count)
3384 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3387 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3388 struct radeon_ps *radeon_state)
3390 struct ci_power_info *pi = ci_get_pi(rdev);
3391 struct ci_ps *state = ci_get_ps(radeon_state);
3392 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3393 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3394 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3397 if (!pi->need_update_smu7_dpm_table)
3400 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3401 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3403 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3404 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3406 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3407 ret = ci_populate_all_graphic_levels(rdev);
3412 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3413 ret = ci_populate_all_memory_levels(rdev);
3421 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3423 struct ci_power_info *pi = ci_get_pi(rdev);
3424 const struct radeon_clock_and_voltage_limits *max_limits;
3427 if (rdev->pm.dpm.ac_power)
3428 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3430 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3433 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3435 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3436 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3437 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3439 if (!pi->caps_uvd_dpm)
3444 ci_send_msg_to_smc_with_parameter(rdev,
3445 PPSMC_MSG_UVDDPM_SetEnabledMask,
3446 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3448 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3449 pi->uvd_enabled = true;
3450 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3451 ci_send_msg_to_smc_with_parameter(rdev,
3452 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3453 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3456 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3457 pi->uvd_enabled = false;
3458 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3459 ci_send_msg_to_smc_with_parameter(rdev,
3460 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3461 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3465 return (ci_send_msg_to_smc(rdev, enable ?
3466 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3471 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3473 struct ci_power_info *pi = ci_get_pi(rdev);
3474 const struct radeon_clock_and_voltage_limits *max_limits;
3477 if (rdev->pm.dpm.ac_power)
3478 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3480 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3483 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3484 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3485 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3486 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3488 if (!pi->caps_vce_dpm)
3493 ci_send_msg_to_smc_with_parameter(rdev,
3494 PPSMC_MSG_VCEDPM_SetEnabledMask,
3495 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3498 return (ci_send_msg_to_smc(rdev, enable ?
3499 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3503 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3505 struct ci_power_info *pi = ci_get_pi(rdev);
3506 const struct radeon_clock_and_voltage_limits *max_limits;
3509 if (rdev->pm.dpm.ac_power)
3510 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3512 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3515 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3516 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3517 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3518 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3520 if (!pi->caps_samu_dpm)
3525 ci_send_msg_to_smc_with_parameter(rdev,
3526 PPSMC_MSG_SAMUDPM_SetEnabledMask,
3527 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
3529 return (ci_send_msg_to_smc(rdev, enable ?
3530 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
3534 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
3536 struct ci_power_info *pi = ci_get_pi(rdev);
3537 const struct radeon_clock_and_voltage_limits *max_limits;
3540 if (rdev->pm.dpm.ac_power)
3541 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3543 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3546 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
3547 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3548 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3549 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
3551 if (!pi->caps_acp_dpm)
3556 ci_send_msg_to_smc_with_parameter(rdev,
3557 PPSMC_MSG_ACPDPM_SetEnabledMask,
3558 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
3561 return (ci_send_msg_to_smc(rdev, enable ?
3562 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
3567 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
3569 struct ci_power_info *pi = ci_get_pi(rdev);
3573 if (pi->caps_uvd_dpm ||
3574 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
3575 pi->smc_state_table.UvdBootLevel = 0;
3577 pi->smc_state_table.UvdBootLevel =
3578 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
3580 tmp = RREG32_SMC(DPM_TABLE_475);
3581 tmp &= ~UvdBootLevel_MASK;
3582 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
3583 WREG32_SMC(DPM_TABLE_475, tmp);
3586 return ci_enable_uvd_dpm(rdev, !gate);
3590 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
3593 u32 min_evclk = 30000; /* ??? */
3594 struct radeon_vce_clock_voltage_dependency_table *table =
3595 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3597 for (i = 0; i < table->count; i++) {
3598 if (table->entries[i].evclk >= min_evclk)
3602 return table->count - 1;
3605 static int ci_update_vce_dpm(struct radeon_device *rdev,
3606 struct radeon_ps *radeon_new_state,
3607 struct radeon_ps *radeon_current_state)
3609 struct ci_power_info *pi = ci_get_pi(rdev);
3610 bool new_vce_clock_non_zero = (radeon_new_state->evclk != 0);
3611 bool old_vce_clock_non_zero = (radeon_current_state->evclk != 0);
3615 if (new_vce_clock_non_zero != old_vce_clock_non_zero) {
3616 if (new_vce_clock_non_zero) {
3617 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
3619 tmp = RREG32_SMC(DPM_TABLE_475);
3620 tmp &= ~VceBootLevel_MASK;
3621 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
3622 WREG32_SMC(DPM_TABLE_475, tmp);
3624 ret = ci_enable_vce_dpm(rdev, true);
3626 ret = ci_enable_vce_dpm(rdev, false);
3632 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
3634 return ci_enable_samu_dpm(rdev, gate);
3637 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
3639 struct ci_power_info *pi = ci_get_pi(rdev);
3643 pi->smc_state_table.AcpBootLevel = 0;
3645 tmp = RREG32_SMC(DPM_TABLE_475);
3646 tmp &= ~AcpBootLevel_MASK;
3647 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
3648 WREG32_SMC(DPM_TABLE_475, tmp);
3651 return ci_enable_acp_dpm(rdev, !gate);
3655 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
3656 struct radeon_ps *radeon_state)
3658 struct ci_power_info *pi = ci_get_pi(rdev);
3661 ret = ci_trim_dpm_states(rdev, radeon_state);
3665 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3666 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
3667 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3668 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
3669 pi->last_mclk_dpm_enable_mask =
3670 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3671 if (pi->uvd_enabled) {
3672 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
3673 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3675 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
3676 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
3681 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
3686 while ((level_mask & (1 << level)) == 0)
3693 int ci_dpm_force_performance_level(struct radeon_device *rdev,
3694 enum radeon_dpm_forced_level level)
3696 struct ci_power_info *pi = ci_get_pi(rdev);
3697 PPSMC_Result smc_result;
3701 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3702 if ((!pi->sclk_dpm_key_disabled) &&
3703 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3705 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
3709 ret = ci_dpm_force_state_sclk(rdev, levels);
3712 for (i = 0; i < rdev->usec_timeout; i++) {
3713 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3714 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3721 if ((!pi->mclk_dpm_key_disabled) &&
3722 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3724 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3728 ret = ci_dpm_force_state_mclk(rdev, levels);
3731 for (i = 0; i < rdev->usec_timeout; i++) {
3732 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3733 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3740 if ((!pi->pcie_dpm_key_disabled) &&
3741 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3743 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
3747 ret = ci_dpm_force_state_pcie(rdev, level);
3750 for (i = 0; i < rdev->usec_timeout; i++) {
3751 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3752 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3759 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3760 if ((!pi->sclk_dpm_key_disabled) &&
3761 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3762 levels = ci_get_lowest_enabled_level(rdev,
3763 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3764 ret = ci_dpm_force_state_sclk(rdev, levels);
3767 for (i = 0; i < rdev->usec_timeout; i++) {
3768 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3769 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3775 if ((!pi->mclk_dpm_key_disabled) &&
3776 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3777 levels = ci_get_lowest_enabled_level(rdev,
3778 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3779 ret = ci_dpm_force_state_mclk(rdev, levels);
3782 for (i = 0; i < rdev->usec_timeout; i++) {
3783 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3784 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3790 if ((!pi->pcie_dpm_key_disabled) &&
3791 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3792 levels = ci_get_lowest_enabled_level(rdev,
3793 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3794 ret = ci_dpm_force_state_pcie(rdev, levels);
3797 for (i = 0; i < rdev->usec_timeout; i++) {
3798 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3799 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3805 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3806 if (!pi->sclk_dpm_key_disabled) {
3807 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel);
3808 if (smc_result != PPSMC_Result_OK)
3811 if (!pi->mclk_dpm_key_disabled) {
3812 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_NoForcedLevel);
3813 if (smc_result != PPSMC_Result_OK)
3816 if (!pi->pcie_dpm_key_disabled) {
3817 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_UnForceLevel);
3818 if (smc_result != PPSMC_Result_OK)
3823 rdev->pm.dpm.forced_level = level;
3828 static int ci_set_mc_special_registers(struct radeon_device *rdev,
3829 struct ci_mc_reg_table *table)
3831 struct ci_power_info *pi = ci_get_pi(rdev);
3835 for (i = 0, j = table->last; i < table->last; i++) {
3836 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3838 switch(table->mc_reg_address[i].s1 << 2) {
3840 temp_reg = RREG32(MC_PMG_CMD_EMRS);
3841 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
3842 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3843 for (k = 0; k < table->num_entries; k++) {
3844 table->mc_reg_table_entry[k].mc_data[j] =
3845 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3848 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3851 temp_reg = RREG32(MC_PMG_CMD_MRS);
3852 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
3853 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3854 for (k = 0; k < table->num_entries; k++) {
3855 table->mc_reg_table_entry[k].mc_data[j] =
3856 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3858 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3861 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3864 if (!pi->mem_gddr5) {
3865 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
3866 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
3867 for (k = 0; k < table->num_entries; k++) {
3868 table->mc_reg_table_entry[k].mc_data[j] =
3869 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3872 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3876 case MC_SEQ_RESERVE_M:
3877 temp_reg = RREG32(MC_PMG_CMD_MRS1);
3878 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
3879 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3880 for (k = 0; k < table->num_entries; k++) {
3881 table->mc_reg_table_entry[k].mc_data[j] =
3882 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3885 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3899 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
3904 case MC_SEQ_RAS_TIMING >> 2:
3905 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
3907 case MC_SEQ_DLL_STBY >> 2:
3908 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
3910 case MC_SEQ_G5PDX_CMD0 >> 2:
3911 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
3913 case MC_SEQ_G5PDX_CMD1 >> 2:
3914 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
3916 case MC_SEQ_G5PDX_CTRL >> 2:
3917 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
3919 case MC_SEQ_CAS_TIMING >> 2:
3920 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
3922 case MC_SEQ_MISC_TIMING >> 2:
3923 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
3925 case MC_SEQ_MISC_TIMING2 >> 2:
3926 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
3928 case MC_SEQ_PMG_DVS_CMD >> 2:
3929 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
3931 case MC_SEQ_PMG_DVS_CTL >> 2:
3932 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
3934 case MC_SEQ_RD_CTL_D0 >> 2:
3935 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
3937 case MC_SEQ_RD_CTL_D1 >> 2:
3938 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
3940 case MC_SEQ_WR_CTL_D0 >> 2:
3941 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
3943 case MC_SEQ_WR_CTL_D1 >> 2:
3944 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
3946 case MC_PMG_CMD_EMRS >> 2:
3947 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3949 case MC_PMG_CMD_MRS >> 2:
3950 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3952 case MC_PMG_CMD_MRS1 >> 2:
3953 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3955 case MC_SEQ_PMG_TIMING >> 2:
3956 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
3958 case MC_PMG_CMD_MRS2 >> 2:
3959 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
3961 case MC_SEQ_WR_CTL_2 >> 2:
3962 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
3972 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
3976 for (i = 0; i < table->last; i++) {
3977 for (j = 1; j < table->num_entries; j++) {
3978 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
3979 table->mc_reg_table_entry[j].mc_data[i]) {
3980 table->valid_flag |= 1 << i;
3987 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
3992 for (i = 0; i < table->last; i++) {
3993 table->mc_reg_address[i].s0 =
3994 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
3995 address : table->mc_reg_address[i].s1;
3999 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4000 struct ci_mc_reg_table *ci_table)
4004 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4006 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4009 for (i = 0; i < table->last; i++)
4010 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4012 ci_table->last = table->last;
4014 for (i = 0; i < table->num_entries; i++) {
4015 ci_table->mc_reg_table_entry[i].mclk_max =
4016 table->mc_reg_table_entry[i].mclk_max;
4017 for (j = 0; j < table->last; j++)
4018 ci_table->mc_reg_table_entry[i].mc_data[j] =
4019 table->mc_reg_table_entry[i].mc_data[j];
4021 ci_table->num_entries = table->num_entries;
4026 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4028 struct ci_power_info *pi = ci_get_pi(rdev);
4029 struct atom_mc_reg_table *table;
4030 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4031 u8 module_index = rv770_get_memory_module_index(rdev);
4034 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4038 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4039 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4040 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4041 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4042 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4043 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4044 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4045 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4046 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4047 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4048 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4049 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4050 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4051 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4052 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4053 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4054 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4055 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4056 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4057 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4059 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4063 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4067 ci_set_s0_mc_reg_index(ci_table);
4069 ret = ci_set_mc_special_registers(rdev, ci_table);
4073 ci_set_valid_flag(ci_table);
4081 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4082 SMU7_Discrete_MCRegisters *mc_reg_table)
4084 struct ci_power_info *pi = ci_get_pi(rdev);
4087 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4088 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4089 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4091 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4092 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4097 mc_reg_table->last = (u8)i;
4102 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4103 SMU7_Discrete_MCRegisterSet *data,
4104 u32 num_entries, u32 valid_flag)
4108 for (i = 0, j = 0; j < num_entries; j++) {
4109 if (valid_flag & (1 << j)) {
4110 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4116 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4117 const u32 memory_clock,
4118 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4120 struct ci_power_info *pi = ci_get_pi(rdev);
4123 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4124 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4128 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4131 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4132 mc_reg_table_data, pi->mc_reg_table.last,
4133 pi->mc_reg_table.valid_flag);
4136 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4137 SMU7_Discrete_MCRegisters *mc_reg_table)
4139 struct ci_power_info *pi = ci_get_pi(rdev);
4142 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4143 ci_convert_mc_reg_table_entry_to_smc(rdev,
4144 pi->dpm_table.mclk_table.dpm_levels[i].value,
4145 &mc_reg_table->data[i]);
4148 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4150 struct ci_power_info *pi = ci_get_pi(rdev);
4153 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4155 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4158 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4160 return ci_copy_bytes_to_smc(rdev,
4161 pi->mc_reg_table_start,
4162 (u8 *)&pi->smc_mc_reg_table,
4163 sizeof(SMU7_Discrete_MCRegisters),
4167 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4169 struct ci_power_info *pi = ci_get_pi(rdev);
4171 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4174 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4176 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4178 return ci_copy_bytes_to_smc(rdev,
4179 pi->mc_reg_table_start +
4180 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4181 (u8 *)&pi->smc_mc_reg_table.data[0],
4182 sizeof(SMU7_Discrete_MCRegisterSet) *
4183 pi->dpm_table.mclk_table.count,
4187 static void ci_enable_voltage_control(struct radeon_device *rdev)
4189 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4191 tmp |= VOLT_PWRMGT_EN;
4192 WREG32_SMC(GENERAL_PWRMGT, tmp);
4195 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4196 struct radeon_ps *radeon_state)
4198 struct ci_ps *state = ci_get_ps(radeon_state);
4200 u16 pcie_speed, max_speed = 0;
4202 for (i = 0; i < state->performance_level_count; i++) {
4203 pcie_speed = state->performance_levels[i].pcie_gen;
4204 if (max_speed < pcie_speed)
4205 max_speed = pcie_speed;
4211 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4215 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4216 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4218 return (u16)speed_cntl;
4221 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4225 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4226 link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4228 switch (link_width) {
4229 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4231 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4233 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4235 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4237 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4238 /* not actually supported */
4240 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4241 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4247 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4248 struct radeon_ps *radeon_new_state,
4249 struct radeon_ps *radeon_current_state)
4251 struct ci_power_info *pi = ci_get_pi(rdev);
4252 enum radeon_pcie_gen target_link_speed =
4253 ci_get_maximum_link_speed(rdev, radeon_new_state);
4254 enum radeon_pcie_gen current_link_speed;
4256 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4257 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4259 current_link_speed = pi->force_pcie_gen;
4261 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4262 pi->pspp_notify_required = false;
4263 if (target_link_speed > current_link_speed) {
4264 switch (target_link_speed) {
4266 case RADEON_PCIE_GEN3:
4267 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4269 pi->force_pcie_gen = RADEON_PCIE_GEN2;
4270 if (current_link_speed == RADEON_PCIE_GEN2)
4272 case RADEON_PCIE_GEN2:
4273 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4277 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4281 if (target_link_speed < current_link_speed)
4282 pi->pspp_notify_required = true;
4286 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4287 struct radeon_ps *radeon_new_state,
4288 struct radeon_ps *radeon_current_state)
4290 struct ci_power_info *pi = ci_get_pi(rdev);
4291 enum radeon_pcie_gen target_link_speed =
4292 ci_get_maximum_link_speed(rdev, radeon_new_state);
4295 if (pi->pspp_notify_required) {
4296 if (target_link_speed == RADEON_PCIE_GEN3)
4297 request = PCIE_PERF_REQ_PECI_GEN3;
4298 else if (target_link_speed == RADEON_PCIE_GEN2)
4299 request = PCIE_PERF_REQ_PECI_GEN2;
4301 request = PCIE_PERF_REQ_PECI_GEN1;
4303 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4304 (ci_get_current_pcie_speed(rdev) > 0))
4308 radeon_acpi_pcie_performance_request(rdev, request, false);
4313 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4315 struct ci_power_info *pi = ci_get_pi(rdev);
4316 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4317 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4318 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4319 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4320 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4321 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4323 if (allowed_sclk_vddc_table == NULL)
4325 if (allowed_sclk_vddc_table->count < 1)
4327 if (allowed_mclk_vddc_table == NULL)
4329 if (allowed_mclk_vddc_table->count < 1)
4331 if (allowed_mclk_vddci_table == NULL)
4333 if (allowed_mclk_vddci_table->count < 1)
4336 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4337 pi->max_vddc_in_pp_table =
4338 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4340 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4341 pi->max_vddci_in_pp_table =
4342 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4344 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4345 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4346 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4347 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4348 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4349 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4350 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4351 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4356 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4358 struct ci_power_info *pi = ci_get_pi(rdev);
4359 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4362 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4363 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4364 *vddc = leakage_table->actual_voltage[leakage_index];
4370 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4372 struct ci_power_info *pi = ci_get_pi(rdev);
4373 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4376 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4377 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4378 *vddci = leakage_table->actual_voltage[leakage_index];
4384 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4385 struct radeon_clock_voltage_dependency_table *table)
4390 for (i = 0; i < table->count; i++)
4391 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4395 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4396 struct radeon_clock_voltage_dependency_table *table)
4401 for (i = 0; i < table->count; i++)
4402 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4406 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4407 struct radeon_vce_clock_voltage_dependency_table *table)
4412 for (i = 0; i < table->count; i++)
4413 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4417 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4418 struct radeon_uvd_clock_voltage_dependency_table *table)
4423 for (i = 0; i < table->count; i++)
4424 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4428 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
4429 struct radeon_phase_shedding_limits_table *table)
4434 for (i = 0; i < table->count; i++)
4435 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
4439 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
4440 struct radeon_clock_and_voltage_limits *table)
4443 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
4444 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
4448 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
4449 struct radeon_cac_leakage_table *table)
4454 for (i = 0; i < table->count; i++)
4455 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
4459 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
4462 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4463 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
4464 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4465 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
4466 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4467 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
4468 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
4469 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
4470 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4471 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
4472 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4473 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
4474 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4475 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
4476 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4477 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
4478 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
4479 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
4480 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4481 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
4482 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4483 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
4484 ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
4485 &rdev->pm.dpm.dyn_state.cac_leakage_table);
4489 static void ci_get_memory_type(struct radeon_device *rdev)
4491 struct ci_power_info *pi = ci_get_pi(rdev);
4494 tmp = RREG32(MC_SEQ_MISC0);
4496 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
4497 MC_SEQ_MISC0_GDDR5_VALUE)
4498 pi->mem_gddr5 = true;
4500 pi->mem_gddr5 = false;
4504 void ci_update_current_ps(struct radeon_device *rdev,
4505 struct radeon_ps *rps)
4507 struct ci_ps *new_ps = ci_get_ps(rps);
4508 struct ci_power_info *pi = ci_get_pi(rdev);
4510 pi->current_rps = *rps;
4511 pi->current_ps = *new_ps;
4512 pi->current_rps.ps_priv = &pi->current_ps;
4515 void ci_update_requested_ps(struct radeon_device *rdev,
4516 struct radeon_ps *rps)
4518 struct ci_ps *new_ps = ci_get_ps(rps);
4519 struct ci_power_info *pi = ci_get_pi(rdev);
4521 pi->requested_rps = *rps;
4522 pi->requested_ps = *new_ps;
4523 pi->requested_rps.ps_priv = &pi->requested_ps;
4526 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
4528 struct ci_power_info *pi = ci_get_pi(rdev);
4529 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
4530 struct radeon_ps *new_ps = &requested_ps;
4532 ci_update_requested_ps(rdev, new_ps);
4534 ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
4539 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
4541 struct ci_power_info *pi = ci_get_pi(rdev);
4542 struct radeon_ps *new_ps = &pi->requested_rps;
4544 ci_update_current_ps(rdev, new_ps);
4548 void ci_dpm_setup_asic(struct radeon_device *rdev)
4550 ci_read_clock_registers(rdev);
4551 ci_get_memory_type(rdev);
4552 ci_enable_acpi_power_management(rdev);
4553 ci_init_sclk_t(rdev);
4556 int ci_dpm_enable(struct radeon_device *rdev)
4558 struct ci_power_info *pi = ci_get_pi(rdev);
4559 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4562 if (ci_is_smc_running(rdev))
4564 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
4565 ci_enable_voltage_control(rdev);
4566 ret = ci_construct_voltage_tables(rdev);
4568 DRM_ERROR("ci_construct_voltage_tables failed\n");
4572 if (pi->caps_dynamic_ac_timing) {
4573 ret = ci_initialize_mc_reg_table(rdev);
4575 pi->caps_dynamic_ac_timing = false;
4578 ci_enable_spread_spectrum(rdev, true);
4579 if (pi->thermal_protection)
4580 ci_enable_thermal_protection(rdev, true);
4581 ci_program_sstp(rdev);
4582 ci_enable_display_gap(rdev);
4583 ci_program_vc(rdev);
4584 ret = ci_upload_firmware(rdev);
4586 DRM_ERROR("ci_upload_firmware failed\n");
4589 ret = ci_process_firmware_header(rdev);
4591 DRM_ERROR("ci_process_firmware_header failed\n");
4594 ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
4596 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
4599 ret = ci_init_smc_table(rdev);
4601 DRM_ERROR("ci_init_smc_table failed\n");
4604 ret = ci_init_arb_table_index(rdev);
4606 DRM_ERROR("ci_init_arb_table_index failed\n");
4609 if (pi->caps_dynamic_ac_timing) {
4610 ret = ci_populate_initial_mc_reg_table(rdev);
4612 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
4616 ret = ci_populate_pm_base(rdev);
4618 DRM_ERROR("ci_populate_pm_base failed\n");
4621 ci_dpm_start_smc(rdev);
4622 ci_enable_vr_hot_gpio_interrupt(rdev);
4623 ret = ci_notify_smc_display_change(rdev, false);
4625 DRM_ERROR("ci_notify_smc_display_change failed\n");
4628 ci_enable_sclk_control(rdev, true);
4629 ret = ci_enable_ulv(rdev, true);
4631 DRM_ERROR("ci_enable_ulv failed\n");
4634 ret = ci_enable_ds_master_switch(rdev, true);
4636 DRM_ERROR("ci_enable_ds_master_switch failed\n");
4639 ret = ci_start_dpm(rdev);
4641 DRM_ERROR("ci_start_dpm failed\n");
4644 ret = ci_enable_didt(rdev, true);
4646 DRM_ERROR("ci_enable_didt failed\n");
4649 ret = ci_enable_smc_cac(rdev, true);
4651 DRM_ERROR("ci_enable_smc_cac failed\n");
4654 ret = ci_enable_power_containment(rdev, true);
4656 DRM_ERROR("ci_enable_power_containment failed\n");
4659 if (rdev->irq.installed &&
4660 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
4662 PPSMC_Result result;
4664 ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
4666 DRM_ERROR("ci_set_thermal_temperature_range failed\n");
4669 rdev->irq.dpm_thermal = true;
4670 radeon_irq_set(rdev);
4672 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
4674 if (result != PPSMC_Result_OK)
4675 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
4679 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
4681 ci_dpm_powergate_uvd(rdev, true);
4683 ci_update_current_ps(rdev, boot_ps);
4688 int ci_dpm_late_enable(struct radeon_device *rdev)
4692 if (rdev->irq.installed &&
4693 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
4695 PPSMC_Result result;
4697 ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
4699 DRM_ERROR("ci_set_thermal_temperature_range failed\n");
4702 rdev->irq.dpm_thermal = true;
4703 radeon_irq_set(rdev);
4705 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
4707 if (result != PPSMC_Result_OK)
4708 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
4712 ci_dpm_powergate_uvd(rdev, true);
4717 void ci_dpm_disable(struct radeon_device *rdev)
4719 struct ci_power_info *pi = ci_get_pi(rdev);
4720 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4722 ci_dpm_powergate_uvd(rdev, false);
4724 if (!ci_is_smc_running(rdev))
4727 if (pi->thermal_protection)
4728 ci_enable_thermal_protection(rdev, false);
4729 ci_enable_power_containment(rdev, false);
4730 ci_enable_smc_cac(rdev, false);
4731 ci_enable_didt(rdev, false);
4732 ci_enable_spread_spectrum(rdev, false);
4733 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
4735 ci_enable_ds_master_switch(rdev, true);
4736 ci_enable_ulv(rdev, false);
4738 ci_reset_to_default(rdev);
4739 ci_dpm_stop_smc(rdev);
4740 ci_force_switch_to_arb_f0(rdev);
4742 ci_update_current_ps(rdev, boot_ps);
4745 int ci_dpm_set_power_state(struct radeon_device *rdev)
4747 struct ci_power_info *pi = ci_get_pi(rdev);
4748 struct radeon_ps *new_ps = &pi->requested_rps;
4749 struct radeon_ps *old_ps = &pi->current_rps;
4752 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
4753 if (pi->pcie_performance_request)
4754 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
4755 ret = ci_freeze_sclk_mclk_dpm(rdev);
4757 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
4760 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
4762 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
4765 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
4767 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
4771 ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
4773 DRM_ERROR("ci_update_vce_dpm failed\n");
4777 ret = ci_update_sclk_t(rdev);
4779 DRM_ERROR("ci_update_sclk_t failed\n");
4782 if (pi->caps_dynamic_ac_timing) {
4783 ret = ci_update_and_upload_mc_reg_table(rdev);
4785 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
4789 ret = ci_program_memory_timing_parameters(rdev);
4791 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
4794 ret = ci_unfreeze_sclk_mclk_dpm(rdev);
4796 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
4799 ret = ci_upload_dpm_level_enable_mask(rdev);
4801 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
4804 if (pi->pcie_performance_request)
4805 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
4810 int ci_dpm_power_control_set_level(struct radeon_device *rdev)
4812 return ci_power_control_set_level(rdev);
4815 void ci_dpm_reset_asic(struct radeon_device *rdev)
4817 ci_set_boot_state(rdev);
4820 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
4822 ci_program_display_gap(rdev);
4826 struct _ATOM_POWERPLAY_INFO info;
4827 struct _ATOM_POWERPLAY_INFO_V2 info_2;
4828 struct _ATOM_POWERPLAY_INFO_V3 info_3;
4829 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
4830 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
4831 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
4834 union pplib_clock_info {
4835 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
4836 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
4837 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
4838 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
4839 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
4840 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
4843 union pplib_power_state {
4844 struct _ATOM_PPLIB_STATE v1;
4845 struct _ATOM_PPLIB_STATE_V2 v2;
4848 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
4849 struct radeon_ps *rps,
4850 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
4853 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
4854 rps->class = le16_to_cpu(non_clock_info->usClassification);
4855 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
4857 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
4858 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
4859 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
4865 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
4866 rdev->pm.dpm.boot_ps = rps;
4867 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
4868 rdev->pm.dpm.uvd_ps = rps;
4871 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
4872 struct radeon_ps *rps, int index,
4873 union pplib_clock_info *clock_info)
4875 struct ci_power_info *pi = ci_get_pi(rdev);
4876 struct ci_ps *ps = ci_get_ps(rps);
4877 struct ci_pl *pl = &ps->performance_levels[index];
4879 ps->performance_level_count = index + 1;
4881 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
4882 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
4883 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
4884 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
4886 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
4888 pi->vbios_boot_state.pcie_gen_bootup_value,
4889 clock_info->ci.ucPCIEGen);
4890 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
4891 pi->vbios_boot_state.pcie_lane_bootup_value,
4892 le16_to_cpu(clock_info->ci.usPCIELane));
4894 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
4895 pi->acpi_pcie_gen = pl->pcie_gen;
4898 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
4899 pi->ulv.supported = true;
4901 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
4904 /* patch up boot state */
4905 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
4906 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
4907 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
4908 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
4909 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
4912 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
4913 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
4914 pi->use_pcie_powersaving_levels = true;
4915 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
4916 pi->pcie_gen_powersaving.max = pl->pcie_gen;
4917 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
4918 pi->pcie_gen_powersaving.min = pl->pcie_gen;
4919 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
4920 pi->pcie_lane_powersaving.max = pl->pcie_lane;
4921 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
4922 pi->pcie_lane_powersaving.min = pl->pcie_lane;
4924 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
4925 pi->use_pcie_performance_levels = true;
4926 if (pi->pcie_gen_performance.max < pl->pcie_gen)
4927 pi->pcie_gen_performance.max = pl->pcie_gen;
4928 if (pi->pcie_gen_performance.min > pl->pcie_gen)
4929 pi->pcie_gen_performance.min = pl->pcie_gen;
4930 if (pi->pcie_lane_performance.max < pl->pcie_lane)
4931 pi->pcie_lane_performance.max = pl->pcie_lane;
4932 if (pi->pcie_lane_performance.min > pl->pcie_lane)
4933 pi->pcie_lane_performance.min = pl->pcie_lane;
4940 static int ci_parse_power_table(struct radeon_device *rdev)
4942 struct radeon_mode_info *mode_info = &rdev->mode_info;
4943 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
4944 union pplib_power_state *power_state;
4945 int i, j, k, non_clock_array_index, clock_array_index;
4946 union pplib_clock_info *clock_info;
4947 struct _StateArray *state_array;
4948 struct _ClockInfoArray *clock_info_array;
4949 struct _NonClockInfoArray *non_clock_info_array;
4950 union power_info *power_info;
4951 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
4954 u8 *power_state_offset;
4957 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
4958 &frev, &crev, &data_offset))
4960 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
4962 state_array = (struct _StateArray *)
4963 (mode_info->atom_context->bios + data_offset +
4964 le16_to_cpu(power_info->pplib.usStateArrayOffset));
4965 clock_info_array = (struct _ClockInfoArray *)
4966 (mode_info->atom_context->bios + data_offset +
4967 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
4968 non_clock_info_array = (struct _NonClockInfoArray *)
4969 (mode_info->atom_context->bios + data_offset +
4970 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
4972 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
4973 state_array->ucNumEntries, GFP_KERNEL);
4974 if (!rdev->pm.dpm.ps)
4976 power_state_offset = (u8 *)state_array->states;
4977 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
4978 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
4979 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
4980 for (i = 0; i < state_array->ucNumEntries; i++) {
4982 power_state = (union pplib_power_state *)power_state_offset;
4983 non_clock_array_index = power_state->v2.nonClockInfoIndex;
4984 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
4985 &non_clock_info_array->nonClockInfo[non_clock_array_index];
4986 if (!rdev->pm.power_state[i].clock_info)
4988 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
4990 kfree(rdev->pm.dpm.ps);
4993 rdev->pm.dpm.ps[i].ps_priv = ps;
4994 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
4996 non_clock_info_array->ucEntrySize);
4998 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
4999 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5000 clock_array_index = idx[j];
5001 if (clock_array_index >= clock_info_array->ucNumEntries)
5003 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5005 clock_info = (union pplib_clock_info *)
5006 ((u8 *)&clock_info_array->clockInfo[0] +
5007 (clock_array_index * clock_info_array->ucEntrySize));
5008 ci_parse_pplib_clock_info(rdev,
5009 &rdev->pm.dpm.ps[i], k,
5013 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5015 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5019 int ci_get_vbios_boot_values(struct radeon_device *rdev,
5020 struct ci_vbios_boot_state *boot_state)
5022 struct radeon_mode_info *mode_info = &rdev->mode_info;
5023 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5024 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5028 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5029 &frev, &crev, &data_offset)) {
5031 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5033 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5034 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5035 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5036 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5037 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5038 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5039 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5046 void ci_dpm_fini(struct radeon_device *rdev)
5050 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5051 kfree(rdev->pm.dpm.ps[i].ps_priv);
5053 kfree(rdev->pm.dpm.ps);
5054 kfree(rdev->pm.dpm.priv);
5055 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5056 r600_free_extended_power_table(rdev);
5059 int ci_dpm_init(struct radeon_device *rdev)
5061 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5062 u16 data_offset, size;
5064 struct ci_power_info *pi;
5068 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5071 rdev->pm.dpm.priv = pi;
5073 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5075 pi->sys_pcie_mask = 0;
5077 pi->sys_pcie_mask = mask;
5078 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5080 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5081 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5082 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5083 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5085 pi->pcie_lane_performance.max = 0;
5086 pi->pcie_lane_performance.min = 16;
5087 pi->pcie_lane_powersaving.max = 0;
5088 pi->pcie_lane_powersaving.min = 16;
5090 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5095 ret = ci_parse_power_table(rdev);
5100 ret = r600_parse_extended_power_table(rdev);
5106 pi->dll_default_on = false;
5107 pi->sram_end = SMC_RAM_END;
5109 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5110 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5111 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5112 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5113 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5114 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5115 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5116 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5118 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5120 pi->sclk_dpm_key_disabled = 0;
5121 pi->mclk_dpm_key_disabled = 0;
5122 pi->pcie_dpm_key_disabled = 0;
5124 pi->caps_sclk_ds = true;
5126 pi->mclk_strobe_mode_threshold = 40000;
5127 pi->mclk_stutter_mode_threshold = 40000;
5128 pi->mclk_edc_enable_threshold = 40000;
5129 pi->mclk_edc_wr_enable_threshold = 40000;
5131 ci_initialize_powertune_defaults(rdev);
5133 pi->caps_fps = false;
5135 pi->caps_sclk_throttle_low_notification = false;
5137 pi->caps_uvd_dpm = true;
5139 ci_get_leakage_voltages(rdev);
5140 ci_patch_dependency_tables_with_leakage(rdev);
5141 ci_set_private_data_variables_based_on_pptable(rdev);
5143 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5144 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5145 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5149 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5150 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5151 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5152 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5153 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5154 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5155 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5156 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5157 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5159 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5160 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5161 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5163 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5164 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5165 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5166 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5168 if (rdev->family == CHIP_HAWAII) {
5169 pi->thermal_temp_setting.temperature_low = 94500;
5170 pi->thermal_temp_setting.temperature_high = 95000;
5171 pi->thermal_temp_setting.temperature_shutdown = 104000;
5173 pi->thermal_temp_setting.temperature_low = 99500;
5174 pi->thermal_temp_setting.temperature_high = 100000;
5175 pi->thermal_temp_setting.temperature_shutdown = 104000;
5178 pi->uvd_enabled = false;
5180 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5181 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5182 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5183 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5184 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5185 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5186 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5188 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5189 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5190 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5191 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5192 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5194 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5197 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5198 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5199 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5200 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5201 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5203 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5206 pi->vddc_phase_shed_control = true;
5208 #if defined(CONFIG_ACPI)
5209 pi->pcie_performance_request =
5210 radeon_acpi_is_pcie_performance_request_supported(rdev);
5212 pi->pcie_performance_request = false;
5215 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5216 &frev, &crev, &data_offset)) {
5217 pi->caps_sclk_ss_support = true;
5218 pi->caps_mclk_ss_support = true;
5219 pi->dynamic_ss = true;
5221 pi->caps_sclk_ss_support = false;
5222 pi->caps_mclk_ss_support = false;
5223 pi->dynamic_ss = true;
5226 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5227 pi->thermal_protection = true;
5229 pi->thermal_protection = false;
5231 pi->caps_dynamic_ac_timing = true;
5233 pi->uvd_power_gated = false;
5235 /* make sure dc limits are valid */
5236 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5237 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5238 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5239 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5244 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5247 u32 sclk = ci_get_average_sclk_freq(rdev);
5248 u32 mclk = ci_get_average_mclk_freq(rdev);
5250 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
5254 void ci_dpm_print_power_state(struct radeon_device *rdev,
5255 struct radeon_ps *rps)
5257 struct ci_ps *ps = ci_get_ps(rps);
5261 r600_dpm_print_class_info(rps->class, rps->class2);
5262 r600_dpm_print_cap_info(rps->caps);
5263 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5264 for (i = 0; i < ps->performance_level_count; i++) {
5265 pl = &ps->performance_levels[i];
5266 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5267 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5269 r600_dpm_print_ps_status(rdev, rps);
5272 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5274 struct ci_power_info *pi = ci_get_pi(rdev);
5275 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5278 return requested_state->performance_levels[0].sclk;
5280 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5283 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5285 struct ci_power_info *pi = ci_get_pi(rdev);
5286 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5289 return requested_state->performance_levels[0].mclk;
5291 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;