drivers/gpu/drm/radeon/ci_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "cikd.h"
  27 #include "r600_dpm.h"
  28 #include "ci_dpm.h"
  29 #include "atom.h"
  30 #include <linux/seq_file.h>
  31
  32 #define MC_CG_ARB_FREQ_F0           0x0a
  33 #define MC_CG_ARB_FREQ_F1           0x0b
  34 #define MC_CG_ARB_FREQ_F2           0x0c
  35 #define MC_CG_ARB_FREQ_F3           0x0d
  36
  37 #define SMC_RAM_END 0x40000
  38
  39 #define VOLTAGE_SCALE               4
  40 #define VOLTAGE_VID_OFFSET_SCALE1    625
  41 #define VOLTAGE_VID_OFFSET_SCALE2    100
  42
  43 static const struct ci_pt_defaults defaults_hawaii_xt =
  44 {
  45         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
  46         { 0x84,  0x0,   0x0,   0x7F,  0x0,   0x0,   0x5A,  0x60,  0x51,  0x8E,  0x79,  0x6B,  0x5F,  0x90,  0x79  },
  47         { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
  48 };
  49
  50 static const struct ci_pt_defaults defaults_hawaii_pro =
  51 {
  52         1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
  53         { 0x93,  0x0,   0x0,   0x97,  0x0,   0x0,   0x6B,  0x60,  0x51,  0x95,  0x79,  0x6B,  0x5F,  0x90,  0x79  },
  54         { 0x1EA, 0x1EA, 0x1EA, 0x224, 0x224, 0x224, 0x24F, 0x24F, 0x24F, 0x28E, 0x28E, 0x28E, 0x2BC, 0x2BC, 0x2BC }
  55 };
  56
  57 static const struct ci_pt_defaults defaults_bonaire_xt =
  58 {
  59         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  60         { 0x79,  0x253, 0x25D, 0xAE,  0x72,  0x80,  0x83,  0x86,  0x6F,  0xC8,  0xC9,  0xC9,  0x2F,  0x4D,  0x61  },
  61         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
  62 };
  63
  64 static const struct ci_pt_defaults defaults_bonaire_pro =
  65 {
  66         1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
  67         { 0x8C,  0x23F, 0x244, 0xA6,  0x83,  0x85,  0x86,  0x86,  0x83,  0xDB,  0xDB,  0xDA,  0x67,  0x60,  0x5F  },
  68         { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
  69 };
  70
  71 static const struct ci_pt_defaults defaults_saturn_xt =
  72 {
  73         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
  74         { 0x8C,  0x247, 0x249, 0xA6,  0x80,  0x81,  0x8B,  0x89,  0x86,  0xC9,  0xCA,  0xC9,  0x4D,  0x4D,  0x4D  },
  75         { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
  76 };
  77
  78 static const struct ci_pt_defaults defaults_saturn_pro =
  79 {
  80         1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
  81         { 0x96,  0x21D, 0x23B, 0xA1,  0x85,  0x87,  0x83,  0x84,  0x81,  0xE6,  0xE6,  0xE6,  0x71,  0x6A,  0x6A  },
  82         { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
  83 };
  84
  85 static const struct ci_pt_config_reg didt_config_ci[] =
  86 {
  87         { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  88         { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  89         { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  90         { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  91         { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  92         { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  93         { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  94         { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  95         { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  96         { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  97         { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  98         { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
  99         { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 100         { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 101         { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 102         { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 103         { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 104         { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 105         { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 106         { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 107         { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 108         { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 109         { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 110         { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 111         { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 112         { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 113         { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 114         { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 115         { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 116         { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 117         { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 118         { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 119         { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 120         { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 121         { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 122         { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 123         { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 124         { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 125         { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 126         { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 127         { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 128         { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 129         { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 130         { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 131         { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 132         { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 133         { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 134         { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 135         { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 136         { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 137         { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 138         { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 139         { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 140         { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 141         { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 142         { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 143         { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 144         { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 145         { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 146         { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 147         { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 148         { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 149         { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 150         { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 151         { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 152         { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 153         { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
 154         { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
 155         { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
 156         { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 157         { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
 158         { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
 159         { 0xFFFFFFFF }
 160 };
 161
 162 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
 163 extern void btc_get_max_clock_from_voltage_dependency_table(struct radeon_clock_voltage_dependency_table *table,
 164                                                             u32 *max_clock);
 165 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
 166                                        u32 arb_freq_src, u32 arb_freq_dest);
 167 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
 168 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
 169 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
 170                                                      u32 max_voltage_steps,
 171                                                      struct atom_voltage_table *voltage_table);
 172 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
 173 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
 174
 175 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
 176                                          struct atom_voltage_table_entry *voltage_table,
 177                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
 178 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
 179 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
 180                                        u32 target_tdp);
 181 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
 182
 183 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
 184 {
 185         struct ci_power_info *pi = rdev->pm.dpm.priv;
 186
 187         return pi;
 188 }
 189
 190 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
 191 {
 192         struct ci_ps *ps = rps->ps_priv;
 193
 194         return ps;
 195 }
 196
 197 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
 198 {
 199         struct ci_power_info *pi = ci_get_pi(rdev);
 200
 201         switch (rdev->pdev->device) {
 202         case 0x6650:
 203         case 0x6658:
 204         case 0x665C:
 205         default:
 206                 pi->powertune_defaults = &defaults_bonaire_xt;
 207                 break;
 208         case 0x6651:
 209         case 0x665D:
 210                 pi->powertune_defaults = &defaults_bonaire_pro;
 211                 break;
 212         case 0x6640:
 213                 pi->powertune_defaults = &defaults_saturn_xt;
 214                 break;
 215         case 0x6641:
 216                 pi->powertune_defaults = &defaults_saturn_pro;
 217                 break;
 218         case 0x67B8:
 219         case 0x67B0:
 220         case 0x67A0:
 221         case 0x67A1:
 222         case 0x67A2:
 223         case 0x67A8:
 224         case 0x67A9:
 225         case 0x67AA:
 226         case 0x67B9:
 227         case 0x67BE:
 228                 pi->powertune_defaults = &defaults_hawaii_xt;
 229                 break;
 230         case 0x67BA:
 231         case 0x67B1:
 232                 pi->powertune_defaults = &defaults_hawaii_pro;
 233                 break;
 234         }
 235
 236         pi->dte_tj_offset = 0;
 237
 238         pi->caps_power_containment = true;
 239         pi->caps_cac = false;
 240         pi->caps_sq_ramping = false;
 241         pi->caps_db_ramping = false;
 242         pi->caps_td_ramping = false;
 243         pi->caps_tcp_ramping = false;
 244
 245         if (pi->caps_power_containment) {
 246                 pi->caps_cac = true;
 247                 pi->enable_bapm_feature = true;
 248                 pi->enable_tdc_limit_feature = true;
 249                 pi->enable_pkg_pwr_tracking_feature = true;
 250         }
 251 }
 252
 253 static u8 ci_convert_to_vid(u16 vddc)
 254 {
 255         return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
 256 }
 257
 258 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
 259 {
 260         struct ci_power_info *pi = ci_get_pi(rdev);
 261         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 262         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 263         u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
 264         u32 i;
 265
 266         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
 267                 return -EINVAL;
 268         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
 269                 return -EINVAL;
 270         if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
 271             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
 272                 return -EINVAL;
 273
 274         for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
 275                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
 276                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
 277                         hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
 278                         hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
 279                 } else {
 280                         lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
 281                         hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
 282                 }
 283         }
 284         return 0;
 285 }
 286
 287 static int ci_populate_vddc_vid(struct radeon_device *rdev)
 288 {
 289         struct ci_power_info *pi = ci_get_pi(rdev);
 290         u8 *vid = pi->smc_powertune_table.VddCVid;
 291         u32 i;
 292
 293         if (pi->vddc_voltage_table.count > 8)
 294                 return -EINVAL;
 295
 296         for (i = 0; i < pi->vddc_voltage_table.count; i++)
 297                 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
 298
 299         return 0;
 300 }
 301
 302 static int ci_populate_svi_load_line(struct radeon_device *rdev)
 303 {
 304         struct ci_power_info *pi = ci_get_pi(rdev);
 305         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 306
 307         pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
 308         pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
 309         pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
 310         pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
 311
 312         return 0;
 313 }
 314
 315 static int ci_populate_tdc_limit(struct radeon_device *rdev)
 316 {
 317         struct ci_power_info *pi = ci_get_pi(rdev);
 318         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 319         u16 tdc_limit;
 320
 321         tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
 322         pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
 323         pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 324                 pt_defaults->tdc_vddc_throttle_release_limit_perc;
 325         pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
 326
 327         return 0;
 328 }
 329
 330 static int ci_populate_dw8(struct radeon_device *rdev)
 331 {
 332         struct ci_power_info *pi = ci_get_pi(rdev);
 333         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 334         int ret;
 335
 336         ret = ci_read_smc_sram_dword(rdev,
 337                                      SMU7_FIRMWARE_HEADER_LOCATION +
 338                                      offsetof(SMU7_Firmware_Header, PmFuseTable) +
 339                                      offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
 340                                      (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
 341                                      pi->sram_end);
 342         if (ret)
 343                 return -EINVAL;
 344         else
 345                 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
 346
 347         return 0;
 348 }
 349
 350 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
 351 {
 352         struct ci_power_info *pi = ci_get_pi(rdev);
 353         u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
 354         u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
 355         int i, min, max;
 356
 357         min = max = hi_vid[0];
 358         for (i = 0; i < 8; i++) {
 359                 if (0 != hi_vid[i]) {
 360                         if (min > hi_vid[i])
 361                                 min = hi_vid[i];
 362                         if (max < hi_vid[i])
 363                                 max = hi_vid[i];
 364                 }
 365
 366                 if (0 != lo_vid[i]) {
 367                         if (min > lo_vid[i])
 368                                 min = lo_vid[i];
 369                         if (max < lo_vid[i])
 370                                 max = lo_vid[i];
 371                 }
 372         }
 373
 374         if ((min == 0) || (max == 0))
 375                 return -EINVAL;
 376         pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
 377         pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
 378
 379         return 0;
 380 }
 381
 382 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
 383 {
 384         struct ci_power_info *pi = ci_get_pi(rdev);
 385         u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
 386         u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
 387         struct radeon_cac_tdp_table *cac_tdp_table =
 388                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 389
 390         hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
 391         lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
 392
 393         pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
 394         pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
 395
 396         return 0;
 397 }
 398
 399 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
 400 {
 401         struct ci_power_info *pi = ci_get_pi(rdev);
 402         const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
 403         SMU7_Discrete_DpmTable  *dpm_table = &pi->smc_state_table;
 404         struct radeon_cac_tdp_table *cac_tdp_table =
 405                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 406         struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
 407         int i, j, k;
 408         const u16 *def1;
 409         const u16 *def2;
 410
 411         dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
 412         dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
 413
 414         dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
 415         dpm_table->GpuTjMax =
 416                 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
 417         dpm_table->GpuTjHyst = 8;
 418
 419         dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
 420
 421         if (ppm) {
 422                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
 423                 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
 424         } else {
 425                 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
 426                 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
 427         }
 428
 429         dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
 430         def1 = pt_defaults->bapmti_r;
 431         def2 = pt_defaults->bapmti_rc;
 432
 433         for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
 434                 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
 435                         for (k = 0; k < SMU7_DTE_SINKS; k++) {
 436                                 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
 437                                 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
 438                                 def1++;
 439                                 def2++;
 440                         }
 441                 }
 442         }
 443
 444         return 0;
 445 }
 446
 447 static int ci_populate_pm_base(struct radeon_device *rdev)
 448 {
 449         struct ci_power_info *pi = ci_get_pi(rdev);
 450         u32 pm_fuse_table_offset;
 451         int ret;
 452
 453         if (pi->caps_power_containment) {
 454                 ret = ci_read_smc_sram_dword(rdev,
 455                                              SMU7_FIRMWARE_HEADER_LOCATION +
 456                                              offsetof(SMU7_Firmware_Header, PmFuseTable),
 457                                              &pm_fuse_table_offset, pi->sram_end);
 458                 if (ret)
 459                         return ret;
 460                 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
 461                 if (ret)
 462                         return ret;
 463                 ret = ci_populate_vddc_vid(rdev);
 464                 if (ret)
 465                         return ret;
 466                 ret = ci_populate_svi_load_line(rdev);
 467                 if (ret)
 468                         return ret;
 469                 ret = ci_populate_tdc_limit(rdev);
 470                 if (ret)
 471                         return ret;
 472                 ret = ci_populate_dw8(rdev);
 473                 if (ret)
 474                         return ret;
 475                 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
 476                 if (ret)
 477                         return ret;
 478                 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
 479                 if (ret)
 480                         return ret;
 481                 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
 482                                            (u8 *)&pi->smc_powertune_table,
 483                                            sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
 484                 if (ret)
 485                         return ret;
 486         }
 487
 488         return 0;
 489 }
 490
 491 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
 492 {
 493         struct ci_power_info *pi = ci_get_pi(rdev);
 494         u32 data;
 495
 496         if (pi->caps_sq_ramping) {
 497                 data = RREG32_DIDT(DIDT_SQ_CTRL0);
 498                 if (enable)
 499                         data |= DIDT_CTRL_EN;
 500                 else
 501                         data &= ~DIDT_CTRL_EN;
 502                 WREG32_DIDT(DIDT_SQ_CTRL0, data);
 503         }
 504
 505         if (pi->caps_db_ramping) {
 506                 data = RREG32_DIDT(DIDT_DB_CTRL0);
 507                 if (enable)
 508                         data |= DIDT_CTRL_EN;
 509                 else
 510                         data &= ~DIDT_CTRL_EN;
 511                 WREG32_DIDT(DIDT_DB_CTRL0, data);
 512         }
 513
 514         if (pi->caps_td_ramping) {
 515                 data = RREG32_DIDT(DIDT_TD_CTRL0);
 516                 if (enable)
 517                         data |= DIDT_CTRL_EN;
 518                 else
 519                         data &= ~DIDT_CTRL_EN;
 520                 WREG32_DIDT(DIDT_TD_CTRL0, data);
 521         }
 522
 523         if (pi->caps_tcp_ramping) {
 524                 data = RREG32_DIDT(DIDT_TCP_CTRL0);
 525                 if (enable)
 526                         data |= DIDT_CTRL_EN;
 527                 else
 528                         data &= ~DIDT_CTRL_EN;
 529                 WREG32_DIDT(DIDT_TCP_CTRL0, data);
 530         }
 531 }
 532
 533 static int ci_program_pt_config_registers(struct radeon_device *rdev,
 534                                           const struct ci_pt_config_reg *cac_config_regs)
 535 {
 536         const struct ci_pt_config_reg *config_regs = cac_config_regs;
 537         u32 data;
 538         u32 cache = 0;
 539
 540         if (config_regs == NULL)
 541                 return -EINVAL;
 542
 543         while (config_regs->offset != 0xFFFFFFFF) {
 544                 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
 545                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 546                 } else {
 547                         switch (config_regs->type) {
 548                         case CISLANDS_CONFIGREG_SMC_IND:
 549                                 data = RREG32_SMC(config_regs->offset);
 550                                 break;
 551                         case CISLANDS_CONFIGREG_DIDT_IND:
 552                                 data = RREG32_DIDT(config_regs->offset);
 553                                 break;
 554                         default:
 555                                 data = RREG32(config_regs->offset << 2);
 556                                 break;
 557                         }
 558
 559                         data &= ~config_regs->mask;
 560                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 561                         data |= cache;
 562
 563                         switch (config_regs->type) {
 564                         case CISLANDS_CONFIGREG_SMC_IND:
 565                                 WREG32_SMC(config_regs->offset, data);
 566                                 break;
 567                         case CISLANDS_CONFIGREG_DIDT_IND:
 568                                 WREG32_DIDT(config_regs->offset, data);
 569                                 break;
 570                         default:
 571                                 WREG32(config_regs->offset << 2, data);
 572                                 break;
 573                         }
 574                         cache = 0;
 575                 }
 576                 config_regs++;
 577         }
 578         return 0;
 579 }
 580
 581 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
 582 {
 583         struct ci_power_info *pi = ci_get_pi(rdev);
 584         int ret;
 585
 586         if (pi->caps_sq_ramping || pi->caps_db_ramping ||
 587             pi->caps_td_ramping || pi->caps_tcp_ramping) {
 588                 cik_enter_rlc_safe_mode(rdev);
 589
 590                 if (enable) {
 591                         ret = ci_program_pt_config_registers(rdev, didt_config_ci);
 592                         if (ret) {
 593                                 cik_exit_rlc_safe_mode(rdev);
 594                                 return ret;
 595                         }
 596                 }
 597
 598                 ci_do_enable_didt(rdev, enable);
 599
 600                 cik_exit_rlc_safe_mode(rdev);
 601         }
 602
 603         return 0;
 604 }
 605
 606 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
 607 {
 608         struct ci_power_info *pi = ci_get_pi(rdev);
 609         PPSMC_Result smc_result;
 610         int ret = 0;
 611
 612         if (enable) {
 613                 pi->power_containment_features = 0;
 614                 if (pi->caps_power_containment) {
 615                         if (pi->enable_bapm_feature) {
 616                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
 617                                 if (smc_result != PPSMC_Result_OK)
 618                                         ret = -EINVAL;
 619                                 else
 620                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
 621                         }
 622
 623                         if (pi->enable_tdc_limit_feature) {
 624                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
 625                                 if (smc_result != PPSMC_Result_OK)
 626                                         ret = -EINVAL;
 627                                 else
 628                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
 629                         }
 630
 631                         if (pi->enable_pkg_pwr_tracking_feature) {
 632                                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
 633                                 if (smc_result != PPSMC_Result_OK) {
 634                                         ret = -EINVAL;
 635                                 } else {
 636                                         struct radeon_cac_tdp_table *cac_tdp_table =
 637                                                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 638                                         u32 default_pwr_limit =
 639                                                 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
 640
 641                                         pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
 642
 643                                         ci_set_power_limit(rdev, default_pwr_limit);
 644                                 }
 645                         }
 646                 }
 647         } else {
 648                 if (pi->caps_power_containment && pi->power_containment_features) {
 649                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
 650                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
 651
 652                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
 653                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
 654
 655                         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
 656                                 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
 657                         pi->power_containment_features = 0;
 658                 }
 659         }
 660
 661         return ret;
 662 }
 663
 664 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
 665 {
 666         struct ci_power_info *pi = ci_get_pi(rdev);
 667         PPSMC_Result smc_result;
 668         int ret = 0;
 669
 670         if (pi->caps_cac) {
 671                 if (enable) {
 672                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
 673                         if (smc_result != PPSMC_Result_OK) {
 674                                 ret = -EINVAL;
 675                                 pi->cac_enabled = false;
 676                         } else {
 677                                 pi->cac_enabled = true;
 678                         }
 679                 } else if (pi->cac_enabled) {
 680                         ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
 681                         pi->cac_enabled = false;
 682                 }
 683         }
 684
 685         return ret;
 686 }
 687
 688 static int ci_power_control_set_level(struct radeon_device *rdev)
 689 {
 690         struct ci_power_info *pi = ci_get_pi(rdev);
 691         struct radeon_cac_tdp_table *cac_tdp_table =
 692                 rdev->pm.dpm.dyn_state.cac_tdp_table;
 693         s32 adjust_percent;
 694         s32 target_tdp;
 695         int ret = 0;
 696         bool adjust_polarity = false; /* ??? */
 697
 698         if (pi->caps_power_containment &&
 699             (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)) {
 700                 adjust_percent = adjust_polarity ?
 701                         rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
 702                 target_tdp = ((100 + adjust_percent) *
 703                               (s32)cac_tdp_table->configurable_tdp) / 100;
 704                 target_tdp *= 256;
 705
 706                 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
 707         }
 708
 709         return ret;
 710 }
 711
 712 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
 713 {
 714         struct ci_power_info *pi = ci_get_pi(rdev);
 715
 716         if (pi->uvd_power_gated == gate)
 717                 return;
 718
 719         pi->uvd_power_gated = gate;
 720
 721         ci_update_uvd_dpm(rdev, gate);
 722 }
 723
 724 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
 725 {
 726         struct ci_power_info *pi = ci_get_pi(rdev);
 727         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
 728         u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
 729
 730         if (vblank_time < switch_limit)
 731                 return true;
 732         else
 733                 return false;
 734
 735 }
 736
 737 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
 738                                         struct radeon_ps *rps)
 739 {
 740         struct ci_ps *ps = ci_get_ps(rps);
 741         struct ci_power_info *pi = ci_get_pi(rdev);
 742         struct radeon_clock_and_voltage_limits *max_limits;
 743         bool disable_mclk_switching;
 744         u32 sclk, mclk;
 745         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
 746         int i;
 747
 748         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
 749             ci_dpm_vblank_too_short(rdev))
 750                 disable_mclk_switching = true;
 751         else
 752                 disable_mclk_switching = false;
 753
 754         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
 755                 pi->battery_state = true;
 756         else
 757                 pi->battery_state = false;
 758
 759         if (rdev->pm.dpm.ac_power)
 760                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
 761         else
 762                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
 763
 764         if (rdev->pm.dpm.ac_power == false) {
 765                 for (i = 0; i < ps->performance_level_count; i++) {
 766                         if (ps->performance_levels[i].mclk > max_limits->mclk)
 767                                 ps->performance_levels[i].mclk = max_limits->mclk;
 768                         if (ps->performance_levels[i].sclk > max_limits->sclk)
 769                                 ps->performance_levels[i].sclk = max_limits->sclk;
 770                 }
 771         }
 772
 773         /* limit clocks to max supported clocks based on voltage dependency tables */
 774         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
 775                                                         &max_sclk_vddc);
 776         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
 777                                                         &max_mclk_vddci);
 778         btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
 779                                                         &max_mclk_vddc);
 780
 781         for (i = 0; i < ps->performance_level_count; i++) {
 782                 if (max_sclk_vddc) {
 783                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
 784                                 ps->performance_levels[i].sclk = max_sclk_vddc;
 785                 }
 786                 if (max_mclk_vddci) {
 787                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
 788                                 ps->performance_levels[i].mclk = max_mclk_vddci;
 789                 }
 790                 if (max_mclk_vddc) {
 791                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
 792                                 ps->performance_levels[i].mclk = max_mclk_vddc;
 793                 }
 794         }
 795
 796         /* XXX validate the min clocks required for display */
 797
 798         if (disable_mclk_switching) {
 799                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
 800                 sclk = ps->performance_levels[0].sclk;
 801         } else {
 802                 mclk = ps->performance_levels[0].mclk;
 803                 sclk = ps->performance_levels[0].sclk;
 804         }
 805
 806         ps->performance_levels[0].sclk = sclk;
 807         ps->performance_levels[0].mclk = mclk;
 808
 809         if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
 810                 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
 811
 812         if (disable_mclk_switching) {
 813                 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
 814                         ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
 815         } else {
 816                 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
 817                         ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
 818         }
 819 }
 820
 821 static int ci_set_thermal_temperature_range(struct radeon_device *rdev,
 822                                             int min_temp, int max_temp)
 823 {
 824         int low_temp = 0 * 1000;
 825         int high_temp = 255 * 1000;
 826         u32 tmp;
 827
 828         if (low_temp < min_temp)
 829                 low_temp = min_temp;
 830         if (high_temp > max_temp)
 831                 high_temp = max_temp;
 832         if (high_temp < low_temp) {
 833                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
 834                 return -EINVAL;
 835         }
 836
 837         tmp = RREG32_SMC(CG_THERMAL_INT);
 838         tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
 839         tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
 840                 CI_DIG_THERM_INTL(low_temp / 1000);
 841         WREG32_SMC(CG_THERMAL_INT, tmp);
 842
 843 #if 0
 844         /* XXX: need to figure out how to handle this properly */
 845         tmp = RREG32_SMC(CG_THERMAL_CTRL);
 846         tmp &= DIG_THERM_DPM_MASK;
 847         tmp |= DIG_THERM_DPM(high_temp / 1000);
 848         WREG32_SMC(CG_THERMAL_CTRL, tmp);
 849 #endif
 850
 851         return 0;
 852 }
 853
 854 #if 0
 855 static int ci_read_smc_soft_register(struct radeon_device *rdev,
 856                                      u16 reg_offset, u32 *value)
 857 {
 858         struct ci_power_info *pi = ci_get_pi(rdev);
 859
 860         return ci_read_smc_sram_dword(rdev,
 861                                       pi->soft_regs_start + reg_offset,
 862                                       value, pi->sram_end);
 863 }
 864 #endif
 865
 866 static int ci_write_smc_soft_register(struct radeon_device *rdev,
 867                                       u16 reg_offset, u32 value)
 868 {
 869         struct ci_power_info *pi = ci_get_pi(rdev);
 870
 871         return ci_write_smc_sram_dword(rdev,
 872                                        pi->soft_regs_start + reg_offset,
 873                                        value, pi->sram_end);
 874 }
 875
 876 static void ci_init_fps_limits(struct radeon_device *rdev)
 877 {
 878         struct ci_power_info *pi = ci_get_pi(rdev);
 879         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
 880
 881         if (pi->caps_fps) {
 882                 u16 tmp;
 883
 884                 tmp = 45;
 885                 table->FpsHighT = cpu_to_be16(tmp);
 886
 887                 tmp = 30;
 888                 table->FpsLowT = cpu_to_be16(tmp);
 889         }
 890 }
 891
 892 static int ci_update_sclk_t(struct radeon_device *rdev)
 893 {
 894         struct ci_power_info *pi = ci_get_pi(rdev);
 895         int ret = 0;
 896         u32 low_sclk_interrupt_t = 0;
 897
 898         if (pi->caps_sclk_throttle_low_notification) {
 899                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 900
 901                 ret = ci_copy_bytes_to_smc(rdev,
 902                                            pi->dpm_table_start +
 903                                            offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
 904                                            (u8 *)&low_sclk_interrupt_t,
 905                                            sizeof(u32), pi->sram_end);
 906
 907         }
 908
 909         return ret;
 910 }
 911
 912 static void ci_get_leakage_voltages(struct radeon_device *rdev)
 913 {
 914         struct ci_power_info *pi = ci_get_pi(rdev);
 915         u16 leakage_id, virtual_voltage_id;
 916         u16 vddc, vddci;
 917         int i;
 918
 919         pi->vddc_leakage.count = 0;
 920         pi->vddci_leakage.count = 0;
 921
 922         if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
 923                 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
 924                         virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
 925                         if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
 926                                                                                  virtual_voltage_id,
 927                                                                                  leakage_id) == 0) {
 928                                 if (vddc != 0 && vddc != virtual_voltage_id) {
 929                                         pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
 930                                         pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
 931                                         pi->vddc_leakage.count++;
 932                                 }
 933                                 if (vddci != 0 && vddci != virtual_voltage_id) {
 934                                         pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
 935                                         pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
 936                                         pi->vddci_leakage.count++;
 937                                 }
 938                         }
 939                 }
 940         }
 941 }
 942
 943 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
 944 {
 945         struct ci_power_info *pi = ci_get_pi(rdev);
 946         bool want_thermal_protection;
 947         enum radeon_dpm_event_src dpm_event_src;
 948         u32 tmp;
 949
 950         switch (sources) {
 951         case 0:
 952         default:
 953                 want_thermal_protection = false;
 954                 break;
 955         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
 956                 want_thermal_protection = true;
 957                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
 958                 break;
 959         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
 960                 want_thermal_protection = true;
 961                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
 962                 break;
 963         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
 964               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
 965                 want_thermal_protection = true;
 966                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
 967                 break;
 968         }
 969
 970         if (want_thermal_protection) {
 971 #if 0
 972                 /* XXX: need to figure out how to handle this properly */
 973                 tmp = RREG32_SMC(CG_THERMAL_CTRL);
 974                 tmp &= DPM_EVENT_SRC_MASK;
 975                 tmp |= DPM_EVENT_SRC(dpm_event_src);
 976                 WREG32_SMC(CG_THERMAL_CTRL, tmp);
 977 #endif
 978
 979                 tmp = RREG32_SMC(GENERAL_PWRMGT);
 980                 if (pi->thermal_protection)
 981                         tmp &= ~THERMAL_PROTECTION_DIS;
 982                 else
 983                         tmp |= THERMAL_PROTECTION_DIS;
 984                 WREG32_SMC(GENERAL_PWRMGT, tmp);
 985         } else {
 986                 tmp = RREG32_SMC(GENERAL_PWRMGT);
 987                 tmp |= THERMAL_PROTECTION_DIS;
 988                 WREG32_SMC(GENERAL_PWRMGT, tmp);
 989         }
 990 }
 991
 992 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
 993                                            enum radeon_dpm_auto_throttle_src source,
 994                                            bool enable)
 995 {
 996         struct ci_power_info *pi = ci_get_pi(rdev);
 997
 998         if (enable) {
 999                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1000                         pi->active_auto_throttle_sources |= 1 << source;
1001                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1002                 }
1003         } else {
1004                 if (pi->active_auto_throttle_sources & (1 << source)) {
1005                         pi->active_auto_throttle_sources &= ~(1 << source);
1006                         ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1007                 }
1008         }
1009 }
1010
1011 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1012 {
1013         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1014                 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1015 }
1016
1017 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1018 {
1019         struct ci_power_info *pi = ci_get_pi(rdev);
1020         PPSMC_Result smc_result;
1021
1022         if (!pi->need_update_smu7_dpm_table)
1023                 return 0;
1024
1025         if ((!pi->sclk_dpm_key_disabled) &&
1026             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1027                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1028                 if (smc_result != PPSMC_Result_OK)
1029                         return -EINVAL;
1030         }
1031
1032         if ((!pi->mclk_dpm_key_disabled) &&
1033             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1034                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1035                 if (smc_result != PPSMC_Result_OK)
1036                         return -EINVAL;
1037         }
1038
1039         pi->need_update_smu7_dpm_table = 0;
1040         return 0;
1041 }
1042
1043 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1044 {
1045         struct ci_power_info *pi = ci_get_pi(rdev);
1046         PPSMC_Result smc_result;
1047
1048         if (enable) {
1049                 if (!pi->sclk_dpm_key_disabled) {
1050                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1051                         if (smc_result != PPSMC_Result_OK)
1052                                 return -EINVAL;
1053                 }
1054
1055                 if (!pi->mclk_dpm_key_disabled) {
1056                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1057                         if (smc_result != PPSMC_Result_OK)
1058                                 return -EINVAL;
1059
1060                         WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1061
1062                         WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1063                         WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1064                         WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1065
1066                         udelay(10);
1067
1068                         WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1069                         WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1070                         WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1071                 }
1072         } else {
1073                 if (!pi->sclk_dpm_key_disabled) {
1074                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1075                         if (smc_result != PPSMC_Result_OK)
1076                                 return -EINVAL;
1077                 }
1078
1079                 if (!pi->mclk_dpm_key_disabled) {
1080                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1081                         if (smc_result != PPSMC_Result_OK)
1082                                 return -EINVAL;
1083                 }
1084         }
1085
1086         return 0;
1087 }
1088
1089 static int ci_start_dpm(struct radeon_device *rdev)
1090 {
1091         struct ci_power_info *pi = ci_get_pi(rdev);
1092         PPSMC_Result smc_result;
1093         int ret;
1094         u32 tmp;
1095
1096         tmp = RREG32_SMC(GENERAL_PWRMGT);
1097         tmp |= GLOBAL_PWRMGT_EN;
1098         WREG32_SMC(GENERAL_PWRMGT, tmp);
1099
1100         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1101         tmp |= DYNAMIC_PM_EN;
1102         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1103
1104         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1105
1106         WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1107
1108         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1109         if (smc_result != PPSMC_Result_OK)
1110                 return -EINVAL;
1111
1112         ret = ci_enable_sclk_mclk_dpm(rdev, true);
1113         if (ret)
1114                 return ret;
1115
1116         if (!pi->pcie_dpm_key_disabled) {
1117                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1118                 if (smc_result != PPSMC_Result_OK)
1119                         return -EINVAL;
1120         }
1121
1122         return 0;
1123 }
1124
1125 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1126 {
1127         struct ci_power_info *pi = ci_get_pi(rdev);
1128         PPSMC_Result smc_result;
1129
1130         if (!pi->need_update_smu7_dpm_table)
1131                 return 0;
1132
1133         if ((!pi->sclk_dpm_key_disabled) &&
1134             (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1135                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1136                 if (smc_result != PPSMC_Result_OK)
1137                         return -EINVAL;
1138         }
1139
1140         if ((!pi->mclk_dpm_key_disabled) &&
1141             (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1142                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1143                 if (smc_result != PPSMC_Result_OK)
1144                         return -EINVAL;
1145         }
1146
1147         return 0;
1148 }
1149
1150 static int ci_stop_dpm(struct radeon_device *rdev)
1151 {
1152         struct ci_power_info *pi = ci_get_pi(rdev);
1153         PPSMC_Result smc_result;
1154         int ret;
1155         u32 tmp;
1156
1157         tmp = RREG32_SMC(GENERAL_PWRMGT);
1158         tmp &= ~GLOBAL_PWRMGT_EN;
1159         WREG32_SMC(GENERAL_PWRMGT, tmp);
1160
1161         tmp = RREG32(SCLK_PWRMGT_CNTL);
1162         tmp &= ~DYNAMIC_PM_EN;
1163         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1164
1165         if (!pi->pcie_dpm_key_disabled) {
1166                 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1167                 if (smc_result != PPSMC_Result_OK)
1168                         return -EINVAL;
1169         }
1170
1171         ret = ci_enable_sclk_mclk_dpm(rdev, false);
1172         if (ret)
1173                 return ret;
1174
1175         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1176         if (smc_result != PPSMC_Result_OK)
1177                 return -EINVAL;
1178
1179         return 0;
1180 }
1181
1182 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1183 {
1184         u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1185
1186         if (enable)
1187                 tmp &= ~SCLK_PWRMGT_OFF;
1188         else
1189                 tmp |= SCLK_PWRMGT_OFF;
1190         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1191 }
1192
1193 #if 0
1194 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1195                                         bool ac_power)
1196 {
1197         struct ci_power_info *pi = ci_get_pi(rdev);
1198         struct radeon_cac_tdp_table *cac_tdp_table =
1199                 rdev->pm.dpm.dyn_state.cac_tdp_table;
1200         u32 power_limit;
1201
1202         if (ac_power)
1203                 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1204         else
1205                 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1206
1207         ci_set_power_limit(rdev, power_limit);
1208
1209         if (pi->caps_automatic_dc_transition) {
1210                 if (ac_power)
1211                         ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1212                 else
1213                         ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1214         }
1215
1216         return 0;
1217 }
1218 #endif
1219
1220 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1221                                                       PPSMC_Msg msg, u32 parameter)
1222 {
1223         WREG32(SMC_MSG_ARG_0, parameter);
1224         return ci_send_msg_to_smc(rdev, msg);
1225 }
1226
1227 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1228                                                         PPSMC_Msg msg, u32 *parameter)
1229 {
1230         PPSMC_Result smc_result;
1231
1232         smc_result = ci_send_msg_to_smc(rdev, msg);
1233
1234         if ((smc_result == PPSMC_Result_OK) && parameter)
1235                 *parameter = RREG32(SMC_MSG_ARG_0);
1236
1237         return smc_result;
1238 }
1239
1240 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1241 {
1242         struct ci_power_info *pi = ci_get_pi(rdev);
1243
1244         if (!pi->sclk_dpm_key_disabled) {
1245                 PPSMC_Result smc_result =
1246                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, n);
1247                 if (smc_result != PPSMC_Result_OK)
1248                         return -EINVAL;
1249         }
1250
1251         return 0;
1252 }
1253
1254 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1255 {
1256         struct ci_power_info *pi = ci_get_pi(rdev);
1257
1258         if (!pi->mclk_dpm_key_disabled) {
1259                 PPSMC_Result smc_result =
1260                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_ForceState, n);
1261                 if (smc_result != PPSMC_Result_OK)
1262                         return -EINVAL;
1263         }
1264
1265         return 0;
1266 }
1267
1268 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1269 {
1270         struct ci_power_info *pi = ci_get_pi(rdev);
1271
1272         if (!pi->pcie_dpm_key_disabled) {
1273                 PPSMC_Result smc_result =
1274                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1275                 if (smc_result != PPSMC_Result_OK)
1276                         return -EINVAL;
1277         }
1278
1279         return 0;
1280 }
1281
1282 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1283 {
1284         struct ci_power_info *pi = ci_get_pi(rdev);
1285
1286         if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1287                 PPSMC_Result smc_result =
1288                         ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1289                 if (smc_result != PPSMC_Result_OK)
1290                         return -EINVAL;
1291         }
1292
1293         return 0;
1294 }
1295
1296 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1297                                        u32 target_tdp)
1298 {
1299         PPSMC_Result smc_result =
1300                 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1301         if (smc_result != PPSMC_Result_OK)
1302                 return -EINVAL;
1303         return 0;
1304 }
1305
1306 static int ci_set_boot_state(struct radeon_device *rdev)
1307 {
1308         return ci_enable_sclk_mclk_dpm(rdev, false);
1309 }
1310
1311 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1312 {
1313         u32 sclk_freq;
1314         PPSMC_Result smc_result =
1315                 ci_send_msg_to_smc_return_parameter(rdev,
1316                                                     PPSMC_MSG_API_GetSclkFrequency,
1317                                                     &sclk_freq);
1318         if (smc_result != PPSMC_Result_OK)
1319                 sclk_freq = 0;
1320
1321         return sclk_freq;
1322 }
1323
1324 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1325 {
1326         u32 mclk_freq;
1327         PPSMC_Result smc_result =
1328                 ci_send_msg_to_smc_return_parameter(rdev,
1329                                                     PPSMC_MSG_API_GetMclkFrequency,
1330                                                     &mclk_freq);
1331         if (smc_result != PPSMC_Result_OK)
1332                 mclk_freq = 0;
1333
1334         return mclk_freq;
1335 }
1336
1337 static void ci_dpm_start_smc(struct radeon_device *rdev)
1338 {
1339         int i;
1340
1341         ci_program_jump_on_start(rdev);
1342         ci_start_smc_clock(rdev);
1343         ci_start_smc(rdev);
1344         for (i = 0; i < rdev->usec_timeout; i++) {
1345                 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1346                         break;
1347         }
1348 }
1349
1350 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1351 {
1352         ci_reset_smc(rdev);
1353         ci_stop_smc_clock(rdev);
1354 }
1355
1356 static int ci_process_firmware_header(struct radeon_device *rdev)
1357 {
1358         struct ci_power_info *pi = ci_get_pi(rdev);
1359         u32 tmp;
1360         int ret;
1361
1362         ret = ci_read_smc_sram_dword(rdev,
1363                                      SMU7_FIRMWARE_HEADER_LOCATION +
1364                                      offsetof(SMU7_Firmware_Header, DpmTable),
1365                                      &tmp, pi->sram_end);
1366         if (ret)
1367                 return ret;
1368
1369         pi->dpm_table_start = tmp;
1370
1371         ret = ci_read_smc_sram_dword(rdev,
1372                                      SMU7_FIRMWARE_HEADER_LOCATION +
1373                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
1374                                      &tmp, pi->sram_end);
1375         if (ret)
1376                 return ret;
1377
1378         pi->soft_regs_start = tmp;
1379
1380         ret = ci_read_smc_sram_dword(rdev,
1381                                      SMU7_FIRMWARE_HEADER_LOCATION +
1382                                      offsetof(SMU7_Firmware_Header, mcRegisterTable),
1383                                      &tmp, pi->sram_end);
1384         if (ret)
1385                 return ret;
1386
1387         pi->mc_reg_table_start = tmp;
1388
1389         ret = ci_read_smc_sram_dword(rdev,
1390                                      SMU7_FIRMWARE_HEADER_LOCATION +
1391                                      offsetof(SMU7_Firmware_Header, FanTable),
1392                                      &tmp, pi->sram_end);
1393         if (ret)
1394                 return ret;
1395
1396         pi->fan_table_start = tmp;
1397
1398         ret = ci_read_smc_sram_dword(rdev,
1399                                      SMU7_FIRMWARE_HEADER_LOCATION +
1400                                      offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1401                                      &tmp, pi->sram_end);
1402         if (ret)
1403                 return ret;
1404
1405         pi->arb_table_start = tmp;
1406
1407         return 0;
1408 }
1409
1410 static void ci_read_clock_registers(struct radeon_device *rdev)
1411 {
1412         struct ci_power_info *pi = ci_get_pi(rdev);
1413
1414         pi->clock_registers.cg_spll_func_cntl =
1415                 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1416         pi->clock_registers.cg_spll_func_cntl_2 =
1417                 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1418         pi->clock_registers.cg_spll_func_cntl_3 =
1419                 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1420         pi->clock_registers.cg_spll_func_cntl_4 =
1421                 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1422         pi->clock_registers.cg_spll_spread_spectrum =
1423                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1424         pi->clock_registers.cg_spll_spread_spectrum_2 =
1425                 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1426         pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1427         pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1428         pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1429         pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1430         pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1431         pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1432         pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1433         pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1434         pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1435 }
1436
1437 static void ci_init_sclk_t(struct radeon_device *rdev)
1438 {
1439         struct ci_power_info *pi = ci_get_pi(rdev);
1440
1441         pi->low_sclk_interrupt_t = 0;
1442 }
1443
1444 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1445                                          bool enable)
1446 {
1447         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1448
1449         if (enable)
1450                 tmp &= ~THERMAL_PROTECTION_DIS;
1451         else
1452                 tmp |= THERMAL_PROTECTION_DIS;
1453         WREG32_SMC(GENERAL_PWRMGT, tmp);
1454 }
1455
1456 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1457 {
1458         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1459
1460         tmp |= STATIC_PM_EN;
1461
1462         WREG32_SMC(GENERAL_PWRMGT, tmp);
1463 }
1464
1465 #if 0
1466 static int ci_enter_ulp_state(struct radeon_device *rdev)
1467 {
1468
1469         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1470
1471         udelay(25000);
1472
1473         return 0;
1474 }
1475
1476 static int ci_exit_ulp_state(struct radeon_device *rdev)
1477 {
1478         int i;
1479
1480         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1481
1482         udelay(7000);
1483
1484         for (i = 0; i < rdev->usec_timeout; i++) {
1485                 if (RREG32(SMC_RESP_0) == 1)
1486                         break;
1487                 udelay(1000);
1488         }
1489
1490         return 0;
1491 }
1492 #endif
1493
1494 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1495                                         bool has_display)
1496 {
1497         PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1498
1499         return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?  0 : -EINVAL;
1500 }
1501
1502 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1503                                       bool enable)
1504 {
1505         struct ci_power_info *pi = ci_get_pi(rdev);
1506
1507         if (enable) {
1508                 if (pi->caps_sclk_ds) {
1509                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1510                                 return -EINVAL;
1511                 } else {
1512                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1513                                 return -EINVAL;
1514                 }
1515         } else {
1516                 if (pi->caps_sclk_ds) {
1517                         if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1518                                 return -EINVAL;
1519                 }
1520         }
1521
1522         return 0;
1523 }
1524
1525 static void ci_program_display_gap(struct radeon_device *rdev)
1526 {
1527         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1528         u32 pre_vbi_time_in_us;
1529         u32 frame_time_in_us;
1530         u32 ref_clock = rdev->clock.spll.reference_freq;
1531         u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1532         u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1533
1534         tmp &= ~DISP_GAP_MASK;
1535         if (rdev->pm.dpm.new_active_crtc_count > 0)
1536                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1537         else
1538                 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1539         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1540
1541         if (refresh_rate == 0)
1542                 refresh_rate = 60;
1543         if (vblank_time == 0xffffffff)
1544                 vblank_time = 500;
1545         frame_time_in_us = 1000000 / refresh_rate;
1546         pre_vbi_time_in_us =
1547                 frame_time_in_us - 200 - vblank_time;
1548         tmp = pre_vbi_time_in_us * (ref_clock / 100);
1549
1550         WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1551         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1552         ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1553
1554
1555         ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1556
1557 }
1558
1559 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1560 {
1561         struct ci_power_info *pi = ci_get_pi(rdev);
1562         u32 tmp;
1563
1564         if (enable) {
1565                 if (pi->caps_sclk_ss_support) {
1566                         tmp = RREG32_SMC(GENERAL_PWRMGT);
1567                         tmp |= DYN_SPREAD_SPECTRUM_EN;
1568                         WREG32_SMC(GENERAL_PWRMGT, tmp);
1569                 }
1570         } else {
1571                 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1572                 tmp &= ~SSEN;
1573                 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
1574
1575                 tmp = RREG32_SMC(GENERAL_PWRMGT);
1576                 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
1577                 WREG32_SMC(GENERAL_PWRMGT, tmp);
1578         }
1579 }
1580
1581 static void ci_program_sstp(struct radeon_device *rdev)
1582 {
1583         WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
1584 }
1585
1586 static void ci_enable_display_gap(struct radeon_device *rdev)
1587 {
1588         u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1589
1590         tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
1591         tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1592                 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
1593
1594         WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1595 }
1596
1597 static void ci_program_vc(struct radeon_device *rdev)
1598 {
1599         u32 tmp;
1600
1601         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1602         tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
1603         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1604
1605         WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
1606         WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
1607         WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
1608         WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
1609         WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
1610         WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
1611         WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
1612         WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
1613 }
1614
1615 static void ci_clear_vc(struct radeon_device *rdev)
1616 {
1617         u32 tmp;
1618
1619         tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1620         tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
1621         WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1622
1623         WREG32_SMC(CG_FTV_0, 0);
1624         WREG32_SMC(CG_FTV_1, 0);
1625         WREG32_SMC(CG_FTV_2, 0);
1626         WREG32_SMC(CG_FTV_3, 0);
1627         WREG32_SMC(CG_FTV_4, 0);
1628         WREG32_SMC(CG_FTV_5, 0);
1629         WREG32_SMC(CG_FTV_6, 0);
1630         WREG32_SMC(CG_FTV_7, 0);
1631 }
1632
1633 static int ci_upload_firmware(struct radeon_device *rdev)
1634 {
1635         struct ci_power_info *pi = ci_get_pi(rdev);
1636         int i, ret;
1637
1638         for (i = 0; i < rdev->usec_timeout; i++) {
1639                 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
1640                         break;
1641         }
1642         WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
1643
1644         ci_stop_smc_clock(rdev);
1645         ci_reset_smc(rdev);
1646
1647         ret = ci_load_smc_ucode(rdev, pi->sram_end);
1648
1649         return ret;
1650
1651 }
1652
1653 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
1654                                      struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
1655                                      struct atom_voltage_table *voltage_table)
1656 {
1657         u32 i;
1658
1659         if (voltage_dependency_table == NULL)
1660                 return -EINVAL;
1661
1662         voltage_table->mask_low = 0;
1663         voltage_table->phase_delay = 0;
1664
1665         voltage_table->count = voltage_dependency_table->count;
1666         for (i = 0; i < voltage_table->count; i++) {
1667                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
1668                 voltage_table->entries[i].smio_low = 0;
1669         }
1670
1671         return 0;
1672 }
1673
1674 static int ci_construct_voltage_tables(struct radeon_device *rdev)
1675 {
1676         struct ci_power_info *pi = ci_get_pi(rdev);
1677         int ret;
1678
1679         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1680                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
1681                                                     VOLTAGE_OBJ_GPIO_LUT,
1682                                                     &pi->vddc_voltage_table);
1683                 if (ret)
1684                         return ret;
1685         } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1686                 ret = ci_get_svi2_voltage_table(rdev,
1687                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
1688                                                 &pi->vddc_voltage_table);
1689                 if (ret)
1690                         return ret;
1691         }
1692
1693         if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
1694                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
1695                                                          &pi->vddc_voltage_table);
1696
1697         if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1698                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
1699                                                     VOLTAGE_OBJ_GPIO_LUT,
1700                                                     &pi->vddci_voltage_table);
1701                 if (ret)
1702                         return ret;
1703         } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1704                 ret = ci_get_svi2_voltage_table(rdev,
1705                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
1706                                                 &pi->vddci_voltage_table);
1707                 if (ret)
1708                         return ret;
1709         }
1710
1711         if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
1712                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
1713                                                          &pi->vddci_voltage_table);
1714
1715         if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
1716                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
1717                                                     VOLTAGE_OBJ_GPIO_LUT,
1718                                                     &pi->mvdd_voltage_table);
1719                 if (ret)
1720                         return ret;
1721         } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
1722                 ret = ci_get_svi2_voltage_table(rdev,
1723                                                 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
1724                                                 &pi->mvdd_voltage_table);
1725                 if (ret)
1726                         return ret;
1727         }
1728
1729         if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
1730                 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
1731                                                          &pi->mvdd_voltage_table);
1732
1733         return 0;
1734 }
1735
1736 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
1737                                           struct atom_voltage_table_entry *voltage_table,
1738                                           SMU7_Discrete_VoltageLevel *smc_voltage_table)
1739 {
1740         int ret;
1741
1742         ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
1743                                             &smc_voltage_table->StdVoltageHiSidd,
1744                                             &smc_voltage_table->StdVoltageLoSidd);
1745
1746         if (ret) {
1747                 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
1748                 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
1749         }
1750
1751         smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
1752         smc_voltage_table->StdVoltageHiSidd =
1753                 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
1754         smc_voltage_table->StdVoltageLoSidd =
1755                 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
1756 }
1757
1758 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
1759                                       SMU7_Discrete_DpmTable *table)
1760 {
1761         struct ci_power_info *pi = ci_get_pi(rdev);
1762         unsigned int count;
1763
1764         table->VddcLevelCount = pi->vddc_voltage_table.count;
1765         for (count = 0; count < table->VddcLevelCount; count++) {
1766                 ci_populate_smc_voltage_table(rdev,
1767                                               &pi->vddc_voltage_table.entries[count],
1768                                               &table->VddcLevel[count]);
1769
1770                 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1771                         table->VddcLevel[count].Smio |=
1772                                 pi->vddc_voltage_table.entries[count].smio_low;
1773                 else
1774                         table->VddcLevel[count].Smio = 0;
1775         }
1776         table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
1777
1778         return 0;
1779 }
1780
1781 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
1782                                        SMU7_Discrete_DpmTable *table)
1783 {
1784         unsigned int count;
1785         struct ci_power_info *pi = ci_get_pi(rdev);
1786
1787         table->VddciLevelCount = pi->vddci_voltage_table.count;
1788         for (count = 0; count < table->VddciLevelCount; count++) {
1789                 ci_populate_smc_voltage_table(rdev,
1790                                               &pi->vddci_voltage_table.entries[count],
1791                                               &table->VddciLevel[count]);
1792
1793                 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1794                         table->VddciLevel[count].Smio |=
1795                                 pi->vddci_voltage_table.entries[count].smio_low;
1796                 else
1797                         table->VddciLevel[count].Smio = 0;
1798         }
1799         table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
1800
1801         return 0;
1802 }
1803
1804 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
1805                                       SMU7_Discrete_DpmTable *table)
1806 {
1807         struct ci_power_info *pi = ci_get_pi(rdev);
1808         unsigned int count;
1809
1810         table->MvddLevelCount = pi->mvdd_voltage_table.count;
1811         for (count = 0; count < table->MvddLevelCount; count++) {
1812                 ci_populate_smc_voltage_table(rdev,
1813                                               &pi->mvdd_voltage_table.entries[count],
1814                                               &table->MvddLevel[count]);
1815
1816                 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
1817                         table->MvddLevel[count].Smio |=
1818                                 pi->mvdd_voltage_table.entries[count].smio_low;
1819                 else
1820                         table->MvddLevel[count].Smio = 0;
1821         }
1822         table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
1823
1824         return 0;
1825 }
1826
1827 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
1828                                           SMU7_Discrete_DpmTable *table)
1829 {
1830         int ret;
1831
1832         ret = ci_populate_smc_vddc_table(rdev, table);
1833         if (ret)
1834                 return ret;
1835
1836         ret = ci_populate_smc_vddci_table(rdev, table);
1837         if (ret)
1838                 return ret;
1839
1840         ret = ci_populate_smc_mvdd_table(rdev, table);
1841         if (ret)
1842                 return ret;
1843
1844         return 0;
1845 }
1846
1847 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
1848                                   SMU7_Discrete_VoltageLevel *voltage)
1849 {
1850         struct ci_power_info *pi = ci_get_pi(rdev);
1851         u32 i = 0;
1852
1853         if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
1854                 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
1855                         if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
1856                                 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
1857                                 break;
1858                         }
1859                 }
1860
1861                 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
1862                         return -EINVAL;
1863         }
1864
1865         return -EINVAL;
1866 }
1867
1868 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
1869                                          struct atom_voltage_table_entry *voltage_table,
1870                                          u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
1871 {
1872         u16 v_index, idx;
1873         bool voltage_found = false;
1874         *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
1875         *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
1876
1877         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
1878                 return -EINVAL;
1879
1880         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
1881                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1882                         if (voltage_table->value ==
1883                             rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1884                                 voltage_found = true;
1885                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1886                                         idx = v_index;
1887                                 else
1888                                         idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1889                                 *std_voltage_lo_sidd =
1890                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1891                                 *std_voltage_hi_sidd =
1892                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1893                                 break;
1894                         }
1895                 }
1896
1897                 if (!voltage_found) {
1898                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
1899                                 if (voltage_table->value <=
1900                                     rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
1901                                         voltage_found = true;
1902                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
1903                                                 idx = v_index;
1904                                         else
1905                                                 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
1906                                         *std_voltage_lo_sidd =
1907                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
1908                                         *std_voltage_hi_sidd =
1909                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
1910                                         break;
1911                                 }
1912                         }
1913                 }
1914         }
1915
1916         return 0;
1917 }
1918
1919 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
1920                                                   const struct radeon_phase_shedding_limits_table *limits,
1921                                                   u32 sclk,
1922                                                   u32 *phase_shedding)
1923 {
1924         unsigned int i;
1925
1926         *phase_shedding = 1;
1927
1928         for (i = 0; i < limits->count; i++) {
1929                 if (sclk < limits->entries[i].sclk) {
1930                         *phase_shedding = i;
1931                         break;
1932                 }
1933         }
1934 }
1935
1936 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
1937                                                   const struct radeon_phase_shedding_limits_table *limits,
1938                                                   u32 mclk,
1939                                                   u32 *phase_shedding)
1940 {
1941         unsigned int i;
1942
1943         *phase_shedding = 1;
1944
1945         for (i = 0; i < limits->count; i++) {
1946                 if (mclk < limits->entries[i].mclk) {
1947                         *phase_shedding = i;
1948                         break;
1949                 }
1950         }
1951 }
1952
1953 static int ci_init_arb_table_index(struct radeon_device *rdev)
1954 {
1955         struct ci_power_info *pi = ci_get_pi(rdev);
1956         u32 tmp;
1957         int ret;
1958
1959         ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
1960                                      &tmp, pi->sram_end);
1961         if (ret)
1962                 return ret;
1963
1964         tmp &= 0x00FFFFFF;
1965         tmp |= MC_CG_ARB_FREQ_F1 << 24;
1966
1967         return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
1968                                        tmp, pi->sram_end);
1969 }
1970
1971 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
1972                                          struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
1973                                          u32 clock, u32 *voltage)
1974 {
1975         u32 i = 0;
1976
1977         if (allowed_clock_voltage_table->count == 0)
1978                 return -EINVAL;
1979
1980         for (i = 0; i < allowed_clock_voltage_table->count; i++) {
1981                 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
1982                         *voltage = allowed_clock_voltage_table->entries[i].v;
1983                         return 0;
1984                 }
1985         }
1986
1987         *voltage = allowed_clock_voltage_table->entries[i-1].v;
1988
1989         return 0;
1990 }
1991
1992 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1993                                              u32 sclk, u32 min_sclk_in_sr)
1994 {
1995         u32 i;
1996         u32 tmp;
1997         u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
1998                 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
1999
2000         if (sclk < min)
2001                 return 0;
2002
2003         for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID;  ; i--) {
2004                 tmp = sclk / (1 << i);
2005                 if (tmp >= min || i == 0)
2006                         break;
2007         }
2008
2009         return (u8)i;
2010 }
2011
2012 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2013 {
2014         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2015 }
2016
2017 static int ci_reset_to_default(struct radeon_device *rdev)
2018 {
2019         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2020                 0 : -EINVAL;
2021 }
2022
2023 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2024 {
2025         u32 tmp;
2026
2027         tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2028
2029         if (tmp == MC_CG_ARB_FREQ_F0)
2030                 return 0;
2031
2032         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2033 }
2034
2035 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2036                                                 u32 sclk,
2037                                                 u32 mclk,
2038                                                 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2039 {
2040         u32 dram_timing;
2041         u32 dram_timing2;
2042         u32 burst_time;
2043
2044         radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2045
2046         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
2047         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2048         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2049
2050         arb_regs->McArbDramTiming  = cpu_to_be32(dram_timing);
2051         arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2052         arb_regs->McArbBurstTime = (u8)burst_time;
2053
2054         return 0;
2055 }
2056
2057 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2058 {
2059         struct ci_power_info *pi = ci_get_pi(rdev);
2060         SMU7_Discrete_MCArbDramTimingTable arb_regs;
2061         u32 i, j;
2062         int ret =  0;
2063
2064         memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2065
2066         for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2067                 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2068                         ret = ci_populate_memory_timing_parameters(rdev,
2069                                                                    pi->dpm_table.sclk_table.dpm_levels[i].value,
2070                                                                    pi->dpm_table.mclk_table.dpm_levels[j].value,
2071                                                                    &arb_regs.entries[i][j]);
2072                         if (ret)
2073                                 break;
2074                 }
2075         }
2076
2077         if (ret == 0)
2078                 ret = ci_copy_bytes_to_smc(rdev,
2079                                            pi->arb_table_start,
2080                                            (u8 *)&arb_regs,
2081                                            sizeof(SMU7_Discrete_MCArbDramTimingTable),
2082                                            pi->sram_end);
2083
2084         return ret;
2085 }
2086
2087 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2088 {
2089         struct ci_power_info *pi = ci_get_pi(rdev);
2090
2091         if (pi->need_update_smu7_dpm_table == 0)
2092                 return 0;
2093
2094         return ci_do_program_memory_timing_parameters(rdev);
2095 }
2096
2097 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2098                                           struct radeon_ps *radeon_boot_state)
2099 {
2100         struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2101         struct ci_power_info *pi = ci_get_pi(rdev);
2102         u32 level = 0;
2103
2104         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2105                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2106                     boot_state->performance_levels[0].sclk) {
2107                         pi->smc_state_table.GraphicsBootLevel = level;
2108                         break;
2109                 }
2110         }
2111
2112         for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2113                 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2114                     boot_state->performance_levels[0].mclk) {
2115                         pi->smc_state_table.MemoryBootLevel = level;
2116                         break;
2117                 }
2118         }
2119 }
2120
2121 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2122 {
2123         u32 i;
2124         u32 mask_value = 0;
2125
2126         for (i = dpm_table->count; i > 0; i--) {
2127                 mask_value = mask_value << 1;
2128                 if (dpm_table->dpm_levels[i-1].enabled)
2129                         mask_value |= 0x1;
2130                 else
2131                         mask_value &= 0xFFFFFFFE;
2132         }
2133
2134         return mask_value;
2135 }
2136
2137 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2138                                        SMU7_Discrete_DpmTable *table)
2139 {
2140         struct ci_power_info *pi = ci_get_pi(rdev);
2141         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2142         u32 i;
2143
2144         for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2145                 table->LinkLevel[i].PcieGenSpeed =
2146                         (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2147                 table->LinkLevel[i].PcieLaneCount =
2148                         r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2149                 table->LinkLevel[i].EnabledForActivity = 1;
2150                 table->LinkLevel[i].DownT = cpu_to_be32(5);
2151                 table->LinkLevel[i].UpT = cpu_to_be32(30);
2152         }
2153
2154         pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2155         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2156                 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2157 }
2158
2159 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2160                                      SMU7_Discrete_DpmTable *table)
2161 {
2162         u32 count;
2163         struct atom_clock_dividers dividers;
2164         int ret = -EINVAL;
2165
2166         table->UvdLevelCount =
2167                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2168
2169         for (count = 0; count < table->UvdLevelCount; count++) {
2170                 table->UvdLevel[count].VclkFrequency =
2171                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2172                 table->UvdLevel[count].DclkFrequency =
2173                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2174                 table->UvdLevel[count].MinVddc =
2175                         rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2176                 table->UvdLevel[count].MinVddcPhases = 1;
2177
2178                 ret = radeon_atom_get_clock_dividers(rdev,
2179                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2180                                                      table->UvdLevel[count].VclkFrequency, false, &dividers);
2181                 if (ret)
2182                         return ret;
2183
2184                 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2185
2186                 ret = radeon_atom_get_clock_dividers(rdev,
2187                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2188                                                      table->UvdLevel[count].DclkFrequency, false, &dividers);
2189                 if (ret)
2190                         return ret;
2191
2192                 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2193
2194                 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2195                 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2196                 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2197         }
2198
2199         return ret;
2200 }
2201
2202 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2203                                      SMU7_Discrete_DpmTable *table)
2204 {
2205         u32 count;
2206         struct atom_clock_dividers dividers;
2207         int ret = -EINVAL;
2208
2209         table->VceLevelCount =
2210                 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2211
2212         for (count = 0; count < table->VceLevelCount; count++) {
2213                 table->VceLevel[count].Frequency =
2214                         rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2215                 table->VceLevel[count].MinVoltage =
2216                         (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2217                 table->VceLevel[count].MinPhases = 1;
2218
2219                 ret = radeon_atom_get_clock_dividers(rdev,
2220                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2221                                                      table->VceLevel[count].Frequency, false, &dividers);
2222                 if (ret)
2223                         return ret;
2224
2225                 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2226
2227                 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2228                 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2229         }
2230
2231         return ret;
2232
2233 }
2234
2235 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2236                                      SMU7_Discrete_DpmTable *table)
2237 {
2238         u32 count;
2239         struct atom_clock_dividers dividers;
2240         int ret = -EINVAL;
2241
2242         table->AcpLevelCount = (u8)
2243                 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2244
2245         for (count = 0; count < table->AcpLevelCount; count++) {
2246                 table->AcpLevel[count].Frequency =
2247                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2248                 table->AcpLevel[count].MinVoltage =
2249                         rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2250                 table->AcpLevel[count].MinPhases = 1;
2251
2252                 ret = radeon_atom_get_clock_dividers(rdev,
2253                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2254                                                      table->AcpLevel[count].Frequency, false, &dividers);
2255                 if (ret)
2256                         return ret;
2257
2258                 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2259
2260                 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2261                 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2262         }
2263
2264         return ret;
2265 }
2266
2267 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2268                                       SMU7_Discrete_DpmTable *table)
2269 {
2270         u32 count;
2271         struct atom_clock_dividers dividers;
2272         int ret = -EINVAL;
2273
2274         table->SamuLevelCount =
2275                 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2276
2277         for (count = 0; count < table->SamuLevelCount; count++) {
2278                 table->SamuLevel[count].Frequency =
2279                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2280                 table->SamuLevel[count].MinVoltage =
2281                         rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2282                 table->SamuLevel[count].MinPhases = 1;
2283
2284                 ret = radeon_atom_get_clock_dividers(rdev,
2285                                                      COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2286                                                      table->SamuLevel[count].Frequency, false, &dividers);
2287                 if (ret)
2288                         return ret;
2289
2290                 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2291
2292                 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2293                 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2294         }
2295
2296         return ret;
2297 }
2298
2299 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2300                                     u32 memory_clock,
2301                                     SMU7_Discrete_MemoryLevel *mclk,
2302                                     bool strobe_mode,
2303                                     bool dll_state_on)
2304 {
2305         struct ci_power_info *pi = ci_get_pi(rdev);
2306         u32  dll_cntl = pi->clock_registers.dll_cntl;
2307         u32  mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2308         u32  mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2309         u32  mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2310         u32  mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2311         u32  mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2312         u32  mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2313         u32  mpll_ss1 = pi->clock_registers.mpll_ss1;
2314         u32  mpll_ss2 = pi->clock_registers.mpll_ss2;
2315         struct atom_mpll_param mpll_param;
2316         int ret;
2317
2318         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2319         if (ret)
2320                 return ret;
2321
2322         mpll_func_cntl &= ~BWCTRL_MASK;
2323         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2324
2325         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2326         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2327                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2328
2329         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2330         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2331
2332         if (pi->mem_gddr5) {
2333                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2334                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2335                         YCLK_POST_DIV(mpll_param.post_div);
2336         }
2337
2338         if (pi->caps_mclk_ss_support) {
2339                 struct radeon_atom_ss ss;
2340                 u32 freq_nom;
2341                 u32 tmp;
2342                 u32 reference_clock = rdev->clock.mpll.reference_freq;
2343
2344                 if (pi->mem_gddr5)
2345                         freq_nom = memory_clock * 4;
2346                 else
2347                         freq_nom = memory_clock * 2;
2348
2349                 tmp = (freq_nom / reference_clock);
2350                 tmp = tmp * tmp;
2351                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2352                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2353                         u32 clks = reference_clock * 5 / ss.rate;
2354                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2355
2356                         mpll_ss1 &= ~CLKV_MASK;
2357                         mpll_ss1 |= CLKV(clkv);
2358
2359                         mpll_ss2 &= ~CLKS_MASK;
2360                         mpll_ss2 |= CLKS(clks);
2361                 }
2362         }
2363
2364         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2365         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2366
2367         if (dll_state_on)
2368                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2369         else
2370                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2371
2372         mclk->MclkFrequency = memory_clock;
2373         mclk->MpllFuncCntl = mpll_func_cntl;
2374         mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2375         mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2376         mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2377         mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2378         mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2379         mclk->DllCntl = dll_cntl;
2380         mclk->MpllSs1 = mpll_ss1;
2381         mclk->MpllSs2 = mpll_ss2;
2382
2383         return 0;
2384 }
2385
2386 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2387                                            u32 memory_clock,
2388                                            SMU7_Discrete_MemoryLevel *memory_level)
2389 {
2390         struct ci_power_info *pi = ci_get_pi(rdev);
2391         int ret;
2392         bool dll_state_on;
2393
2394         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2395                 ret = ci_get_dependency_volt_by_clk(rdev,
2396                                                     &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2397                                                     memory_clock, &memory_level->MinVddc);
2398                 if (ret)
2399                         return ret;
2400         }
2401
2402         if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2403                 ret = ci_get_dependency_volt_by_clk(rdev,
2404                                                     &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2405                                                     memory_clock, &memory_level->MinVddci);
2406                 if (ret)
2407                         return ret;
2408         }
2409
2410         if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2411                 ret = ci_get_dependency_volt_by_clk(rdev,
2412                                                     &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2413                                                     memory_clock, &memory_level->MinMvdd);
2414                 if (ret)
2415                         return ret;
2416         }
2417
2418         memory_level->MinVddcPhases = 1;
2419
2420         if (pi->vddc_phase_shed_control)
2421                 ci_populate_phase_value_based_on_mclk(rdev,
2422                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2423                                                       memory_clock,
2424                                                       &memory_level->MinVddcPhases);
2425
2426         memory_level->EnabledForThrottle = 1;
2427         memory_level->EnabledForActivity = 1;
2428         memory_level->UpH = 0;
2429         memory_level->DownH = 100;
2430         memory_level->VoltageDownH = 0;
2431         memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2432
2433         memory_level->StutterEnable = false;
2434         memory_level->StrobeEnable = false;
2435         memory_level->EdcReadEnable = false;
2436         memory_level->EdcWriteEnable = false;
2437         memory_level->RttEnable = false;
2438
2439         memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2440
2441         if (pi->mclk_stutter_mode_threshold &&
2442             (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2443             (pi->uvd_enabled == false) &&
2444             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2445             (rdev->pm.dpm.new_active_crtc_count <= 2))
2446                 memory_level->StutterEnable = true;
2447
2448         if (pi->mclk_strobe_mode_threshold &&
2449             (memory_clock <= pi->mclk_strobe_mode_threshold))
2450                 memory_level->StrobeEnable = 1;
2451
2452         if (pi->mem_gddr5) {
2453                 memory_level->StrobeRatio =
2454                         si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2455                 if (pi->mclk_edc_enable_threshold &&
2456                     (memory_clock > pi->mclk_edc_enable_threshold))
2457                         memory_level->EdcReadEnable = true;
2458
2459                 if (pi->mclk_edc_wr_enable_threshold &&
2460                     (memory_clock > pi->mclk_edc_wr_enable_threshold))
2461                         memory_level->EdcWriteEnable = true;
2462
2463                 if (memory_level->StrobeEnable) {
2464                         if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2465                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2466                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2467                         else
2468                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2469                 } else {
2470                         dll_state_on = pi->dll_default_on;
2471                 }
2472         } else {
2473                 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2474                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2475         }
2476
2477         ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2478         if (ret)
2479                 return ret;
2480
2481         memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2482         memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2483         memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2484         memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2485
2486         memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2487         memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2488         memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2489         memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2490         memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2491         memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2492         memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2493         memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2494         memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2495         memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2496         memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2497
2498         return 0;
2499 }
2500
2501 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2502                                       SMU7_Discrete_DpmTable *table)
2503 {
2504         struct ci_power_info *pi = ci_get_pi(rdev);
2505         struct atom_clock_dividers dividers;
2506         SMU7_Discrete_VoltageLevel voltage_level;
2507         u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2508         u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2509         u32 dll_cntl = pi->clock_registers.dll_cntl;
2510         u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2511         int ret;
2512
2513         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2514
2515         if (pi->acpi_vddc)
2516                 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2517         else
2518                 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2519
2520         table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2521
2522         table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2523
2524         ret = radeon_atom_get_clock_dividers(rdev,
2525                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2526                                              table->ACPILevel.SclkFrequency, false, &dividers);
2527         if (ret)
2528                 return ret;
2529
2530         table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2531         table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2532         table->ACPILevel.DeepSleepDivId = 0;
2533
2534         spll_func_cntl &= ~SPLL_PWRON;
2535         spll_func_cntl |= SPLL_RESET;
2536
2537         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2538         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
2539
2540         table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2541         table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2542         table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2543         table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
2544         table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
2545         table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2546         table->ACPILevel.CcPwrDynRm = 0;
2547         table->ACPILevel.CcPwrDynRm1 = 0;
2548
2549         table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
2550         table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
2551         table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
2552         table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
2553         table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
2554         table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
2555         table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
2556         table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
2557         table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
2558         table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
2559         table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
2560
2561         table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
2562         table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
2563
2564         if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2565                 if (pi->acpi_vddci)
2566                         table->MemoryACPILevel.MinVddci =
2567                                 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
2568                 else
2569                         table->MemoryACPILevel.MinVddci =
2570                                 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
2571         }
2572
2573         if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
2574                 table->MemoryACPILevel.MinMvdd = 0;
2575         else
2576                 table->MemoryACPILevel.MinMvdd =
2577                         cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
2578
2579         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
2580         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2581
2582         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
2583
2584         table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
2585         table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
2586         table->MemoryACPILevel.MpllAdFuncCntl =
2587                 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
2588         table->MemoryACPILevel.MpllDqFuncCntl =
2589                 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
2590         table->MemoryACPILevel.MpllFuncCntl =
2591                 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
2592         table->MemoryACPILevel.MpllFuncCntl_1 =
2593                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
2594         table->MemoryACPILevel.MpllFuncCntl_2 =
2595                 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
2596         table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
2597         table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
2598
2599         table->MemoryACPILevel.EnabledForThrottle = 0;
2600         table->MemoryACPILevel.EnabledForActivity = 0;
2601         table->MemoryACPILevel.UpH = 0;
2602         table->MemoryACPILevel.DownH = 100;
2603         table->MemoryACPILevel.VoltageDownH = 0;
2604         table->MemoryACPILevel.ActivityLevel =
2605                 cpu_to_be16((u16)pi->mclk_activity_target);
2606
2607         table->MemoryACPILevel.StutterEnable = false;
2608         table->MemoryACPILevel.StrobeEnable = false;
2609         table->MemoryACPILevel.EdcReadEnable = false;
2610         table->MemoryACPILevel.EdcWriteEnable = false;
2611         table->MemoryACPILevel.RttEnable = false;
2612
2613         return 0;
2614 }
2615
2616
2617 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
2618 {
2619         struct ci_power_info *pi = ci_get_pi(rdev);
2620         struct ci_ulv_parm *ulv = &pi->ulv;
2621
2622         if (ulv->supported) {
2623                 if (enable)
2624                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
2625                                 0 : -EINVAL;
2626                 else
2627                         return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
2628                                 0 : -EINVAL;
2629         }
2630
2631         return 0;
2632 }
2633
2634 static int ci_populate_ulv_level(struct radeon_device *rdev,
2635                                  SMU7_Discrete_Ulv *state)
2636 {
2637         struct ci_power_info *pi = ci_get_pi(rdev);
2638         u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
2639
2640         state->CcPwrDynRm = 0;
2641         state->CcPwrDynRm1 = 0;
2642
2643         if (ulv_voltage == 0) {
2644                 pi->ulv.supported = false;
2645                 return 0;
2646         }
2647
2648         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2649                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2650                         state->VddcOffset = 0;
2651                 else
2652                         state->VddcOffset =
2653                                 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
2654         } else {
2655                 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
2656                         state->VddcOffsetVid = 0;
2657                 else
2658                         state->VddcOffsetVid = (u8)
2659                                 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
2660                                  VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
2661         }
2662         state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
2663
2664         state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
2665         state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
2666         state->VddcOffset = cpu_to_be16(state->VddcOffset);
2667
2668         return 0;
2669 }
2670
2671 static int ci_calculate_sclk_params(struct radeon_device *rdev,
2672                                     u32 engine_clock,
2673                                     SMU7_Discrete_GraphicsLevel *sclk)
2674 {
2675         struct ci_power_info *pi = ci_get_pi(rdev);
2676         struct atom_clock_dividers dividers;
2677         u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
2678         u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
2679         u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
2680         u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2681         u32 reference_clock = rdev->clock.spll.reference_freq;
2682         u32 reference_divider;
2683         u32 fbdiv;
2684         int ret;
2685
2686         ret = radeon_atom_get_clock_dividers(rdev,
2687                                              COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2688                                              engine_clock, false, &dividers);
2689         if (ret)
2690                 return ret;
2691
2692         reference_divider = 1 + dividers.ref_div;
2693         fbdiv = dividers.fb_div & 0x3FFFFFF;
2694
2695         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2696         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2697         spll_func_cntl_3 |= SPLL_DITHEN;
2698
2699         if (pi->caps_sclk_ss_support) {
2700                 struct radeon_atom_ss ss;
2701                 u32 vco_freq = engine_clock * dividers.post_div;
2702
2703                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2704                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2705                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2706                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2707
2708                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
2709                         cg_spll_spread_spectrum |= CLK_S(clk_s);
2710                         cg_spll_spread_spectrum |= SSEN;
2711
2712                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2713                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2714                 }
2715         }
2716
2717         sclk->SclkFrequency = engine_clock;
2718         sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
2719         sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
2720         sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
2721         sclk->SpllSpreadSpectrum2  = cg_spll_spread_spectrum_2;
2722         sclk->SclkDid = (u8)dividers.post_divider;
2723
2724         return 0;
2725 }
2726
2727 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
2728                                             u32 engine_clock,
2729                                             u16 sclk_activity_level_t,
2730                                             SMU7_Discrete_GraphicsLevel *graphic_level)
2731 {
2732         struct ci_power_info *pi = ci_get_pi(rdev);
2733         int ret;
2734
2735         ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
2736         if (ret)
2737                 return ret;
2738
2739         ret = ci_get_dependency_volt_by_clk(rdev,
2740                                             &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2741                                             engine_clock, &graphic_level->MinVddc);
2742         if (ret)
2743                 return ret;
2744
2745         graphic_level->SclkFrequency = engine_clock;
2746
2747         graphic_level->Flags =  0;
2748         graphic_level->MinVddcPhases = 1;
2749
2750         if (pi->vddc_phase_shed_control)
2751                 ci_populate_phase_value_based_on_sclk(rdev,
2752                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2753                                                       engine_clock,
2754                                                       &graphic_level->MinVddcPhases);
2755
2756         graphic_level->ActivityLevel = sclk_activity_level_t;
2757
2758         graphic_level->CcPwrDynRm = 0;
2759         graphic_level->CcPwrDynRm1 = 0;
2760         graphic_level->EnabledForActivity = 1;
2761         graphic_level->EnabledForThrottle = 1;
2762         graphic_level->UpH = 0;
2763         graphic_level->DownH = 0;
2764         graphic_level->VoltageDownH = 0;
2765         graphic_level->PowerThrottle = 0;
2766
2767         if (pi->caps_sclk_ds)
2768                 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
2769                                                                                    engine_clock,
2770                                                                                    CISLAND_MINIMUM_ENGINE_CLOCK);
2771
2772         graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2773
2774         graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
2775         graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
2776         graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
2777         graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
2778         graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
2779         graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
2780         graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
2781         graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
2782         graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
2783         graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
2784         graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
2785
2786         return 0;
2787 }
2788
2789 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
2790 {
2791         struct ci_power_info *pi = ci_get_pi(rdev);
2792         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2793         u32 level_array_address = pi->dpm_table_start +
2794                 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
2795         u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
2796                 SMU7_MAX_LEVELS_GRAPHICS;
2797         SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
2798         u32 i, ret;
2799
2800         memset(levels, 0, level_array_size);
2801
2802         for (i = 0; i < dpm_table->sclk_table.count; i++) {
2803                 ret = ci_populate_single_graphic_level(rdev,
2804                                                        dpm_table->sclk_table.dpm_levels[i].value,
2805                                                        (u16)pi->activity_target[i],
2806                                                        &pi->smc_state_table.GraphicsLevel[i]);
2807                 if (ret)
2808                         return ret;
2809                 if (i == (dpm_table->sclk_table.count - 1))
2810                         pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
2811                                 PPSMC_DISPLAY_WATERMARK_HIGH;
2812         }
2813
2814         pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
2815         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
2816                 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
2817
2818         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2819                                    (u8 *)levels, level_array_size,
2820                                    pi->sram_end);
2821         if (ret)
2822                 return ret;
2823
2824         return 0;
2825 }
2826
2827 static int ci_populate_ulv_state(struct radeon_device *rdev,
2828                                  SMU7_Discrete_Ulv *ulv_level)
2829 {
2830         return ci_populate_ulv_level(rdev, ulv_level);
2831 }
2832
2833 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
2834 {
2835         struct ci_power_info *pi = ci_get_pi(rdev);
2836         struct ci_dpm_table *dpm_table = &pi->dpm_table;
2837         u32 level_array_address = pi->dpm_table_start +
2838                 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
2839         u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
2840                 SMU7_MAX_LEVELS_MEMORY;
2841         SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
2842         u32 i, ret;
2843
2844         memset(levels, 0, level_array_size);
2845
2846         for (i = 0; i < dpm_table->mclk_table.count; i++) {
2847                 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
2848                         return -EINVAL;
2849                 ret = ci_populate_single_memory_level(rdev,
2850                                                       dpm_table->mclk_table.dpm_levels[i].value,
2851                                                       &pi->smc_state_table.MemoryLevel[i]);
2852                 if (ret)
2853                         return ret;
2854         }
2855
2856         pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
2857
2858         pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
2859         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
2860                 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
2861
2862         pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
2863                 PPSMC_DISPLAY_WATERMARK_HIGH;
2864
2865         ret = ci_copy_bytes_to_smc(rdev, level_array_address,
2866                                    (u8 *)levels, level_array_size,
2867                                    pi->sram_end);
2868         if (ret)
2869                 return ret;
2870
2871         return 0;
2872 }
2873
2874 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
2875                                       struct ci_single_dpm_table* dpm_table,
2876                                       u32 count)
2877 {
2878         u32 i;
2879
2880         dpm_table->count = count;
2881         for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
2882                 dpm_table->dpm_levels[i].enabled = false;
2883 }
2884
2885 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
2886                                       u32 index, u32 pcie_gen, u32 pcie_lanes)
2887 {
2888         dpm_table->dpm_levels[index].value = pcie_gen;
2889         dpm_table->dpm_levels[index].param1 = pcie_lanes;
2890         dpm_table->dpm_levels[index].enabled = true;
2891 }
2892
2893 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
2894 {
2895         struct ci_power_info *pi = ci_get_pi(rdev);
2896
2897         if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
2898                 return -EINVAL;
2899
2900         if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
2901                 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
2902                 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
2903         } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
2904                 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
2905                 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
2906         }
2907
2908         ci_reset_single_dpm_table(rdev,
2909                                   &pi->dpm_table.pcie_speed_table,
2910                                   SMU7_MAX_LEVELS_LINK);
2911
2912         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
2913                                   pi->pcie_gen_powersaving.min,
2914                                   pi->pcie_lane_powersaving.min);
2915         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
2916                                   pi->pcie_gen_performance.min,
2917                                   pi->pcie_lane_performance.min);
2918         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
2919                                   pi->pcie_gen_powersaving.min,
2920                                   pi->pcie_lane_powersaving.max);
2921         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
2922                                   pi->pcie_gen_performance.min,
2923                                   pi->pcie_lane_performance.max);
2924         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
2925                                   pi->pcie_gen_powersaving.max,
2926                                   pi->pcie_lane_powersaving.max);
2927         ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
2928                                   pi->pcie_gen_performance.max,
2929                                   pi->pcie_lane_performance.max);
2930
2931         pi->dpm_table.pcie_speed_table.count = 6;
2932
2933         return 0;
2934 }
2935
2936 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
2937 {
2938         struct ci_power_info *pi = ci_get_pi(rdev);
2939         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
2940                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2941         struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
2942                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
2943         struct radeon_cac_leakage_table *std_voltage_table =
2944                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2945         u32 i;
2946
2947         if (allowed_sclk_vddc_table == NULL)
2948                 return -EINVAL;
2949         if (allowed_sclk_vddc_table->count < 1)
2950                 return -EINVAL;
2951         if (allowed_mclk_table == NULL)
2952                 return -EINVAL;
2953         if (allowed_mclk_table->count < 1)
2954                 return -EINVAL;
2955
2956         memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
2957
2958         ci_reset_single_dpm_table(rdev,
2959                                   &pi->dpm_table.sclk_table,
2960                                   SMU7_MAX_LEVELS_GRAPHICS);
2961         ci_reset_single_dpm_table(rdev,
2962                                   &pi->dpm_table.mclk_table,
2963                                   SMU7_MAX_LEVELS_MEMORY);
2964         ci_reset_single_dpm_table(rdev,
2965                                   &pi->dpm_table.vddc_table,
2966                                   SMU7_MAX_LEVELS_VDDC);
2967         ci_reset_single_dpm_table(rdev,
2968                                   &pi->dpm_table.vddci_table,
2969                                   SMU7_MAX_LEVELS_VDDCI);
2970         ci_reset_single_dpm_table(rdev,
2971                                   &pi->dpm_table.mvdd_table,
2972                                   SMU7_MAX_LEVELS_MVDD);
2973
2974         pi->dpm_table.sclk_table.count = 0;
2975         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
2976                 if ((i == 0) ||
2977                     (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
2978                      allowed_sclk_vddc_table->entries[i].clk)) {
2979                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
2980                                 allowed_sclk_vddc_table->entries[i].clk;
2981                         pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = true;
2982                         pi->dpm_table.sclk_table.count++;
2983                 }
2984         }
2985
2986         pi->dpm_table.mclk_table.count = 0;
2987         for (i = 0; i < allowed_mclk_table->count; i++) {
2988                 if ((i==0) ||
2989                     (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
2990                      allowed_mclk_table->entries[i].clk)) {
2991                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
2992                                 allowed_mclk_table->entries[i].clk;
2993                         pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = true;
2994                         pi->dpm_table.mclk_table.count++;
2995                 }
2996         }
2997
2998         for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
2999                 pi->dpm_table.vddc_table.dpm_levels[i].value =
3000                         allowed_sclk_vddc_table->entries[i].v;
3001                 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3002                         std_voltage_table->entries[i].leakage;
3003                 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3004         }
3005         pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3006
3007         allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3008         if (allowed_mclk_table) {
3009                 for (i = 0; i < allowed_mclk_table->count; i++) {
3010                         pi->dpm_table.vddci_table.dpm_levels[i].value =
3011                                 allowed_mclk_table->entries[i].v;
3012                         pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3013                 }
3014                 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3015         }
3016
3017         allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3018         if (allowed_mclk_table) {
3019                 for (i = 0; i < allowed_mclk_table->count; i++) {
3020                         pi->dpm_table.mvdd_table.dpm_levels[i].value =
3021                                 allowed_mclk_table->entries[i].v;
3022                         pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3023                 }
3024                 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3025         }
3026
3027         ci_setup_default_pcie_tables(rdev);
3028
3029         return 0;
3030 }
3031
3032 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3033                               u32 value, u32 *boot_level)
3034 {
3035         u32 i;
3036         int ret = -EINVAL;
3037
3038         for(i = 0; i < table->count; i++) {
3039                 if (value == table->dpm_levels[i].value) {
3040                         *boot_level = i;
3041                         ret = 0;
3042                 }
3043         }
3044
3045         return ret;
3046 }
3047
3048 static int ci_init_smc_table(struct radeon_device *rdev)
3049 {
3050         struct ci_power_info *pi = ci_get_pi(rdev);
3051         struct ci_ulv_parm *ulv = &pi->ulv;
3052         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3053         SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3054         int ret;
3055
3056         ret = ci_setup_default_dpm_tables(rdev);
3057         if (ret)
3058                 return ret;
3059
3060         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3061                 ci_populate_smc_voltage_tables(rdev, table);
3062
3063         ci_init_fps_limits(rdev);
3064
3065         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3066                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3067
3068         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3069                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3070
3071         if (pi->mem_gddr5)
3072                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3073
3074         if (ulv->supported) {
3075                 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3076                 if (ret)
3077                         return ret;
3078                 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3079         }
3080
3081         ret = ci_populate_all_graphic_levels(rdev);
3082         if (ret)
3083                 return ret;
3084
3085         ret = ci_populate_all_memory_levels(rdev);
3086         if (ret)
3087                 return ret;
3088
3089         ci_populate_smc_link_level(rdev, table);
3090
3091         ret = ci_populate_smc_acpi_level(rdev, table);
3092         if (ret)
3093                 return ret;
3094
3095         ret = ci_populate_smc_vce_level(rdev, table);
3096         if (ret)
3097                 return ret;
3098
3099         ret = ci_populate_smc_acp_level(rdev, table);
3100         if (ret)
3101                 return ret;
3102
3103         ret = ci_populate_smc_samu_level(rdev, table);
3104         if (ret)
3105                 return ret;
3106
3107         ret = ci_do_program_memory_timing_parameters(rdev);
3108         if (ret)
3109                 return ret;
3110
3111         ret = ci_populate_smc_uvd_level(rdev, table);
3112         if (ret)
3113                 return ret;
3114
3115         table->UvdBootLevel  = 0;
3116         table->VceBootLevel  = 0;
3117         table->AcpBootLevel  = 0;
3118         table->SamuBootLevel  = 0;
3119         table->GraphicsBootLevel  = 0;
3120         table->MemoryBootLevel  = 0;
3121
3122         ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3123                                  pi->vbios_boot_state.sclk_bootup_value,
3124                                  (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3125
3126         ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3127                                  pi->vbios_boot_state.mclk_bootup_value,
3128                                  (u32 *)&pi->smc_state_table.MemoryBootLevel);
3129
3130         table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3131         table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3132         table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3133
3134         ci_populate_smc_initial_state(rdev, radeon_boot_state);
3135
3136         ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3137         if (ret)
3138                 return ret;
3139
3140         table->UVDInterval = 1;
3141         table->VCEInterval = 1;
3142         table->ACPInterval = 1;
3143         table->SAMUInterval = 1;
3144         table->GraphicsVoltageChangeEnable = 1;
3145         table->GraphicsThermThrottleEnable = 1;
3146         table->GraphicsInterval = 1;
3147         table->VoltageInterval = 1;
3148         table->ThermalInterval = 1;
3149         table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3150                                              CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3151         table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3152                                             CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3153         table->MemoryVoltageChangeEnable = 1;
3154         table->MemoryInterval = 1;
3155         table->VoltageResponseTime = 0;
3156         table->VddcVddciDelta = 4000;
3157         table->PhaseResponseTime = 0;
3158         table->MemoryThermThrottleEnable = 1;
3159         table->PCIeBootLinkLevel = 0;
3160         table->PCIeGenInterval = 1;
3161         if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3162                 table->SVI2Enable  = 1;
3163         else
3164                 table->SVI2Enable  = 0;
3165
3166         table->ThermGpio = 17;
3167         table->SclkStepSize = 0x4000;
3168
3169         table->SystemFlags = cpu_to_be32(table->SystemFlags);
3170         table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3171         table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3172         table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3173         table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3174         table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3175         table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3176         table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3177         table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3178         table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3179         table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3180         table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3181         table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3182         table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3183
3184         ret = ci_copy_bytes_to_smc(rdev,
3185                                    pi->dpm_table_start +
3186                                    offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3187                                    (u8 *)&table->SystemFlags,
3188                                    sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3189                                    pi->sram_end);
3190         if (ret)
3191                 return ret;
3192
3193         return 0;
3194 }
3195
3196 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3197                                       struct ci_single_dpm_table *dpm_table,
3198                                       u32 low_limit, u32 high_limit)
3199 {
3200         u32 i;
3201
3202         for (i = 0; i < dpm_table->count; i++) {
3203                 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3204                     (dpm_table->dpm_levels[i].value > high_limit))
3205                         dpm_table->dpm_levels[i].enabled = false;
3206                 else
3207                         dpm_table->dpm_levels[i].enabled = true;
3208         }
3209 }
3210
3211 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3212                                     u32 speed_low, u32 lanes_low,
3213                                     u32 speed_high, u32 lanes_high)
3214 {
3215         struct ci_power_info *pi = ci_get_pi(rdev);
3216         struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3217         u32 i, j;
3218
3219         for (i = 0; i < pcie_table->count; i++) {
3220                 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3221                     (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3222                     (pcie_table->dpm_levels[i].value > speed_high) ||
3223                     (pcie_table->dpm_levels[i].param1 > lanes_high))
3224                         pcie_table->dpm_levels[i].enabled = false;
3225                 else
3226                         pcie_table->dpm_levels[i].enabled = true;
3227         }
3228
3229         for (i = 0; i < pcie_table->count; i++) {
3230                 if (pcie_table->dpm_levels[i].enabled) {
3231                         for (j = i + 1; j < pcie_table->count; j++) {
3232                                 if (pcie_table->dpm_levels[j].enabled) {
3233                                         if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3234                                             (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3235                                                 pcie_table->dpm_levels[j].enabled = false;
3236                                 }
3237                         }
3238                 }
3239         }
3240 }
3241
3242 static int ci_trim_dpm_states(struct radeon_device *rdev,
3243                               struct radeon_ps *radeon_state)
3244 {
3245         struct ci_ps *state = ci_get_ps(radeon_state);
3246         struct ci_power_info *pi = ci_get_pi(rdev);
3247         u32 high_limit_count;
3248
3249         if (state->performance_level_count < 1)
3250                 return -EINVAL;
3251
3252         if (state->performance_level_count == 1)
3253                 high_limit_count = 0;
3254         else
3255                 high_limit_count = 1;
3256
3257         ci_trim_single_dpm_states(rdev,
3258                                   &pi->dpm_table.sclk_table,
3259                                   state->performance_levels[0].sclk,
3260                                   state->performance_levels[high_limit_count].sclk);
3261
3262         ci_trim_single_dpm_states(rdev,
3263                                   &pi->dpm_table.mclk_table,
3264                                   state->performance_levels[0].mclk,
3265                                   state->performance_levels[high_limit_count].mclk);
3266
3267         ci_trim_pcie_dpm_states(rdev,
3268                                 state->performance_levels[0].pcie_gen,
3269                                 state->performance_levels[0].pcie_lane,
3270                                 state->performance_levels[high_limit_count].pcie_gen,
3271                                 state->performance_levels[high_limit_count].pcie_lane);
3272
3273         return 0;
3274 }
3275
3276 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3277 {
3278         struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3279                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3280         struct radeon_clock_voltage_dependency_table *vddc_table =
3281                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3282         u32 requested_voltage = 0;
3283         u32 i;
3284
3285         if (disp_voltage_table == NULL)
3286                 return -EINVAL;
3287         if (!disp_voltage_table->count)
3288                 return -EINVAL;
3289
3290         for (i = 0; i < disp_voltage_table->count; i++) {
3291                 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3292                         requested_voltage = disp_voltage_table->entries[i].v;
3293         }
3294
3295         for (i = 0; i < vddc_table->count; i++) {
3296                 if (requested_voltage <= vddc_table->entries[i].v) {
3297                         requested_voltage = vddc_table->entries[i].v;
3298                         return (ci_send_msg_to_smc_with_parameter(rdev,
3299                                                                   PPSMC_MSG_VddC_Request,
3300                                                                   requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3301                                 0 : -EINVAL;
3302                 }
3303         }
3304
3305         return -EINVAL;
3306 }
3307
3308 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3309 {
3310         struct ci_power_info *pi = ci_get_pi(rdev);
3311         PPSMC_Result result;
3312
3313         if (!pi->sclk_dpm_key_disabled) {
3314                 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3315                         result = ci_send_msg_to_smc_with_parameter(rdev,
3316                                                                    PPSMC_MSG_SCLKDPM_SetEnabledMask,
3317                                                                    pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3318                         if (result != PPSMC_Result_OK)
3319                                 return -EINVAL;
3320                 }
3321         }
3322
3323         if (!pi->mclk_dpm_key_disabled) {
3324                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3325                         result = ci_send_msg_to_smc_with_parameter(rdev,
3326                                                                    PPSMC_MSG_MCLKDPM_SetEnabledMask,
3327                                                                    pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3328                         if (result != PPSMC_Result_OK)
3329                                 return -EINVAL;
3330                 }
3331         }
3332
3333         if (!pi->pcie_dpm_key_disabled) {
3334                 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3335                         result = ci_send_msg_to_smc_with_parameter(rdev,
3336                                                                    PPSMC_MSG_PCIeDPM_SetEnabledMask,
3337                                                                    pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3338                         if (result != PPSMC_Result_OK)
3339                                 return -EINVAL;
3340                 }
3341         }
3342
3343         ci_apply_disp_minimum_voltage_request(rdev);
3344
3345         return 0;
3346 }
3347
3348 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3349                                                    struct radeon_ps *radeon_state)
3350 {
3351         struct ci_power_info *pi = ci_get_pi(rdev);
3352         struct ci_ps *state = ci_get_ps(radeon_state);
3353         struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3354         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3355         struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3356         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3357         u32 i;
3358
3359         pi->need_update_smu7_dpm_table = 0;
3360
3361         for (i = 0; i < sclk_table->count; i++) {
3362                 if (sclk == sclk_table->dpm_levels[i].value)
3363                         break;
3364         }
3365
3366         if (i >= sclk_table->count) {
3367                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3368         } else {
3369                 /* XXX check display min clock requirements */
3370                 if (0 != CISLAND_MINIMUM_ENGINE_CLOCK)
3371                         pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3372         }
3373
3374         for (i = 0; i < mclk_table->count; i++) {
3375                 if (mclk == mclk_table->dpm_levels[i].value)
3376                         break;
3377         }
3378
3379         if (i >= mclk_table->count)
3380                 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3381
3382         if (rdev->pm.dpm.current_active_crtc_count !=
3383             rdev->pm.dpm.new_active_crtc_count)
3384                 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3385 }
3386
3387 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3388                                                        struct radeon_ps *radeon_state)
3389 {
3390         struct ci_power_info *pi = ci_get_pi(rdev);
3391         struct ci_ps *state = ci_get_ps(radeon_state);
3392         u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3393         u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3394         struct ci_dpm_table *dpm_table = &pi->dpm_table;
3395         int ret;
3396
3397         if (!pi->need_update_smu7_dpm_table)
3398                 return 0;
3399
3400         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3401                 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3402
3403         if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3404                 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3405
3406         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3407                 ret = ci_populate_all_graphic_levels(rdev);
3408                 if (ret)
3409                         return ret;
3410         }
3411
3412         if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3413                 ret = ci_populate_all_memory_levels(rdev);
3414                 if (ret)
3415                         return ret;
3416         }
3417
3418         return 0;
3419 }
3420
3421 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3422 {
3423         struct ci_power_info *pi = ci_get_pi(rdev);
3424         const struct radeon_clock_and_voltage_limits *max_limits;
3425         int i;
3426
3427         if (rdev->pm.dpm.ac_power)
3428                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3429         else
3430                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3431
3432         if (enable) {
3433                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3434
3435                 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3436                         if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3437                                 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3438
3439                                 if (!pi->caps_uvd_dpm)
3440                                         break;
3441                         }
3442                 }
3443
3444                 ci_send_msg_to_smc_with_parameter(rdev,
3445                                                   PPSMC_MSG_UVDDPM_SetEnabledMask,
3446                                                   pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3447
3448                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3449                         pi->uvd_enabled = true;
3450                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3451                         ci_send_msg_to_smc_with_parameter(rdev,
3452                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3453                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3454                 }
3455         } else {
3456                 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3457                         pi->uvd_enabled = false;
3458                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3459                         ci_send_msg_to_smc_with_parameter(rdev,
3460                                                           PPSMC_MSG_MCLKDPM_SetEnabledMask,
3461                                                           pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3462                 }
3463         }
3464
3465         return (ci_send_msg_to_smc(rdev, enable ?
3466                                    PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3467                 0 : -EINVAL;
3468 }
3469
3470 #if 0
3471 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3472 {
3473         struct ci_power_info *pi = ci_get_pi(rdev);
3474         const struct radeon_clock_and_voltage_limits *max_limits;
3475         int i;
3476
3477         if (rdev->pm.dpm.ac_power)
3478                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3479         else
3480                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3481
3482         if (enable) {
3483                 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3484                 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3485                         if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3486                                 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3487
3488                                 if (!pi->caps_vce_dpm)
3489                                         break;
3490                         }
3491                 }
3492
3493                 ci_send_msg_to_smc_with_parameter(rdev,
3494                                                   PPSMC_MSG_VCEDPM_SetEnabledMask,
3495                                                   pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3496         }
3497
3498         return (ci_send_msg_to_smc(rdev, enable ?
3499                                    PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3500                 0 : -EINVAL;
3501 }
3502
3503 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3504 {
3505         struct ci_power_info *pi = ci_get_pi(rdev);
3506         const struct radeon_clock_and_voltage_limits *max_limits;
3507         int i;
3508
3509         if (rdev->pm.dpm.ac_power)
3510                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3511         else
3512                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3513
3514         if (enable) {
3515                 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3516                 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3517                         if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3518                                 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3519
3520                                 if (!pi->caps_samu_dpm)
3521                                         break;
3522                         }
3523                 }
3524
3525                 ci_send_msg_to_smc_with_parameter(rdev,
3526                                                   PPSMC_MSG_SAMUDPM_SetEnabledMask,
3527                                                   pi->dpm_level_enable_mask.samu_dpm_enable_mask);
3528         }
3529         return (ci_send_msg_to_smc(rdev, enable ?
3530                                    PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
3531                 0 : -EINVAL;
3532 }
3533
3534 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
3535 {
3536         struct ci_power_info *pi = ci_get_pi(rdev);
3537         const struct radeon_clock_and_voltage_limits *max_limits;
3538         int i;
3539
3540         if (rdev->pm.dpm.ac_power)
3541                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3542         else
3543                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3544
3545         if (enable) {
3546                 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
3547                 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3548                         if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3549                                 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
3550
3551                                 if (!pi->caps_acp_dpm)
3552                                         break;
3553                         }
3554                 }
3555
3556                 ci_send_msg_to_smc_with_parameter(rdev,
3557                                                   PPSMC_MSG_ACPDPM_SetEnabledMask,
3558                                                   pi->dpm_level_enable_mask.acp_dpm_enable_mask);
3559         }
3560
3561         return (ci_send_msg_to_smc(rdev, enable ?
3562                                    PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
3563                 0 : -EINVAL;
3564 }
3565 #endif
3566
3567 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
3568 {
3569         struct ci_power_info *pi = ci_get_pi(rdev);
3570         u32 tmp;
3571
3572         if (!gate) {
3573                 if (pi->caps_uvd_dpm ||
3574                     (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
3575                         pi->smc_state_table.UvdBootLevel = 0;
3576                 else
3577                         pi->smc_state_table.UvdBootLevel =
3578                                 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
3579
3580                 tmp = RREG32_SMC(DPM_TABLE_475);
3581                 tmp &= ~UvdBootLevel_MASK;
3582                 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
3583                 WREG32_SMC(DPM_TABLE_475, tmp);
3584         }
3585
3586         return ci_enable_uvd_dpm(rdev, !gate);
3587 }
3588
3589 #if 0
3590 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
3591 {
3592         u8 i;
3593         u32 min_evclk = 30000; /* ??? */
3594         struct radeon_vce_clock_voltage_dependency_table *table =
3595                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3596
3597         for (i = 0; i < table->count; i++) {
3598                 if (table->entries[i].evclk >= min_evclk)
3599                         return i;
3600         }
3601
3602         return table->count - 1;
3603 }
3604
3605 static int ci_update_vce_dpm(struct radeon_device *rdev,
3606                              struct radeon_ps *radeon_new_state,
3607                              struct radeon_ps *radeon_current_state)
3608 {
3609         struct ci_power_info *pi = ci_get_pi(rdev);
3610         bool new_vce_clock_non_zero = (radeon_new_state->evclk != 0);
3611         bool old_vce_clock_non_zero = (radeon_current_state->evclk != 0);
3612         int ret = 0;
3613         u32 tmp;
3614
3615         if (new_vce_clock_non_zero != old_vce_clock_non_zero) {
3616                 if (new_vce_clock_non_zero) {
3617                         pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
3618
3619                         tmp = RREG32_SMC(DPM_TABLE_475);
3620                         tmp &= ~VceBootLevel_MASK;
3621                         tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
3622                         WREG32_SMC(DPM_TABLE_475, tmp);
3623
3624                         ret = ci_enable_vce_dpm(rdev, true);
3625                 } else {
3626                         ret = ci_enable_vce_dpm(rdev, false);
3627                 }
3628         }
3629         return ret;
3630 }
3631
3632 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
3633 {
3634         return ci_enable_samu_dpm(rdev, gate);
3635 }
3636
3637 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
3638 {
3639         struct ci_power_info *pi = ci_get_pi(rdev);
3640         u32 tmp;
3641
3642         if (!gate) {
3643                 pi->smc_state_table.AcpBootLevel = 0;
3644
3645                 tmp = RREG32_SMC(DPM_TABLE_475);
3646                 tmp &= ~AcpBootLevel_MASK;
3647                 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
3648                 WREG32_SMC(DPM_TABLE_475, tmp);
3649         }
3650
3651         return ci_enable_acp_dpm(rdev, !gate);
3652 }
3653 #endif
3654
3655 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
3656                                              struct radeon_ps *radeon_state)
3657 {
3658         struct ci_power_info *pi = ci_get_pi(rdev);
3659         int ret;
3660
3661         ret = ci_trim_dpm_states(rdev, radeon_state);
3662         if (ret)
3663                 return ret;
3664
3665         pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3666                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
3667         pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3668                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
3669         pi->last_mclk_dpm_enable_mask =
3670                 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3671         if (pi->uvd_enabled) {
3672                 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
3673                         pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3674         }
3675         pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
3676                 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
3677
3678         return 0;
3679 }
3680
3681 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
3682                                        u32 level_mask)
3683 {
3684         u32 level = 0;
3685
3686         while ((level_mask & (1 << level)) == 0)
3687                 level++;
3688
3689         return level;
3690 }
3691
3692
3693 int ci_dpm_force_performance_level(struct radeon_device *rdev,
3694                                    enum radeon_dpm_forced_level level)
3695 {
3696         struct ci_power_info *pi = ci_get_pi(rdev);
3697         PPSMC_Result smc_result;
3698         u32 tmp, levels, i;
3699         int ret;
3700
3701         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3702                 if ((!pi->sclk_dpm_key_disabled) &&
3703                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3704                         levels = 0;
3705                         tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
3706                         while (tmp >>= 1)
3707                                 levels++;
3708                         if (levels) {
3709                                 ret = ci_dpm_force_state_sclk(rdev, levels);
3710                                 if (ret)
3711                                         return ret;
3712                                 for (i = 0; i < rdev->usec_timeout; i++) {
3713                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3714                                                CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3715                                         if (tmp == levels)
3716                                                 break;
3717                                         udelay(1);
3718                                 }
3719                         }
3720                 }
3721                 if ((!pi->mclk_dpm_key_disabled) &&
3722                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3723                         levels = 0;
3724                         tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
3725                         while (tmp >>= 1)
3726                                 levels++;
3727                         if (levels) {
3728                                 ret = ci_dpm_force_state_mclk(rdev, levels);
3729                                 if (ret)
3730                                         return ret;
3731                                 for (i = 0; i < rdev->usec_timeout; i++) {
3732                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3733                                                CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3734                                         if (tmp == levels)
3735                                                 break;
3736                                         udelay(1);
3737                                 }
3738                         }
3739                 }
3740                 if ((!pi->pcie_dpm_key_disabled) &&
3741                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3742                         levels = 0;
3743                         tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
3744                         while (tmp >>= 1)
3745                                 levels++;
3746                         if (levels) {
3747                                 ret = ci_dpm_force_state_pcie(rdev, level);
3748                                 if (ret)
3749                                         return ret;
3750                                 for (i = 0; i < rdev->usec_timeout; i++) {
3751                                         tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3752                                                CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3753                                         if (tmp == levels)
3754                                                 break;
3755                                         udelay(1);
3756                                 }
3757                         }
3758                 }
3759         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3760                 if ((!pi->sclk_dpm_key_disabled) &&
3761                     pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3762                         levels = ci_get_lowest_enabled_level(rdev,
3763                                                              pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3764                         ret = ci_dpm_force_state_sclk(rdev, levels);
3765                         if (ret)
3766                                 return ret;
3767                         for (i = 0; i < rdev->usec_timeout; i++) {
3768                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3769                                        CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
3770                                 if (tmp == levels)
3771                                         break;
3772                                 udelay(1);
3773                         }
3774                 }
3775                 if ((!pi->mclk_dpm_key_disabled) &&
3776                     pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3777                         levels = ci_get_lowest_enabled_level(rdev,
3778                                                              pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3779                         ret = ci_dpm_force_state_mclk(rdev, levels);
3780                         if (ret)
3781                                 return ret;
3782                         for (i = 0; i < rdev->usec_timeout; i++) {
3783                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
3784                                        CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
3785                                 if (tmp == levels)
3786                                         break;
3787                                 udelay(1);
3788                         }
3789                 }
3790                 if ((!pi->pcie_dpm_key_disabled) &&
3791                     pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3792                         levels = ci_get_lowest_enabled_level(rdev,
3793                                                              pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3794                         ret = ci_dpm_force_state_pcie(rdev, levels);
3795                         if (ret)
3796                                 return ret;
3797                         for (i = 0; i < rdev->usec_timeout; i++) {
3798                                 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
3799                                        CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
3800                                 if (tmp == levels)
3801                                         break;
3802                                 udelay(1);
3803                         }
3804                 }
3805         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3806                 if (!pi->sclk_dpm_key_disabled) {
3807                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel);
3808                         if (smc_result != PPSMC_Result_OK)
3809                                 return -EINVAL;
3810                 }
3811                 if (!pi->mclk_dpm_key_disabled) {
3812                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_NoForcedLevel);
3813                         if (smc_result != PPSMC_Result_OK)
3814                                 return -EINVAL;
3815                 }
3816                 if (!pi->pcie_dpm_key_disabled) {
3817                         smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_UnForceLevel);
3818                         if (smc_result != PPSMC_Result_OK)
3819                                 return -EINVAL;
3820                 }
3821         }
3822
3823         rdev->pm.dpm.forced_level = level;
3824
3825         return 0;
3826 }
3827
3828 static int ci_set_mc_special_registers(struct radeon_device *rdev,
3829                                        struct ci_mc_reg_table *table)
3830 {
3831         struct ci_power_info *pi = ci_get_pi(rdev);
3832         u8 i, j, k;
3833         u32 temp_reg;
3834
3835         for (i = 0, j = table->last; i < table->last; i++) {
3836                 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3837                         return -EINVAL;
3838                 switch(table->mc_reg_address[i].s1 << 2) {
3839                 case MC_SEQ_MISC1:
3840                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
3841                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
3842                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3843                         for (k = 0; k < table->num_entries; k++) {
3844                                 table->mc_reg_table_entry[k].mc_data[j] =
3845                                         ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3846                         }
3847                         j++;
3848                         if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3849                                 return -EINVAL;
3850
3851                         temp_reg = RREG32(MC_PMG_CMD_MRS);
3852                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
3853                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3854                         for (k = 0; k < table->num_entries; k++) {
3855                                 table->mc_reg_table_entry[k].mc_data[j] =
3856                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3857                                 if (!pi->mem_gddr5)
3858                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3859                         }
3860                         j++;
3861                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3862                                 return -EINVAL;
3863
3864                         if (!pi->mem_gddr5) {
3865                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
3866                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
3867                                 for (k = 0; k < table->num_entries; k++) {
3868                                         table->mc_reg_table_entry[k].mc_data[j] =
3869                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3870                                 }
3871                                 j++;
3872                                 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3873                                         return -EINVAL;
3874                         }
3875                         break;
3876                 case MC_SEQ_RESERVE_M:
3877                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
3878                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
3879                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3880                         for (k = 0; k < table->num_entries; k++) {
3881                                 table->mc_reg_table_entry[k].mc_data[j] =
3882                                         (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3883                         }
3884                         j++;
3885                         if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
3886                                 return -EINVAL;
3887                         break;
3888                 default:
3889                         break;
3890                 }
3891
3892         }
3893
3894         table->last = j;
3895
3896         return 0;
3897 }
3898
3899 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
3900 {
3901         bool result = true;
3902
3903         switch(in_reg) {
3904         case MC_SEQ_RAS_TIMING >> 2:
3905                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
3906                 break;
3907         case MC_SEQ_DLL_STBY >> 2:
3908                 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
3909                 break;
3910         case MC_SEQ_G5PDX_CMD0 >> 2:
3911                 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
3912                 break;
3913         case MC_SEQ_G5PDX_CMD1 >> 2:
3914                 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
3915                 break;
3916         case MC_SEQ_G5PDX_CTRL >> 2:
3917                 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
3918                 break;
3919         case MC_SEQ_CAS_TIMING >> 2:
3920                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
3921             break;
3922         case MC_SEQ_MISC_TIMING >> 2:
3923                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
3924                 break;
3925         case MC_SEQ_MISC_TIMING2 >> 2:
3926                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
3927                 break;
3928         case MC_SEQ_PMG_DVS_CMD >> 2:
3929                 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
3930                 break;
3931         case MC_SEQ_PMG_DVS_CTL >> 2:
3932                 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
3933                 break;
3934         case MC_SEQ_RD_CTL_D0 >> 2:
3935                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
3936                 break;
3937         case MC_SEQ_RD_CTL_D1 >> 2:
3938                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
3939                 break;
3940         case MC_SEQ_WR_CTL_D0 >> 2:
3941                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
3942                 break;
3943         case MC_SEQ_WR_CTL_D1 >> 2:
3944                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
3945                 break;
3946         case MC_PMG_CMD_EMRS >> 2:
3947                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
3948                 break;
3949         case MC_PMG_CMD_MRS >> 2:
3950                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
3951                 break;
3952         case MC_PMG_CMD_MRS1 >> 2:
3953                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
3954                 break;
3955         case MC_SEQ_PMG_TIMING >> 2:
3956                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
3957                 break;
3958         case MC_PMG_CMD_MRS2 >> 2:
3959                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
3960                 break;
3961         case MC_SEQ_WR_CTL_2 >> 2:
3962                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
3963                 break;
3964         default:
3965                 result = false;
3966                 break;
3967         }
3968
3969         return result;
3970 }
3971
3972 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
3973 {
3974         u8 i, j;
3975
3976         for (i = 0; i < table->last; i++) {
3977                 for (j = 1; j < table->num_entries; j++) {
3978                         if (table->mc_reg_table_entry[j-1].mc_data[i] !=
3979                             table->mc_reg_table_entry[j].mc_data[i]) {
3980                                 table->valid_flag |= 1 << i;
3981                                 break;
3982                         }
3983                 }
3984         }
3985 }
3986
3987 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
3988 {
3989         u32 i;
3990         u16 address;
3991
3992         for (i = 0; i < table->last; i++) {
3993                 table->mc_reg_address[i].s0 =
3994                         ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
3995                         address : table->mc_reg_address[i].s1;
3996         }
3997 }
3998
3999 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4000                                       struct ci_mc_reg_table *ci_table)
4001 {
4002         u8 i, j;
4003
4004         if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4005                 return -EINVAL;
4006         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4007                 return -EINVAL;
4008
4009         for (i = 0; i < table->last; i++)
4010                 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4011
4012         ci_table->last = table->last;
4013
4014         for (i = 0; i < table->num_entries; i++) {
4015                 ci_table->mc_reg_table_entry[i].mclk_max =
4016                         table->mc_reg_table_entry[i].mclk_max;
4017                 for (j = 0; j < table->last; j++)
4018                         ci_table->mc_reg_table_entry[i].mc_data[j] =
4019                                 table->mc_reg_table_entry[i].mc_data[j];
4020         }
4021         ci_table->num_entries = table->num_entries;
4022
4023         return 0;
4024 }
4025
4026 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4027 {
4028         struct ci_power_info *pi = ci_get_pi(rdev);
4029         struct atom_mc_reg_table *table;
4030         struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4031         u8 module_index = rv770_get_memory_module_index(rdev);
4032         int ret;
4033
4034         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4035         if (!table)
4036                 return -ENOMEM;
4037
4038         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4039         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4040         WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4041         WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4042         WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4043         WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4044         WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4045         WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4046         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4047         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4048         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4049         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4050         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4051         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4052         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4053         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4054         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4055         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4056         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4057         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4058
4059         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4060         if (ret)
4061                 goto init_mc_done;
4062
4063         ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4064         if (ret)
4065                 goto init_mc_done;
4066
4067         ci_set_s0_mc_reg_index(ci_table);
4068
4069         ret = ci_set_mc_special_registers(rdev, ci_table);
4070         if (ret)
4071                 goto init_mc_done;
4072
4073         ci_set_valid_flag(ci_table);
4074
4075 init_mc_done:
4076         kfree(table);
4077
4078         return ret;
4079 }
4080
4081 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4082                                         SMU7_Discrete_MCRegisters *mc_reg_table)
4083 {
4084         struct ci_power_info *pi = ci_get_pi(rdev);
4085         u32 i, j;
4086
4087         for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4088                 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4089                         if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4090                                 return -EINVAL;
4091                         mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4092                         mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4093                         i++;
4094                 }
4095         }
4096
4097         mc_reg_table->last = (u8)i;
4098
4099         return 0;
4100 }
4101
4102 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4103                                     SMU7_Discrete_MCRegisterSet *data,
4104                                     u32 num_entries, u32 valid_flag)
4105 {
4106         u32 i, j;
4107
4108         for (i = 0, j = 0; j < num_entries; j++) {
4109                 if (valid_flag & (1 << j)) {
4110                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
4111                         i++;
4112                 }
4113         }
4114 }
4115
4116 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4117                                                  const u32 memory_clock,
4118                                                  SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4119 {
4120         struct ci_power_info *pi = ci_get_pi(rdev);
4121         u32 i = 0;
4122
4123         for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4124                 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4125                         break;
4126         }
4127
4128         if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4129                 --i;
4130
4131         ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4132                                 mc_reg_table_data, pi->mc_reg_table.last,
4133                                 pi->mc_reg_table.valid_flag);
4134 }
4135
4136 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4137                                            SMU7_Discrete_MCRegisters *mc_reg_table)
4138 {
4139         struct ci_power_info *pi = ci_get_pi(rdev);
4140         u32 i;
4141
4142         for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4143                 ci_convert_mc_reg_table_entry_to_smc(rdev,
4144                                                      pi->dpm_table.mclk_table.dpm_levels[i].value,
4145                                                      &mc_reg_table->data[i]);
4146 }
4147
4148 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4149 {
4150         struct ci_power_info *pi = ci_get_pi(rdev);
4151         int ret;
4152
4153         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4154
4155         ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4156         if (ret)
4157                 return ret;
4158         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4159
4160         return ci_copy_bytes_to_smc(rdev,
4161                                     pi->mc_reg_table_start,
4162                                     (u8 *)&pi->smc_mc_reg_table,
4163                                     sizeof(SMU7_Discrete_MCRegisters),
4164                                     pi->sram_end);
4165 }
4166
4167 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4168 {
4169         struct ci_power_info *pi = ci_get_pi(rdev);
4170
4171         if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4172                 return 0;
4173
4174         memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4175
4176         ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4177
4178         return ci_copy_bytes_to_smc(rdev,
4179                                     pi->mc_reg_table_start +
4180                                     offsetof(SMU7_Discrete_MCRegisters, data[0]),
4181                                     (u8 *)&pi->smc_mc_reg_table.data[0],
4182                                     sizeof(SMU7_Discrete_MCRegisterSet) *
4183                                     pi->dpm_table.mclk_table.count,
4184                                     pi->sram_end);
4185 }
4186
4187 static void ci_enable_voltage_control(struct radeon_device *rdev)
4188 {
4189         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4190
4191         tmp |= VOLT_PWRMGT_EN;
4192         WREG32_SMC(GENERAL_PWRMGT, tmp);
4193 }
4194
4195 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4196                                                       struct radeon_ps *radeon_state)
4197 {
4198         struct ci_ps *state = ci_get_ps(radeon_state);
4199         int i;
4200         u16 pcie_speed, max_speed = 0;
4201
4202         for (i = 0; i < state->performance_level_count; i++) {
4203                 pcie_speed = state->performance_levels[i].pcie_gen;
4204                 if (max_speed < pcie_speed)
4205                         max_speed = pcie_speed;
4206         }
4207
4208         return max_speed;
4209 }
4210
4211 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4212 {
4213         u32 speed_cntl = 0;
4214
4215         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4216         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4217
4218         return (u16)speed_cntl;
4219 }
4220
4221 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4222 {
4223         u32 link_width = 0;
4224
4225         link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4226         link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4227
4228         switch (link_width) {
4229         case RADEON_PCIE_LC_LINK_WIDTH_X1:
4230                 return 1;
4231         case RADEON_PCIE_LC_LINK_WIDTH_X2:
4232                 return 2;
4233         case RADEON_PCIE_LC_LINK_WIDTH_X4:
4234                 return 4;
4235         case RADEON_PCIE_LC_LINK_WIDTH_X8:
4236                 return 8;
4237         case RADEON_PCIE_LC_LINK_WIDTH_X12:
4238                 /* not actually supported */
4239                 return 12;
4240         case RADEON_PCIE_LC_LINK_WIDTH_X0:
4241         case RADEON_PCIE_LC_LINK_WIDTH_X16:
4242         default:
4243                 return 16;
4244         }
4245 }
4246
4247 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4248                                                              struct radeon_ps *radeon_new_state,
4249                                                              struct radeon_ps *radeon_current_state)
4250 {
4251         struct ci_power_info *pi = ci_get_pi(rdev);
4252         enum radeon_pcie_gen target_link_speed =
4253                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4254         enum radeon_pcie_gen current_link_speed;
4255
4256         if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4257                 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4258         else
4259                 current_link_speed = pi->force_pcie_gen;
4260
4261         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4262         pi->pspp_notify_required = false;
4263         if (target_link_speed > current_link_speed) {
4264                 switch (target_link_speed) {
4265 #ifdef CONFIG_ACPI
4266                 case RADEON_PCIE_GEN3:
4267                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4268                                 break;
4269                         pi->force_pcie_gen = RADEON_PCIE_GEN2;
4270                         if (current_link_speed == RADEON_PCIE_GEN2)
4271                                 break;
4272                 case RADEON_PCIE_GEN2:
4273                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4274                                 break;
4275 #endif
4276                 default:
4277                         pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4278                         break;
4279                 }
4280         } else {
4281                 if (target_link_speed < current_link_speed)
4282                         pi->pspp_notify_required = true;
4283         }
4284 }
4285
4286 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4287                                                            struct radeon_ps *radeon_new_state,
4288                                                            struct radeon_ps *radeon_current_state)
4289 {
4290         struct ci_power_info *pi = ci_get_pi(rdev);
4291         enum radeon_pcie_gen target_link_speed =
4292                 ci_get_maximum_link_speed(rdev, radeon_new_state);
4293         u8 request;
4294
4295         if (pi->pspp_notify_required) {
4296                 if (target_link_speed == RADEON_PCIE_GEN3)
4297                         request = PCIE_PERF_REQ_PECI_GEN3;
4298                 else if (target_link_speed == RADEON_PCIE_GEN2)
4299                         request = PCIE_PERF_REQ_PECI_GEN2;
4300                 else
4301                         request = PCIE_PERF_REQ_PECI_GEN1;
4302
4303                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4304                     (ci_get_current_pcie_speed(rdev) > 0))
4305                         return;
4306
4307 #ifdef CONFIG_ACPI
4308                 radeon_acpi_pcie_performance_request(rdev, request, false);
4309 #endif
4310         }
4311 }
4312
4313 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4314 {
4315         struct ci_power_info *pi = ci_get_pi(rdev);
4316         struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4317                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4318         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4319                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4320         struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4321                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4322
4323         if (allowed_sclk_vddc_table == NULL)
4324                 return -EINVAL;
4325         if (allowed_sclk_vddc_table->count < 1)
4326                 return -EINVAL;
4327         if (allowed_mclk_vddc_table == NULL)
4328                 return -EINVAL;
4329         if (allowed_mclk_vddc_table->count < 1)
4330                 return -EINVAL;
4331         if (allowed_mclk_vddci_table == NULL)
4332                 return -EINVAL;
4333         if (allowed_mclk_vddci_table->count < 1)
4334                 return -EINVAL;
4335
4336         pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4337         pi->max_vddc_in_pp_table =
4338                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4339
4340         pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4341         pi->max_vddci_in_pp_table =
4342                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4343
4344         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4345                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4346         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4347                 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4348         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4349                 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4350         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4351                 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4352
4353         return 0;
4354 }
4355
4356 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4357 {
4358         struct ci_power_info *pi = ci_get_pi(rdev);
4359         struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4360         u32 leakage_index;
4361
4362         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4363                 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4364                         *vddc = leakage_table->actual_voltage[leakage_index];
4365                         break;
4366                 }
4367         }
4368 }
4369
4370 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4371 {
4372         struct ci_power_info *pi = ci_get_pi(rdev);
4373         struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4374         u32 leakage_index;
4375
4376         for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4377                 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4378                         *vddci = leakage_table->actual_voltage[leakage_index];
4379                         break;
4380                 }
4381         }
4382 }
4383
4384 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4385                                                                       struct radeon_clock_voltage_dependency_table *table)
4386 {
4387         u32 i;
4388
4389         if (table) {
4390                 for (i = 0; i < table->count; i++)
4391                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4392         }
4393 }
4394
4395 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4396                                                                        struct radeon_clock_voltage_dependency_table *table)
4397 {
4398         u32 i;
4399
4400         if (table) {
4401                 for (i = 0; i < table->count; i++)
4402                         ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4403         }
4404 }
4405
4406 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4407                                                                           struct radeon_vce_clock_voltage_dependency_table *table)
4408 {
4409         u32 i;
4410
4411         if (table) {
4412                 for (i = 0; i < table->count; i++)
4413                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4414         }
4415 }
4416
4417 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4418                                                                           struct radeon_uvd_clock_voltage_dependency_table *table)
4419 {
4420         u32 i;
4421
4422         if (table) {
4423                 for (i = 0; i < table->count; i++)
4424                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4425         }
4426 }
4427
4428 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
4429                                                                    struct radeon_phase_shedding_limits_table *table)
4430 {
4431         u32 i;
4432
4433         if (table) {
4434                 for (i = 0; i < table->count; i++)
4435                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
4436         }
4437 }
4438
4439 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
4440                                                             struct radeon_clock_and_voltage_limits *table)
4441 {
4442         if (table) {
4443                 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
4444                 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
4445         }
4446 }
4447
4448 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
4449                                                          struct radeon_cac_leakage_table *table)
4450 {
4451         u32 i;
4452
4453         if (table) {
4454                 for (i = 0; i < table->count; i++)
4455                         ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
4456         }
4457 }
4458
4459 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
4460 {
4461
4462         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4463                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
4464         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4465                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
4466         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4467                                                                   &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
4468         ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
4469                                                                    &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
4470         ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4471                                                                       &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
4472         ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4473                                                                       &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
4474         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4475                                                                   &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
4476         ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4477                                                                   &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
4478         ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
4479                                                                &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
4480         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4481                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
4482         ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
4483                                                         &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
4484         ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
4485                                                      &rdev->pm.dpm.dyn_state.cac_leakage_table);
4486
4487 }
4488
4489 static void ci_get_memory_type(struct radeon_device *rdev)
4490 {
4491         struct ci_power_info *pi = ci_get_pi(rdev);
4492         u32 tmp;
4493
4494         tmp = RREG32(MC_SEQ_MISC0);
4495
4496         if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
4497             MC_SEQ_MISC0_GDDR5_VALUE)
4498                 pi->mem_gddr5 = true;
4499         else
4500                 pi->mem_gddr5 = false;
4501
4502 }
4503
4504 void ci_update_current_ps(struct radeon_device *rdev,
4505                           struct radeon_ps *rps)
4506 {
4507         struct ci_ps *new_ps = ci_get_ps(rps);
4508         struct ci_power_info *pi = ci_get_pi(rdev);
4509
4510         pi->current_rps = *rps;
4511         pi->current_ps = *new_ps;
4512         pi->current_rps.ps_priv = &pi->current_ps;
4513 }
4514
4515 void ci_update_requested_ps(struct radeon_device *rdev,
4516                             struct radeon_ps *rps)
4517 {
4518         struct ci_ps *new_ps = ci_get_ps(rps);
4519         struct ci_power_info *pi = ci_get_pi(rdev);
4520
4521         pi->requested_rps = *rps;
4522         pi->requested_ps = *new_ps;
4523         pi->requested_rps.ps_priv = &pi->requested_ps;
4524 }
4525
4526 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
4527 {
4528         struct ci_power_info *pi = ci_get_pi(rdev);
4529         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
4530         struct radeon_ps *new_ps = &requested_ps;
4531
4532         ci_update_requested_ps(rdev, new_ps);
4533
4534         ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
4535
4536         return 0;
4537 }
4538
4539 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
4540 {
4541         struct ci_power_info *pi = ci_get_pi(rdev);
4542         struct radeon_ps *new_ps = &pi->requested_rps;
4543
4544         ci_update_current_ps(rdev, new_ps);
4545 }
4546
4547
4548 void ci_dpm_setup_asic(struct radeon_device *rdev)
4549 {
4550         ci_read_clock_registers(rdev);
4551         ci_get_memory_type(rdev);
4552         ci_enable_acpi_power_management(rdev);
4553         ci_init_sclk_t(rdev);
4554 }
4555
4556 int ci_dpm_enable(struct radeon_device *rdev)
4557 {
4558         struct ci_power_info *pi = ci_get_pi(rdev);
4559         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4560         int ret;
4561
4562         if (ci_is_smc_running(rdev))
4563                 return -EINVAL;
4564         if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
4565                 ci_enable_voltage_control(rdev);
4566                 ret = ci_construct_voltage_tables(rdev);
4567                 if (ret) {
4568                         DRM_ERROR("ci_construct_voltage_tables failed\n");
4569                         return ret;
4570                 }
4571         }
4572         if (pi->caps_dynamic_ac_timing) {
4573                 ret = ci_initialize_mc_reg_table(rdev);
4574                 if (ret)
4575                         pi->caps_dynamic_ac_timing = false;
4576         }
4577         if (pi->dynamic_ss)
4578                 ci_enable_spread_spectrum(rdev, true);
4579         if (pi->thermal_protection)
4580                 ci_enable_thermal_protection(rdev, true);
4581         ci_program_sstp(rdev);
4582         ci_enable_display_gap(rdev);
4583         ci_program_vc(rdev);
4584         ret = ci_upload_firmware(rdev);
4585         if (ret) {
4586                 DRM_ERROR("ci_upload_firmware failed\n");
4587                 return ret;
4588         }
4589         ret = ci_process_firmware_header(rdev);
4590         if (ret) {
4591                 DRM_ERROR("ci_process_firmware_header failed\n");
4592                 return ret;
4593         }
4594         ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
4595         if (ret) {
4596                 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
4597                 return ret;
4598         }
4599         ret = ci_init_smc_table(rdev);
4600         if (ret) {
4601                 DRM_ERROR("ci_init_smc_table failed\n");
4602                 return ret;
4603         }
4604         ret = ci_init_arb_table_index(rdev);
4605         if (ret) {
4606                 DRM_ERROR("ci_init_arb_table_index failed\n");
4607                 return ret;
4608         }
4609         if (pi->caps_dynamic_ac_timing) {
4610                 ret = ci_populate_initial_mc_reg_table(rdev);
4611                 if (ret) {
4612                         DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
4613                         return ret;
4614                 }
4615         }
4616         ret = ci_populate_pm_base(rdev);
4617         if (ret) {
4618                 DRM_ERROR("ci_populate_pm_base failed\n");
4619                 return ret;
4620         }
4621         ci_dpm_start_smc(rdev);
4622         ci_enable_vr_hot_gpio_interrupt(rdev);
4623         ret = ci_notify_smc_display_change(rdev, false);
4624         if (ret) {
4625                 DRM_ERROR("ci_notify_smc_display_change failed\n");
4626                 return ret;
4627         }
4628         ci_enable_sclk_control(rdev, true);
4629         ret = ci_enable_ulv(rdev, true);
4630         if (ret) {
4631                 DRM_ERROR("ci_enable_ulv failed\n");
4632                 return ret;
4633         }
4634         ret = ci_enable_ds_master_switch(rdev, true);
4635         if (ret) {
4636                 DRM_ERROR("ci_enable_ds_master_switch failed\n");
4637                 return ret;
4638         }
4639         ret = ci_start_dpm(rdev);
4640         if (ret) {
4641                 DRM_ERROR("ci_start_dpm failed\n");
4642                 return ret;
4643         }
4644         ret = ci_enable_didt(rdev, true);
4645         if (ret) {
4646                 DRM_ERROR("ci_enable_didt failed\n");
4647                 return ret;
4648         }
4649         ret = ci_enable_smc_cac(rdev, true);
4650         if (ret) {
4651                 DRM_ERROR("ci_enable_smc_cac failed\n");
4652                 return ret;
4653         }
4654         ret = ci_enable_power_containment(rdev, true);
4655         if (ret) {
4656                 DRM_ERROR("ci_enable_power_containment failed\n");
4657                 return ret;
4658         }
4659
4660         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
4661
4662         ci_update_current_ps(rdev, boot_ps);
4663
4664         return 0;
4665 }
4666
4667 int ci_dpm_late_enable(struct radeon_device *rdev)
4668 {
4669         int ret;
4670
4671         if (rdev->irq.installed &&
4672             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
4673 #if 0
4674                 PPSMC_Result result;
4675 #endif
4676                 ret = ci_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
4677                 if (ret) {
4678                         DRM_ERROR("ci_set_thermal_temperature_range failed\n");
4679                         return ret;
4680                 }
4681                 rdev->irq.dpm_thermal = true;
4682                 radeon_irq_set(rdev);
4683 #if 0
4684                 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
4685
4686                 if (result != PPSMC_Result_OK)
4687                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
4688 #endif
4689         }
4690
4691         ci_dpm_powergate_uvd(rdev, true);
4692
4693         return 0;
4694 }
4695
4696 void ci_dpm_disable(struct radeon_device *rdev)
4697 {
4698         struct ci_power_info *pi = ci_get_pi(rdev);
4699         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
4700
4701         ci_dpm_powergate_uvd(rdev, false);
4702
4703         if (!ci_is_smc_running(rdev))
4704                 return;
4705
4706         if (pi->thermal_protection)
4707                 ci_enable_thermal_protection(rdev, false);
4708         ci_enable_power_containment(rdev, false);
4709         ci_enable_smc_cac(rdev, false);
4710         ci_enable_didt(rdev, false);
4711         ci_enable_spread_spectrum(rdev, false);
4712         ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
4713         ci_stop_dpm(rdev);
4714         ci_enable_ds_master_switch(rdev, true);
4715         ci_enable_ulv(rdev, false);
4716         ci_clear_vc(rdev);
4717         ci_reset_to_default(rdev);
4718         ci_dpm_stop_smc(rdev);
4719         ci_force_switch_to_arb_f0(rdev);
4720
4721         ci_update_current_ps(rdev, boot_ps);
4722 }
4723
4724 int ci_dpm_set_power_state(struct radeon_device *rdev)
4725 {
4726         struct ci_power_info *pi = ci_get_pi(rdev);
4727         struct radeon_ps *new_ps = &pi->requested_rps;
4728         struct radeon_ps *old_ps = &pi->current_rps;
4729         int ret;
4730
4731         ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
4732         if (pi->pcie_performance_request)
4733                 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
4734         ret = ci_freeze_sclk_mclk_dpm(rdev);
4735         if (ret) {
4736                 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
4737                 return ret;
4738         }
4739         ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
4740         if (ret) {
4741                 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
4742                 return ret;
4743         }
4744         ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
4745         if (ret) {
4746                 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
4747                 return ret;
4748         }
4749 #if 0
4750         ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
4751         if (ret) {
4752                 DRM_ERROR("ci_update_vce_dpm failed\n");
4753                 return ret;
4754         }
4755 #endif
4756         ret = ci_update_sclk_t(rdev);
4757         if (ret) {
4758                 DRM_ERROR("ci_update_sclk_t failed\n");
4759                 return ret;
4760         }
4761         if (pi->caps_dynamic_ac_timing) {
4762                 ret = ci_update_and_upload_mc_reg_table(rdev);
4763                 if (ret) {
4764                         DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
4765                         return ret;
4766                 }
4767         }
4768         ret = ci_program_memory_timing_parameters(rdev);
4769         if (ret) {
4770                 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
4771                 return ret;
4772         }
4773         ret = ci_unfreeze_sclk_mclk_dpm(rdev);
4774         if (ret) {
4775                 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
4776                 return ret;
4777         }
4778         ret = ci_upload_dpm_level_enable_mask(rdev);
4779         if (ret) {
4780                 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
4781                 return ret;
4782         }
4783         if (pi->pcie_performance_request)
4784                 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
4785
4786         return 0;
4787 }
4788
4789 int ci_dpm_power_control_set_level(struct radeon_device *rdev)
4790 {
4791         return ci_power_control_set_level(rdev);
4792 }
4793
4794 void ci_dpm_reset_asic(struct radeon_device *rdev)
4795 {
4796         ci_set_boot_state(rdev);
4797 }
4798
4799 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
4800 {
4801         ci_program_display_gap(rdev);
4802 }
4803
4804 union power_info {
4805         struct _ATOM_POWERPLAY_INFO info;
4806         struct _ATOM_POWERPLAY_INFO_V2 info_2;
4807         struct _ATOM_POWERPLAY_INFO_V3 info_3;
4808         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
4809         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
4810         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
4811 };
4812
4813 union pplib_clock_info {
4814         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
4815         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
4816         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
4817         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
4818         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
4819         struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
4820 };
4821
4822 union pplib_power_state {
4823         struct _ATOM_PPLIB_STATE v1;
4824         struct _ATOM_PPLIB_STATE_V2 v2;
4825 };
4826
4827 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
4828                                           struct radeon_ps *rps,
4829                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
4830                                           u8 table_rev)
4831 {
4832         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
4833         rps->class = le16_to_cpu(non_clock_info->usClassification);
4834         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
4835
4836         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
4837                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
4838                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
4839         } else {
4840                 rps->vclk = 0;
4841                 rps->dclk = 0;
4842         }
4843
4844         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
4845                 rdev->pm.dpm.boot_ps = rps;
4846         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
4847                 rdev->pm.dpm.uvd_ps = rps;
4848 }
4849
4850 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
4851                                       struct radeon_ps *rps, int index,
4852                                       union pplib_clock_info *clock_info)
4853 {
4854         struct ci_power_info *pi = ci_get_pi(rdev);
4855         struct ci_ps *ps = ci_get_ps(rps);
4856         struct ci_pl *pl = &ps->performance_levels[index];
4857
4858         ps->performance_level_count = index + 1;
4859
4860         pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
4861         pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
4862         pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
4863         pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
4864
4865         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
4866                                                  pi->sys_pcie_mask,
4867                                                  pi->vbios_boot_state.pcie_gen_bootup_value,
4868                                                  clock_info->ci.ucPCIEGen);
4869         pl->pcie_lane = r600_get_pcie_lane_support(rdev,
4870                                                    pi->vbios_boot_state.pcie_lane_bootup_value,
4871                                                    le16_to_cpu(clock_info->ci.usPCIELane));
4872
4873         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
4874                 pi->acpi_pcie_gen = pl->pcie_gen;
4875         }
4876
4877         if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
4878                 pi->ulv.supported = true;
4879                 pi->ulv.pl = *pl;
4880                 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
4881         }
4882
4883         /* patch up boot state */
4884         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
4885                 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
4886                 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
4887                 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
4888                 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
4889         }
4890
4891         switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
4892         case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
4893                 pi->use_pcie_powersaving_levels = true;
4894                 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
4895                         pi->pcie_gen_powersaving.max = pl->pcie_gen;
4896                 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
4897                         pi->pcie_gen_powersaving.min = pl->pcie_gen;
4898                 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
4899                         pi->pcie_lane_powersaving.max = pl->pcie_lane;
4900                 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
4901                         pi->pcie_lane_powersaving.min = pl->pcie_lane;
4902                 break;
4903         case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
4904                 pi->use_pcie_performance_levels = true;
4905                 if (pi->pcie_gen_performance.max < pl->pcie_gen)
4906                         pi->pcie_gen_performance.max = pl->pcie_gen;
4907                 if (pi->pcie_gen_performance.min > pl->pcie_gen)
4908                         pi->pcie_gen_performance.min = pl->pcie_gen;
4909                 if (pi->pcie_lane_performance.max < pl->pcie_lane)
4910                         pi->pcie_lane_performance.max = pl->pcie_lane;
4911                 if (pi->pcie_lane_performance.min > pl->pcie_lane)
4912                         pi->pcie_lane_performance.min = pl->pcie_lane;
4913                 break;
4914         default:
4915                 break;
4916         }
4917 }
4918
4919 static int ci_parse_power_table(struct radeon_device *rdev)
4920 {
4921         struct radeon_mode_info *mode_info = &rdev->mode_info;
4922         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
4923         union pplib_power_state *power_state;
4924         int i, j, k, non_clock_array_index, clock_array_index;
4925         union pplib_clock_info *clock_info;
4926         struct _StateArray *state_array;
4927         struct _ClockInfoArray *clock_info_array;
4928         struct _NonClockInfoArray *non_clock_info_array;
4929         union power_info *power_info;
4930         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
4931         u16 data_offset;
4932         u8 frev, crev;
4933         u8 *power_state_offset;
4934         struct ci_ps *ps;
4935
4936         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
4937                                    &frev, &crev, &data_offset))
4938                 return -EINVAL;
4939         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
4940
4941         state_array = (struct _StateArray *)
4942                 (mode_info->atom_context->bios + data_offset +
4943                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
4944         clock_info_array = (struct _ClockInfoArray *)
4945                 (mode_info->atom_context->bios + data_offset +
4946                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
4947         non_clock_info_array = (struct _NonClockInfoArray *)
4948                 (mode_info->atom_context->bios + data_offset +
4949                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
4950
4951         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
4952                                   state_array->ucNumEntries, GFP_KERNEL);
4953         if (!rdev->pm.dpm.ps)
4954                 return -ENOMEM;
4955         power_state_offset = (u8 *)state_array->states;
4956         rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
4957         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
4958         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
4959         for (i = 0; i < state_array->ucNumEntries; i++) {
4960                 u8 *idx;
4961                 power_state = (union pplib_power_state *)power_state_offset;
4962                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
4963                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
4964                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
4965                 if (!rdev->pm.power_state[i].clock_info)
4966                         return -EINVAL;
4967                 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
4968                 if (ps == NULL) {
4969                         kfree(rdev->pm.dpm.ps);
4970                         return -ENOMEM;
4971                 }
4972                 rdev->pm.dpm.ps[i].ps_priv = ps;
4973                 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
4974                                               non_clock_info,
4975                                               non_clock_info_array->ucEntrySize);
4976                 k = 0;
4977                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
4978                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
4979                         clock_array_index = idx[j];
4980                         if (clock_array_index >= clock_info_array->ucNumEntries)
4981                                 continue;
4982                         if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
4983                                 break;
4984                         clock_info = (union pplib_clock_info *)
4985                                 ((u8 *)&clock_info_array->clockInfo[0] +
4986                                  (clock_array_index * clock_info_array->ucEntrySize));
4987                         ci_parse_pplib_clock_info(rdev,
4988                                                   &rdev->pm.dpm.ps[i], k,
4989                                                   clock_info);
4990                         k++;
4991                 }
4992                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
4993         }
4994         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
4995         return 0;
4996 }
4997
4998 int ci_get_vbios_boot_values(struct radeon_device *rdev,
4999                              struct ci_vbios_boot_state *boot_state)
5000 {
5001         struct radeon_mode_info *mode_info = &rdev->mode_info;
5002         int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5003         ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5004         u8 frev, crev;
5005         u16 data_offset;
5006
5007         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5008                                    &frev, &crev, &data_offset)) {
5009                 firmware_info =
5010                         (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5011                                                     data_offset);
5012                 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5013                 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5014                 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5015                 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5016                 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5017                 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5018                 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5019
5020                 return 0;
5021         }
5022         return -EINVAL;
5023 }
5024
5025 void ci_dpm_fini(struct radeon_device *rdev)
5026 {
5027         int i;
5028
5029         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5030                 kfree(rdev->pm.dpm.ps[i].ps_priv);
5031         }
5032         kfree(rdev->pm.dpm.ps);
5033         kfree(rdev->pm.dpm.priv);
5034         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5035         r600_free_extended_power_table(rdev);
5036 }
5037
5038 int ci_dpm_init(struct radeon_device *rdev)
5039 {
5040         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5041         u16 data_offset, size;
5042         u8 frev, crev;
5043         struct ci_power_info *pi;
5044         int ret;
5045         u32 mask;
5046
5047         pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5048         if (pi == NULL)
5049                 return -ENOMEM;
5050         rdev->pm.dpm.priv = pi;
5051
5052         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5053         if (ret)
5054                 pi->sys_pcie_mask = 0;
5055         else
5056                 pi->sys_pcie_mask = mask;
5057         pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5058
5059         pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5060         pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5061         pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5062         pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5063
5064         pi->pcie_lane_performance.max = 0;
5065         pi->pcie_lane_performance.min = 16;
5066         pi->pcie_lane_powersaving.max = 0;
5067         pi->pcie_lane_powersaving.min = 16;
5068
5069         ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5070         if (ret) {
5071                 ci_dpm_fini(rdev);
5072                 return ret;
5073         }
5074         ret = ci_parse_power_table(rdev);
5075         if (ret) {
5076                 ci_dpm_fini(rdev);
5077                 return ret;
5078         }
5079         ret = r600_parse_extended_power_table(rdev);
5080         if (ret) {
5081                 ci_dpm_fini(rdev);
5082                 return ret;
5083         }
5084
5085         pi->dll_default_on = false;
5086         pi->sram_end = SMC_RAM_END;
5087
5088         pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5089         pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5090         pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5091         pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5092         pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5093         pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5094         pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5095         pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5096
5097         pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5098
5099         pi->sclk_dpm_key_disabled = 0;
5100         pi->mclk_dpm_key_disabled = 0;
5101         pi->pcie_dpm_key_disabled = 0;
5102
5103         pi->caps_sclk_ds = true;
5104
5105         pi->mclk_strobe_mode_threshold = 40000;
5106         pi->mclk_stutter_mode_threshold = 40000;
5107         pi->mclk_edc_enable_threshold = 40000;
5108         pi->mclk_edc_wr_enable_threshold = 40000;
5109
5110         ci_initialize_powertune_defaults(rdev);
5111
5112         pi->caps_fps = false;
5113
5114         pi->caps_sclk_throttle_low_notification = false;
5115
5116         pi->caps_uvd_dpm = true;
5117
5118         ci_get_leakage_voltages(rdev);
5119         ci_patch_dependency_tables_with_leakage(rdev);
5120         ci_set_private_data_variables_based_on_pptable(rdev);
5121
5122         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5123                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5124         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5125                 ci_dpm_fini(rdev);
5126                 return -ENOMEM;
5127         }
5128         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5129         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5130         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5131         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5132         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5133         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5134         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5135         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5136         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5137
5138         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5139         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5140         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5141
5142         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5143         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5144         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5145         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5146
5147         if (rdev->family == CHIP_HAWAII) {
5148                 pi->thermal_temp_setting.temperature_low = 94500;
5149                 pi->thermal_temp_setting.temperature_high = 95000;
5150                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5151         } else {
5152                 pi->thermal_temp_setting.temperature_low = 99500;
5153                 pi->thermal_temp_setting.temperature_high = 100000;
5154                 pi->thermal_temp_setting.temperature_shutdown = 104000;
5155         }
5156
5157         pi->uvd_enabled = false;
5158
5159         pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5160         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5161         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5162         if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5163                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5164         else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5165                 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5166
5167         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5168                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5169                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5170                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5171                         pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5172                 else
5173                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5174         }
5175
5176         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5177                 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5178                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5179                 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5180                         pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5181                 else
5182                         rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5183         }
5184
5185         pi->vddc_phase_shed_control = true;
5186
5187 #if defined(CONFIG_ACPI)
5188         pi->pcie_performance_request =
5189                 radeon_acpi_is_pcie_performance_request_supported(rdev);
5190 #else
5191         pi->pcie_performance_request = false;
5192 #endif
5193
5194         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5195                                    &frev, &crev, &data_offset)) {
5196                 pi->caps_sclk_ss_support = true;
5197                 pi->caps_mclk_ss_support = true;
5198                 pi->dynamic_ss = true;
5199         } else {
5200                 pi->caps_sclk_ss_support = false;
5201                 pi->caps_mclk_ss_support = false;
5202                 pi->dynamic_ss = true;
5203         }
5204
5205         if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5206                 pi->thermal_protection = true;
5207         else
5208                 pi->thermal_protection = false;
5209
5210         pi->caps_dynamic_ac_timing = true;
5211
5212         pi->uvd_power_gated = false;
5213
5214         /* make sure dc limits are valid */
5215         if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5216             (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5217                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5218                         rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5219
5220         return 0;
5221 }
5222
5223 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5224                                                     struct seq_file *m)
5225 {
5226         u32 sclk = ci_get_average_sclk_freq(rdev);
5227         u32 mclk = ci_get_average_mclk_freq(rdev);
5228
5229         seq_printf(m, "power level avg    sclk: %u mclk: %u\n",
5230                    sclk, mclk);
5231 }
5232
5233 void ci_dpm_print_power_state(struct radeon_device *rdev,
5234                               struct radeon_ps *rps)
5235 {
5236         struct ci_ps *ps = ci_get_ps(rps);
5237         struct ci_pl *pl;
5238         int i;
5239
5240         r600_dpm_print_class_info(rps->class, rps->class2);
5241         r600_dpm_print_cap_info(rps->caps);
5242         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5243         for (i = 0; i < ps->performance_level_count; i++) {
5244                 pl = &ps->performance_levels[i];
5245                 printk("\t\tpower level %d    sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5246                        i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5247         }
5248         r600_dpm_print_ps_status(rdev, rps);
5249 }
5250
5251 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5252 {
5253         struct ci_power_info *pi = ci_get_pi(rdev);
5254         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5255
5256         if (low)
5257                 return requested_state->performance_levels[0].sclk;
5258         else
5259                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5260 }
5261
5262 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5263 {
5264         struct ci_power_info *pi = ci_get_pi(rdev);
5265         struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5266
5267         if (low)
5268                 return requested_state->performance_levels[0].mclk;
5269         else
5270                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
5271 }