2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/firmware.h>
27 #include "radeon_asic.h"
28 #include "radeon_ucode.h"
33 #include <linux/seq_file.h>
35 #define MC_CG_ARB_FREQ_F0 0x0a
36 #define MC_CG_ARB_FREQ_F1 0x0b
37 #define MC_CG_ARB_FREQ_F2 0x0c
38 #define MC_CG_ARB_FREQ_F3 0x0d
40 #define SMC_RAM_END 0x40000
42 #define VOLTAGE_SCALE 4
43 #define VOLTAGE_VID_OFFSET_SCALE1 625
44 #define VOLTAGE_VID_OFFSET_SCALE2 100
46 static const struct ci_pt_defaults defaults_hawaii_xt =
48 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0xB0000,
49 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
50 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
53 static const struct ci_pt_defaults defaults_hawaii_pro =
55 1, 0xF, 0xFD, 0x19, 5, 0x14, 0, 0x65062,
56 { 0x2E, 0x00, 0x00, 0x88, 0x00, 0x00, 0x72, 0x60, 0x51, 0xA7, 0x79, 0x6B, 0x90, 0xBD, 0x79 },
57 { 0x217, 0x217, 0x217, 0x242, 0x242, 0x242, 0x269, 0x269, 0x269, 0x2A1, 0x2A1, 0x2A1, 0x2C9, 0x2C9, 0x2C9 }
60 static const struct ci_pt_defaults defaults_bonaire_xt =
62 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
63 { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61 },
64 { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 }
67 static const struct ci_pt_defaults defaults_bonaire_pro =
69 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0x65062,
70 { 0x8C, 0x23F, 0x244, 0xA6, 0x83, 0x85, 0x86, 0x86, 0x83, 0xDB, 0xDB, 0xDA, 0x67, 0x60, 0x5F },
71 { 0x187, 0x193, 0x193, 0x1C7, 0x1D1, 0x1D1, 0x210, 0x219, 0x219, 0x266, 0x26C, 0x26C, 0x2C9, 0x2CB, 0x2CB }
74 static const struct ci_pt_defaults defaults_saturn_xt =
76 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x70000,
77 { 0x8C, 0x247, 0x249, 0xA6, 0x80, 0x81, 0x8B, 0x89, 0x86, 0xC9, 0xCA, 0xC9, 0x4D, 0x4D, 0x4D },
78 { 0x187, 0x187, 0x187, 0x1C7, 0x1C7, 0x1C7, 0x210, 0x210, 0x210, 0x266, 0x266, 0x266, 0x2C9, 0x2C9, 0x2C9 }
81 static const struct ci_pt_defaults defaults_saturn_pro =
83 1, 0xF, 0xFD, 0x19, 5, 55, 0, 0x30000,
84 { 0x96, 0x21D, 0x23B, 0xA1, 0x85, 0x87, 0x83, 0x84, 0x81, 0xE6, 0xE6, 0xE6, 0x71, 0x6A, 0x6A },
85 { 0x193, 0x19E, 0x19E, 0x1D2, 0x1DC, 0x1DC, 0x21A, 0x223, 0x223, 0x26E, 0x27E, 0x274, 0x2CF, 0x2D2, 0x2D2 }
88 static const struct ci_pt_config_reg didt_config_ci[] =
90 { 0x10, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
91 { 0x10, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
92 { 0x10, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
93 { 0x10, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
94 { 0x11, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
95 { 0x11, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
96 { 0x11, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
97 { 0x11, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
98 { 0x12, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
99 { 0x12, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
100 { 0x12, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
101 { 0x12, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
102 { 0x2, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
103 { 0x2, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
104 { 0x2, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
105 { 0x1, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
106 { 0x1, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
107 { 0x0, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
108 { 0x30, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
109 { 0x30, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
110 { 0x30, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
111 { 0x30, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
112 { 0x31, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
113 { 0x31, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
114 { 0x31, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
115 { 0x31, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
116 { 0x32, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
117 { 0x32, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
118 { 0x32, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
119 { 0x32, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
120 { 0x22, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
121 { 0x22, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
122 { 0x22, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
123 { 0x21, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
124 { 0x21, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
125 { 0x20, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
126 { 0x50, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
127 { 0x50, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
128 { 0x50, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
129 { 0x50, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
130 { 0x51, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
131 { 0x51, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
132 { 0x51, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
133 { 0x51, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
134 { 0x52, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
135 { 0x52, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
136 { 0x52, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
137 { 0x52, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
138 { 0x42, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
139 { 0x42, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
140 { 0x42, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
141 { 0x41, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
142 { 0x41, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
143 { 0x40, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
144 { 0x70, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
145 { 0x70, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
146 { 0x70, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
147 { 0x70, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
148 { 0x71, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
149 { 0x71, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
150 { 0x71, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
151 { 0x71, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
152 { 0x72, 0x000000ff, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
153 { 0x72, 0x0000ff00, 8, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
154 { 0x72, 0x00ff0000, 16, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
155 { 0x72, 0xff000000, 24, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
156 { 0x62, 0x00003fff, 0, 0x4, CISLANDS_CONFIGREG_DIDT_IND },
157 { 0x62, 0x03ff0000, 16, 0x80, CISLANDS_CONFIGREG_DIDT_IND },
158 { 0x62, 0x78000000, 27, 0x3, CISLANDS_CONFIGREG_DIDT_IND },
159 { 0x61, 0x0000ffff, 0, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
160 { 0x61, 0xffff0000, 16, 0x3FFF, CISLANDS_CONFIGREG_DIDT_IND },
161 { 0x60, 0x00000001, 0, 0x0, CISLANDS_CONFIGREG_DIDT_IND },
165 extern u8 rv770_get_memory_module_index(struct radeon_device *rdev);
166 extern int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
167 u32 arb_freq_src, u32 arb_freq_dest);
168 extern u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock);
169 extern u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode);
170 extern void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
171 u32 max_voltage_steps,
172 struct atom_voltage_table *voltage_table);
173 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
174 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
175 extern int ci_mc_load_microcode(struct radeon_device *rdev);
176 extern void cik_update_cg(struct radeon_device *rdev,
177 u32 block, bool enable);
179 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
180 struct atom_voltage_table_entry *voltage_table,
181 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd);
182 static int ci_set_power_limit(struct radeon_device *rdev, u32 n);
183 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
185 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate);
187 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
188 PPSMC_Msg msg, u32 parameter);
190 static struct ci_power_info *ci_get_pi(struct radeon_device *rdev)
192 struct ci_power_info *pi = rdev->pm.dpm.priv;
197 static struct ci_ps *ci_get_ps(struct radeon_ps *rps)
199 struct ci_ps *ps = rps->ps_priv;
204 static void ci_initialize_powertune_defaults(struct radeon_device *rdev)
206 struct ci_power_info *pi = ci_get_pi(rdev);
208 switch (rdev->pdev->device) {
216 pi->powertune_defaults = &defaults_bonaire_xt;
222 pi->powertune_defaults = &defaults_saturn_xt;
226 pi->powertune_defaults = &defaults_hawaii_xt;
230 pi->powertune_defaults = &defaults_hawaii_pro;
240 pi->powertune_defaults = &defaults_bonaire_xt;
244 pi->dte_tj_offset = 0;
246 pi->caps_power_containment = true;
247 pi->caps_cac = false;
248 pi->caps_sq_ramping = false;
249 pi->caps_db_ramping = false;
250 pi->caps_td_ramping = false;
251 pi->caps_tcp_ramping = false;
253 if (pi->caps_power_containment) {
255 if (rdev->family == CHIP_HAWAII)
256 pi->enable_bapm_feature = false;
258 pi->enable_bapm_feature = true;
259 pi->enable_tdc_limit_feature = true;
260 pi->enable_pkg_pwr_tracking_feature = true;
264 static u8 ci_convert_to_vid(u16 vddc)
266 return (6200 - (vddc * VOLTAGE_SCALE)) / 25;
269 static int ci_populate_bapm_vddc_vid_sidd(struct radeon_device *rdev)
271 struct ci_power_info *pi = ci_get_pi(rdev);
272 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
273 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
274 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2;
277 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries == NULL)
279 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count > 8)
281 if (rdev->pm.dpm.dyn_state.cac_leakage_table.count !=
282 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count)
285 for (i = 0; i < rdev->pm.dpm.dyn_state.cac_leakage_table.count; i++) {
286 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
287 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc1);
288 hi_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc2);
289 hi2_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc3);
291 lo_vid[i] = ci_convert_to_vid(rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].vddc);
292 hi_vid[i] = ci_convert_to_vid((u16)rdev->pm.dpm.dyn_state.cac_leakage_table.entries[i].leakage);
298 static int ci_populate_vddc_vid(struct radeon_device *rdev)
300 struct ci_power_info *pi = ci_get_pi(rdev);
301 u8 *vid = pi->smc_powertune_table.VddCVid;
304 if (pi->vddc_voltage_table.count > 8)
307 for (i = 0; i < pi->vddc_voltage_table.count; i++)
308 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value);
313 static int ci_populate_svi_load_line(struct radeon_device *rdev)
315 struct ci_power_info *pi = ci_get_pi(rdev);
316 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
318 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en;
319 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc;
320 pi->smc_powertune_table.SviLoadLineTrimVddC = 3;
321 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0;
326 static int ci_populate_tdc_limit(struct radeon_device *rdev)
328 struct ci_power_info *pi = ci_get_pi(rdev);
329 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
332 tdc_limit = rdev->pm.dpm.dyn_state.cac_tdp_table->tdc * 256;
333 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit);
334 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
335 pt_defaults->tdc_vddc_throttle_release_limit_perc;
336 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt;
341 static int ci_populate_dw8(struct radeon_device *rdev)
343 struct ci_power_info *pi = ci_get_pi(rdev);
344 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
347 ret = ci_read_smc_sram_dword(rdev,
348 SMU7_FIRMWARE_HEADER_LOCATION +
349 offsetof(SMU7_Firmware_Header, PmFuseTable) +
350 offsetof(SMU7_Discrete_PmFuses, TdcWaterfallCtl),
351 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl,
356 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl;
361 static int ci_populate_fuzzy_fan(struct radeon_device *rdev)
363 struct ci_power_info *pi = ci_get_pi(rdev);
365 if ((rdev->pm.dpm.fan.fan_output_sensitivity & (1 << 15)) ||
366 (rdev->pm.dpm.fan.fan_output_sensitivity == 0))
367 rdev->pm.dpm.fan.fan_output_sensitivity =
368 rdev->pm.dpm.fan.default_fan_output_sensitivity;
370 pi->smc_powertune_table.FuzzyFan_PwmSetDelta =
371 cpu_to_be16(rdev->pm.dpm.fan.fan_output_sensitivity);
376 static int ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(struct radeon_device *rdev)
378 struct ci_power_info *pi = ci_get_pi(rdev);
379 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd;
380 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd;
383 min = max = hi_vid[0];
384 for (i = 0; i < 8; i++) {
385 if (0 != hi_vid[i]) {
392 if (0 != lo_vid[i]) {
400 if ((min == 0) || (max == 0))
402 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max;
403 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min;
408 static int ci_populate_bapm_vddc_base_leakage_sidd(struct radeon_device *rdev)
410 struct ci_power_info *pi = ci_get_pi(rdev);
411 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd;
412 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd;
413 struct radeon_cac_tdp_table *cac_tdp_table =
414 rdev->pm.dpm.dyn_state.cac_tdp_table;
416 hi_sidd = cac_tdp_table->high_cac_leakage / 100 * 256;
417 lo_sidd = cac_tdp_table->low_cac_leakage / 100 * 256;
419 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd);
420 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd);
425 static int ci_populate_bapm_parameters_in_dpm_table(struct radeon_device *rdev)
427 struct ci_power_info *pi = ci_get_pi(rdev);
428 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults;
429 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table;
430 struct radeon_cac_tdp_table *cac_tdp_table =
431 rdev->pm.dpm.dyn_state.cac_tdp_table;
432 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
437 dpm_table->DefaultTdp = cac_tdp_table->tdp * 256;
438 dpm_table->TargetTdp = cac_tdp_table->configurable_tdp * 256;
440 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset;
441 dpm_table->GpuTjMax =
442 (u8)(pi->thermal_temp_setting.temperature_high / 1000);
443 dpm_table->GpuTjHyst = 8;
445 dpm_table->DTEAmbientTempBase = pt_defaults->dte_ambient_temp_base;
448 dpm_table->PPM_PkgPwrLimit = cpu_to_be16((u16)ppm->dgpu_tdp * 256 / 1000);
449 dpm_table->PPM_TemperatureLimit = cpu_to_be16((u16)ppm->tj_max * 256);
451 dpm_table->PPM_PkgPwrLimit = cpu_to_be16(0);
452 dpm_table->PPM_TemperatureLimit = cpu_to_be16(0);
455 dpm_table->BAPM_TEMP_GRADIENT = cpu_to_be32(pt_defaults->bapm_temp_gradient);
456 def1 = pt_defaults->bapmti_r;
457 def2 = pt_defaults->bapmti_rc;
459 for (i = 0; i < SMU7_DTE_ITERATIONS; i++) {
460 for (j = 0; j < SMU7_DTE_SOURCES; j++) {
461 for (k = 0; k < SMU7_DTE_SINKS; k++) {
462 dpm_table->BAPMTI_R[i][j][k] = cpu_to_be16(*def1);
463 dpm_table->BAPMTI_RC[i][j][k] = cpu_to_be16(*def2);
473 static int ci_populate_pm_base(struct radeon_device *rdev)
475 struct ci_power_info *pi = ci_get_pi(rdev);
476 u32 pm_fuse_table_offset;
479 if (pi->caps_power_containment) {
480 ret = ci_read_smc_sram_dword(rdev,
481 SMU7_FIRMWARE_HEADER_LOCATION +
482 offsetof(SMU7_Firmware_Header, PmFuseTable),
483 &pm_fuse_table_offset, pi->sram_end);
486 ret = ci_populate_bapm_vddc_vid_sidd(rdev);
489 ret = ci_populate_vddc_vid(rdev);
492 ret = ci_populate_svi_load_line(rdev);
495 ret = ci_populate_tdc_limit(rdev);
498 ret = ci_populate_dw8(rdev);
501 ret = ci_populate_fuzzy_fan(rdev);
504 ret = ci_min_max_v_gnbl_pm_lid_from_bapm_vddc(rdev);
507 ret = ci_populate_bapm_vddc_base_leakage_sidd(rdev);
510 ret = ci_copy_bytes_to_smc(rdev, pm_fuse_table_offset,
511 (u8 *)&pi->smc_powertune_table,
512 sizeof(SMU7_Discrete_PmFuses), pi->sram_end);
520 static void ci_do_enable_didt(struct radeon_device *rdev, const bool enable)
522 struct ci_power_info *pi = ci_get_pi(rdev);
525 if (pi->caps_sq_ramping) {
526 data = RREG32_DIDT(DIDT_SQ_CTRL0);
528 data |= DIDT_CTRL_EN;
530 data &= ~DIDT_CTRL_EN;
531 WREG32_DIDT(DIDT_SQ_CTRL0, data);
534 if (pi->caps_db_ramping) {
535 data = RREG32_DIDT(DIDT_DB_CTRL0);
537 data |= DIDT_CTRL_EN;
539 data &= ~DIDT_CTRL_EN;
540 WREG32_DIDT(DIDT_DB_CTRL0, data);
543 if (pi->caps_td_ramping) {
544 data = RREG32_DIDT(DIDT_TD_CTRL0);
546 data |= DIDT_CTRL_EN;
548 data &= ~DIDT_CTRL_EN;
549 WREG32_DIDT(DIDT_TD_CTRL0, data);
552 if (pi->caps_tcp_ramping) {
553 data = RREG32_DIDT(DIDT_TCP_CTRL0);
555 data |= DIDT_CTRL_EN;
557 data &= ~DIDT_CTRL_EN;
558 WREG32_DIDT(DIDT_TCP_CTRL0, data);
562 static int ci_program_pt_config_registers(struct radeon_device *rdev,
563 const struct ci_pt_config_reg *cac_config_regs)
565 const struct ci_pt_config_reg *config_regs = cac_config_regs;
569 if (config_regs == NULL)
572 while (config_regs->offset != 0xFFFFFFFF) {
573 if (config_regs->type == CISLANDS_CONFIGREG_CACHE) {
574 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
576 switch (config_regs->type) {
577 case CISLANDS_CONFIGREG_SMC_IND:
578 data = RREG32_SMC(config_regs->offset);
580 case CISLANDS_CONFIGREG_DIDT_IND:
581 data = RREG32_DIDT(config_regs->offset);
584 data = RREG32(config_regs->offset << 2);
588 data &= ~config_regs->mask;
589 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
592 switch (config_regs->type) {
593 case CISLANDS_CONFIGREG_SMC_IND:
594 WREG32_SMC(config_regs->offset, data);
596 case CISLANDS_CONFIGREG_DIDT_IND:
597 WREG32_DIDT(config_regs->offset, data);
600 WREG32(config_regs->offset << 2, data);
610 static int ci_enable_didt(struct radeon_device *rdev, bool enable)
612 struct ci_power_info *pi = ci_get_pi(rdev);
615 if (pi->caps_sq_ramping || pi->caps_db_ramping ||
616 pi->caps_td_ramping || pi->caps_tcp_ramping) {
617 cik_enter_rlc_safe_mode(rdev);
620 ret = ci_program_pt_config_registers(rdev, didt_config_ci);
622 cik_exit_rlc_safe_mode(rdev);
627 ci_do_enable_didt(rdev, enable);
629 cik_exit_rlc_safe_mode(rdev);
635 static int ci_enable_power_containment(struct radeon_device *rdev, bool enable)
637 struct ci_power_info *pi = ci_get_pi(rdev);
638 PPSMC_Result smc_result;
642 pi->power_containment_features = 0;
643 if (pi->caps_power_containment) {
644 if (pi->enable_bapm_feature) {
645 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
646 if (smc_result != PPSMC_Result_OK)
649 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM;
652 if (pi->enable_tdc_limit_feature) {
653 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitEnable);
654 if (smc_result != PPSMC_Result_OK)
657 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
660 if (pi->enable_pkg_pwr_tracking_feature) {
661 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitEnable);
662 if (smc_result != PPSMC_Result_OK) {
665 struct radeon_cac_tdp_table *cac_tdp_table =
666 rdev->pm.dpm.dyn_state.cac_tdp_table;
667 u32 default_pwr_limit =
668 (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
670 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
672 ci_set_power_limit(rdev, default_pwr_limit);
677 if (pi->caps_power_containment && pi->power_containment_features) {
678 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit)
679 ci_send_msg_to_smc(rdev, PPSMC_MSG_TDCLimitDisable);
681 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM)
682 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
684 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit)
685 ci_send_msg_to_smc(rdev, PPSMC_MSG_PkgPwrLimitDisable);
686 pi->power_containment_features = 0;
693 static int ci_enable_smc_cac(struct radeon_device *rdev, bool enable)
695 struct ci_power_info *pi = ci_get_pi(rdev);
696 PPSMC_Result smc_result;
701 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
702 if (smc_result != PPSMC_Result_OK) {
704 pi->cac_enabled = false;
706 pi->cac_enabled = true;
708 } else if (pi->cac_enabled) {
709 ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
710 pi->cac_enabled = false;
717 static int ci_enable_thermal_based_sclk_dpm(struct radeon_device *rdev,
720 struct ci_power_info *pi = ci_get_pi(rdev);
721 PPSMC_Result smc_result = PPSMC_Result_OK;
723 if (pi->thermal_sclk_dpm_enabled) {
725 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_ENABLE_THERMAL_DPM);
727 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DISABLE_THERMAL_DPM);
730 if (smc_result == PPSMC_Result_OK)
736 static int ci_power_control_set_level(struct radeon_device *rdev)
738 struct ci_power_info *pi = ci_get_pi(rdev);
739 struct radeon_cac_tdp_table *cac_tdp_table =
740 rdev->pm.dpm.dyn_state.cac_tdp_table;
744 bool adjust_polarity = false; /* ??? */
746 if (pi->caps_power_containment) {
747 adjust_percent = adjust_polarity ?
748 rdev->pm.dpm.tdp_adjustment : (-1 * rdev->pm.dpm.tdp_adjustment);
749 target_tdp = ((100 + adjust_percent) *
750 (s32)cac_tdp_table->configurable_tdp) / 100;
752 ret = ci_set_overdrive_target_tdp(rdev, (u32)target_tdp);
758 void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
760 struct ci_power_info *pi = ci_get_pi(rdev);
762 if (pi->uvd_power_gated == gate)
765 pi->uvd_power_gated = gate;
767 ci_update_uvd_dpm(rdev, gate);
770 bool ci_dpm_vblank_too_short(struct radeon_device *rdev)
772 struct ci_power_info *pi = ci_get_pi(rdev);
773 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
774 u32 switch_limit = pi->mem_gddr5 ? 450 : 300;
776 if (vblank_time < switch_limit)
783 static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
784 struct radeon_ps *rps)
786 struct ci_ps *ps = ci_get_ps(rps);
787 struct ci_power_info *pi = ci_get_pi(rdev);
788 struct radeon_clock_and_voltage_limits *max_limits;
789 bool disable_mclk_switching;
793 if (rps->vce_active) {
794 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
795 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
801 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
802 ci_dpm_vblank_too_short(rdev))
803 disable_mclk_switching = true;
805 disable_mclk_switching = false;
807 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
808 pi->battery_state = true;
810 pi->battery_state = false;
812 if (rdev->pm.dpm.ac_power)
813 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
815 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
817 if (rdev->pm.dpm.ac_power == false) {
818 for (i = 0; i < ps->performance_level_count; i++) {
819 if (ps->performance_levels[i].mclk > max_limits->mclk)
820 ps->performance_levels[i].mclk = max_limits->mclk;
821 if (ps->performance_levels[i].sclk > max_limits->sclk)
822 ps->performance_levels[i].sclk = max_limits->sclk;
826 /* XXX validate the min clocks required for display */
828 if (disable_mclk_switching) {
829 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
830 sclk = ps->performance_levels[0].sclk;
832 mclk = ps->performance_levels[0].mclk;
833 sclk = ps->performance_levels[0].sclk;
836 if (rps->vce_active) {
837 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
838 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
839 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
840 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
843 ps->performance_levels[0].sclk = sclk;
844 ps->performance_levels[0].mclk = mclk;
846 if (ps->performance_levels[1].sclk < ps->performance_levels[0].sclk)
847 ps->performance_levels[1].sclk = ps->performance_levels[0].sclk;
849 if (disable_mclk_switching) {
850 if (ps->performance_levels[0].mclk < ps->performance_levels[1].mclk)
851 ps->performance_levels[0].mclk = ps->performance_levels[1].mclk;
853 if (ps->performance_levels[1].mclk < ps->performance_levels[0].mclk)
854 ps->performance_levels[1].mclk = ps->performance_levels[0].mclk;
858 static int ci_thermal_set_temperature_range(struct radeon_device *rdev,
859 int min_temp, int max_temp)
861 int low_temp = 0 * 1000;
862 int high_temp = 255 * 1000;
865 if (low_temp < min_temp)
867 if (high_temp > max_temp)
868 high_temp = max_temp;
869 if (high_temp < low_temp) {
870 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
874 tmp = RREG32_SMC(CG_THERMAL_INT);
875 tmp &= ~(CI_DIG_THERM_INTH_MASK | CI_DIG_THERM_INTL_MASK);
876 tmp |= CI_DIG_THERM_INTH(high_temp / 1000) |
877 CI_DIG_THERM_INTL(low_temp / 1000);
878 WREG32_SMC(CG_THERMAL_INT, tmp);
881 /* XXX: need to figure out how to handle this properly */
882 tmp = RREG32_SMC(CG_THERMAL_CTRL);
883 tmp &= DIG_THERM_DPM_MASK;
884 tmp |= DIG_THERM_DPM(high_temp / 1000);
885 WREG32_SMC(CG_THERMAL_CTRL, tmp);
888 rdev->pm.dpm.thermal.min_temp = low_temp;
889 rdev->pm.dpm.thermal.max_temp = high_temp;
894 static int ci_thermal_enable_alert(struct radeon_device *rdev,
897 u32 thermal_int = RREG32_SMC(CG_THERMAL_INT);
901 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
902 WREG32_SMC(CG_THERMAL_INT, thermal_int);
903 rdev->irq.dpm_thermal = false;
904 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Enable);
905 if (result != PPSMC_Result_OK) {
906 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
910 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
911 WREG32_SMC(CG_THERMAL_INT, thermal_int);
912 rdev->irq.dpm_thermal = true;
913 result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Thermal_Cntl_Disable);
914 if (result != PPSMC_Result_OK) {
915 DRM_DEBUG_KMS("Could not disable thermal interrupts.\n");
923 static void ci_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode)
925 struct ci_power_info *pi = ci_get_pi(rdev);
928 if (pi->fan_ctrl_is_in_default_mode) {
929 tmp = (RREG32_SMC(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
930 pi->fan_ctrl_default_mode = tmp;
931 tmp = (RREG32_SMC(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
933 pi->fan_ctrl_is_in_default_mode = false;
936 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
938 WREG32_SMC(CG_FDO_CTRL2, tmp);
940 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
941 tmp |= FDO_PWM_MODE(mode);
942 WREG32_SMC(CG_FDO_CTRL2, tmp);
945 static int ci_thermal_setup_fan_table(struct radeon_device *rdev)
947 struct ci_power_info *pi = ci_get_pi(rdev);
948 SMU7_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
950 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
951 u16 fdo_min, slope1, slope2;
952 u32 reference_clock, tmp;
956 if (!pi->fan_table_start) {
957 rdev->pm.dpm.fan.ucode_fan_control = false;
961 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
964 rdev->pm.dpm.fan.ucode_fan_control = false;
968 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100;
969 do_div(tmp64, 10000);
970 fdo_min = (u16)tmp64;
972 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min;
973 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med;
975 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min;
976 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med;
978 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
979 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
981 fan_table.TempMin = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100);
982 fan_table.TempMed = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100);
983 fan_table.TempMax = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100);
985 fan_table.Slope1 = cpu_to_be16(slope1);
986 fan_table.Slope2 = cpu_to_be16(slope2);
988 fan_table.FdoMin = cpu_to_be16(fdo_min);
990 fan_table.HystDown = cpu_to_be16(rdev->pm.dpm.fan.t_hyst);
992 fan_table.HystUp = cpu_to_be16(1);
994 fan_table.HystSlope = cpu_to_be16(1);
996 fan_table.TempRespLim = cpu_to_be16(5);
998 reference_clock = radeon_get_xclk(rdev);
1000 fan_table.RefreshPeriod = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay *
1001 reference_clock) / 1600);
1003 fan_table.FdoMax = cpu_to_be16((u16)duty100);
1005 tmp = (RREG32_SMC(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
1006 fan_table.TempSrc = (uint8_t)tmp;
1008 ret = ci_copy_bytes_to_smc(rdev,
1009 pi->fan_table_start,
1015 DRM_ERROR("Failed to load fan table to the SMC.");
1016 rdev->pm.dpm.fan.ucode_fan_control = false;
1022 static int ci_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev)
1024 struct ci_power_info *pi = ci_get_pi(rdev);
1027 if (pi->caps_od_fuzzy_fan_control_support) {
1028 ret = ci_send_msg_to_smc_with_parameter(rdev,
1029 PPSMC_StartFanControl,
1031 if (ret != PPSMC_Result_OK)
1033 ret = ci_send_msg_to_smc_with_parameter(rdev,
1034 PPSMC_MSG_SetFanPwmMax,
1035 rdev->pm.dpm.fan.default_max_fan_pwm);
1036 if (ret != PPSMC_Result_OK)
1039 ret = ci_send_msg_to_smc_with_parameter(rdev,
1040 PPSMC_StartFanControl,
1042 if (ret != PPSMC_Result_OK)
1050 static int ci_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev)
1054 ret = ci_send_msg_to_smc(rdev, PPSMC_StopFanControl);
1055 if (ret == PPSMC_Result_OK)
1061 static int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
1067 if (rdev->pm.no_fan)
1070 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1071 duty = (RREG32_SMC(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
1076 tmp64 = (u64)duty * 100;
1077 do_div(tmp64, duty100);
1078 *speed = (u32)tmp64;
1086 static int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
1093 if (rdev->pm.no_fan)
1099 if (rdev->pm.dpm.fan.ucode_fan_control)
1100 ci_fan_ctrl_stop_smc_fan_control(rdev);
1102 duty100 = (RREG32_SMC(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
1107 tmp64 = (u64)speed * duty100;
1111 tmp = RREG32_SMC(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
1112 tmp |= FDO_STATIC_DUTY(duty);
1113 WREG32_SMC(CG_FDO_CTRL0, tmp);
1115 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
1120 static int ci_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev,
1124 u32 xclk = radeon_get_xclk(rdev);
1126 if (rdev->pm.no_fan)
1129 if (rdev->pm.fan_pulses_per_revolution == 0)
1132 tach_period = (RREG32_SMC(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
1133 if (tach_period == 0)
1136 *speed = 60 * xclk * 10000 / tach_period;
1141 static int ci_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev,
1144 u32 tach_period, tmp;
1145 u32 xclk = radeon_get_xclk(rdev);
1147 if (rdev->pm.no_fan)
1150 if (rdev->pm.fan_pulses_per_revolution == 0)
1153 if ((speed < rdev->pm.fan_min_rpm) ||
1154 (speed > rdev->pm.fan_max_rpm))
1157 if (rdev->pm.dpm.fan.ucode_fan_control)
1158 ci_fan_ctrl_stop_smc_fan_control(rdev);
1160 tach_period = 60 * xclk * 10000 / (8 * speed);
1161 tmp = RREG32_SMC(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
1162 tmp |= TARGET_PERIOD(tach_period);
1163 WREG32_SMC(CG_TACH_CTRL, tmp);
1165 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM);
1171 static void ci_fan_ctrl_set_default_mode(struct radeon_device *rdev)
1173 struct ci_power_info *pi = ci_get_pi(rdev);
1176 if (!pi->fan_ctrl_is_in_default_mode) {
1177 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
1178 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode);
1179 WREG32_SMC(CG_FDO_CTRL2, tmp);
1181 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TMIN_MASK;
1182 tmp |= TMIN(pi->t_min);
1183 WREG32_SMC(CG_FDO_CTRL2, tmp);
1184 pi->fan_ctrl_is_in_default_mode = true;
1188 static void ci_thermal_start_smc_fan_control(struct radeon_device *rdev)
1190 if (rdev->pm.dpm.fan.ucode_fan_control) {
1191 ci_fan_ctrl_start_smc_fan_control(rdev);
1192 ci_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC);
1196 static void ci_thermal_initialize(struct radeon_device *rdev)
1200 if (rdev->pm.fan_pulses_per_revolution) {
1201 tmp = RREG32_SMC(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
1202 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1);
1203 WREG32_SMC(CG_TACH_CTRL, tmp);
1206 tmp = RREG32_SMC(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
1207 tmp |= TACH_PWM_RESP_RATE(0x28);
1208 WREG32_SMC(CG_FDO_CTRL2, tmp);
1211 static int ci_thermal_start_thermal_controller(struct radeon_device *rdev)
1215 ci_thermal_initialize(rdev);
1216 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1219 ret = ci_thermal_enable_alert(rdev, true);
1222 if (rdev->pm.dpm.fan.ucode_fan_control) {
1223 ret = ci_thermal_setup_fan_table(rdev);
1226 ci_thermal_start_smc_fan_control(rdev);
1232 static void ci_thermal_stop_thermal_controller(struct radeon_device *rdev)
1234 if (!rdev->pm.no_fan)
1235 ci_fan_ctrl_set_default_mode(rdev);
1239 static int ci_read_smc_soft_register(struct radeon_device *rdev,
1240 u16 reg_offset, u32 *value)
1242 struct ci_power_info *pi = ci_get_pi(rdev);
1244 return ci_read_smc_sram_dword(rdev,
1245 pi->soft_regs_start + reg_offset,
1246 value, pi->sram_end);
1250 static int ci_write_smc_soft_register(struct radeon_device *rdev,
1251 u16 reg_offset, u32 value)
1253 struct ci_power_info *pi = ci_get_pi(rdev);
1255 return ci_write_smc_sram_dword(rdev,
1256 pi->soft_regs_start + reg_offset,
1257 value, pi->sram_end);
1260 static void ci_init_fps_limits(struct radeon_device *rdev)
1262 struct ci_power_info *pi = ci_get_pi(rdev);
1263 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
1269 table->FpsHighT = cpu_to_be16(tmp);
1272 table->FpsLowT = cpu_to_be16(tmp);
1276 static int ci_update_sclk_t(struct radeon_device *rdev)
1278 struct ci_power_info *pi = ci_get_pi(rdev);
1280 u32 low_sclk_interrupt_t = 0;
1282 if (pi->caps_sclk_throttle_low_notification) {
1283 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
1285 ret = ci_copy_bytes_to_smc(rdev,
1286 pi->dpm_table_start +
1287 offsetof(SMU7_Discrete_DpmTable, LowSclkInterruptT),
1288 (u8 *)&low_sclk_interrupt_t,
1289 sizeof(u32), pi->sram_end);
1296 static void ci_get_leakage_voltages(struct radeon_device *rdev)
1298 struct ci_power_info *pi = ci_get_pi(rdev);
1299 u16 leakage_id, virtual_voltage_id;
1303 pi->vddc_leakage.count = 0;
1304 pi->vddci_leakage.count = 0;
1306 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_EVV) {
1307 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1308 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1309 if (radeon_atom_get_voltage_evv(rdev, virtual_voltage_id, &vddc) != 0)
1311 if (vddc != 0 && vddc != virtual_voltage_id) {
1312 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1313 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1314 pi->vddc_leakage.count++;
1317 } else if (radeon_atom_get_leakage_id_from_vbios(rdev, &leakage_id) == 0) {
1318 for (i = 0; i < CISLANDS_MAX_LEAKAGE_COUNT; i++) {
1319 virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
1320 if (radeon_atom_get_leakage_vddc_based_on_leakage_params(rdev, &vddc, &vddci,
1323 if (vddc != 0 && vddc != virtual_voltage_id) {
1324 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc;
1325 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id;
1326 pi->vddc_leakage.count++;
1328 if (vddci != 0 && vddci != virtual_voltage_id) {
1329 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci;
1330 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id;
1331 pi->vddci_leakage.count++;
1338 static void ci_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
1340 struct ci_power_info *pi = ci_get_pi(rdev);
1341 bool want_thermal_protection;
1342 enum radeon_dpm_event_src dpm_event_src;
1348 want_thermal_protection = false;
1350 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
1351 want_thermal_protection = true;
1352 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
1354 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
1355 want_thermal_protection = true;
1356 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
1358 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
1359 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
1360 want_thermal_protection = true;
1361 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
1365 if (want_thermal_protection) {
1367 /* XXX: need to figure out how to handle this properly */
1368 tmp = RREG32_SMC(CG_THERMAL_CTRL);
1369 tmp &= DPM_EVENT_SRC_MASK;
1370 tmp |= DPM_EVENT_SRC(dpm_event_src);
1371 WREG32_SMC(CG_THERMAL_CTRL, tmp);
1374 tmp = RREG32_SMC(GENERAL_PWRMGT);
1375 if (pi->thermal_protection)
1376 tmp &= ~THERMAL_PROTECTION_DIS;
1378 tmp |= THERMAL_PROTECTION_DIS;
1379 WREG32_SMC(GENERAL_PWRMGT, tmp);
1381 tmp = RREG32_SMC(GENERAL_PWRMGT);
1382 tmp |= THERMAL_PROTECTION_DIS;
1383 WREG32_SMC(GENERAL_PWRMGT, tmp);
1387 static void ci_enable_auto_throttle_source(struct radeon_device *rdev,
1388 enum radeon_dpm_auto_throttle_src source,
1391 struct ci_power_info *pi = ci_get_pi(rdev);
1394 if (!(pi->active_auto_throttle_sources & (1 << source))) {
1395 pi->active_auto_throttle_sources |= 1 << source;
1396 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1399 if (pi->active_auto_throttle_sources & (1 << source)) {
1400 pi->active_auto_throttle_sources &= ~(1 << source);
1401 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
1406 static void ci_enable_vr_hot_gpio_interrupt(struct radeon_device *rdev)
1408 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1409 ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableVRHotGPIOInterrupt);
1412 static int ci_unfreeze_sclk_mclk_dpm(struct radeon_device *rdev)
1414 struct ci_power_info *pi = ci_get_pi(rdev);
1415 PPSMC_Result smc_result;
1417 if (!pi->need_update_smu7_dpm_table)
1420 if ((!pi->sclk_dpm_key_disabled) &&
1421 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1422 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_UnfreezeLevel);
1423 if (smc_result != PPSMC_Result_OK)
1427 if ((!pi->mclk_dpm_key_disabled) &&
1428 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1429 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_UnfreezeLevel);
1430 if (smc_result != PPSMC_Result_OK)
1434 pi->need_update_smu7_dpm_table = 0;
1438 static int ci_enable_sclk_mclk_dpm(struct radeon_device *rdev, bool enable)
1440 struct ci_power_info *pi = ci_get_pi(rdev);
1441 PPSMC_Result smc_result;
1444 if (!pi->sclk_dpm_key_disabled) {
1445 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Enable);
1446 if (smc_result != PPSMC_Result_OK)
1450 if (!pi->mclk_dpm_key_disabled) {
1451 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Enable);
1452 if (smc_result != PPSMC_Result_OK)
1455 WREG32_P(MC_SEQ_CNTL_3, CAC_EN, ~CAC_EN);
1457 WREG32_SMC(LCAC_MC0_CNTL, 0x05);
1458 WREG32_SMC(LCAC_MC1_CNTL, 0x05);
1459 WREG32_SMC(LCAC_CPL_CNTL, 0x100005);
1463 WREG32_SMC(LCAC_MC0_CNTL, 0x400005);
1464 WREG32_SMC(LCAC_MC1_CNTL, 0x400005);
1465 WREG32_SMC(LCAC_CPL_CNTL, 0x500005);
1468 if (!pi->sclk_dpm_key_disabled) {
1469 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_DPM_Disable);
1470 if (smc_result != PPSMC_Result_OK)
1474 if (!pi->mclk_dpm_key_disabled) {
1475 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_Disable);
1476 if (smc_result != PPSMC_Result_OK)
1484 static int ci_start_dpm(struct radeon_device *rdev)
1486 struct ci_power_info *pi = ci_get_pi(rdev);
1487 PPSMC_Result smc_result;
1491 tmp = RREG32_SMC(GENERAL_PWRMGT);
1492 tmp |= GLOBAL_PWRMGT_EN;
1493 WREG32_SMC(GENERAL_PWRMGT, tmp);
1495 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1496 tmp |= DYNAMIC_PM_EN;
1497 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1499 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VoltageChangeTimeout), 0x1000);
1501 WREG32_P(BIF_LNCNT_RESET, 0, ~RESET_LNCNT_EN);
1503 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Enable);
1504 if (smc_result != PPSMC_Result_OK)
1507 ret = ci_enable_sclk_mclk_dpm(rdev, true);
1511 if (!pi->pcie_dpm_key_disabled) {
1512 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Enable);
1513 if (smc_result != PPSMC_Result_OK)
1520 static int ci_freeze_sclk_mclk_dpm(struct radeon_device *rdev)
1522 struct ci_power_info *pi = ci_get_pi(rdev);
1523 PPSMC_Result smc_result;
1525 if (!pi->need_update_smu7_dpm_table)
1528 if ((!pi->sclk_dpm_key_disabled) &&
1529 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) {
1530 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_SCLKDPM_FreezeLevel);
1531 if (smc_result != PPSMC_Result_OK)
1535 if ((!pi->mclk_dpm_key_disabled) &&
1536 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) {
1537 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_MCLKDPM_FreezeLevel);
1538 if (smc_result != PPSMC_Result_OK)
1545 static int ci_stop_dpm(struct radeon_device *rdev)
1547 struct ci_power_info *pi = ci_get_pi(rdev);
1548 PPSMC_Result smc_result;
1552 tmp = RREG32_SMC(GENERAL_PWRMGT);
1553 tmp &= ~GLOBAL_PWRMGT_EN;
1554 WREG32_SMC(GENERAL_PWRMGT, tmp);
1556 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1557 tmp &= ~DYNAMIC_PM_EN;
1558 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1560 if (!pi->pcie_dpm_key_disabled) {
1561 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_PCIeDPM_Disable);
1562 if (smc_result != PPSMC_Result_OK)
1566 ret = ci_enable_sclk_mclk_dpm(rdev, false);
1570 smc_result = ci_send_msg_to_smc(rdev, PPSMC_MSG_Voltage_Cntl_Disable);
1571 if (smc_result != PPSMC_Result_OK)
1577 static void ci_enable_sclk_control(struct radeon_device *rdev, bool enable)
1579 u32 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1582 tmp &= ~SCLK_PWRMGT_OFF;
1584 tmp |= SCLK_PWRMGT_OFF;
1585 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
1589 static int ci_notify_hw_of_power_source(struct radeon_device *rdev,
1592 struct ci_power_info *pi = ci_get_pi(rdev);
1593 struct radeon_cac_tdp_table *cac_tdp_table =
1594 rdev->pm.dpm.dyn_state.cac_tdp_table;
1598 power_limit = (u32)(cac_tdp_table->maximum_power_delivery_limit * 256);
1600 power_limit = (u32)(cac_tdp_table->battery_power_limit * 256);
1602 ci_set_power_limit(rdev, power_limit);
1604 if (pi->caps_automatic_dc_transition) {
1606 ci_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC);
1608 ci_send_msg_to_smc(rdev, PPSMC_MSG_Remove_DC_Clamp);
1615 static PPSMC_Result ci_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1616 PPSMC_Msg msg, u32 parameter)
1618 WREG32(SMC_MSG_ARG_0, parameter);
1619 return ci_send_msg_to_smc(rdev, msg);
1622 static PPSMC_Result ci_send_msg_to_smc_return_parameter(struct radeon_device *rdev,
1623 PPSMC_Msg msg, u32 *parameter)
1625 PPSMC_Result smc_result;
1627 smc_result = ci_send_msg_to_smc(rdev, msg);
1629 if ((smc_result == PPSMC_Result_OK) && parameter)
1630 *parameter = RREG32(SMC_MSG_ARG_0);
1635 static int ci_dpm_force_state_sclk(struct radeon_device *rdev, u32 n)
1637 struct ci_power_info *pi = ci_get_pi(rdev);
1639 if (!pi->sclk_dpm_key_disabled) {
1640 PPSMC_Result smc_result =
1641 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SCLKDPM_SetEnabledMask, 1 << n);
1642 if (smc_result != PPSMC_Result_OK)
1649 static int ci_dpm_force_state_mclk(struct radeon_device *rdev, u32 n)
1651 struct ci_power_info *pi = ci_get_pi(rdev);
1653 if (!pi->mclk_dpm_key_disabled) {
1654 PPSMC_Result smc_result =
1655 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_MCLKDPM_SetEnabledMask, 1 << n);
1656 if (smc_result != PPSMC_Result_OK)
1663 static int ci_dpm_force_state_pcie(struct radeon_device *rdev, u32 n)
1665 struct ci_power_info *pi = ci_get_pi(rdev);
1667 if (!pi->pcie_dpm_key_disabled) {
1668 PPSMC_Result smc_result =
1669 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PCIeDPM_ForceLevel, n);
1670 if (smc_result != PPSMC_Result_OK)
1677 static int ci_set_power_limit(struct radeon_device *rdev, u32 n)
1679 struct ci_power_info *pi = ci_get_pi(rdev);
1681 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
1682 PPSMC_Result smc_result =
1683 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_PkgPwrSetLimit, n);
1684 if (smc_result != PPSMC_Result_OK)
1691 static int ci_set_overdrive_target_tdp(struct radeon_device *rdev,
1694 PPSMC_Result smc_result =
1695 ci_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
1696 if (smc_result != PPSMC_Result_OK)
1701 static int ci_set_boot_state(struct radeon_device *rdev)
1703 return ci_enable_sclk_mclk_dpm(rdev, false);
1706 static u32 ci_get_average_sclk_freq(struct radeon_device *rdev)
1709 PPSMC_Result smc_result =
1710 ci_send_msg_to_smc_return_parameter(rdev,
1711 PPSMC_MSG_API_GetSclkFrequency,
1713 if (smc_result != PPSMC_Result_OK)
1719 static u32 ci_get_average_mclk_freq(struct radeon_device *rdev)
1722 PPSMC_Result smc_result =
1723 ci_send_msg_to_smc_return_parameter(rdev,
1724 PPSMC_MSG_API_GetMclkFrequency,
1726 if (smc_result != PPSMC_Result_OK)
1732 static void ci_dpm_start_smc(struct radeon_device *rdev)
1736 ci_program_jump_on_start(rdev);
1737 ci_start_smc_clock(rdev);
1739 for (i = 0; i < rdev->usec_timeout; i++) {
1740 if (RREG32_SMC(FIRMWARE_FLAGS) & INTERRUPTS_ENABLED)
1745 static void ci_dpm_stop_smc(struct radeon_device *rdev)
1748 ci_stop_smc_clock(rdev);
1751 static int ci_process_firmware_header(struct radeon_device *rdev)
1753 struct ci_power_info *pi = ci_get_pi(rdev);
1757 ret = ci_read_smc_sram_dword(rdev,
1758 SMU7_FIRMWARE_HEADER_LOCATION +
1759 offsetof(SMU7_Firmware_Header, DpmTable),
1760 &tmp, pi->sram_end);
1764 pi->dpm_table_start = tmp;
1766 ret = ci_read_smc_sram_dword(rdev,
1767 SMU7_FIRMWARE_HEADER_LOCATION +
1768 offsetof(SMU7_Firmware_Header, SoftRegisters),
1769 &tmp, pi->sram_end);
1773 pi->soft_regs_start = tmp;
1775 ret = ci_read_smc_sram_dword(rdev,
1776 SMU7_FIRMWARE_HEADER_LOCATION +
1777 offsetof(SMU7_Firmware_Header, mcRegisterTable),
1778 &tmp, pi->sram_end);
1782 pi->mc_reg_table_start = tmp;
1784 ret = ci_read_smc_sram_dword(rdev,
1785 SMU7_FIRMWARE_HEADER_LOCATION +
1786 offsetof(SMU7_Firmware_Header, FanTable),
1787 &tmp, pi->sram_end);
1791 pi->fan_table_start = tmp;
1793 ret = ci_read_smc_sram_dword(rdev,
1794 SMU7_FIRMWARE_HEADER_LOCATION +
1795 offsetof(SMU7_Firmware_Header, mcArbDramTimingTable),
1796 &tmp, pi->sram_end);
1800 pi->arb_table_start = tmp;
1805 static void ci_read_clock_registers(struct radeon_device *rdev)
1807 struct ci_power_info *pi = ci_get_pi(rdev);
1809 pi->clock_registers.cg_spll_func_cntl =
1810 RREG32_SMC(CG_SPLL_FUNC_CNTL);
1811 pi->clock_registers.cg_spll_func_cntl_2 =
1812 RREG32_SMC(CG_SPLL_FUNC_CNTL_2);
1813 pi->clock_registers.cg_spll_func_cntl_3 =
1814 RREG32_SMC(CG_SPLL_FUNC_CNTL_3);
1815 pi->clock_registers.cg_spll_func_cntl_4 =
1816 RREG32_SMC(CG_SPLL_FUNC_CNTL_4);
1817 pi->clock_registers.cg_spll_spread_spectrum =
1818 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1819 pi->clock_registers.cg_spll_spread_spectrum_2 =
1820 RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM_2);
1821 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1822 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1823 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1824 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1825 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
1826 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
1827 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
1828 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1829 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1832 static void ci_init_sclk_t(struct radeon_device *rdev)
1834 struct ci_power_info *pi = ci_get_pi(rdev);
1836 pi->low_sclk_interrupt_t = 0;
1839 static void ci_enable_thermal_protection(struct radeon_device *rdev,
1842 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1845 tmp &= ~THERMAL_PROTECTION_DIS;
1847 tmp |= THERMAL_PROTECTION_DIS;
1848 WREG32_SMC(GENERAL_PWRMGT, tmp);
1851 static void ci_enable_acpi_power_management(struct radeon_device *rdev)
1853 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
1855 tmp |= STATIC_PM_EN;
1857 WREG32_SMC(GENERAL_PWRMGT, tmp);
1861 static int ci_enter_ulp_state(struct radeon_device *rdev)
1864 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
1871 static int ci_exit_ulp_state(struct radeon_device *rdev)
1875 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
1879 for (i = 0; i < rdev->usec_timeout; i++) {
1880 if (RREG32(SMC_RESP_0) == 1)
1889 static int ci_notify_smc_display_change(struct radeon_device *rdev,
1892 PPSMC_Msg msg = has_display ? PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
1894 return (ci_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 0 : -EINVAL;
1897 static int ci_enable_ds_master_switch(struct radeon_device *rdev,
1900 struct ci_power_info *pi = ci_get_pi(rdev);
1903 if (pi->caps_sclk_ds) {
1904 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_ON) != PPSMC_Result_OK)
1907 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1911 if (pi->caps_sclk_ds) {
1912 if (ci_send_msg_to_smc(rdev, PPSMC_MSG_MASTER_DeepSleep_OFF) != PPSMC_Result_OK)
1920 static void ci_program_display_gap(struct radeon_device *rdev)
1922 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1923 u32 pre_vbi_time_in_us;
1924 u32 frame_time_in_us;
1925 u32 ref_clock = rdev->clock.spll.reference_freq;
1926 u32 refresh_rate = r600_dpm_get_vrefresh(rdev);
1927 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
1929 tmp &= ~DISP_GAP_MASK;
1930 if (rdev->pm.dpm.new_active_crtc_count > 0)
1931 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
1933 tmp |= DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE);
1934 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1936 if (refresh_rate == 0)
1938 if (vblank_time == 0xffffffff)
1940 frame_time_in_us = 1000000 / refresh_rate;
1941 pre_vbi_time_in_us =
1942 frame_time_in_us - 200 - vblank_time;
1943 tmp = pre_vbi_time_in_us * (ref_clock / 100);
1945 WREG32_SMC(CG_DISPLAY_GAP_CNTL2, tmp);
1946 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, PreVBlankGap), 0x64);
1947 ci_write_smc_soft_register(rdev, offsetof(SMU7_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us));
1950 ci_notify_smc_display_change(rdev, (rdev->pm.dpm.new_active_crtc_count == 1));
1954 static void ci_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
1956 struct ci_power_info *pi = ci_get_pi(rdev);
1960 if (pi->caps_sclk_ss_support) {
1961 tmp = RREG32_SMC(GENERAL_PWRMGT);
1962 tmp |= DYN_SPREAD_SPECTRUM_EN;
1963 WREG32_SMC(GENERAL_PWRMGT, tmp);
1966 tmp = RREG32_SMC(CG_SPLL_SPREAD_SPECTRUM);
1968 WREG32_SMC(CG_SPLL_SPREAD_SPECTRUM, tmp);
1970 tmp = RREG32_SMC(GENERAL_PWRMGT);
1971 tmp &= ~DYN_SPREAD_SPECTRUM_EN;
1972 WREG32_SMC(GENERAL_PWRMGT, tmp);
1976 static void ci_program_sstp(struct radeon_device *rdev)
1978 WREG32_SMC(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
1981 static void ci_enable_display_gap(struct radeon_device *rdev)
1983 u32 tmp = RREG32_SMC(CG_DISPLAY_GAP_CNTL);
1985 tmp &= ~(DISP_GAP_MASK | DISP_GAP_MCHG_MASK);
1986 tmp |= (DISP_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
1987 DISP_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK));
1989 WREG32_SMC(CG_DISPLAY_GAP_CNTL, tmp);
1992 static void ci_program_vc(struct radeon_device *rdev)
1996 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
1997 tmp &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
1998 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2000 WREG32_SMC(CG_FTV_0, CISLANDS_VRC_DFLT0);
2001 WREG32_SMC(CG_FTV_1, CISLANDS_VRC_DFLT1);
2002 WREG32_SMC(CG_FTV_2, CISLANDS_VRC_DFLT2);
2003 WREG32_SMC(CG_FTV_3, CISLANDS_VRC_DFLT3);
2004 WREG32_SMC(CG_FTV_4, CISLANDS_VRC_DFLT4);
2005 WREG32_SMC(CG_FTV_5, CISLANDS_VRC_DFLT5);
2006 WREG32_SMC(CG_FTV_6, CISLANDS_VRC_DFLT6);
2007 WREG32_SMC(CG_FTV_7, CISLANDS_VRC_DFLT7);
2010 static void ci_clear_vc(struct radeon_device *rdev)
2014 tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
2015 tmp |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
2016 WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
2018 WREG32_SMC(CG_FTV_0, 0);
2019 WREG32_SMC(CG_FTV_1, 0);
2020 WREG32_SMC(CG_FTV_2, 0);
2021 WREG32_SMC(CG_FTV_3, 0);
2022 WREG32_SMC(CG_FTV_4, 0);
2023 WREG32_SMC(CG_FTV_5, 0);
2024 WREG32_SMC(CG_FTV_6, 0);
2025 WREG32_SMC(CG_FTV_7, 0);
2028 static int ci_upload_firmware(struct radeon_device *rdev)
2030 struct ci_power_info *pi = ci_get_pi(rdev);
2033 for (i = 0; i < rdev->usec_timeout; i++) {
2034 if (RREG32_SMC(RCU_UC_EVENTS) & BOOT_SEQ_DONE)
2037 WREG32_SMC(SMC_SYSCON_MISC_CNTL, 1);
2039 ci_stop_smc_clock(rdev);
2042 ret = ci_load_smc_ucode(rdev, pi->sram_end);
2048 static int ci_get_svi2_voltage_table(struct radeon_device *rdev,
2049 struct radeon_clock_voltage_dependency_table *voltage_dependency_table,
2050 struct atom_voltage_table *voltage_table)
2054 if (voltage_dependency_table == NULL)
2057 voltage_table->mask_low = 0;
2058 voltage_table->phase_delay = 0;
2060 voltage_table->count = voltage_dependency_table->count;
2061 for (i = 0; i < voltage_table->count; i++) {
2062 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
2063 voltage_table->entries[i].smio_low = 0;
2069 static int ci_construct_voltage_tables(struct radeon_device *rdev)
2071 struct ci_power_info *pi = ci_get_pi(rdev);
2074 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2075 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
2076 VOLTAGE_OBJ_GPIO_LUT,
2077 &pi->vddc_voltage_table);
2080 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2081 ret = ci_get_svi2_voltage_table(rdev,
2082 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2083 &pi->vddc_voltage_table);
2088 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC)
2089 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDC,
2090 &pi->vddc_voltage_table);
2092 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2093 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
2094 VOLTAGE_OBJ_GPIO_LUT,
2095 &pi->vddci_voltage_table);
2098 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2099 ret = ci_get_svi2_voltage_table(rdev,
2100 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2101 &pi->vddci_voltage_table);
2106 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI)
2107 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_VDDCI,
2108 &pi->vddci_voltage_table);
2110 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) {
2111 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
2112 VOLTAGE_OBJ_GPIO_LUT,
2113 &pi->mvdd_voltage_table);
2116 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
2117 ret = ci_get_svi2_voltage_table(rdev,
2118 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2119 &pi->mvdd_voltage_table);
2124 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD)
2125 si_trim_voltage_table_to_fit_state_table(rdev, SMU7_MAX_LEVELS_MVDD,
2126 &pi->mvdd_voltage_table);
2131 static void ci_populate_smc_voltage_table(struct radeon_device *rdev,
2132 struct atom_voltage_table_entry *voltage_table,
2133 SMU7_Discrete_VoltageLevel *smc_voltage_table)
2137 ret = ci_get_std_voltage_value_sidd(rdev, voltage_table,
2138 &smc_voltage_table->StdVoltageHiSidd,
2139 &smc_voltage_table->StdVoltageLoSidd);
2142 smc_voltage_table->StdVoltageHiSidd = voltage_table->value * VOLTAGE_SCALE;
2143 smc_voltage_table->StdVoltageLoSidd = voltage_table->value * VOLTAGE_SCALE;
2146 smc_voltage_table->Voltage = cpu_to_be16(voltage_table->value * VOLTAGE_SCALE);
2147 smc_voltage_table->StdVoltageHiSidd =
2148 cpu_to_be16(smc_voltage_table->StdVoltageHiSidd);
2149 smc_voltage_table->StdVoltageLoSidd =
2150 cpu_to_be16(smc_voltage_table->StdVoltageLoSidd);
2153 static int ci_populate_smc_vddc_table(struct radeon_device *rdev,
2154 SMU7_Discrete_DpmTable *table)
2156 struct ci_power_info *pi = ci_get_pi(rdev);
2159 table->VddcLevelCount = pi->vddc_voltage_table.count;
2160 for (count = 0; count < table->VddcLevelCount; count++) {
2161 ci_populate_smc_voltage_table(rdev,
2162 &pi->vddc_voltage_table.entries[count],
2163 &table->VddcLevel[count]);
2165 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2166 table->VddcLevel[count].Smio |=
2167 pi->vddc_voltage_table.entries[count].smio_low;
2169 table->VddcLevel[count].Smio = 0;
2171 table->VddcLevelCount = cpu_to_be32(table->VddcLevelCount);
2176 static int ci_populate_smc_vddci_table(struct radeon_device *rdev,
2177 SMU7_Discrete_DpmTable *table)
2180 struct ci_power_info *pi = ci_get_pi(rdev);
2182 table->VddciLevelCount = pi->vddci_voltage_table.count;
2183 for (count = 0; count < table->VddciLevelCount; count++) {
2184 ci_populate_smc_voltage_table(rdev,
2185 &pi->vddci_voltage_table.entries[count],
2186 &table->VddciLevel[count]);
2188 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2189 table->VddciLevel[count].Smio |=
2190 pi->vddci_voltage_table.entries[count].smio_low;
2192 table->VddciLevel[count].Smio = 0;
2194 table->VddciLevelCount = cpu_to_be32(table->VddciLevelCount);
2199 static int ci_populate_smc_mvdd_table(struct radeon_device *rdev,
2200 SMU7_Discrete_DpmTable *table)
2202 struct ci_power_info *pi = ci_get_pi(rdev);
2205 table->MvddLevelCount = pi->mvdd_voltage_table.count;
2206 for (count = 0; count < table->MvddLevelCount; count++) {
2207 ci_populate_smc_voltage_table(rdev,
2208 &pi->mvdd_voltage_table.entries[count],
2209 &table->MvddLevel[count]);
2211 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO)
2212 table->MvddLevel[count].Smio |=
2213 pi->mvdd_voltage_table.entries[count].smio_low;
2215 table->MvddLevel[count].Smio = 0;
2217 table->MvddLevelCount = cpu_to_be32(table->MvddLevelCount);
2222 static int ci_populate_smc_voltage_tables(struct radeon_device *rdev,
2223 SMU7_Discrete_DpmTable *table)
2227 ret = ci_populate_smc_vddc_table(rdev, table);
2231 ret = ci_populate_smc_vddci_table(rdev, table);
2235 ret = ci_populate_smc_mvdd_table(rdev, table);
2242 static int ci_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
2243 SMU7_Discrete_VoltageLevel *voltage)
2245 struct ci_power_info *pi = ci_get_pi(rdev);
2248 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2249 for (i = 0; i < rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count; i++) {
2250 if (mclk <= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries[i].clk) {
2251 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value;
2256 if (i >= rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.count)
2263 static int ci_get_std_voltage_value_sidd(struct radeon_device *rdev,
2264 struct atom_voltage_table_entry *voltage_table,
2265 u16 *std_voltage_hi_sidd, u16 *std_voltage_lo_sidd)
2268 bool voltage_found = false;
2269 *std_voltage_hi_sidd = voltage_table->value * VOLTAGE_SCALE;
2270 *std_voltage_lo_sidd = voltage_table->value * VOLTAGE_SCALE;
2272 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
2275 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
2276 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2277 if (voltage_table->value ==
2278 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2279 voltage_found = true;
2280 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2283 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2284 *std_voltage_lo_sidd =
2285 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2286 *std_voltage_hi_sidd =
2287 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2292 if (!voltage_found) {
2293 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
2294 if (voltage_table->value <=
2295 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
2296 voltage_found = true;
2297 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
2300 idx = rdev->pm.dpm.dyn_state.cac_leakage_table.count - 1;
2301 *std_voltage_lo_sidd =
2302 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].vddc * VOLTAGE_SCALE;
2303 *std_voltage_hi_sidd =
2304 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[idx].leakage * VOLTAGE_SCALE;
2314 static void ci_populate_phase_value_based_on_sclk(struct radeon_device *rdev,
2315 const struct radeon_phase_shedding_limits_table *limits,
2317 u32 *phase_shedding)
2321 *phase_shedding = 1;
2323 for (i = 0; i < limits->count; i++) {
2324 if (sclk < limits->entries[i].sclk) {
2325 *phase_shedding = i;
2331 static void ci_populate_phase_value_based_on_mclk(struct radeon_device *rdev,
2332 const struct radeon_phase_shedding_limits_table *limits,
2334 u32 *phase_shedding)
2338 *phase_shedding = 1;
2340 for (i = 0; i < limits->count; i++) {
2341 if (mclk < limits->entries[i].mclk) {
2342 *phase_shedding = i;
2348 static int ci_init_arb_table_index(struct radeon_device *rdev)
2350 struct ci_power_info *pi = ci_get_pi(rdev);
2354 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start,
2355 &tmp, pi->sram_end);
2360 tmp |= MC_CG_ARB_FREQ_F1 << 24;
2362 return ci_write_smc_sram_dword(rdev, pi->arb_table_start,
2366 static int ci_get_dependency_volt_by_clk(struct radeon_device *rdev,
2367 struct radeon_clock_voltage_dependency_table *allowed_clock_voltage_table,
2368 u32 clock, u32 *voltage)
2372 if (allowed_clock_voltage_table->count == 0)
2375 for (i = 0; i < allowed_clock_voltage_table->count; i++) {
2376 if (allowed_clock_voltage_table->entries[i].clk >= clock) {
2377 *voltage = allowed_clock_voltage_table->entries[i].v;
2382 *voltage = allowed_clock_voltage_table->entries[i-1].v;
2387 static u8 ci_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
2388 u32 sclk, u32 min_sclk_in_sr)
2392 u32 min = (min_sclk_in_sr > CISLAND_MINIMUM_ENGINE_CLOCK) ?
2393 min_sclk_in_sr : CISLAND_MINIMUM_ENGINE_CLOCK;
2398 for (i = CISLAND_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
2399 tmp = sclk / (1 << i);
2400 if (tmp >= min || i == 0)
2407 static int ci_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
2409 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
2412 static int ci_reset_to_default(struct radeon_device *rdev)
2414 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
2418 static int ci_force_switch_to_arb_f0(struct radeon_device *rdev)
2422 tmp = (RREG32_SMC(SMC_SCRATCH9) & 0x0000ff00) >> 8;
2424 if (tmp == MC_CG_ARB_FREQ_F0)
2427 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
2430 static void ci_register_patching_mc_arb(struct radeon_device *rdev,
2431 const u32 engine_clock,
2432 const u32 memory_clock,
2438 tmp = RREG32(MC_SEQ_MISC0);
2439 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
2442 ((rdev->pdev->device == 0x67B0) ||
2443 (rdev->pdev->device == 0x67B1))) {
2444 if ((memory_clock > 100000) && (memory_clock <= 125000)) {
2445 tmp2 = (((0x31 * engine_clock) / 125000) - 1) & 0xff;
2446 *dram_timimg2 &= ~0x00ff0000;
2447 *dram_timimg2 |= tmp2 << 16;
2448 } else if ((memory_clock > 125000) && (memory_clock <= 137500)) {
2449 tmp2 = (((0x36 * engine_clock) / 137500) - 1) & 0xff;
2450 *dram_timimg2 &= ~0x00ff0000;
2451 *dram_timimg2 |= tmp2 << 16;
2457 static int ci_populate_memory_timing_parameters(struct radeon_device *rdev,
2460 SMU7_Discrete_MCArbDramTimingTableEntry *arb_regs)
2466 radeon_atom_set_engine_dram_timings(rdev, sclk, mclk);
2468 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
2469 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
2470 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
2472 ci_register_patching_mc_arb(rdev, sclk, mclk, &dram_timing2);
2474 arb_regs->McArbDramTiming = cpu_to_be32(dram_timing);
2475 arb_regs->McArbDramTiming2 = cpu_to_be32(dram_timing2);
2476 arb_regs->McArbBurstTime = (u8)burst_time;
2481 static int ci_do_program_memory_timing_parameters(struct radeon_device *rdev)
2483 struct ci_power_info *pi = ci_get_pi(rdev);
2484 SMU7_Discrete_MCArbDramTimingTable arb_regs;
2488 memset(&arb_regs, 0, sizeof(SMU7_Discrete_MCArbDramTimingTable));
2490 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) {
2491 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) {
2492 ret = ci_populate_memory_timing_parameters(rdev,
2493 pi->dpm_table.sclk_table.dpm_levels[i].value,
2494 pi->dpm_table.mclk_table.dpm_levels[j].value,
2495 &arb_regs.entries[i][j]);
2502 ret = ci_copy_bytes_to_smc(rdev,
2503 pi->arb_table_start,
2505 sizeof(SMU7_Discrete_MCArbDramTimingTable),
2511 static int ci_program_memory_timing_parameters(struct radeon_device *rdev)
2513 struct ci_power_info *pi = ci_get_pi(rdev);
2515 if (pi->need_update_smu7_dpm_table == 0)
2518 return ci_do_program_memory_timing_parameters(rdev);
2521 static void ci_populate_smc_initial_state(struct radeon_device *rdev,
2522 struct radeon_ps *radeon_boot_state)
2524 struct ci_ps *boot_state = ci_get_ps(radeon_boot_state);
2525 struct ci_power_info *pi = ci_get_pi(rdev);
2528 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; level++) {
2529 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[level].clk >=
2530 boot_state->performance_levels[0].sclk) {
2531 pi->smc_state_table.GraphicsBootLevel = level;
2536 for (level = 0; level < rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.count; level++) {
2537 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries[level].clk >=
2538 boot_state->performance_levels[0].mclk) {
2539 pi->smc_state_table.MemoryBootLevel = level;
2545 static u32 ci_get_dpm_level_enable_mask_value(struct ci_single_dpm_table *dpm_table)
2550 for (i = dpm_table->count; i > 0; i--) {
2551 mask_value = mask_value << 1;
2552 if (dpm_table->dpm_levels[i-1].enabled)
2555 mask_value &= 0xFFFFFFFE;
2561 static void ci_populate_smc_link_level(struct radeon_device *rdev,
2562 SMU7_Discrete_DpmTable *table)
2564 struct ci_power_info *pi = ci_get_pi(rdev);
2565 struct ci_dpm_table *dpm_table = &pi->dpm_table;
2568 for (i = 0; i < dpm_table->pcie_speed_table.count; i++) {
2569 table->LinkLevel[i].PcieGenSpeed =
2570 (u8)dpm_table->pcie_speed_table.dpm_levels[i].value;
2571 table->LinkLevel[i].PcieLaneCount =
2572 r600_encode_pci_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
2573 table->LinkLevel[i].EnabledForActivity = 1;
2574 table->LinkLevel[i].DownT = cpu_to_be32(5);
2575 table->LinkLevel[i].UpT = cpu_to_be32(30);
2578 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count;
2579 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
2580 ci_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
2583 static int ci_populate_smc_uvd_level(struct radeon_device *rdev,
2584 SMU7_Discrete_DpmTable *table)
2587 struct atom_clock_dividers dividers;
2590 table->UvdLevelCount =
2591 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count;
2593 for (count = 0; count < table->UvdLevelCount; count++) {
2594 table->UvdLevel[count].VclkFrequency =
2595 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].vclk;
2596 table->UvdLevel[count].DclkFrequency =
2597 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].dclk;
2598 table->UvdLevel[count].MinVddc =
2599 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2600 table->UvdLevel[count].MinVddcPhases = 1;
2602 ret = radeon_atom_get_clock_dividers(rdev,
2603 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2604 table->UvdLevel[count].VclkFrequency, false, ÷rs);
2608 table->UvdLevel[count].VclkDivider = (u8)dividers.post_divider;
2610 ret = radeon_atom_get_clock_dividers(rdev,
2611 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2612 table->UvdLevel[count].DclkFrequency, false, ÷rs);
2616 table->UvdLevel[count].DclkDivider = (u8)dividers.post_divider;
2618 table->UvdLevel[count].VclkFrequency = cpu_to_be32(table->UvdLevel[count].VclkFrequency);
2619 table->UvdLevel[count].DclkFrequency = cpu_to_be32(table->UvdLevel[count].DclkFrequency);
2620 table->UvdLevel[count].MinVddc = cpu_to_be16(table->UvdLevel[count].MinVddc);
2626 static int ci_populate_smc_vce_level(struct radeon_device *rdev,
2627 SMU7_Discrete_DpmTable *table)
2630 struct atom_clock_dividers dividers;
2633 table->VceLevelCount =
2634 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count;
2636 for (count = 0; count < table->VceLevelCount; count++) {
2637 table->VceLevel[count].Frequency =
2638 rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].evclk;
2639 table->VceLevel[count].MinVoltage =
2640 (u16)rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2641 table->VceLevel[count].MinPhases = 1;
2643 ret = radeon_atom_get_clock_dividers(rdev,
2644 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2645 table->VceLevel[count].Frequency, false, ÷rs);
2649 table->VceLevel[count].Divider = (u8)dividers.post_divider;
2651 table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
2652 table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
2659 static int ci_populate_smc_acp_level(struct radeon_device *rdev,
2660 SMU7_Discrete_DpmTable *table)
2663 struct atom_clock_dividers dividers;
2666 table->AcpLevelCount = (u8)
2667 (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count);
2669 for (count = 0; count < table->AcpLevelCount; count++) {
2670 table->AcpLevel[count].Frequency =
2671 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].clk;
2672 table->AcpLevel[count].MinVoltage =
2673 rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[count].v;
2674 table->AcpLevel[count].MinPhases = 1;
2676 ret = radeon_atom_get_clock_dividers(rdev,
2677 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2678 table->AcpLevel[count].Frequency, false, ÷rs);
2682 table->AcpLevel[count].Divider = (u8)dividers.post_divider;
2684 table->AcpLevel[count].Frequency = cpu_to_be32(table->AcpLevel[count].Frequency);
2685 table->AcpLevel[count].MinVoltage = cpu_to_be16(table->AcpLevel[count].MinVoltage);
2691 static int ci_populate_smc_samu_level(struct radeon_device *rdev,
2692 SMU7_Discrete_DpmTable *table)
2695 struct atom_clock_dividers dividers;
2698 table->SamuLevelCount =
2699 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count;
2701 for (count = 0; count < table->SamuLevelCount; count++) {
2702 table->SamuLevel[count].Frequency =
2703 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].clk;
2704 table->SamuLevel[count].MinVoltage =
2705 rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[count].v * VOLTAGE_SCALE;
2706 table->SamuLevel[count].MinPhases = 1;
2708 ret = radeon_atom_get_clock_dividers(rdev,
2709 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK,
2710 table->SamuLevel[count].Frequency, false, ÷rs);
2714 table->SamuLevel[count].Divider = (u8)dividers.post_divider;
2716 table->SamuLevel[count].Frequency = cpu_to_be32(table->SamuLevel[count].Frequency);
2717 table->SamuLevel[count].MinVoltage = cpu_to_be16(table->SamuLevel[count].MinVoltage);
2723 static int ci_calculate_mclk_params(struct radeon_device *rdev,
2725 SMU7_Discrete_MemoryLevel *mclk,
2729 struct ci_power_info *pi = ci_get_pi(rdev);
2730 u32 dll_cntl = pi->clock_registers.dll_cntl;
2731 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2732 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl;
2733 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl;
2734 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl;
2735 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1;
2736 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2;
2737 u32 mpll_ss1 = pi->clock_registers.mpll_ss1;
2738 u32 mpll_ss2 = pi->clock_registers.mpll_ss2;
2739 struct atom_mpll_param mpll_param;
2742 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
2746 mpll_func_cntl &= ~BWCTRL_MASK;
2747 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
2749 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
2750 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
2751 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
2753 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
2754 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
2756 if (pi->mem_gddr5) {
2757 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
2758 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
2759 YCLK_POST_DIV(mpll_param.post_div);
2762 if (pi->caps_mclk_ss_support) {
2763 struct radeon_atom_ss ss;
2766 u32 reference_clock = rdev->clock.mpll.reference_freq;
2768 if (mpll_param.qdr == 1)
2769 freq_nom = memory_clock * 4 * (1 << mpll_param.post_div);
2771 freq_nom = memory_clock * 2 * (1 << mpll_param.post_div);
2773 tmp = (freq_nom / reference_clock);
2775 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2776 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
2777 u32 clks = reference_clock * 5 / ss.rate;
2778 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
2780 mpll_ss1 &= ~CLKV_MASK;
2781 mpll_ss1 |= CLKV(clkv);
2783 mpll_ss2 &= ~CLKS_MASK;
2784 mpll_ss2 |= CLKS(clks);
2788 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2789 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
2792 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
2794 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
2796 mclk->MclkFrequency = memory_clock;
2797 mclk->MpllFuncCntl = mpll_func_cntl;
2798 mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
2799 mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
2800 mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
2801 mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
2802 mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
2803 mclk->DllCntl = dll_cntl;
2804 mclk->MpllSs1 = mpll_ss1;
2805 mclk->MpllSs2 = mpll_ss2;
2810 static int ci_populate_single_memory_level(struct radeon_device *rdev,
2812 SMU7_Discrete_MemoryLevel *memory_level)
2814 struct ci_power_info *pi = ci_get_pi(rdev);
2818 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk.entries) {
2819 ret = ci_get_dependency_volt_by_clk(rdev,
2820 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2821 memory_clock, &memory_level->MinVddc);
2826 if (rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk.entries) {
2827 ret = ci_get_dependency_volt_by_clk(rdev,
2828 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2829 memory_clock, &memory_level->MinVddci);
2834 if (rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk.entries) {
2835 ret = ci_get_dependency_volt_by_clk(rdev,
2836 &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk,
2837 memory_clock, &memory_level->MinMvdd);
2842 memory_level->MinVddcPhases = 1;
2844 if (pi->vddc_phase_shed_control)
2845 ci_populate_phase_value_based_on_mclk(rdev,
2846 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
2848 &memory_level->MinVddcPhases);
2850 memory_level->EnabledForThrottle = 1;
2851 memory_level->UpH = 0;
2852 memory_level->DownH = 100;
2853 memory_level->VoltageDownH = 0;
2854 memory_level->ActivityLevel = (u16)pi->mclk_activity_target;
2856 memory_level->StutterEnable = false;
2857 memory_level->StrobeEnable = false;
2858 memory_level->EdcReadEnable = false;
2859 memory_level->EdcWriteEnable = false;
2860 memory_level->RttEnable = false;
2862 memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2864 if (pi->mclk_stutter_mode_threshold &&
2865 (memory_clock <= pi->mclk_stutter_mode_threshold) &&
2866 (pi->uvd_enabled == false) &&
2867 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
2868 (rdev->pm.dpm.new_active_crtc_count <= 2))
2869 memory_level->StutterEnable = true;
2871 if (pi->mclk_strobe_mode_threshold &&
2872 (memory_clock <= pi->mclk_strobe_mode_threshold))
2873 memory_level->StrobeEnable = 1;
2875 if (pi->mem_gddr5) {
2876 memory_level->StrobeRatio =
2877 si_get_mclk_frequency_ratio(memory_clock, memory_level->StrobeEnable);
2878 if (pi->mclk_edc_enable_threshold &&
2879 (memory_clock > pi->mclk_edc_enable_threshold))
2880 memory_level->EdcReadEnable = true;
2882 if (pi->mclk_edc_wr_enable_threshold &&
2883 (memory_clock > pi->mclk_edc_wr_enable_threshold))
2884 memory_level->EdcWriteEnable = true;
2886 if (memory_level->StrobeEnable) {
2887 if (si_get_mclk_frequency_ratio(memory_clock, true) >=
2888 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2889 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2891 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2893 dll_state_on = pi->dll_default_on;
2896 memory_level->StrobeRatio = si_get_ddr3_mclk_frequency_ratio(memory_clock);
2897 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2900 ret = ci_calculate_mclk_params(rdev, memory_clock, memory_level, memory_level->StrobeEnable, dll_state_on);
2904 memory_level->MinVddc = cpu_to_be32(memory_level->MinVddc * VOLTAGE_SCALE);
2905 memory_level->MinVddcPhases = cpu_to_be32(memory_level->MinVddcPhases);
2906 memory_level->MinVddci = cpu_to_be32(memory_level->MinVddci * VOLTAGE_SCALE);
2907 memory_level->MinMvdd = cpu_to_be32(memory_level->MinMvdd * VOLTAGE_SCALE);
2909 memory_level->MclkFrequency = cpu_to_be32(memory_level->MclkFrequency);
2910 memory_level->ActivityLevel = cpu_to_be16(memory_level->ActivityLevel);
2911 memory_level->MpllFuncCntl = cpu_to_be32(memory_level->MpllFuncCntl);
2912 memory_level->MpllFuncCntl_1 = cpu_to_be32(memory_level->MpllFuncCntl_1);
2913 memory_level->MpllFuncCntl_2 = cpu_to_be32(memory_level->MpllFuncCntl_2);
2914 memory_level->MpllAdFuncCntl = cpu_to_be32(memory_level->MpllAdFuncCntl);
2915 memory_level->MpllDqFuncCntl = cpu_to_be32(memory_level->MpllDqFuncCntl);
2916 memory_level->MclkPwrmgtCntl = cpu_to_be32(memory_level->MclkPwrmgtCntl);
2917 memory_level->DllCntl = cpu_to_be32(memory_level->DllCntl);
2918 memory_level->MpllSs1 = cpu_to_be32(memory_level->MpllSs1);
2919 memory_level->MpllSs2 = cpu_to_be32(memory_level->MpllSs2);
2924 static int ci_populate_smc_acpi_level(struct radeon_device *rdev,
2925 SMU7_Discrete_DpmTable *table)
2927 struct ci_power_info *pi = ci_get_pi(rdev);
2928 struct atom_clock_dividers dividers;
2929 SMU7_Discrete_VoltageLevel voltage_level;
2930 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl;
2931 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2;
2932 u32 dll_cntl = pi->clock_registers.dll_cntl;
2933 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl;
2936 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
2939 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE);
2941 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE);
2943 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1;
2945 table->ACPILevel.SclkFrequency = rdev->clock.spll.reference_freq;
2947 ret = radeon_atom_get_clock_dividers(rdev,
2948 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
2949 table->ACPILevel.SclkFrequency, false, ÷rs);
2953 table->ACPILevel.SclkDid = (u8)dividers.post_divider;
2954 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
2955 table->ACPILevel.DeepSleepDivId = 0;
2957 spll_func_cntl &= ~SPLL_PWRON;
2958 spll_func_cntl |= SPLL_RESET;
2960 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2961 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
2963 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
2964 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
2965 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3;
2966 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4;
2967 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum;
2968 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2;
2969 table->ACPILevel.CcPwrDynRm = 0;
2970 table->ACPILevel.CcPwrDynRm1 = 0;
2972 table->ACPILevel.Flags = cpu_to_be32(table->ACPILevel.Flags);
2973 table->ACPILevel.MinVddcPhases = cpu_to_be32(table->ACPILevel.MinVddcPhases);
2974 table->ACPILevel.SclkFrequency = cpu_to_be32(table->ACPILevel.SclkFrequency);
2975 table->ACPILevel.CgSpllFuncCntl = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl);
2976 table->ACPILevel.CgSpllFuncCntl2 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl2);
2977 table->ACPILevel.CgSpllFuncCntl3 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl3);
2978 table->ACPILevel.CgSpllFuncCntl4 = cpu_to_be32(table->ACPILevel.CgSpllFuncCntl4);
2979 table->ACPILevel.SpllSpreadSpectrum = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum);
2980 table->ACPILevel.SpllSpreadSpectrum2 = cpu_to_be32(table->ACPILevel.SpllSpreadSpectrum2);
2981 table->ACPILevel.CcPwrDynRm = cpu_to_be32(table->ACPILevel.CcPwrDynRm);
2982 table->ACPILevel.CcPwrDynRm1 = cpu_to_be32(table->ACPILevel.CcPwrDynRm1);
2984 table->MemoryACPILevel.MinVddc = table->ACPILevel.MinVddc;
2985 table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;
2987 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
2989 table->MemoryACPILevel.MinVddci =
2990 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE);
2992 table->MemoryACPILevel.MinVddci =
2993 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE);
2996 if (ci_populate_mvdd_value(rdev, 0, &voltage_level))
2997 table->MemoryACPILevel.MinMvdd = 0;
2999 table->MemoryACPILevel.MinMvdd =
3000 cpu_to_be32(voltage_level.Voltage * VOLTAGE_SCALE);
3002 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
3003 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
3005 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
3007 table->MemoryACPILevel.DllCntl = cpu_to_be32(dll_cntl);
3008 table->MemoryACPILevel.MclkPwrmgtCntl = cpu_to_be32(mclk_pwrmgt_cntl);
3009 table->MemoryACPILevel.MpllAdFuncCntl =
3010 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl);
3011 table->MemoryACPILevel.MpllDqFuncCntl =
3012 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl);
3013 table->MemoryACPILevel.MpllFuncCntl =
3014 cpu_to_be32(pi->clock_registers.mpll_func_cntl);
3015 table->MemoryACPILevel.MpllFuncCntl_1 =
3016 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1);
3017 table->MemoryACPILevel.MpllFuncCntl_2 =
3018 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2);
3019 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1);
3020 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2);
3022 table->MemoryACPILevel.EnabledForThrottle = 0;
3023 table->MemoryACPILevel.EnabledForActivity = 0;
3024 table->MemoryACPILevel.UpH = 0;
3025 table->MemoryACPILevel.DownH = 100;
3026 table->MemoryACPILevel.VoltageDownH = 0;
3027 table->MemoryACPILevel.ActivityLevel =
3028 cpu_to_be16((u16)pi->mclk_activity_target);
3030 table->MemoryACPILevel.StutterEnable = false;
3031 table->MemoryACPILevel.StrobeEnable = false;
3032 table->MemoryACPILevel.EdcReadEnable = false;
3033 table->MemoryACPILevel.EdcWriteEnable = false;
3034 table->MemoryACPILevel.RttEnable = false;
3040 static int ci_enable_ulv(struct radeon_device *rdev, bool enable)
3042 struct ci_power_info *pi = ci_get_pi(rdev);
3043 struct ci_ulv_parm *ulv = &pi->ulv;
3045 if (ulv->supported) {
3047 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
3050 return (ci_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
3057 static int ci_populate_ulv_level(struct radeon_device *rdev,
3058 SMU7_Discrete_Ulv *state)
3060 struct ci_power_info *pi = ci_get_pi(rdev);
3061 u16 ulv_voltage = rdev->pm.dpm.backbias_response_time;
3063 state->CcPwrDynRm = 0;
3064 state->CcPwrDynRm1 = 0;
3066 if (ulv_voltage == 0) {
3067 pi->ulv.supported = false;
3071 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) {
3072 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3073 state->VddcOffset = 0;
3076 rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage;
3078 if (ulv_voltage > rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v)
3079 state->VddcOffsetVid = 0;
3081 state->VddcOffsetVid = (u8)
3082 ((rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[0].v - ulv_voltage) *
3083 VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
3085 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1;
3087 state->CcPwrDynRm = cpu_to_be32(state->CcPwrDynRm);
3088 state->CcPwrDynRm1 = cpu_to_be32(state->CcPwrDynRm1);
3089 state->VddcOffset = cpu_to_be16(state->VddcOffset);
3094 static int ci_calculate_sclk_params(struct radeon_device *rdev,
3096 SMU7_Discrete_GraphicsLevel *sclk)
3098 struct ci_power_info *pi = ci_get_pi(rdev);
3099 struct atom_clock_dividers dividers;
3100 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3;
3101 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4;
3102 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum;
3103 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2;
3104 u32 reference_clock = rdev->clock.spll.reference_freq;
3105 u32 reference_divider;
3109 ret = radeon_atom_get_clock_dividers(rdev,
3110 COMPUTE_GPUCLK_INPUT_FLAG_SCLK,
3111 engine_clock, false, ÷rs);
3115 reference_divider = 1 + dividers.ref_div;
3116 fbdiv = dividers.fb_div & 0x3FFFFFF;
3118 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
3119 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
3120 spll_func_cntl_3 |= SPLL_DITHEN;
3122 if (pi->caps_sclk_ss_support) {
3123 struct radeon_atom_ss ss;
3124 u32 vco_freq = engine_clock * dividers.post_div;
3126 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
3127 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
3128 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
3129 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
3131 cg_spll_spread_spectrum &= ~CLK_S_MASK;
3132 cg_spll_spread_spectrum |= CLK_S(clk_s);
3133 cg_spll_spread_spectrum |= SSEN;
3135 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
3136 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
3140 sclk->SclkFrequency = engine_clock;
3141 sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
3142 sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
3143 sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
3144 sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
3145 sclk->SclkDid = (u8)dividers.post_divider;
3150 static int ci_populate_single_graphic_level(struct radeon_device *rdev,
3152 u16 sclk_activity_level_t,
3153 SMU7_Discrete_GraphicsLevel *graphic_level)
3155 struct ci_power_info *pi = ci_get_pi(rdev);
3158 ret = ci_calculate_sclk_params(rdev, engine_clock, graphic_level);
3162 ret = ci_get_dependency_volt_by_clk(rdev,
3163 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3164 engine_clock, &graphic_level->MinVddc);
3168 graphic_level->SclkFrequency = engine_clock;
3170 graphic_level->Flags = 0;
3171 graphic_level->MinVddcPhases = 1;
3173 if (pi->vddc_phase_shed_control)
3174 ci_populate_phase_value_based_on_sclk(rdev,
3175 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
3177 &graphic_level->MinVddcPhases);
3179 graphic_level->ActivityLevel = sclk_activity_level_t;
3181 graphic_level->CcPwrDynRm = 0;
3182 graphic_level->CcPwrDynRm1 = 0;
3183 graphic_level->EnabledForThrottle = 1;
3184 graphic_level->UpH = 0;
3185 graphic_level->DownH = 0;
3186 graphic_level->VoltageDownH = 0;
3187 graphic_level->PowerThrottle = 0;
3189 if (pi->caps_sclk_ds)
3190 graphic_level->DeepSleepDivId = ci_get_sleep_divider_id_from_clock(rdev,
3192 CISLAND_MINIMUM_ENGINE_CLOCK);
3194 graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
3196 graphic_level->Flags = cpu_to_be32(graphic_level->Flags);
3197 graphic_level->MinVddc = cpu_to_be32(graphic_level->MinVddc * VOLTAGE_SCALE);
3198 graphic_level->MinVddcPhases = cpu_to_be32(graphic_level->MinVddcPhases);
3199 graphic_level->SclkFrequency = cpu_to_be32(graphic_level->SclkFrequency);
3200 graphic_level->ActivityLevel = cpu_to_be16(graphic_level->ActivityLevel);
3201 graphic_level->CgSpllFuncCntl3 = cpu_to_be32(graphic_level->CgSpllFuncCntl3);
3202 graphic_level->CgSpllFuncCntl4 = cpu_to_be32(graphic_level->CgSpllFuncCntl4);
3203 graphic_level->SpllSpreadSpectrum = cpu_to_be32(graphic_level->SpllSpreadSpectrum);
3204 graphic_level->SpllSpreadSpectrum2 = cpu_to_be32(graphic_level->SpllSpreadSpectrum2);
3205 graphic_level->CcPwrDynRm = cpu_to_be32(graphic_level->CcPwrDynRm);
3206 graphic_level->CcPwrDynRm1 = cpu_to_be32(graphic_level->CcPwrDynRm1);
3211 static int ci_populate_all_graphic_levels(struct radeon_device *rdev)
3213 struct ci_power_info *pi = ci_get_pi(rdev);
3214 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3215 u32 level_array_address = pi->dpm_table_start +
3216 offsetof(SMU7_Discrete_DpmTable, GraphicsLevel);
3217 u32 level_array_size = sizeof(SMU7_Discrete_GraphicsLevel) *
3218 SMU7_MAX_LEVELS_GRAPHICS;
3219 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel;
3222 memset(levels, 0, level_array_size);
3224 for (i = 0; i < dpm_table->sclk_table.count; i++) {
3225 ret = ci_populate_single_graphic_level(rdev,
3226 dpm_table->sclk_table.dpm_levels[i].value,
3227 (u16)pi->activity_target[i],
3228 &pi->smc_state_table.GraphicsLevel[i]);
3232 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
3233 if (i == (dpm_table->sclk_table.count - 1))
3234 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark =
3235 PPSMC_DISPLAY_WATERMARK_HIGH;
3237 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
3239 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count;
3240 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
3241 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
3243 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3244 (u8 *)levels, level_array_size,
3252 static int ci_populate_ulv_state(struct radeon_device *rdev,
3253 SMU7_Discrete_Ulv *ulv_level)
3255 return ci_populate_ulv_level(rdev, ulv_level);
3258 static int ci_populate_all_memory_levels(struct radeon_device *rdev)
3260 struct ci_power_info *pi = ci_get_pi(rdev);
3261 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3262 u32 level_array_address = pi->dpm_table_start +
3263 offsetof(SMU7_Discrete_DpmTable, MemoryLevel);
3264 u32 level_array_size = sizeof(SMU7_Discrete_MemoryLevel) *
3265 SMU7_MAX_LEVELS_MEMORY;
3266 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel;
3269 memset(levels, 0, level_array_size);
3271 for (i = 0; i < dpm_table->mclk_table.count; i++) {
3272 if (dpm_table->mclk_table.dpm_levels[i].value == 0)
3274 ret = ci_populate_single_memory_level(rdev,
3275 dpm_table->mclk_table.dpm_levels[i].value,
3276 &pi->smc_state_table.MemoryLevel[i]);
3281 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;
3283 if ((dpm_table->mclk_table.count >= 2) &&
3284 ((rdev->pdev->device == 0x67B0) || (rdev->pdev->device == 0x67B1))) {
3285 pi->smc_state_table.MemoryLevel[1].MinVddc =
3286 pi->smc_state_table.MemoryLevel[0].MinVddc;
3287 pi->smc_state_table.MemoryLevel[1].MinVddcPhases =
3288 pi->smc_state_table.MemoryLevel[0].MinVddcPhases;
3291 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F);
3293 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count;
3294 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
3295 ci_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
3297 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark =
3298 PPSMC_DISPLAY_WATERMARK_HIGH;
3300 ret = ci_copy_bytes_to_smc(rdev, level_array_address,
3301 (u8 *)levels, level_array_size,
3309 static void ci_reset_single_dpm_table(struct radeon_device *rdev,
3310 struct ci_single_dpm_table* dpm_table,
3315 dpm_table->count = count;
3316 for (i = 0; i < MAX_REGULAR_DPM_NUMBER; i++)
3317 dpm_table->dpm_levels[i].enabled = false;
3320 static void ci_setup_pcie_table_entry(struct ci_single_dpm_table* dpm_table,
3321 u32 index, u32 pcie_gen, u32 pcie_lanes)
3323 dpm_table->dpm_levels[index].value = pcie_gen;
3324 dpm_table->dpm_levels[index].param1 = pcie_lanes;
3325 dpm_table->dpm_levels[index].enabled = true;
3328 static int ci_setup_default_pcie_tables(struct radeon_device *rdev)
3330 struct ci_power_info *pi = ci_get_pi(rdev);
3332 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels)
3335 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) {
3336 pi->pcie_gen_powersaving = pi->pcie_gen_performance;
3337 pi->pcie_lane_powersaving = pi->pcie_lane_performance;
3338 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) {
3339 pi->pcie_gen_performance = pi->pcie_gen_powersaving;
3340 pi->pcie_lane_performance = pi->pcie_lane_powersaving;
3343 ci_reset_single_dpm_table(rdev,
3344 &pi->dpm_table.pcie_speed_table,
3345 SMU7_MAX_LEVELS_LINK);
3347 if (rdev->family == CHIP_BONAIRE)
3348 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3349 pi->pcie_gen_powersaving.min,
3350 pi->pcie_lane_powersaving.max);
3352 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0,
3353 pi->pcie_gen_powersaving.min,
3354 pi->pcie_lane_powersaving.min);
3355 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1,
3356 pi->pcie_gen_performance.min,
3357 pi->pcie_lane_performance.min);
3358 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2,
3359 pi->pcie_gen_powersaving.min,
3360 pi->pcie_lane_powersaving.max);
3361 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3,
3362 pi->pcie_gen_performance.min,
3363 pi->pcie_lane_performance.max);
3364 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4,
3365 pi->pcie_gen_powersaving.max,
3366 pi->pcie_lane_powersaving.max);
3367 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5,
3368 pi->pcie_gen_performance.max,
3369 pi->pcie_lane_performance.max);
3371 pi->dpm_table.pcie_speed_table.count = 6;
3376 static int ci_setup_default_dpm_tables(struct radeon_device *rdev)
3378 struct ci_power_info *pi = ci_get_pi(rdev);
3379 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
3380 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3381 struct radeon_clock_voltage_dependency_table *allowed_mclk_table =
3382 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
3383 struct radeon_cac_leakage_table *std_voltage_table =
3384 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3387 if (allowed_sclk_vddc_table == NULL)
3389 if (allowed_sclk_vddc_table->count < 1)
3391 if (allowed_mclk_table == NULL)
3393 if (allowed_mclk_table->count < 1)
3396 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table));
3398 ci_reset_single_dpm_table(rdev,
3399 &pi->dpm_table.sclk_table,
3400 SMU7_MAX_LEVELS_GRAPHICS);
3401 ci_reset_single_dpm_table(rdev,
3402 &pi->dpm_table.mclk_table,
3403 SMU7_MAX_LEVELS_MEMORY);
3404 ci_reset_single_dpm_table(rdev,
3405 &pi->dpm_table.vddc_table,
3406 SMU7_MAX_LEVELS_VDDC);
3407 ci_reset_single_dpm_table(rdev,
3408 &pi->dpm_table.vddci_table,
3409 SMU7_MAX_LEVELS_VDDCI);
3410 ci_reset_single_dpm_table(rdev,
3411 &pi->dpm_table.mvdd_table,
3412 SMU7_MAX_LEVELS_MVDD);
3414 pi->dpm_table.sclk_table.count = 0;
3415 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3417 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value !=
3418 allowed_sclk_vddc_table->entries[i].clk)) {
3419 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value =
3420 allowed_sclk_vddc_table->entries[i].clk;
3421 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled =
3422 (i == 0) ? true : false;
3423 pi->dpm_table.sclk_table.count++;
3427 pi->dpm_table.mclk_table.count = 0;
3428 for (i = 0; i < allowed_mclk_table->count; i++) {
3430 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value !=
3431 allowed_mclk_table->entries[i].clk)) {
3432 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value =
3433 allowed_mclk_table->entries[i].clk;
3434 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled =
3435 (i == 0) ? true : false;
3436 pi->dpm_table.mclk_table.count++;
3440 for (i = 0; i < allowed_sclk_vddc_table->count; i++) {
3441 pi->dpm_table.vddc_table.dpm_levels[i].value =
3442 allowed_sclk_vddc_table->entries[i].v;
3443 pi->dpm_table.vddc_table.dpm_levels[i].param1 =
3444 std_voltage_table->entries[i].leakage;
3445 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true;
3447 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count;
3449 allowed_mclk_table = &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
3450 if (allowed_mclk_table) {
3451 for (i = 0; i < allowed_mclk_table->count; i++) {
3452 pi->dpm_table.vddci_table.dpm_levels[i].value =
3453 allowed_mclk_table->entries[i].v;
3454 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true;
3456 pi->dpm_table.vddci_table.count = allowed_mclk_table->count;
3459 allowed_mclk_table = &rdev->pm.dpm.dyn_state.mvdd_dependency_on_mclk;
3460 if (allowed_mclk_table) {
3461 for (i = 0; i < allowed_mclk_table->count; i++) {
3462 pi->dpm_table.mvdd_table.dpm_levels[i].value =
3463 allowed_mclk_table->entries[i].v;
3464 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true;
3466 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count;
3469 ci_setup_default_pcie_tables(rdev);
3474 static int ci_find_boot_level(struct ci_single_dpm_table *table,
3475 u32 value, u32 *boot_level)
3480 for(i = 0; i < table->count; i++) {
3481 if (value == table->dpm_levels[i].value) {
3490 static int ci_init_smc_table(struct radeon_device *rdev)
3492 struct ci_power_info *pi = ci_get_pi(rdev);
3493 struct ci_ulv_parm *ulv = &pi->ulv;
3494 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
3495 SMU7_Discrete_DpmTable *table = &pi->smc_state_table;
3498 ret = ci_setup_default_dpm_tables(rdev);
3502 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE)
3503 ci_populate_smc_voltage_tables(rdev, table);
3505 ci_init_fps_limits(rdev);
3507 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
3508 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
3510 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
3511 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
3514 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
3516 if (ulv->supported) {
3517 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv);
3520 WREG32_SMC(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
3523 ret = ci_populate_all_graphic_levels(rdev);
3527 ret = ci_populate_all_memory_levels(rdev);
3531 ci_populate_smc_link_level(rdev, table);
3533 ret = ci_populate_smc_acpi_level(rdev, table);
3537 ret = ci_populate_smc_vce_level(rdev, table);
3541 ret = ci_populate_smc_acp_level(rdev, table);
3545 ret = ci_populate_smc_samu_level(rdev, table);
3549 ret = ci_do_program_memory_timing_parameters(rdev);
3553 ret = ci_populate_smc_uvd_level(rdev, table);
3557 table->UvdBootLevel = 0;
3558 table->VceBootLevel = 0;
3559 table->AcpBootLevel = 0;
3560 table->SamuBootLevel = 0;
3561 table->GraphicsBootLevel = 0;
3562 table->MemoryBootLevel = 0;
3564 ret = ci_find_boot_level(&pi->dpm_table.sclk_table,
3565 pi->vbios_boot_state.sclk_bootup_value,
3566 (u32 *)&pi->smc_state_table.GraphicsBootLevel);
3568 ret = ci_find_boot_level(&pi->dpm_table.mclk_table,
3569 pi->vbios_boot_state.mclk_bootup_value,
3570 (u32 *)&pi->smc_state_table.MemoryBootLevel);
3572 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value;
3573 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value;
3574 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value;
3576 ci_populate_smc_initial_state(rdev, radeon_boot_state);
3578 ret = ci_populate_bapm_parameters_in_dpm_table(rdev);
3582 table->UVDInterval = 1;
3583 table->VCEInterval = 1;
3584 table->ACPInterval = 1;
3585 table->SAMUInterval = 1;
3586 table->GraphicsVoltageChangeEnable = 1;
3587 table->GraphicsThermThrottleEnable = 1;
3588 table->GraphicsInterval = 1;
3589 table->VoltageInterval = 1;
3590 table->ThermalInterval = 1;
3591 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high *
3592 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3593 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low *
3594 CISLANDS_Q88_FORMAT_CONVERSION_UNIT) / 1000);
3595 table->MemoryVoltageChangeEnable = 1;
3596 table->MemoryInterval = 1;
3597 table->VoltageResponseTime = 0;
3598 table->VddcVddciDelta = 4000;
3599 table->PhaseResponseTime = 0;
3600 table->MemoryThermThrottleEnable = 1;
3601 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1;
3602 table->PCIeGenInterval = 1;
3603 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2)
3604 table->SVI2Enable = 1;
3606 table->SVI2Enable = 0;
3608 table->ThermGpio = 17;
3609 table->SclkStepSize = 0x4000;
3611 table->SystemFlags = cpu_to_be32(table->SystemFlags);
3612 table->SmioMaskVddcVid = cpu_to_be32(table->SmioMaskVddcVid);
3613 table->SmioMaskVddcPhase = cpu_to_be32(table->SmioMaskVddcPhase);
3614 table->SmioMaskVddciVid = cpu_to_be32(table->SmioMaskVddciVid);
3615 table->SmioMaskMvddVid = cpu_to_be32(table->SmioMaskMvddVid);
3616 table->SclkStepSize = cpu_to_be32(table->SclkStepSize);
3617 table->TemperatureLimitHigh = cpu_to_be16(table->TemperatureLimitHigh);
3618 table->TemperatureLimitLow = cpu_to_be16(table->TemperatureLimitLow);
3619 table->VddcVddciDelta = cpu_to_be16(table->VddcVddciDelta);
3620 table->VoltageResponseTime = cpu_to_be16(table->VoltageResponseTime);
3621 table->PhaseResponseTime = cpu_to_be16(table->PhaseResponseTime);
3622 table->BootVddc = cpu_to_be16(table->BootVddc * VOLTAGE_SCALE);
3623 table->BootVddci = cpu_to_be16(table->BootVddci * VOLTAGE_SCALE);
3624 table->BootMVdd = cpu_to_be16(table->BootMVdd * VOLTAGE_SCALE);
3626 ret = ci_copy_bytes_to_smc(rdev,
3627 pi->dpm_table_start +
3628 offsetof(SMU7_Discrete_DpmTable, SystemFlags),
3629 (u8 *)&table->SystemFlags,
3630 sizeof(SMU7_Discrete_DpmTable) - 3 * sizeof(SMU7_PIDController),
3638 static void ci_trim_single_dpm_states(struct radeon_device *rdev,
3639 struct ci_single_dpm_table *dpm_table,
3640 u32 low_limit, u32 high_limit)
3644 for (i = 0; i < dpm_table->count; i++) {
3645 if ((dpm_table->dpm_levels[i].value < low_limit) ||
3646 (dpm_table->dpm_levels[i].value > high_limit))
3647 dpm_table->dpm_levels[i].enabled = false;
3649 dpm_table->dpm_levels[i].enabled = true;
3653 static void ci_trim_pcie_dpm_states(struct radeon_device *rdev,
3654 u32 speed_low, u32 lanes_low,
3655 u32 speed_high, u32 lanes_high)
3657 struct ci_power_info *pi = ci_get_pi(rdev);
3658 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table;
3661 for (i = 0; i < pcie_table->count; i++) {
3662 if ((pcie_table->dpm_levels[i].value < speed_low) ||
3663 (pcie_table->dpm_levels[i].param1 < lanes_low) ||
3664 (pcie_table->dpm_levels[i].value > speed_high) ||
3665 (pcie_table->dpm_levels[i].param1 > lanes_high))
3666 pcie_table->dpm_levels[i].enabled = false;
3668 pcie_table->dpm_levels[i].enabled = true;
3671 for (i = 0; i < pcie_table->count; i++) {
3672 if (pcie_table->dpm_levels[i].enabled) {
3673 for (j = i + 1; j < pcie_table->count; j++) {
3674 if (pcie_table->dpm_levels[j].enabled) {
3675 if ((pcie_table->dpm_levels[i].value == pcie_table->dpm_levels[j].value) &&
3676 (pcie_table->dpm_levels[i].param1 == pcie_table->dpm_levels[j].param1))
3677 pcie_table->dpm_levels[j].enabled = false;
3684 static int ci_trim_dpm_states(struct radeon_device *rdev,
3685 struct radeon_ps *radeon_state)
3687 struct ci_ps *state = ci_get_ps(radeon_state);
3688 struct ci_power_info *pi = ci_get_pi(rdev);
3689 u32 high_limit_count;
3691 if (state->performance_level_count < 1)
3694 if (state->performance_level_count == 1)
3695 high_limit_count = 0;
3697 high_limit_count = 1;
3699 ci_trim_single_dpm_states(rdev,
3700 &pi->dpm_table.sclk_table,
3701 state->performance_levels[0].sclk,
3702 state->performance_levels[high_limit_count].sclk);
3704 ci_trim_single_dpm_states(rdev,
3705 &pi->dpm_table.mclk_table,
3706 state->performance_levels[0].mclk,
3707 state->performance_levels[high_limit_count].mclk);
3709 ci_trim_pcie_dpm_states(rdev,
3710 state->performance_levels[0].pcie_gen,
3711 state->performance_levels[0].pcie_lane,
3712 state->performance_levels[high_limit_count].pcie_gen,
3713 state->performance_levels[high_limit_count].pcie_lane);
3718 static int ci_apply_disp_minimum_voltage_request(struct radeon_device *rdev)
3720 struct radeon_clock_voltage_dependency_table *disp_voltage_table =
3721 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk;
3722 struct radeon_clock_voltage_dependency_table *vddc_table =
3723 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
3724 u32 requested_voltage = 0;
3727 if (disp_voltage_table == NULL)
3729 if (!disp_voltage_table->count)
3732 for (i = 0; i < disp_voltage_table->count; i++) {
3733 if (rdev->clock.current_dispclk == disp_voltage_table->entries[i].clk)
3734 requested_voltage = disp_voltage_table->entries[i].v;
3737 for (i = 0; i < vddc_table->count; i++) {
3738 if (requested_voltage <= vddc_table->entries[i].v) {
3739 requested_voltage = vddc_table->entries[i].v;
3740 return (ci_send_msg_to_smc_with_parameter(rdev,
3741 PPSMC_MSG_VddC_Request,
3742 requested_voltage * VOLTAGE_SCALE) == PPSMC_Result_OK) ?
3750 static int ci_upload_dpm_level_enable_mask(struct radeon_device *rdev)
3752 struct ci_power_info *pi = ci_get_pi(rdev);
3753 PPSMC_Result result;
3755 ci_apply_disp_minimum_voltage_request(rdev);
3757 if (!pi->sclk_dpm_key_disabled) {
3758 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
3759 result = ci_send_msg_to_smc_with_parameter(rdev,
3760 PPSMC_MSG_SCLKDPM_SetEnabledMask,
3761 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
3762 if (result != PPSMC_Result_OK)
3767 if (!pi->mclk_dpm_key_disabled) {
3768 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
3769 result = ci_send_msg_to_smc_with_parameter(rdev,
3770 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3771 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3772 if (result != PPSMC_Result_OK)
3777 if (!pi->pcie_dpm_key_disabled) {
3778 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
3779 result = ci_send_msg_to_smc_with_parameter(rdev,
3780 PPSMC_MSG_PCIeDPM_SetEnabledMask,
3781 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
3782 if (result != PPSMC_Result_OK)
3790 static void ci_find_dpm_states_clocks_in_dpm_table(struct radeon_device *rdev,
3791 struct radeon_ps *radeon_state)
3793 struct ci_power_info *pi = ci_get_pi(rdev);
3794 struct ci_ps *state = ci_get_ps(radeon_state);
3795 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table;
3796 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3797 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table;
3798 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3801 pi->need_update_smu7_dpm_table = 0;
3803 for (i = 0; i < sclk_table->count; i++) {
3804 if (sclk == sclk_table->dpm_levels[i].value)
3808 if (i >= sclk_table->count) {
3809 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK;
3811 /* XXX check display min clock requirements */
3812 if (CISLAND_MINIMUM_ENGINE_CLOCK != CISLAND_MINIMUM_ENGINE_CLOCK)
3813 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK;
3816 for (i = 0; i < mclk_table->count; i++) {
3817 if (mclk == mclk_table->dpm_levels[i].value)
3821 if (i >= mclk_table->count)
3822 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK;
3824 if (rdev->pm.dpm.current_active_crtc_count !=
3825 rdev->pm.dpm.new_active_crtc_count)
3826 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK;
3829 static int ci_populate_and_upload_sclk_mclk_dpm_levels(struct radeon_device *rdev,
3830 struct radeon_ps *radeon_state)
3832 struct ci_power_info *pi = ci_get_pi(rdev);
3833 struct ci_ps *state = ci_get_ps(radeon_state);
3834 u32 sclk = state->performance_levels[state->performance_level_count-1].sclk;
3835 u32 mclk = state->performance_levels[state->performance_level_count-1].mclk;
3836 struct ci_dpm_table *dpm_table = &pi->dpm_table;
3839 if (!pi->need_update_smu7_dpm_table)
3842 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK)
3843 dpm_table->sclk_table.dpm_levels[dpm_table->sclk_table.count-1].value = sclk;
3845 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)
3846 dpm_table->mclk_table.dpm_levels[dpm_table->mclk_table.count-1].value = mclk;
3848 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) {
3849 ret = ci_populate_all_graphic_levels(rdev);
3854 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) {
3855 ret = ci_populate_all_memory_levels(rdev);
3863 static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
3865 struct ci_power_info *pi = ci_get_pi(rdev);
3866 const struct radeon_clock_and_voltage_limits *max_limits;
3869 if (rdev->pm.dpm.ac_power)
3870 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3872 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3875 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0;
3877 for (i = rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3878 if (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3879 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i;
3881 if (!pi->caps_uvd_dpm)
3886 ci_send_msg_to_smc_with_parameter(rdev,
3887 PPSMC_MSG_UVDDPM_SetEnabledMask,
3888 pi->dpm_level_enable_mask.uvd_dpm_enable_mask);
3890 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3891 pi->uvd_enabled = true;
3892 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
3893 ci_send_msg_to_smc_with_parameter(rdev,
3894 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3895 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3898 if (pi->last_mclk_dpm_enable_mask & 0x1) {
3899 pi->uvd_enabled = false;
3900 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1;
3901 ci_send_msg_to_smc_with_parameter(rdev,
3902 PPSMC_MSG_MCLKDPM_SetEnabledMask,
3903 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
3907 return (ci_send_msg_to_smc(rdev, enable ?
3908 PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable) == PPSMC_Result_OK) ?
3912 static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
3914 struct ci_power_info *pi = ci_get_pi(rdev);
3915 const struct radeon_clock_and_voltage_limits *max_limits;
3918 if (rdev->pm.dpm.ac_power)
3919 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3921 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3924 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0;
3925 for (i = rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3926 if (rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3927 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i;
3929 if (!pi->caps_vce_dpm)
3934 ci_send_msg_to_smc_with_parameter(rdev,
3935 PPSMC_MSG_VCEDPM_SetEnabledMask,
3936 pi->dpm_level_enable_mask.vce_dpm_enable_mask);
3939 return (ci_send_msg_to_smc(rdev, enable ?
3940 PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable) == PPSMC_Result_OK) ?
3945 static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
3947 struct ci_power_info *pi = ci_get_pi(rdev);
3948 const struct radeon_clock_and_voltage_limits *max_limits;
3951 if (rdev->pm.dpm.ac_power)
3952 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3954 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3957 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
3958 for (i = rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3959 if (rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3960 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
3962 if (!pi->caps_samu_dpm)
3967 ci_send_msg_to_smc_with_parameter(rdev,
3968 PPSMC_MSG_SAMUDPM_SetEnabledMask,
3969 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
3971 return (ci_send_msg_to_smc(rdev, enable ?
3972 PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable) == PPSMC_Result_OK) ?
3976 static int ci_enable_acp_dpm(struct radeon_device *rdev, bool enable)
3978 struct ci_power_info *pi = ci_get_pi(rdev);
3979 const struct radeon_clock_and_voltage_limits *max_limits;
3982 if (rdev->pm.dpm.ac_power)
3983 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3985 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3988 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
3989 for (i = rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.count - 1; i >= 0; i--) {
3990 if (rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table.entries[i].v <= max_limits->vddc) {
3991 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
3993 if (!pi->caps_acp_dpm)
3998 ci_send_msg_to_smc_with_parameter(rdev,
3999 PPSMC_MSG_ACPDPM_SetEnabledMask,
4000 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4003 return (ci_send_msg_to_smc(rdev, enable ?
4004 PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable) == PPSMC_Result_OK) ?
4009 static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
4011 struct ci_power_info *pi = ci_get_pi(rdev);
4015 if (pi->caps_uvd_dpm ||
4016 (rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count <= 0))
4017 pi->smc_state_table.UvdBootLevel = 0;
4019 pi->smc_state_table.UvdBootLevel =
4020 rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table.count - 1;
4022 tmp = RREG32_SMC(DPM_TABLE_475);
4023 tmp &= ~UvdBootLevel_MASK;
4024 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel);
4025 WREG32_SMC(DPM_TABLE_475, tmp);
4028 return ci_enable_uvd_dpm(rdev, !gate);
4031 static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
4034 u32 min_evclk = 30000; /* ??? */
4035 struct radeon_vce_clock_voltage_dependency_table *table =
4036 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
4038 for (i = 0; i < table->count; i++) {
4039 if (table->entries[i].evclk >= min_evclk)
4043 return table->count - 1;
4046 static int ci_update_vce_dpm(struct radeon_device *rdev,
4047 struct radeon_ps *radeon_new_state,
4048 struct radeon_ps *radeon_current_state)
4050 struct ci_power_info *pi = ci_get_pi(rdev);
4054 if (radeon_current_state->evclk != radeon_new_state->evclk) {
4055 if (radeon_new_state->evclk) {
4056 /* turn the clocks on when encoding */
4057 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, false);
4059 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
4060 tmp = RREG32_SMC(DPM_TABLE_475);
4061 tmp &= ~VceBootLevel_MASK;
4062 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel);
4063 WREG32_SMC(DPM_TABLE_475, tmp);
4065 ret = ci_enable_vce_dpm(rdev, true);
4067 /* turn the clocks off when not encoding */
4068 cik_update_cg(rdev, RADEON_CG_BLOCK_VCE, true);
4070 ret = ci_enable_vce_dpm(rdev, false);
4077 static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
4079 return ci_enable_samu_dpm(rdev, gate);
4082 static int ci_update_acp_dpm(struct radeon_device *rdev, bool gate)
4084 struct ci_power_info *pi = ci_get_pi(rdev);
4088 pi->smc_state_table.AcpBootLevel = 0;
4090 tmp = RREG32_SMC(DPM_TABLE_475);
4091 tmp &= ~AcpBootLevel_MASK;
4092 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4093 WREG32_SMC(DPM_TABLE_475, tmp);
4096 return ci_enable_acp_dpm(rdev, !gate);
4100 static int ci_generate_dpm_level_enable_mask(struct radeon_device *rdev,
4101 struct radeon_ps *radeon_state)
4103 struct ci_power_info *pi = ci_get_pi(rdev);
4106 ret = ci_trim_dpm_states(rdev, radeon_state);
4110 pi->dpm_level_enable_mask.sclk_dpm_enable_mask =
4111 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table);
4112 pi->dpm_level_enable_mask.mclk_dpm_enable_mask =
4113 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table);
4114 pi->last_mclk_dpm_enable_mask =
4115 pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4116 if (pi->uvd_enabled) {
4117 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1)
4118 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE;
4120 pi->dpm_level_enable_mask.pcie_dpm_enable_mask =
4121 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table);
4126 static u32 ci_get_lowest_enabled_level(struct radeon_device *rdev,
4131 while ((level_mask & (1 << level)) == 0)
4138 int ci_dpm_force_performance_level(struct radeon_device *rdev,
4139 enum radeon_dpm_forced_level level)
4141 struct ci_power_info *pi = ci_get_pi(rdev);
4145 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
4146 if ((!pi->pcie_dpm_key_disabled) &&
4147 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4149 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask;
4153 ret = ci_dpm_force_state_pcie(rdev, level);
4156 for (i = 0; i < rdev->usec_timeout; i++) {
4157 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4158 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4165 if ((!pi->sclk_dpm_key_disabled) &&
4166 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4168 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask;
4172 ret = ci_dpm_force_state_sclk(rdev, levels);
4175 for (i = 0; i < rdev->usec_timeout; i++) {
4176 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4177 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4184 if ((!pi->mclk_dpm_key_disabled) &&
4185 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4187 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask;
4191 ret = ci_dpm_force_state_mclk(rdev, levels);
4194 for (i = 0; i < rdev->usec_timeout; i++) {
4195 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4196 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4203 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
4204 if ((!pi->sclk_dpm_key_disabled) &&
4205 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) {
4206 levels = ci_get_lowest_enabled_level(rdev,
4207 pi->dpm_level_enable_mask.sclk_dpm_enable_mask);
4208 ret = ci_dpm_force_state_sclk(rdev, levels);
4211 for (i = 0; i < rdev->usec_timeout; i++) {
4212 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4213 CURR_SCLK_INDEX_MASK) >> CURR_SCLK_INDEX_SHIFT;
4219 if ((!pi->mclk_dpm_key_disabled) &&
4220 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) {
4221 levels = ci_get_lowest_enabled_level(rdev,
4222 pi->dpm_level_enable_mask.mclk_dpm_enable_mask);
4223 ret = ci_dpm_force_state_mclk(rdev, levels);
4226 for (i = 0; i < rdev->usec_timeout; i++) {
4227 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) &
4228 CURR_MCLK_INDEX_MASK) >> CURR_MCLK_INDEX_SHIFT;
4234 if ((!pi->pcie_dpm_key_disabled) &&
4235 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) {
4236 levels = ci_get_lowest_enabled_level(rdev,
4237 pi->dpm_level_enable_mask.pcie_dpm_enable_mask);
4238 ret = ci_dpm_force_state_pcie(rdev, levels);
4241 for (i = 0; i < rdev->usec_timeout; i++) {
4242 tmp = (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX_1) &
4243 CURR_PCIE_INDEX_MASK) >> CURR_PCIE_INDEX_SHIFT;
4249 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
4250 if (!pi->pcie_dpm_key_disabled) {
4251 PPSMC_Result smc_result;
4253 smc_result = ci_send_msg_to_smc(rdev,
4254 PPSMC_MSG_PCIeDPM_UnForceLevel);
4255 if (smc_result != PPSMC_Result_OK)
4258 ret = ci_upload_dpm_level_enable_mask(rdev);
4263 rdev->pm.dpm.forced_level = level;
4268 static int ci_set_mc_special_registers(struct radeon_device *rdev,
4269 struct ci_mc_reg_table *table)
4271 struct ci_power_info *pi = ci_get_pi(rdev);
4275 for (i = 0, j = table->last; i < table->last; i++) {
4276 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4278 switch(table->mc_reg_address[i].s1 << 2) {
4280 temp_reg = RREG32(MC_PMG_CMD_EMRS);
4281 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
4282 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4283 for (k = 0; k < table->num_entries; k++) {
4284 table->mc_reg_table_entry[k].mc_data[j] =
4285 ((temp_reg & 0xffff0000)) | ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
4288 if (j >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4291 temp_reg = RREG32(MC_PMG_CMD_MRS);
4292 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
4293 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4294 for (k = 0; k < table->num_entries; k++) {
4295 table->mc_reg_table_entry[k].mc_data[j] =
4296 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4298 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
4301 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4304 if (!pi->mem_gddr5) {
4305 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
4306 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
4307 for (k = 0; k < table->num_entries; k++) {
4308 table->mc_reg_table_entry[k].mc_data[j] =
4309 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
4312 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4316 case MC_SEQ_RESERVE_M:
4317 temp_reg = RREG32(MC_PMG_CMD_MRS1);
4318 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
4319 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4320 for (k = 0; k < table->num_entries; k++) {
4321 table->mc_reg_table_entry[k].mc_data[j] =
4322 (temp_reg & 0xffff0000) | (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
4325 if (j > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4339 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
4344 case MC_SEQ_RAS_TIMING >> 2:
4345 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
4347 case MC_SEQ_DLL_STBY >> 2:
4348 *out_reg = MC_SEQ_DLL_STBY_LP >> 2;
4350 case MC_SEQ_G5PDX_CMD0 >> 2:
4351 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2;
4353 case MC_SEQ_G5PDX_CMD1 >> 2:
4354 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2;
4356 case MC_SEQ_G5PDX_CTRL >> 2:
4357 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2;
4359 case MC_SEQ_CAS_TIMING >> 2:
4360 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
4362 case MC_SEQ_MISC_TIMING >> 2:
4363 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
4365 case MC_SEQ_MISC_TIMING2 >> 2:
4366 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
4368 case MC_SEQ_PMG_DVS_CMD >> 2:
4369 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2;
4371 case MC_SEQ_PMG_DVS_CTL >> 2:
4372 *out_reg = MC_SEQ_PMG_DVS_CTL_LP >> 2;
4374 case MC_SEQ_RD_CTL_D0 >> 2:
4375 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
4377 case MC_SEQ_RD_CTL_D1 >> 2:
4378 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
4380 case MC_SEQ_WR_CTL_D0 >> 2:
4381 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
4383 case MC_SEQ_WR_CTL_D1 >> 2:
4384 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
4386 case MC_PMG_CMD_EMRS >> 2:
4387 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
4389 case MC_PMG_CMD_MRS >> 2:
4390 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
4392 case MC_PMG_CMD_MRS1 >> 2:
4393 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
4395 case MC_SEQ_PMG_TIMING >> 2:
4396 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
4398 case MC_PMG_CMD_MRS2 >> 2:
4399 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
4401 case MC_SEQ_WR_CTL_2 >> 2:
4402 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
4412 static void ci_set_valid_flag(struct ci_mc_reg_table *table)
4416 for (i = 0; i < table->last; i++) {
4417 for (j = 1; j < table->num_entries; j++) {
4418 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
4419 table->mc_reg_table_entry[j].mc_data[i]) {
4420 table->valid_flag |= 1 << i;
4427 static void ci_set_s0_mc_reg_index(struct ci_mc_reg_table *table)
4432 for (i = 0; i < table->last; i++) {
4433 table->mc_reg_address[i].s0 =
4434 ci_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
4435 address : table->mc_reg_address[i].s1;
4439 static int ci_copy_vbios_mc_reg_table(const struct atom_mc_reg_table *table,
4440 struct ci_mc_reg_table *ci_table)
4444 if (table->last > SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4446 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
4449 for (i = 0; i < table->last; i++)
4450 ci_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
4452 ci_table->last = table->last;
4454 for (i = 0; i < table->num_entries; i++) {
4455 ci_table->mc_reg_table_entry[i].mclk_max =
4456 table->mc_reg_table_entry[i].mclk_max;
4457 for (j = 0; j < table->last; j++)
4458 ci_table->mc_reg_table_entry[i].mc_data[j] =
4459 table->mc_reg_table_entry[i].mc_data[j];
4461 ci_table->num_entries = table->num_entries;
4466 static int ci_register_patching_mc_seq(struct radeon_device *rdev,
4467 struct ci_mc_reg_table *table)
4473 tmp = RREG32(MC_SEQ_MISC0);
4474 patch = ((tmp & 0x0000f00) == 0x300) ? true : false;
4477 ((rdev->pdev->device == 0x67B0) ||
4478 (rdev->pdev->device == 0x67B1))) {
4479 for (i = 0; i < table->last; i++) {
4480 if (table->last >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4482 switch(table->mc_reg_address[i].s1 >> 2) {
4484 for (k = 0; k < table->num_entries; k++) {
4485 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4486 (table->mc_reg_table_entry[k].mclk_max == 137500))
4487 table->mc_reg_table_entry[k].mc_data[i] =
4488 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFF8) |
4492 case MC_SEQ_WR_CTL_D0:
4493 for (k = 0; k < table->num_entries; k++) {
4494 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4495 (table->mc_reg_table_entry[k].mclk_max == 137500))
4496 table->mc_reg_table_entry[k].mc_data[i] =
4497 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4501 case MC_SEQ_WR_CTL_D1:
4502 for (k = 0; k < table->num_entries; k++) {
4503 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4504 (table->mc_reg_table_entry[k].mclk_max == 137500))
4505 table->mc_reg_table_entry[k].mc_data[i] =
4506 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFF0F00) |
4510 case MC_SEQ_WR_CTL_2:
4511 for (k = 0; k < table->num_entries; k++) {
4512 if ((table->mc_reg_table_entry[k].mclk_max == 125000) ||
4513 (table->mc_reg_table_entry[k].mclk_max == 137500))
4514 table->mc_reg_table_entry[k].mc_data[i] = 0;
4517 case MC_SEQ_CAS_TIMING:
4518 for (k = 0; k < table->num_entries; k++) {
4519 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4520 table->mc_reg_table_entry[k].mc_data[i] =
4521 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4523 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4524 table->mc_reg_table_entry[k].mc_data[i] =
4525 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFE0FE0F) |
4529 case MC_SEQ_MISC_TIMING:
4530 for (k = 0; k < table->num_entries; k++) {
4531 if (table->mc_reg_table_entry[k].mclk_max == 125000)
4532 table->mc_reg_table_entry[k].mc_data[i] =
4533 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4535 else if (table->mc_reg_table_entry[k].mclk_max == 137500)
4536 table->mc_reg_table_entry[k].mc_data[i] =
4537 (table->mc_reg_table_entry[k].mc_data[i] & 0xFFFFFFE0) |
4546 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4547 tmp = RREG32(MC_SEQ_IO_DEBUG_DATA);
4548 tmp = (tmp & 0xFFF8FFFF) | (1 << 16);
4549 WREG32(MC_SEQ_IO_DEBUG_INDEX, 3);
4550 WREG32(MC_SEQ_IO_DEBUG_DATA, tmp);
4556 static int ci_initialize_mc_reg_table(struct radeon_device *rdev)
4558 struct ci_power_info *pi = ci_get_pi(rdev);
4559 struct atom_mc_reg_table *table;
4560 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table;
4561 u8 module_index = rv770_get_memory_module_index(rdev);
4564 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
4568 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
4569 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
4570 WREG32(MC_SEQ_DLL_STBY_LP, RREG32(MC_SEQ_DLL_STBY));
4571 WREG32(MC_SEQ_G5PDX_CMD0_LP, RREG32(MC_SEQ_G5PDX_CMD0));
4572 WREG32(MC_SEQ_G5PDX_CMD1_LP, RREG32(MC_SEQ_G5PDX_CMD1));
4573 WREG32(MC_SEQ_G5PDX_CTRL_LP, RREG32(MC_SEQ_G5PDX_CTRL));
4574 WREG32(MC_SEQ_PMG_DVS_CMD_LP, RREG32(MC_SEQ_PMG_DVS_CMD));
4575 WREG32(MC_SEQ_PMG_DVS_CTL_LP, RREG32(MC_SEQ_PMG_DVS_CTL));
4576 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
4577 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
4578 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
4579 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
4580 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
4581 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
4582 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
4583 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
4584 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
4585 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
4586 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
4587 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
4589 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
4593 ret = ci_copy_vbios_mc_reg_table(table, ci_table);
4597 ci_set_s0_mc_reg_index(ci_table);
4599 ret = ci_register_patching_mc_seq(rdev, ci_table);
4603 ret = ci_set_mc_special_registers(rdev, ci_table);
4607 ci_set_valid_flag(ci_table);
4615 static int ci_populate_mc_reg_addresses(struct radeon_device *rdev,
4616 SMU7_Discrete_MCRegisters *mc_reg_table)
4618 struct ci_power_info *pi = ci_get_pi(rdev);
4621 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) {
4622 if (pi->mc_reg_table.valid_flag & (1 << j)) {
4623 if (i >= SMU7_DISCRETE_MC_REGISTER_ARRAY_SIZE)
4625 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0);
4626 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1);
4631 mc_reg_table->last = (u8)i;
4636 static void ci_convert_mc_registers(const struct ci_mc_reg_entry *entry,
4637 SMU7_Discrete_MCRegisterSet *data,
4638 u32 num_entries, u32 valid_flag)
4642 for (i = 0, j = 0; j < num_entries; j++) {
4643 if (valid_flag & (1 << j)) {
4644 data->value[i] = cpu_to_be32(entry->mc_data[j]);
4650 static void ci_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
4651 const u32 memory_clock,
4652 SMU7_Discrete_MCRegisterSet *mc_reg_table_data)
4654 struct ci_power_info *pi = ci_get_pi(rdev);
4657 for(i = 0; i < pi->mc_reg_table.num_entries; i++) {
4658 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
4662 if ((i == pi->mc_reg_table.num_entries) && (i > 0))
4665 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i],
4666 mc_reg_table_data, pi->mc_reg_table.last,
4667 pi->mc_reg_table.valid_flag);
4670 static void ci_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
4671 SMU7_Discrete_MCRegisters *mc_reg_table)
4673 struct ci_power_info *pi = ci_get_pi(rdev);
4676 for (i = 0; i < pi->dpm_table.mclk_table.count; i++)
4677 ci_convert_mc_reg_table_entry_to_smc(rdev,
4678 pi->dpm_table.mclk_table.dpm_levels[i].value,
4679 &mc_reg_table->data[i]);
4682 static int ci_populate_initial_mc_reg_table(struct radeon_device *rdev)
4684 struct ci_power_info *pi = ci_get_pi(rdev);
4687 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4689 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table);
4692 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4694 return ci_copy_bytes_to_smc(rdev,
4695 pi->mc_reg_table_start,
4696 (u8 *)&pi->smc_mc_reg_table,
4697 sizeof(SMU7_Discrete_MCRegisters),
4701 static int ci_update_and_upload_mc_reg_table(struct radeon_device *rdev)
4703 struct ci_power_info *pi = ci_get_pi(rdev);
4705 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK))
4708 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters));
4710 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table);
4712 return ci_copy_bytes_to_smc(rdev,
4713 pi->mc_reg_table_start +
4714 offsetof(SMU7_Discrete_MCRegisters, data[0]),
4715 (u8 *)&pi->smc_mc_reg_table.data[0],
4716 sizeof(SMU7_Discrete_MCRegisterSet) *
4717 pi->dpm_table.mclk_table.count,
4721 static void ci_enable_voltage_control(struct radeon_device *rdev)
4723 u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
4725 tmp |= VOLT_PWRMGT_EN;
4726 WREG32_SMC(GENERAL_PWRMGT, tmp);
4729 static enum radeon_pcie_gen ci_get_maximum_link_speed(struct radeon_device *rdev,
4730 struct radeon_ps *radeon_state)
4732 struct ci_ps *state = ci_get_ps(radeon_state);
4734 u16 pcie_speed, max_speed = 0;
4736 for (i = 0; i < state->performance_level_count; i++) {
4737 pcie_speed = state->performance_levels[i].pcie_gen;
4738 if (max_speed < pcie_speed)
4739 max_speed = pcie_speed;
4745 static u16 ci_get_current_pcie_speed(struct radeon_device *rdev)
4749 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
4750 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
4752 return (u16)speed_cntl;
4755 static int ci_get_current_pcie_lane_number(struct radeon_device *rdev)
4759 link_width = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL) & LC_LINK_WIDTH_RD_MASK;
4760 link_width >>= LC_LINK_WIDTH_RD_SHIFT;
4762 switch (link_width) {
4763 case RADEON_PCIE_LC_LINK_WIDTH_X1:
4765 case RADEON_PCIE_LC_LINK_WIDTH_X2:
4767 case RADEON_PCIE_LC_LINK_WIDTH_X4:
4769 case RADEON_PCIE_LC_LINK_WIDTH_X8:
4771 case RADEON_PCIE_LC_LINK_WIDTH_X12:
4772 /* not actually supported */
4774 case RADEON_PCIE_LC_LINK_WIDTH_X0:
4775 case RADEON_PCIE_LC_LINK_WIDTH_X16:
4781 static void ci_request_link_speed_change_before_state_change(struct radeon_device *rdev,
4782 struct radeon_ps *radeon_new_state,
4783 struct radeon_ps *radeon_current_state)
4785 struct ci_power_info *pi = ci_get_pi(rdev);
4786 enum radeon_pcie_gen target_link_speed =
4787 ci_get_maximum_link_speed(rdev, radeon_new_state);
4788 enum radeon_pcie_gen current_link_speed;
4790 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
4791 current_link_speed = ci_get_maximum_link_speed(rdev, radeon_current_state);
4793 current_link_speed = pi->force_pcie_gen;
4795 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
4796 pi->pspp_notify_required = false;
4797 if (target_link_speed > current_link_speed) {
4798 switch (target_link_speed) {
4800 case RADEON_PCIE_GEN3:
4801 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
4803 pi->force_pcie_gen = RADEON_PCIE_GEN2;
4804 if (current_link_speed == RADEON_PCIE_GEN2)
4806 case RADEON_PCIE_GEN2:
4807 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
4811 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev);
4815 if (target_link_speed < current_link_speed)
4816 pi->pspp_notify_required = true;
4820 static void ci_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
4821 struct radeon_ps *radeon_new_state,
4822 struct radeon_ps *radeon_current_state)
4824 struct ci_power_info *pi = ci_get_pi(rdev);
4825 enum radeon_pcie_gen target_link_speed =
4826 ci_get_maximum_link_speed(rdev, radeon_new_state);
4829 if (pi->pspp_notify_required) {
4830 if (target_link_speed == RADEON_PCIE_GEN3)
4831 request = PCIE_PERF_REQ_PECI_GEN3;
4832 else if (target_link_speed == RADEON_PCIE_GEN2)
4833 request = PCIE_PERF_REQ_PECI_GEN2;
4835 request = PCIE_PERF_REQ_PECI_GEN1;
4837 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
4838 (ci_get_current_pcie_speed(rdev) > 0))
4842 radeon_acpi_pcie_performance_request(rdev, request, false);
4847 static int ci_set_private_data_variables_based_on_pptable(struct radeon_device *rdev)
4849 struct ci_power_info *pi = ci_get_pi(rdev);
4850 struct radeon_clock_voltage_dependency_table *allowed_sclk_vddc_table =
4851 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
4852 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddc_table =
4853 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk;
4854 struct radeon_clock_voltage_dependency_table *allowed_mclk_vddci_table =
4855 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk;
4857 if (allowed_sclk_vddc_table == NULL)
4859 if (allowed_sclk_vddc_table->count < 1)
4861 if (allowed_mclk_vddc_table == NULL)
4863 if (allowed_mclk_vddc_table->count < 1)
4865 if (allowed_mclk_vddci_table == NULL)
4867 if (allowed_mclk_vddci_table->count < 1)
4870 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v;
4871 pi->max_vddc_in_pp_table =
4872 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4874 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v;
4875 pi->max_vddci_in_pp_table =
4876 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4878 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk =
4879 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4880 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk =
4881 allowed_mclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].clk;
4882 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc =
4883 allowed_sclk_vddc_table->entries[allowed_sclk_vddc_table->count - 1].v;
4884 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci =
4885 allowed_mclk_vddci_table->entries[allowed_mclk_vddci_table->count - 1].v;
4890 static void ci_patch_with_vddc_leakage(struct radeon_device *rdev, u16 *vddc)
4892 struct ci_power_info *pi = ci_get_pi(rdev);
4893 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage;
4896 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4897 if (leakage_table->leakage_id[leakage_index] == *vddc) {
4898 *vddc = leakage_table->actual_voltage[leakage_index];
4904 static void ci_patch_with_vddci_leakage(struct radeon_device *rdev, u16 *vddci)
4906 struct ci_power_info *pi = ci_get_pi(rdev);
4907 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage;
4910 for (leakage_index = 0; leakage_index < leakage_table->count; leakage_index++) {
4911 if (leakage_table->leakage_id[leakage_index] == *vddci) {
4912 *vddci = leakage_table->actual_voltage[leakage_index];
4918 static void ci_patch_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4919 struct radeon_clock_voltage_dependency_table *table)
4924 for (i = 0; i < table->count; i++)
4925 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4929 static void ci_patch_clock_voltage_dependency_table_with_vddci_leakage(struct radeon_device *rdev,
4930 struct radeon_clock_voltage_dependency_table *table)
4935 for (i = 0; i < table->count; i++)
4936 ci_patch_with_vddci_leakage(rdev, &table->entries[i].v);
4940 static void ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4941 struct radeon_vce_clock_voltage_dependency_table *table)
4946 for (i = 0; i < table->count; i++)
4947 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4951 static void ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(struct radeon_device *rdev,
4952 struct radeon_uvd_clock_voltage_dependency_table *table)
4957 for (i = 0; i < table->count; i++)
4958 ci_patch_with_vddc_leakage(rdev, &table->entries[i].v);
4962 static void ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(struct radeon_device *rdev,
4963 struct radeon_phase_shedding_limits_table *table)
4968 for (i = 0; i < table->count; i++)
4969 ci_patch_with_vddc_leakage(rdev, &table->entries[i].voltage);
4973 static void ci_patch_clock_voltage_limits_with_vddc_leakage(struct radeon_device *rdev,
4974 struct radeon_clock_and_voltage_limits *table)
4977 ci_patch_with_vddc_leakage(rdev, (u16 *)&table->vddc);
4978 ci_patch_with_vddci_leakage(rdev, (u16 *)&table->vddci);
4982 static void ci_patch_cac_leakage_table_with_vddc_leakage(struct radeon_device *rdev,
4983 struct radeon_cac_leakage_table *table)
4988 for (i = 0; i < table->count; i++)
4989 ci_patch_with_vddc_leakage(rdev, &table->entries[i].vddc);
4993 static void ci_patch_dependency_tables_with_leakage(struct radeon_device *rdev)
4996 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4997 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
4998 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
4999 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5000 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5001 &rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk);
5002 ci_patch_clock_voltage_dependency_table_with_vddci_leakage(rdev,
5003 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5004 ci_patch_vce_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5005 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table);
5006 ci_patch_uvd_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5007 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table);
5008 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5009 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table);
5010 ci_patch_clock_voltage_dependency_table_with_vddc_leakage(rdev,
5011 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table);
5012 ci_patch_vddc_phase_shed_limit_table_with_vddc_leakage(rdev,
5013 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table);
5014 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5015 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
5016 ci_patch_clock_voltage_limits_with_vddc_leakage(rdev,
5017 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc);
5018 ci_patch_cac_leakage_table_with_vddc_leakage(rdev,
5019 &rdev->pm.dpm.dyn_state.cac_leakage_table);
5023 static void ci_get_memory_type(struct radeon_device *rdev)
5025 struct ci_power_info *pi = ci_get_pi(rdev);
5028 tmp = RREG32(MC_SEQ_MISC0);
5030 if (((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT) ==
5031 MC_SEQ_MISC0_GDDR5_VALUE)
5032 pi->mem_gddr5 = true;
5034 pi->mem_gddr5 = false;
5038 static void ci_update_current_ps(struct radeon_device *rdev,
5039 struct radeon_ps *rps)
5041 struct ci_ps *new_ps = ci_get_ps(rps);
5042 struct ci_power_info *pi = ci_get_pi(rdev);
5044 pi->current_rps = *rps;
5045 pi->current_ps = *new_ps;
5046 pi->current_rps.ps_priv = &pi->current_ps;
5049 static void ci_update_requested_ps(struct radeon_device *rdev,
5050 struct radeon_ps *rps)
5052 struct ci_ps *new_ps = ci_get_ps(rps);
5053 struct ci_power_info *pi = ci_get_pi(rdev);
5055 pi->requested_rps = *rps;
5056 pi->requested_ps = *new_ps;
5057 pi->requested_rps.ps_priv = &pi->requested_ps;
5060 int ci_dpm_pre_set_power_state(struct radeon_device *rdev)
5062 struct ci_power_info *pi = ci_get_pi(rdev);
5063 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5064 struct radeon_ps *new_ps = &requested_ps;
5066 ci_update_requested_ps(rdev, new_ps);
5068 ci_apply_state_adjust_rules(rdev, &pi->requested_rps);
5073 void ci_dpm_post_set_power_state(struct radeon_device *rdev)
5075 struct ci_power_info *pi = ci_get_pi(rdev);
5076 struct radeon_ps *new_ps = &pi->requested_rps;
5078 ci_update_current_ps(rdev, new_ps);
5082 void ci_dpm_setup_asic(struct radeon_device *rdev)
5086 r = ci_mc_load_microcode(rdev);
5088 DRM_ERROR("Failed to load MC firmware!\n");
5089 ci_read_clock_registers(rdev);
5090 ci_get_memory_type(rdev);
5091 ci_enable_acpi_power_management(rdev);
5092 ci_init_sclk_t(rdev);
5095 int ci_dpm_enable(struct radeon_device *rdev)
5097 struct ci_power_info *pi = ci_get_pi(rdev);
5098 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5101 if (ci_is_smc_running(rdev))
5103 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) {
5104 ci_enable_voltage_control(rdev);
5105 ret = ci_construct_voltage_tables(rdev);
5107 DRM_ERROR("ci_construct_voltage_tables failed\n");
5111 if (pi->caps_dynamic_ac_timing) {
5112 ret = ci_initialize_mc_reg_table(rdev);
5114 pi->caps_dynamic_ac_timing = false;
5117 ci_enable_spread_spectrum(rdev, true);
5118 if (pi->thermal_protection)
5119 ci_enable_thermal_protection(rdev, true);
5120 ci_program_sstp(rdev);
5121 ci_enable_display_gap(rdev);
5122 ci_program_vc(rdev);
5123 ret = ci_upload_firmware(rdev);
5125 DRM_ERROR("ci_upload_firmware failed\n");
5128 ret = ci_process_firmware_header(rdev);
5130 DRM_ERROR("ci_process_firmware_header failed\n");
5133 ret = ci_initial_switch_from_arb_f0_to_f1(rdev);
5135 DRM_ERROR("ci_initial_switch_from_arb_f0_to_f1 failed\n");
5138 ret = ci_init_smc_table(rdev);
5140 DRM_ERROR("ci_init_smc_table failed\n");
5143 ret = ci_init_arb_table_index(rdev);
5145 DRM_ERROR("ci_init_arb_table_index failed\n");
5148 if (pi->caps_dynamic_ac_timing) {
5149 ret = ci_populate_initial_mc_reg_table(rdev);
5151 DRM_ERROR("ci_populate_initial_mc_reg_table failed\n");
5155 ret = ci_populate_pm_base(rdev);
5157 DRM_ERROR("ci_populate_pm_base failed\n");
5160 ci_dpm_start_smc(rdev);
5161 ci_enable_vr_hot_gpio_interrupt(rdev);
5162 ret = ci_notify_smc_display_change(rdev, false);
5164 DRM_ERROR("ci_notify_smc_display_change failed\n");
5167 ci_enable_sclk_control(rdev, true);
5168 ret = ci_enable_ulv(rdev, true);
5170 DRM_ERROR("ci_enable_ulv failed\n");
5173 ret = ci_enable_ds_master_switch(rdev, true);
5175 DRM_ERROR("ci_enable_ds_master_switch failed\n");
5178 ret = ci_start_dpm(rdev);
5180 DRM_ERROR("ci_start_dpm failed\n");
5183 ret = ci_enable_didt(rdev, true);
5185 DRM_ERROR("ci_enable_didt failed\n");
5188 ret = ci_enable_smc_cac(rdev, true);
5190 DRM_ERROR("ci_enable_smc_cac failed\n");
5193 ret = ci_enable_power_containment(rdev, true);
5195 DRM_ERROR("ci_enable_power_containment failed\n");
5199 ret = ci_power_control_set_level(rdev);
5201 DRM_ERROR("ci_power_control_set_level failed\n");
5205 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5207 ret = ci_enable_thermal_based_sclk_dpm(rdev, true);
5209 DRM_ERROR("ci_enable_thermal_based_sclk_dpm failed\n");
5213 ci_thermal_start_thermal_controller(rdev);
5215 ci_update_current_ps(rdev, boot_ps);
5220 static int ci_set_temperature_range(struct radeon_device *rdev)
5224 ret = ci_thermal_enable_alert(rdev, false);
5227 ret = ci_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5230 ret = ci_thermal_enable_alert(rdev, true);
5237 int ci_dpm_late_enable(struct radeon_device *rdev)
5241 ret = ci_set_temperature_range(rdev);
5245 ci_dpm_powergate_uvd(rdev, true);
5250 void ci_dpm_disable(struct radeon_device *rdev)
5252 struct ci_power_info *pi = ci_get_pi(rdev);
5253 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5255 ci_dpm_powergate_uvd(rdev, false);
5257 if (!ci_is_smc_running(rdev))
5260 ci_thermal_stop_thermal_controller(rdev);
5262 if (pi->thermal_protection)
5263 ci_enable_thermal_protection(rdev, false);
5264 ci_enable_power_containment(rdev, false);
5265 ci_enable_smc_cac(rdev, false);
5266 ci_enable_didt(rdev, false);
5267 ci_enable_spread_spectrum(rdev, false);
5268 ci_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5270 ci_enable_ds_master_switch(rdev, false);
5271 ci_enable_ulv(rdev, false);
5273 ci_reset_to_default(rdev);
5274 ci_dpm_stop_smc(rdev);
5275 ci_force_switch_to_arb_f0(rdev);
5276 ci_enable_thermal_based_sclk_dpm(rdev, false);
5278 ci_update_current_ps(rdev, boot_ps);
5281 int ci_dpm_set_power_state(struct radeon_device *rdev)
5283 struct ci_power_info *pi = ci_get_pi(rdev);
5284 struct radeon_ps *new_ps = &pi->requested_rps;
5285 struct radeon_ps *old_ps = &pi->current_rps;
5288 ci_find_dpm_states_clocks_in_dpm_table(rdev, new_ps);
5289 if (pi->pcie_performance_request)
5290 ci_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5291 ret = ci_freeze_sclk_mclk_dpm(rdev);
5293 DRM_ERROR("ci_freeze_sclk_mclk_dpm failed\n");
5296 ret = ci_populate_and_upload_sclk_mclk_dpm_levels(rdev, new_ps);
5298 DRM_ERROR("ci_populate_and_upload_sclk_mclk_dpm_levels failed\n");
5301 ret = ci_generate_dpm_level_enable_mask(rdev, new_ps);
5303 DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
5307 ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
5309 DRM_ERROR("ci_update_vce_dpm failed\n");
5313 ret = ci_update_sclk_t(rdev);
5315 DRM_ERROR("ci_update_sclk_t failed\n");
5318 if (pi->caps_dynamic_ac_timing) {
5319 ret = ci_update_and_upload_mc_reg_table(rdev);
5321 DRM_ERROR("ci_update_and_upload_mc_reg_table failed\n");
5325 ret = ci_program_memory_timing_parameters(rdev);
5327 DRM_ERROR("ci_program_memory_timing_parameters failed\n");
5330 ret = ci_unfreeze_sclk_mclk_dpm(rdev);
5332 DRM_ERROR("ci_unfreeze_sclk_mclk_dpm failed\n");
5335 ret = ci_upload_dpm_level_enable_mask(rdev);
5337 DRM_ERROR("ci_upload_dpm_level_enable_mask failed\n");
5340 if (pi->pcie_performance_request)
5341 ci_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5346 void ci_dpm_reset_asic(struct radeon_device *rdev)
5348 ci_set_boot_state(rdev);
5351 void ci_dpm_display_configuration_changed(struct radeon_device *rdev)
5353 ci_program_display_gap(rdev);
5357 struct _ATOM_POWERPLAY_INFO info;
5358 struct _ATOM_POWERPLAY_INFO_V2 info_2;
5359 struct _ATOM_POWERPLAY_INFO_V3 info_3;
5360 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
5361 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
5362 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
5365 union pplib_clock_info {
5366 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
5367 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
5368 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
5369 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
5370 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
5371 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
5374 union pplib_power_state {
5375 struct _ATOM_PPLIB_STATE v1;
5376 struct _ATOM_PPLIB_STATE_V2 v2;
5379 static void ci_parse_pplib_non_clock_info(struct radeon_device *rdev,
5380 struct radeon_ps *rps,
5381 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
5384 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
5385 rps->class = le16_to_cpu(non_clock_info->usClassification);
5386 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
5388 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
5389 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
5390 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
5396 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
5397 rdev->pm.dpm.boot_ps = rps;
5398 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
5399 rdev->pm.dpm.uvd_ps = rps;
5402 static void ci_parse_pplib_clock_info(struct radeon_device *rdev,
5403 struct radeon_ps *rps, int index,
5404 union pplib_clock_info *clock_info)
5406 struct ci_power_info *pi = ci_get_pi(rdev);
5407 struct ci_ps *ps = ci_get_ps(rps);
5408 struct ci_pl *pl = &ps->performance_levels[index];
5410 ps->performance_level_count = index + 1;
5412 pl->sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5413 pl->sclk |= clock_info->ci.ucEngineClockHigh << 16;
5414 pl->mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5415 pl->mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5417 pl->pcie_gen = r600_get_pcie_gen_support(rdev,
5419 pi->vbios_boot_state.pcie_gen_bootup_value,
5420 clock_info->ci.ucPCIEGen);
5421 pl->pcie_lane = r600_get_pcie_lane_support(rdev,
5422 pi->vbios_boot_state.pcie_lane_bootup_value,
5423 le16_to_cpu(clock_info->ci.usPCIELane));
5425 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
5426 pi->acpi_pcie_gen = pl->pcie_gen;
5429 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
5430 pi->ulv.supported = true;
5432 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT;
5435 /* patch up boot state */
5436 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
5437 pl->mclk = pi->vbios_boot_state.mclk_bootup_value;
5438 pl->sclk = pi->vbios_boot_state.sclk_bootup_value;
5439 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value;
5440 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value;
5443 switch (rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
5444 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
5445 pi->use_pcie_powersaving_levels = true;
5446 if (pi->pcie_gen_powersaving.max < pl->pcie_gen)
5447 pi->pcie_gen_powersaving.max = pl->pcie_gen;
5448 if (pi->pcie_gen_powersaving.min > pl->pcie_gen)
5449 pi->pcie_gen_powersaving.min = pl->pcie_gen;
5450 if (pi->pcie_lane_powersaving.max < pl->pcie_lane)
5451 pi->pcie_lane_powersaving.max = pl->pcie_lane;
5452 if (pi->pcie_lane_powersaving.min > pl->pcie_lane)
5453 pi->pcie_lane_powersaving.min = pl->pcie_lane;
5455 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
5456 pi->use_pcie_performance_levels = true;
5457 if (pi->pcie_gen_performance.max < pl->pcie_gen)
5458 pi->pcie_gen_performance.max = pl->pcie_gen;
5459 if (pi->pcie_gen_performance.min > pl->pcie_gen)
5460 pi->pcie_gen_performance.min = pl->pcie_gen;
5461 if (pi->pcie_lane_performance.max < pl->pcie_lane)
5462 pi->pcie_lane_performance.max = pl->pcie_lane;
5463 if (pi->pcie_lane_performance.min > pl->pcie_lane)
5464 pi->pcie_lane_performance.min = pl->pcie_lane;
5471 static int ci_parse_power_table(struct radeon_device *rdev)
5473 struct radeon_mode_info *mode_info = &rdev->mode_info;
5474 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
5475 union pplib_power_state *power_state;
5476 int i, j, k, non_clock_array_index, clock_array_index;
5477 union pplib_clock_info *clock_info;
5478 struct _StateArray *state_array;
5479 struct _ClockInfoArray *clock_info_array;
5480 struct _NonClockInfoArray *non_clock_info_array;
5481 union power_info *power_info;
5482 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
5485 u8 *power_state_offset;
5488 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
5489 &frev, &crev, &data_offset))
5491 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
5493 state_array = (struct _StateArray *)
5494 (mode_info->atom_context->bios + data_offset +
5495 le16_to_cpu(power_info->pplib.usStateArrayOffset));
5496 clock_info_array = (struct _ClockInfoArray *)
5497 (mode_info->atom_context->bios + data_offset +
5498 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
5499 non_clock_info_array = (struct _NonClockInfoArray *)
5500 (mode_info->atom_context->bios + data_offset +
5501 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
5503 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
5504 state_array->ucNumEntries, GFP_KERNEL);
5505 if (!rdev->pm.dpm.ps)
5507 power_state_offset = (u8 *)state_array->states;
5508 for (i = 0; i < state_array->ucNumEntries; i++) {
5510 power_state = (union pplib_power_state *)power_state_offset;
5511 non_clock_array_index = power_state->v2.nonClockInfoIndex;
5512 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
5513 &non_clock_info_array->nonClockInfo[non_clock_array_index];
5514 if (!rdev->pm.power_state[i].clock_info)
5516 ps = kzalloc(sizeof(struct ci_ps), GFP_KERNEL);
5518 kfree(rdev->pm.dpm.ps);
5521 rdev->pm.dpm.ps[i].ps_priv = ps;
5522 ci_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
5524 non_clock_info_array->ucEntrySize);
5526 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
5527 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
5528 clock_array_index = idx[j];
5529 if (clock_array_index >= clock_info_array->ucNumEntries)
5531 if (k >= CISLANDS_MAX_HARDWARE_POWERLEVELS)
5533 clock_info = (union pplib_clock_info *)
5534 ((u8 *)&clock_info_array->clockInfo[0] +
5535 (clock_array_index * clock_info_array->ucEntrySize));
5536 ci_parse_pplib_clock_info(rdev,
5537 &rdev->pm.dpm.ps[i], k,
5541 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
5543 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
5545 /* fill in the vce power states */
5546 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
5548 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
5549 clock_info = (union pplib_clock_info *)
5550 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
5551 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
5552 sclk |= clock_info->ci.ucEngineClockHigh << 16;
5553 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
5554 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
5555 rdev->pm.dpm.vce_states[i].sclk = sclk;
5556 rdev->pm.dpm.vce_states[i].mclk = mclk;
5562 static int ci_get_vbios_boot_values(struct radeon_device *rdev,
5563 struct ci_vbios_boot_state *boot_state)
5565 struct radeon_mode_info *mode_info = &rdev->mode_info;
5566 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
5567 ATOM_FIRMWARE_INFO_V2_2 *firmware_info;
5571 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
5572 &frev, &crev, &data_offset)) {
5574 (ATOM_FIRMWARE_INFO_V2_2 *)(mode_info->atom_context->bios +
5576 boot_state->mvdd_bootup_value = le16_to_cpu(firmware_info->usBootUpMVDDCVoltage);
5577 boot_state->vddc_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCVoltage);
5578 boot_state->vddci_bootup_value = le16_to_cpu(firmware_info->usBootUpVDDCIVoltage);
5579 boot_state->pcie_gen_bootup_value = ci_get_current_pcie_speed(rdev);
5580 boot_state->pcie_lane_bootup_value = ci_get_current_pcie_lane_number(rdev);
5581 boot_state->sclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultEngineClock);
5582 boot_state->mclk_bootup_value = le32_to_cpu(firmware_info->ulDefaultMemoryClock);
5589 void ci_dpm_fini(struct radeon_device *rdev)
5593 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
5594 kfree(rdev->pm.dpm.ps[i].ps_priv);
5596 kfree(rdev->pm.dpm.ps);
5597 kfree(rdev->pm.dpm.priv);
5598 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
5599 r600_free_extended_power_table(rdev);
5602 int ci_dpm_init(struct radeon_device *rdev)
5604 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
5605 SMU7_Discrete_DpmTable *dpm_table;
5606 struct radeon_gpio_rec gpio;
5607 u16 data_offset, size;
5609 struct ci_power_info *pi;
5613 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL);
5616 rdev->pm.dpm.priv = pi;
5618 ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
5620 pi->sys_pcie_mask = 0;
5622 pi->sys_pcie_mask = mask;
5623 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5625 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1;
5626 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3;
5627 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1;
5628 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3;
5630 pi->pcie_lane_performance.max = 0;
5631 pi->pcie_lane_performance.min = 16;
5632 pi->pcie_lane_powersaving.max = 0;
5633 pi->pcie_lane_powersaving.min = 16;
5635 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state);
5641 ret = r600_get_platform_caps(rdev);
5647 ret = r600_parse_extended_power_table(rdev);
5653 ret = ci_parse_power_table(rdev);
5659 pi->dll_default_on = false;
5660 pi->sram_end = SMC_RAM_END;
5662 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT;
5663 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT;
5664 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT;
5665 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT;
5666 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT;
5667 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT;
5668 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT;
5669 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT;
5671 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT;
5673 pi->sclk_dpm_key_disabled = 0;
5674 pi->mclk_dpm_key_disabled = 0;
5675 pi->pcie_dpm_key_disabled = 0;
5676 pi->thermal_sclk_dpm_enabled = 0;
5678 /* mclk dpm is unstable on some R7 260X cards with the old mc ucode */
5679 if ((rdev->pdev->device == 0x6658) &&
5680 (rdev->mc_fw->size == (BONAIRE_MC_UCODE_SIZE * 4))) {
5681 pi->mclk_dpm_key_disabled = 1;
5684 pi->caps_sclk_ds = true;
5686 pi->mclk_strobe_mode_threshold = 40000;
5687 pi->mclk_stutter_mode_threshold = 40000;
5688 pi->mclk_edc_enable_threshold = 40000;
5689 pi->mclk_edc_wr_enable_threshold = 40000;
5691 ci_initialize_powertune_defaults(rdev);
5693 pi->caps_fps = false;
5695 pi->caps_sclk_throttle_low_notification = false;
5697 pi->caps_uvd_dpm = true;
5698 pi->caps_vce_dpm = true;
5700 ci_get_leakage_voltages(rdev);
5701 ci_patch_dependency_tables_with_leakage(rdev);
5702 ci_set_private_data_variables_based_on_pptable(rdev);
5704 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
5705 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
5706 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
5710 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
5711 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
5712 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
5713 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
5714 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
5715 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
5716 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
5717 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
5718 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
5720 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
5721 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
5722 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
5724 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
5725 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
5726 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
5727 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
5729 if (rdev->family == CHIP_HAWAII) {
5730 pi->thermal_temp_setting.temperature_low = 94500;
5731 pi->thermal_temp_setting.temperature_high = 95000;
5732 pi->thermal_temp_setting.temperature_shutdown = 104000;
5734 pi->thermal_temp_setting.temperature_low = 99500;
5735 pi->thermal_temp_setting.temperature_high = 100000;
5736 pi->thermal_temp_setting.temperature_shutdown = 104000;
5739 pi->uvd_enabled = false;
5741 dpm_table = &pi->smc_state_table;
5743 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_VRHOT_GPIO_PINID);
5745 dpm_table->VRHotGpio = gpio.shift;
5746 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5748 dpm_table->VRHotGpio = CISLANDS_UNUSED_GPIO_PIN;
5749 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_REGULATOR_HOT;
5752 gpio = radeon_atombios_lookup_gpio(rdev, PP_AC_DC_SWITCH_GPIO_PINID);
5754 dpm_table->AcDcGpio = gpio.shift;
5755 rdev->pm.dpm.platform_caps |= ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5757 dpm_table->AcDcGpio = CISLANDS_UNUSED_GPIO_PIN;
5758 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_HARDWAREDC;
5761 gpio = radeon_atombios_lookup_gpio(rdev, VDDC_PCC_GPIO_PINID);
5763 u32 tmp = RREG32_SMC(CNB_PWRMGT_CNTL);
5765 switch (gpio.shift) {
5767 tmp &= ~GNB_SLOW_MODE_MASK;
5768 tmp |= GNB_SLOW_MODE(1);
5771 tmp &= ~GNB_SLOW_MODE_MASK;
5772 tmp |= GNB_SLOW_MODE(2);
5778 tmp |= FORCE_NB_PS1;
5784 DRM_ERROR("Invalid PCC GPIO: %u!\n", gpio.shift);
5787 WREG32_SMC(CNB_PWRMGT_CNTL, tmp);
5790 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5791 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5792 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE;
5793 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_GPIO_LUT))
5794 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5795 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2))
5796 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5798 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL) {
5799 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT))
5800 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5801 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2))
5802 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5804 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_VDDCI_CONTROL;
5807 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_MVDDCONTROL) {
5808 if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT))
5809 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO;
5810 else if (radeon_atom_is_voltage_gpio(rdev, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2))
5811 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2;
5813 rdev->pm.dpm.platform_caps &= ~ATOM_PP_PLATFORM_CAP_MVDDCONTROL;
5816 pi->vddc_phase_shed_control = true;
5818 #if defined(CONFIG_ACPI)
5819 pi->pcie_performance_request =
5820 radeon_acpi_is_pcie_performance_request_supported(rdev);
5822 pi->pcie_performance_request = false;
5825 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
5826 &frev, &crev, &data_offset)) {
5827 pi->caps_sclk_ss_support = true;
5828 pi->caps_mclk_ss_support = true;
5829 pi->dynamic_ss = true;
5831 pi->caps_sclk_ss_support = false;
5832 pi->caps_mclk_ss_support = false;
5833 pi->dynamic_ss = true;
5836 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
5837 pi->thermal_protection = true;
5839 pi->thermal_protection = false;
5841 pi->caps_dynamic_ac_timing = true;
5843 pi->uvd_power_gated = false;
5845 /* make sure dc limits are valid */
5846 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
5847 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
5848 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
5849 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
5851 pi->fan_ctrl_is_in_default_mode = true;
5856 void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
5859 struct ci_power_info *pi = ci_get_pi(rdev);
5860 struct radeon_ps *rps = &pi->current_rps;
5861 u32 sclk = ci_get_average_sclk_freq(rdev);
5862 u32 mclk = ci_get_average_mclk_freq(rdev);
5864 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis");
5865 seq_printf(m, "vce %sabled\n", rps->vce_active ? "en" : "dis");
5866 seq_printf(m, "power level avg sclk: %u mclk: %u\n",
5870 void ci_dpm_print_power_state(struct radeon_device *rdev,
5871 struct radeon_ps *rps)
5873 struct ci_ps *ps = ci_get_ps(rps);
5877 r600_dpm_print_class_info(rps->class, rps->class2);
5878 r600_dpm_print_cap_info(rps->caps);
5879 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
5880 for (i = 0; i < ps->performance_level_count; i++) {
5881 pl = &ps->performance_levels[i];
5882 printk("\t\tpower level %d sclk: %u mclk: %u pcie gen: %u pcie lanes: %u\n",
5883 i, pl->sclk, pl->mclk, pl->pcie_gen + 1, pl->pcie_lane);
5885 r600_dpm_print_ps_status(rdev, rps);
5888 u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low)
5890 struct ci_power_info *pi = ci_get_pi(rdev);
5891 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5894 return requested_state->performance_levels[0].sclk;
5896 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
5899 u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low)
5901 struct ci_power_info *pi = ci_get_pi(rdev);
5902 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps);
5905 return requested_state->performance_levels[0].mclk;
5907 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;