drivers/gpu/drm/radeon/dce6_afmt.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/hdmi.h>
  24 #include <drm/drmP.h>
  25 #include "radeon.h"
  26 #include "sid.h"
  27
  28 static u32 dce6_endpoint_rreg(struct radeon_device *rdev,
  29                               u32 block_offset, u32 reg)
  30 {
  31         u32 r;
  32
  33         WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
  34         r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
  35         return r;
  36 }
  37
  38 static void dce6_endpoint_wreg(struct radeon_device *rdev,
  39                                u32 block_offset, u32 reg, u32 v)
  40 {
  41         if (ASIC_IS_DCE8(rdev))
  42                 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
  43         else
  44                 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
  45                        AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
  46         WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
  47 }
  48
  49 #define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg))
  50 #define WREG32_ENDPOINT(block, reg, v) dce6_endpoint_wreg(rdev, (block), (reg), (v))
  51
  52
  53 static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
  54 {
  55         int i;
  56         u32 offset, tmp;
  57
  58         for (i = 0; i < rdev->audio.num_pins; i++) {
  59                 offset = rdev->audio.pin[i].offset;
  60                 tmp = RREG32_ENDPOINT(offset,
  61                                       AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
  62                 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
  63                         rdev->audio.pin[i].connected = false;
  64                 else
  65                         rdev->audio.pin[i].connected = true;
  66         }
  67 }
  68
  69 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)
  70 {
  71         int i;
  72
  73         dce6_afmt_get_connected_pins(rdev);
  74
  75         for (i = 0; i < rdev->audio.num_pins; i++) {
  76                 if (rdev->audio.pin[i].connected)
  77                         return &rdev->audio.pin[i];
  78         }
  79         DRM_ERROR("No connected audio pins found!\n");
  80         return NULL;
  81 }
  82
  83 void dce6_afmt_select_pin(struct drm_encoder *encoder)
  84 {
  85         struct radeon_device *rdev = encoder->dev->dev_private;
  86         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  87         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  88         u32 offset = dig->afmt->offset;
  89         u32 id = dig->afmt->pin->id;
  90
  91         if (!dig->afmt->pin)
  92                 return;
  93
  94         WREG32(AFMT_AUDIO_SRC_CONTROL + offset, AFMT_AUDIO_SRC_SELECT(id));
  95 }
  96
  97 void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
  98 {
  99         struct radeon_device *rdev = encoder->dev->dev_private;
 100         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 101         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 102         struct drm_connector *connector;
 103         struct radeon_connector *radeon_connector = NULL;
 104         u32 offset, tmp;
 105         u8 *sadb;
 106         int sad_count;
 107
 108         if (!dig->afmt->pin)
 109                 return;
 110
 111         offset = dig->afmt->pin->offset;
 112
 113         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
 114                 if (connector->encoder == encoder)
 115                         radeon_connector = to_radeon_connector(connector);
 116         }
 117
 118         if (!radeon_connector) {
 119                 DRM_ERROR("Couldn't find encoder's connector\n");
 120                 return;
 121         }
 122
 123         sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
 124         if (sad_count < 0) {
 125                 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
 126                 return;
 127         }
 128
 129         /* program the speaker allocation */
 130         tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
 131         tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
 132         /* set HDMI mode */
 133         tmp |= HDMI_CONNECTION;
 134         if (sad_count)
 135                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
 136         else
 137                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
 138         WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
 139
 140         kfree(sadb);
 141 }
 142
 143 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder)
 144 {
 145         struct radeon_device *rdev = encoder->dev->dev_private;
 146         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 147         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 148         u32 offset;
 149         struct drm_connector *connector;
 150         struct radeon_connector *radeon_connector = NULL;
 151         struct cea_sad *sads;
 152         int i, sad_count;
 153
 154         static const u16 eld_reg_to_type[][2] = {
 155                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
 156                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
 157                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
 158                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
 159                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
 160                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
 161                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
 162                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
 163                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
 164                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
 165                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
 166                 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
 167         };
 168
 169         if (!dig->afmt->pin)
 170                 return;
 171
 172         offset = dig->afmt->pin->offset;
 173
 174         list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
 175                 if (connector->encoder == encoder)
 176                         radeon_connector = to_radeon_connector(connector);
 177         }
 178
 179         if (!radeon_connector) {
 180                 DRM_ERROR("Couldn't find encoder's connector\n");
 181                 return;
 182         }
 183
 184         sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
 185         if (sad_count < 0) {
 186                 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
 187                 return;
 188         }
 189         BUG_ON(!sads);
 190
 191         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
 192                 u32 value = 0;
 193                 int j;
 194
 195                 for (j = 0; j < sad_count; j++) {
 196                         struct cea_sad *sad = &sads[j];
 197
 198                         if (sad->format == eld_reg_to_type[i][1]) {
 199                                 value = MAX_CHANNELS(sad->channels) |
 200                                         DESCRIPTOR_BYTE_2(sad->byte2) |
 201                                         SUPPORTED_FREQUENCIES(sad->freq);
 202                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
 203                                         value |= SUPPORTED_FREQUENCIES_STEREO(sad->freq);
 204                                 break;
 205                         }
 206                 }
 207                 WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
 208         }
 209
 210         kfree(sads);
 211 }
 212
 213 static int dce6_audio_chipset_supported(struct radeon_device *rdev)
 214 {
 215         return !ASIC_IS_NODCE(rdev);
 216 }
 217
 218 static void dce6_audio_enable(struct radeon_device *rdev,
 219                               struct r600_audio_pin *pin,
 220                               bool enable)
 221 {
 222         WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL,
 223                         AUDIO_ENABLED);
 224         DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id);
 225 }
 226
 227 static const u32 pin_offsets[7] =
 228 {
 229         (0x5e00 - 0x5e00),
 230         (0x5e18 - 0x5e00),
 231         (0x5e30 - 0x5e00),
 232         (0x5e48 - 0x5e00),
 233         (0x5e60 - 0x5e00),
 234         (0x5e78 - 0x5e00),
 235         (0x5e90 - 0x5e00),
 236 };
 237
 238 int dce6_audio_init(struct radeon_device *rdev)
 239 {
 240         int i;
 241
 242         if (!radeon_audio || !dce6_audio_chipset_supported(rdev))
 243                 return 0;
 244
 245         rdev->audio.enabled = true;
 246
 247         if (ASIC_IS_DCE8(rdev))
 248                 rdev->audio.num_pins = 7;
 249         else
 250                 rdev->audio.num_pins = 6;
 251
 252         for (i = 0; i < rdev->audio.num_pins; i++) {
 253                 rdev->audio.pin[i].channels = -1;
 254                 rdev->audio.pin[i].rate = -1;
 255                 rdev->audio.pin[i].bits_per_sample = -1;
 256                 rdev->audio.pin[i].status_bits = 0;
 257                 rdev->audio.pin[i].category_code = 0;
 258                 rdev->audio.pin[i].connected = false;
 259                 rdev->audio.pin[i].offset = pin_offsets[i];
 260                 rdev->audio.pin[i].id = i;
 261                 dce6_audio_enable(rdev, &rdev->audio.pin[i], true);
 262         }
 263
 264         return 0;
 265 }
 266
 267 void dce6_audio_fini(struct radeon_device *rdev)
 268 {
 269         int i;
 270
 271         if (!rdev->audio.enabled)
 272                 return;
 273
 274         for (i = 0; i < rdev->audio.num_pins; i++)
 275                 dce6_audio_enable(rdev, &rdev->audio.pin[i], false);
 276
 277         rdev->audio.enabled = false;
 278 }