2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
40 static void evergreen_gpu_init(struct radeon_device *rdev);
41 void evergreen_fini(struct radeon_device *rdev);
43 /* get temperature in millidegrees */
44 u32 evergreen_get_temp(struct radeon_device *rdev)
46 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
52 else if ((temp >> 9) & 1)
55 actual_temp = (temp >> 1) & 0xff;
57 return actual_temp * 1000;
60 u32 sumo_get_temp(struct radeon_device *rdev)
62 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
63 u32 actual_temp = (temp >> 1) & 0xff;
65 return actual_temp * 1000;
68 void evergreen_pm_misc(struct radeon_device *rdev)
70 int req_ps_idx = rdev->pm.requested_power_state_index;
71 int req_cm_idx = rdev->pm.requested_clock_mode_index;
72 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
73 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
75 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
76 if (voltage->voltage != rdev->pm.current_vddc) {
77 radeon_atom_set_voltage(rdev, voltage->voltage);
78 rdev->pm.current_vddc = voltage->voltage;
79 DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
84 void evergreen_pm_prepare(struct radeon_device *rdev)
86 struct drm_device *ddev = rdev->ddev;
87 struct drm_crtc *crtc;
88 struct radeon_crtc *radeon_crtc;
91 /* disable any active CRTCs */
92 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
93 radeon_crtc = to_radeon_crtc(crtc);
94 if (radeon_crtc->enabled) {
95 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
96 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
97 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
102 void evergreen_pm_finish(struct radeon_device *rdev)
104 struct drm_device *ddev = rdev->ddev;
105 struct drm_crtc *crtc;
106 struct radeon_crtc *radeon_crtc;
109 /* enable any active CRTCs */
110 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
111 radeon_crtc = to_radeon_crtc(crtc);
112 if (radeon_crtc->enabled) {
113 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
114 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
115 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
120 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
122 bool connected = false;
126 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
130 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
134 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
138 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
142 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
146 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
156 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
157 enum radeon_hpd_id hpd)
160 bool connected = evergreen_hpd_sense(rdev, hpd);
164 tmp = RREG32(DC_HPD1_INT_CONTROL);
166 tmp &= ~DC_HPDx_INT_POLARITY;
168 tmp |= DC_HPDx_INT_POLARITY;
169 WREG32(DC_HPD1_INT_CONTROL, tmp);
172 tmp = RREG32(DC_HPD2_INT_CONTROL);
174 tmp &= ~DC_HPDx_INT_POLARITY;
176 tmp |= DC_HPDx_INT_POLARITY;
177 WREG32(DC_HPD2_INT_CONTROL, tmp);
180 tmp = RREG32(DC_HPD3_INT_CONTROL);
182 tmp &= ~DC_HPDx_INT_POLARITY;
184 tmp |= DC_HPDx_INT_POLARITY;
185 WREG32(DC_HPD3_INT_CONTROL, tmp);
188 tmp = RREG32(DC_HPD4_INT_CONTROL);
190 tmp &= ~DC_HPDx_INT_POLARITY;
192 tmp |= DC_HPDx_INT_POLARITY;
193 WREG32(DC_HPD4_INT_CONTROL, tmp);
196 tmp = RREG32(DC_HPD5_INT_CONTROL);
198 tmp &= ~DC_HPDx_INT_POLARITY;
200 tmp |= DC_HPDx_INT_POLARITY;
201 WREG32(DC_HPD5_INT_CONTROL, tmp);
204 tmp = RREG32(DC_HPD6_INT_CONTROL);
206 tmp &= ~DC_HPDx_INT_POLARITY;
208 tmp |= DC_HPDx_INT_POLARITY;
209 WREG32(DC_HPD6_INT_CONTROL, tmp);
216 void evergreen_hpd_init(struct radeon_device *rdev)
218 struct drm_device *dev = rdev->ddev;
219 struct drm_connector *connector;
220 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
221 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
223 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
224 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
225 switch (radeon_connector->hpd.hpd) {
227 WREG32(DC_HPD1_CONTROL, tmp);
228 rdev->irq.hpd[0] = true;
231 WREG32(DC_HPD2_CONTROL, tmp);
232 rdev->irq.hpd[1] = true;
235 WREG32(DC_HPD3_CONTROL, tmp);
236 rdev->irq.hpd[2] = true;
239 WREG32(DC_HPD4_CONTROL, tmp);
240 rdev->irq.hpd[3] = true;
243 WREG32(DC_HPD5_CONTROL, tmp);
244 rdev->irq.hpd[4] = true;
247 WREG32(DC_HPD6_CONTROL, tmp);
248 rdev->irq.hpd[5] = true;
254 if (rdev->irq.installed)
255 evergreen_irq_set(rdev);
258 void evergreen_hpd_fini(struct radeon_device *rdev)
260 struct drm_device *dev = rdev->ddev;
261 struct drm_connector *connector;
263 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
264 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
265 switch (radeon_connector->hpd.hpd) {
267 WREG32(DC_HPD1_CONTROL, 0);
268 rdev->irq.hpd[0] = false;
271 WREG32(DC_HPD2_CONTROL, 0);
272 rdev->irq.hpd[1] = false;
275 WREG32(DC_HPD3_CONTROL, 0);
276 rdev->irq.hpd[2] = false;
279 WREG32(DC_HPD4_CONTROL, 0);
280 rdev->irq.hpd[3] = false;
283 WREG32(DC_HPD5_CONTROL, 0);
284 rdev->irq.hpd[4] = false;
287 WREG32(DC_HPD6_CONTROL, 0);
288 rdev->irq.hpd[5] = false;
296 /* watermark setup */
298 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
299 struct radeon_crtc *radeon_crtc,
300 struct drm_display_mode *mode,
301 struct drm_display_mode *other_mode)
306 * There are 3 line buffers, each one shared by 2 display controllers.
307 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
308 * the display controllers. The paritioning is done via one of four
309 * preset allocations specified in bits 2:0:
310 * first display controller
311 * 0 - first half of lb (3840 * 2)
312 * 1 - first 3/4 of lb (5760 * 2)
313 * 2 - whole lb (7680 * 2)
314 * 3 - first 1/4 of lb (1920 * 2)
315 * second display controller
316 * 4 - second half of lb (3840 * 2)
317 * 5 - second 3/4 of lb (5760 * 2)
318 * 6 - whole lb (7680 * 2)
319 * 7 - last 1/4 of lb (1920 * 2)
321 if (mode && other_mode) {
322 if (mode->hdisplay > other_mode->hdisplay) {
323 if (mode->hdisplay > 2560)
327 } else if (other_mode->hdisplay > mode->hdisplay) {
328 if (other_mode->hdisplay > 2560)
339 /* second controller of the pair uses second half of the lb */
340 if (radeon_crtc->crtc_id % 2)
342 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
361 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
363 u32 tmp = RREG32(MC_SHARED_CHMAP);
365 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
378 struct evergreen_wm_params {
379 u32 dram_channels; /* number of dram channels */
380 u32 yclk; /* bandwidth per dram data pin in kHz */
381 u32 sclk; /* engine clock in kHz */
382 u32 disp_clk; /* display clock in kHz */
383 u32 src_width; /* viewport width */
384 u32 active_time; /* active display time in ns */
385 u32 blank_time; /* blank time in ns */
386 bool interlaced; /* mode is interlaced */
387 fixed20_12 vsc; /* vertical scale ratio */
388 u32 num_heads; /* number of active crtcs */
389 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
390 u32 lb_size; /* line buffer allocated to pipe */
391 u32 vtaps; /* vertical scaler taps */
394 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
396 /* Calculate DRAM Bandwidth and the part allocated to display. */
397 fixed20_12 dram_efficiency; /* 0.7 */
398 fixed20_12 yclk, dram_channels, bandwidth;
401 a.full = dfixed_const(1000);
402 yclk.full = dfixed_const(wm->yclk);
403 yclk.full = dfixed_div(yclk, a);
404 dram_channels.full = dfixed_const(wm->dram_channels * 4);
405 a.full = dfixed_const(10);
406 dram_efficiency.full = dfixed_const(7);
407 dram_efficiency.full = dfixed_div(dram_efficiency, a);
408 bandwidth.full = dfixed_mul(dram_channels, yclk);
409 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
411 return dfixed_trunc(bandwidth);
414 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
416 /* Calculate DRAM Bandwidth and the part allocated to display. */
417 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
418 fixed20_12 yclk, dram_channels, bandwidth;
421 a.full = dfixed_const(1000);
422 yclk.full = dfixed_const(wm->yclk);
423 yclk.full = dfixed_div(yclk, a);
424 dram_channels.full = dfixed_const(wm->dram_channels * 4);
425 a.full = dfixed_const(10);
426 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
427 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
428 bandwidth.full = dfixed_mul(dram_channels, yclk);
429 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
431 return dfixed_trunc(bandwidth);
434 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
436 /* Calculate the display Data return Bandwidth */
437 fixed20_12 return_efficiency; /* 0.8 */
438 fixed20_12 sclk, bandwidth;
441 a.full = dfixed_const(1000);
442 sclk.full = dfixed_const(wm->sclk);
443 sclk.full = dfixed_div(sclk, a);
444 a.full = dfixed_const(10);
445 return_efficiency.full = dfixed_const(8);
446 return_efficiency.full = dfixed_div(return_efficiency, a);
447 a.full = dfixed_const(32);
448 bandwidth.full = dfixed_mul(a, sclk);
449 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
451 return dfixed_trunc(bandwidth);
454 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
456 /* Calculate the DMIF Request Bandwidth */
457 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
458 fixed20_12 disp_clk, bandwidth;
461 a.full = dfixed_const(1000);
462 disp_clk.full = dfixed_const(wm->disp_clk);
463 disp_clk.full = dfixed_div(disp_clk, a);
464 a.full = dfixed_const(10);
465 disp_clk_request_efficiency.full = dfixed_const(8);
466 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
467 a.full = dfixed_const(32);
468 bandwidth.full = dfixed_mul(a, disp_clk);
469 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
471 return dfixed_trunc(bandwidth);
474 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
476 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
477 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
478 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
479 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
481 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
484 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
486 /* Calculate the display mode Average Bandwidth
487 * DisplayMode should contain the source and destination dimensions,
491 fixed20_12 line_time;
492 fixed20_12 src_width;
493 fixed20_12 bandwidth;
496 a.full = dfixed_const(1000);
497 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
498 line_time.full = dfixed_div(line_time, a);
499 bpp.full = dfixed_const(wm->bytes_per_pixel);
500 src_width.full = dfixed_const(wm->src_width);
501 bandwidth.full = dfixed_mul(src_width, bpp);
502 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
503 bandwidth.full = dfixed_div(bandwidth, line_time);
505 return dfixed_trunc(bandwidth);
508 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
510 /* First calcualte the latency in ns */
511 u32 mc_latency = 2000; /* 2000 ns. */
512 u32 available_bandwidth = evergreen_available_bandwidth(wm);
513 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
514 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
515 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
516 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
517 (wm->num_heads * cursor_line_pair_return_time);
518 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
519 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
522 if (wm->num_heads == 0)
525 a.full = dfixed_const(2);
526 b.full = dfixed_const(1);
527 if ((wm->vsc.full > a.full) ||
528 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
530 ((wm->vsc.full >= a.full) && wm->interlaced))
531 max_src_lines_per_dst_line = 4;
533 max_src_lines_per_dst_line = 2;
535 a.full = dfixed_const(available_bandwidth);
536 b.full = dfixed_const(wm->num_heads);
537 a.full = dfixed_div(a, b);
539 b.full = dfixed_const(1000);
540 c.full = dfixed_const(wm->disp_clk);
541 b.full = dfixed_div(c, b);
542 c.full = dfixed_const(wm->bytes_per_pixel);
543 b.full = dfixed_mul(b, c);
545 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
547 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
548 b.full = dfixed_const(1000);
549 c.full = dfixed_const(lb_fill_bw);
550 b.full = dfixed_div(c, b);
551 a.full = dfixed_div(a, b);
552 line_fill_time = dfixed_trunc(a);
554 if (line_fill_time < wm->active_time)
557 return latency + (line_fill_time - wm->active_time);
561 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
563 if (evergreen_average_bandwidth(wm) <=
564 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
570 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
572 if (evergreen_average_bandwidth(wm) <=
573 (evergreen_available_bandwidth(wm) / wm->num_heads))
579 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
581 u32 lb_partitions = wm->lb_size / wm->src_width;
582 u32 line_time = wm->active_time + wm->blank_time;
583 u32 latency_tolerant_lines;
587 a.full = dfixed_const(1);
588 if (wm->vsc.full > a.full)
589 latency_tolerant_lines = 1;
591 if (lb_partitions <= (wm->vtaps + 1))
592 latency_tolerant_lines = 1;
594 latency_tolerant_lines = 2;
597 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
599 if (evergreen_latency_watermark(wm) <= latency_hiding)
605 static void evergreen_program_watermarks(struct radeon_device *rdev,
606 struct radeon_crtc *radeon_crtc,
607 u32 lb_size, u32 num_heads)
609 struct drm_display_mode *mode = &radeon_crtc->base.mode;
610 struct evergreen_wm_params wm;
613 u32 latency_watermark_a = 0, latency_watermark_b = 0;
614 u32 priority_a_mark = 0, priority_b_mark = 0;
615 u32 priority_a_cnt = PRIORITY_OFF;
616 u32 priority_b_cnt = PRIORITY_OFF;
617 u32 pipe_offset = radeon_crtc->crtc_id * 16;
618 u32 tmp, arb_control3;
621 if (radeon_crtc->base.enabled && num_heads && mode) {
622 pixel_period = 1000000 / (u32)mode->clock;
623 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
627 wm.yclk = rdev->pm.current_mclk * 10;
628 wm.sclk = rdev->pm.current_sclk * 10;
629 wm.disp_clk = mode->clock;
630 wm.src_width = mode->crtc_hdisplay;
631 wm.active_time = mode->crtc_hdisplay * pixel_period;
632 wm.blank_time = line_time - wm.active_time;
633 wm.interlaced = false;
634 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
635 wm.interlaced = true;
636 wm.vsc = radeon_crtc->vsc;
638 if (radeon_crtc->rmx_type != RMX_OFF)
640 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
641 wm.lb_size = lb_size;
642 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
643 wm.num_heads = num_heads;
645 /* set for high clocks */
646 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
647 /* set for low clocks */
648 /* wm.yclk = low clk; wm.sclk = low clk */
649 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
651 /* possibly force display priority to high */
652 /* should really do this at mode validation time... */
653 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
654 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
655 !evergreen_check_latency_hiding(&wm) ||
656 (rdev->disp_priority == 2)) {
657 DRM_INFO("force priority to high\n");
658 priority_a_cnt |= PRIORITY_ALWAYS_ON;
659 priority_b_cnt |= PRIORITY_ALWAYS_ON;
662 a.full = dfixed_const(1000);
663 b.full = dfixed_const(mode->clock);
664 b.full = dfixed_div(b, a);
665 c.full = dfixed_const(latency_watermark_a);
666 c.full = dfixed_mul(c, b);
667 c.full = dfixed_mul(c, radeon_crtc->hsc);
668 c.full = dfixed_div(c, a);
669 a.full = dfixed_const(16);
670 c.full = dfixed_div(c, a);
671 priority_a_mark = dfixed_trunc(c);
672 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
674 a.full = dfixed_const(1000);
675 b.full = dfixed_const(mode->clock);
676 b.full = dfixed_div(b, a);
677 c.full = dfixed_const(latency_watermark_b);
678 c.full = dfixed_mul(c, b);
679 c.full = dfixed_mul(c, radeon_crtc->hsc);
680 c.full = dfixed_div(c, a);
681 a.full = dfixed_const(16);
682 c.full = dfixed_div(c, a);
683 priority_b_mark = dfixed_trunc(c);
684 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
688 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
690 tmp &= ~LATENCY_WATERMARK_MASK(3);
691 tmp |= LATENCY_WATERMARK_MASK(1);
692 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
693 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
694 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
695 LATENCY_HIGH_WATERMARK(line_time)));
697 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
698 tmp &= ~LATENCY_WATERMARK_MASK(3);
699 tmp |= LATENCY_WATERMARK_MASK(2);
700 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
701 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
702 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
703 LATENCY_HIGH_WATERMARK(line_time)));
704 /* restore original selection */
705 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
707 /* write the priority marks */
708 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
709 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
713 void evergreen_bandwidth_update(struct radeon_device *rdev)
715 struct drm_display_mode *mode0 = NULL;
716 struct drm_display_mode *mode1 = NULL;
717 u32 num_heads = 0, lb_size;
720 radeon_update_display_priority(rdev);
722 for (i = 0; i < rdev->num_crtc; i++) {
723 if (rdev->mode_info.crtcs[i]->base.enabled)
726 for (i = 0; i < rdev->num_crtc; i += 2) {
727 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
728 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
729 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
730 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
731 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
732 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
736 static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
741 for (i = 0; i < rdev->usec_timeout; i++) {
743 tmp = RREG32(SRBM_STATUS) & 0x1F00;
754 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
759 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
760 for (i = 0; i < rdev->usec_timeout; i++) {
762 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
763 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
765 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
775 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
780 if (rdev->gart.table.vram.robj == NULL) {
781 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
784 r = radeon_gart_table_vram_pin(rdev);
787 radeon_gart_restore(rdev);
789 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
790 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
791 EFFECTIVE_L2_QUEUE_SIZE(7));
792 WREG32(VM_L2_CNTL2, 0);
793 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
794 /* Setup TLB control */
795 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
796 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
797 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
798 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
799 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
800 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
801 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
802 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
803 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
804 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
805 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
806 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
807 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
808 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
809 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
810 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
811 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
812 (u32)(rdev->dummy_page.addr >> 12));
813 WREG32(VM_CONTEXT1_CNTL, 0);
815 evergreen_pcie_gart_tlb_flush(rdev);
816 rdev->gart.ready = true;
820 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
825 /* Disable all tables */
826 WREG32(VM_CONTEXT0_CNTL, 0);
827 WREG32(VM_CONTEXT1_CNTL, 0);
830 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
831 EFFECTIVE_L2_QUEUE_SIZE(7));
832 WREG32(VM_L2_CNTL2, 0);
833 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
834 /* Setup TLB control */
835 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
836 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
837 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
838 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
839 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
840 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
841 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
842 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
843 if (rdev->gart.table.vram.robj) {
844 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
845 if (likely(r == 0)) {
846 radeon_bo_kunmap(rdev->gart.table.vram.robj);
847 radeon_bo_unpin(rdev->gart.table.vram.robj);
848 radeon_bo_unreserve(rdev->gart.table.vram.robj);
853 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
855 evergreen_pcie_gart_disable(rdev);
856 radeon_gart_table_vram_free(rdev);
857 radeon_gart_fini(rdev);
861 void evergreen_agp_enable(struct radeon_device *rdev)
866 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
867 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
868 EFFECTIVE_L2_QUEUE_SIZE(7));
869 WREG32(VM_L2_CNTL2, 0);
870 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
871 /* Setup TLB control */
872 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
873 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
874 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
875 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
876 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
877 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
878 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
879 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
880 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
881 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
882 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
883 WREG32(VM_CONTEXT0_CNTL, 0);
884 WREG32(VM_CONTEXT1_CNTL, 0);
887 static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
889 save->vga_control[0] = RREG32(D1VGA_CONTROL);
890 save->vga_control[1] = RREG32(D2VGA_CONTROL);
891 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
892 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
893 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
894 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
895 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
896 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
897 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
898 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
899 if (!(rdev->flags & RADEON_IS_IGP)) {
900 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
901 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
902 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
903 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
907 WREG32(VGA_RENDER_CONTROL, 0);
908 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
909 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
910 if (!(rdev->flags & RADEON_IS_IGP)) {
911 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
912 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
913 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
914 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
916 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
917 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
918 if (!(rdev->flags & RADEON_IS_IGP)) {
919 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
920 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
921 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
922 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
924 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
925 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
926 if (!(rdev->flags & RADEON_IS_IGP)) {
927 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
928 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
929 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
930 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
933 WREG32(D1VGA_CONTROL, 0);
934 WREG32(D2VGA_CONTROL, 0);
935 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
936 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
937 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
938 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
941 static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
943 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
944 upper_32_bits(rdev->mc.vram_start));
945 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
946 upper_32_bits(rdev->mc.vram_start));
947 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
948 (u32)rdev->mc.vram_start);
949 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
950 (u32)rdev->mc.vram_start);
952 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
953 upper_32_bits(rdev->mc.vram_start));
954 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
955 upper_32_bits(rdev->mc.vram_start));
956 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
957 (u32)rdev->mc.vram_start);
958 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
959 (u32)rdev->mc.vram_start);
961 if (!(rdev->flags & RADEON_IS_IGP)) {
962 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
963 upper_32_bits(rdev->mc.vram_start));
964 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
965 upper_32_bits(rdev->mc.vram_start));
966 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
967 (u32)rdev->mc.vram_start);
968 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
969 (u32)rdev->mc.vram_start);
971 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
972 upper_32_bits(rdev->mc.vram_start));
973 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
974 upper_32_bits(rdev->mc.vram_start));
975 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
976 (u32)rdev->mc.vram_start);
977 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
978 (u32)rdev->mc.vram_start);
980 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
981 upper_32_bits(rdev->mc.vram_start));
982 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
983 upper_32_bits(rdev->mc.vram_start));
984 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
985 (u32)rdev->mc.vram_start);
986 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
987 (u32)rdev->mc.vram_start);
989 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
990 upper_32_bits(rdev->mc.vram_start));
991 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
992 upper_32_bits(rdev->mc.vram_start));
993 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
994 (u32)rdev->mc.vram_start);
995 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
996 (u32)rdev->mc.vram_start);
999 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1000 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1001 /* Unlock host access */
1002 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1004 /* Restore video state */
1005 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1006 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1007 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1008 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1009 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1010 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1011 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1012 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1013 if (!(rdev->flags & RADEON_IS_IGP)) {
1014 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1015 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1016 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1017 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1019 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1020 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1021 if (!(rdev->flags & RADEON_IS_IGP)) {
1022 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1023 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1024 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1025 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1027 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1028 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1029 if (!(rdev->flags & RADEON_IS_IGP)) {
1030 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1031 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1032 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1033 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1035 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1038 static void evergreen_mc_program(struct radeon_device *rdev)
1040 struct evergreen_mc_save save;
1044 /* Initialize HDP */
1045 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1046 WREG32((0x2c14 + j), 0x00000000);
1047 WREG32((0x2c18 + j), 0x00000000);
1048 WREG32((0x2c1c + j), 0x00000000);
1049 WREG32((0x2c20 + j), 0x00000000);
1050 WREG32((0x2c24 + j), 0x00000000);
1052 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1054 evergreen_mc_stop(rdev, &save);
1055 if (evergreen_mc_wait_for_idle(rdev)) {
1056 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1058 /* Lockout access through VGA aperture*/
1059 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1060 /* Update configuration */
1061 if (rdev->flags & RADEON_IS_AGP) {
1062 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1063 /* VRAM before AGP */
1064 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1065 rdev->mc.vram_start >> 12);
1066 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1067 rdev->mc.gtt_end >> 12);
1069 /* VRAM after AGP */
1070 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1071 rdev->mc.gtt_start >> 12);
1072 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1073 rdev->mc.vram_end >> 12);
1076 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1077 rdev->mc.vram_start >> 12);
1078 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1079 rdev->mc.vram_end >> 12);
1081 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1082 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1083 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1084 WREG32(MC_VM_FB_LOCATION, tmp);
1085 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1086 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1087 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1088 if (rdev->flags & RADEON_IS_AGP) {
1089 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1090 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1091 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1093 WREG32(MC_VM_AGP_BASE, 0);
1094 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1095 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1097 if (evergreen_mc_wait_for_idle(rdev)) {
1098 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1100 evergreen_mc_resume(rdev, &save);
1101 /* we need to own VRAM, so turn off the VGA renderer here
1102 * to stop it overwriting our objects */
1103 rv515_vga_render_disable(rdev);
1110 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1112 const __be32 *fw_data;
1115 if (!rdev->me_fw || !rdev->pfp_fw)
1119 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
1121 fw_data = (const __be32 *)rdev->pfp_fw->data;
1122 WREG32(CP_PFP_UCODE_ADDR, 0);
1123 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1124 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1125 WREG32(CP_PFP_UCODE_ADDR, 0);
1127 fw_data = (const __be32 *)rdev->me_fw->data;
1128 WREG32(CP_ME_RAM_WADDR, 0);
1129 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1130 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1132 WREG32(CP_PFP_UCODE_ADDR, 0);
1133 WREG32(CP_ME_RAM_WADDR, 0);
1134 WREG32(CP_ME_RAM_RADDR, 0);
1138 static int evergreen_cp_start(struct radeon_device *rdev)
1143 r = radeon_ring_lock(rdev, 7);
1145 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1148 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1149 radeon_ring_write(rdev, 0x1);
1150 radeon_ring_write(rdev, 0x0);
1151 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1152 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1153 radeon_ring_write(rdev, 0);
1154 radeon_ring_write(rdev, 0);
1155 radeon_ring_unlock_commit(rdev);
1158 WREG32(CP_ME_CNTL, cp_me);
1160 r = radeon_ring_lock(rdev, evergreen_default_size + 15);
1162 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1166 /* setup clear context state */
1167 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1168 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1170 for (i = 0; i < evergreen_default_size; i++)
1171 radeon_ring_write(rdev, evergreen_default_state[i]);
1173 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1174 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1176 /* set clear context state */
1177 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1178 radeon_ring_write(rdev, 0);
1180 /* SQ_VTX_BASE_VTX_LOC */
1181 radeon_ring_write(rdev, 0xc0026f00);
1182 radeon_ring_write(rdev, 0x00000000);
1183 radeon_ring_write(rdev, 0x00000000);
1184 radeon_ring_write(rdev, 0x00000000);
1187 radeon_ring_write(rdev, 0xc0036f00);
1188 radeon_ring_write(rdev, 0x00000bc4);
1189 radeon_ring_write(rdev, 0xffffffff);
1190 radeon_ring_write(rdev, 0xffffffff);
1191 radeon_ring_write(rdev, 0xffffffff);
1193 radeon_ring_unlock_commit(rdev);
1198 int evergreen_cp_resume(struct radeon_device *rdev)
1204 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1205 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1210 RREG32(GRBM_SOFT_RESET);
1212 WREG32(GRBM_SOFT_RESET, 0);
1213 RREG32(GRBM_SOFT_RESET);
1215 /* Set ring buffer size */
1216 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1217 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1219 tmp |= BUF_SWAP_32BIT;
1221 WREG32(CP_RB_CNTL, tmp);
1222 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1224 /* Set the write pointer delay */
1225 WREG32(CP_RB_WPTR_DELAY, 0);
1227 /* Initialize the ring buffer's read and write pointers */
1228 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1229 WREG32(CP_RB_RPTR_WR, 0);
1230 WREG32(CP_RB_WPTR, 0);
1232 /* set the wb address wether it's enabled or not */
1233 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1234 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1235 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1237 if (rdev->wb.enabled)
1238 WREG32(SCRATCH_UMSK, 0xff);
1240 tmp |= RB_NO_UPDATE;
1241 WREG32(SCRATCH_UMSK, 0);
1245 WREG32(CP_RB_CNTL, tmp);
1247 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1248 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1250 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1251 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1253 evergreen_cp_start(rdev);
1254 rdev->cp.ready = true;
1255 r = radeon_ring_test(rdev);
1257 rdev->cp.ready = false;
1266 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1269 u32 backend_disable_mask)
1271 u32 backend_map = 0;
1272 u32 enabled_backends_mask = 0;
1273 u32 enabled_backends_count = 0;
1275 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1276 u32 cur_backend = 0;
1278 bool force_no_swizzle;
1280 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1281 num_tile_pipes = EVERGREEN_MAX_PIPES;
1282 if (num_tile_pipes < 1)
1284 if (num_backends > EVERGREEN_MAX_BACKENDS)
1285 num_backends = EVERGREEN_MAX_BACKENDS;
1286 if (num_backends < 1)
1289 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1290 if (((backend_disable_mask >> i) & 1) == 0) {
1291 enabled_backends_mask |= (1 << i);
1292 ++enabled_backends_count;
1294 if (enabled_backends_count == num_backends)
1298 if (enabled_backends_count == 0) {
1299 enabled_backends_mask = 1;
1300 enabled_backends_count = 1;
1303 if (enabled_backends_count != num_backends)
1304 num_backends = enabled_backends_count;
1306 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1307 switch (rdev->family) {
1311 force_no_swizzle = false;
1317 force_no_swizzle = true;
1320 if (force_no_swizzle) {
1321 bool last_backend_enabled = false;
1323 force_no_swizzle = false;
1324 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1325 if (((enabled_backends_mask >> i) & 1) == 1) {
1326 if (last_backend_enabled)
1327 force_no_swizzle = true;
1328 last_backend_enabled = true;
1330 last_backend_enabled = false;
1334 switch (num_tile_pipes) {
1339 DRM_ERROR("odd number of pipes!\n");
1342 swizzle_pipe[0] = 0;
1343 swizzle_pipe[1] = 1;
1346 if (force_no_swizzle) {
1347 swizzle_pipe[0] = 0;
1348 swizzle_pipe[1] = 1;
1349 swizzle_pipe[2] = 2;
1350 swizzle_pipe[3] = 3;
1352 swizzle_pipe[0] = 0;
1353 swizzle_pipe[1] = 2;
1354 swizzle_pipe[2] = 1;
1355 swizzle_pipe[3] = 3;
1359 if (force_no_swizzle) {
1360 swizzle_pipe[0] = 0;
1361 swizzle_pipe[1] = 1;
1362 swizzle_pipe[2] = 2;
1363 swizzle_pipe[3] = 3;
1364 swizzle_pipe[4] = 4;
1365 swizzle_pipe[5] = 5;
1367 swizzle_pipe[0] = 0;
1368 swizzle_pipe[1] = 2;
1369 swizzle_pipe[2] = 4;
1370 swizzle_pipe[3] = 1;
1371 swizzle_pipe[4] = 3;
1372 swizzle_pipe[5] = 5;
1376 if (force_no_swizzle) {
1377 swizzle_pipe[0] = 0;
1378 swizzle_pipe[1] = 1;
1379 swizzle_pipe[2] = 2;
1380 swizzle_pipe[3] = 3;
1381 swizzle_pipe[4] = 4;
1382 swizzle_pipe[5] = 5;
1383 swizzle_pipe[6] = 6;
1384 swizzle_pipe[7] = 7;
1386 swizzle_pipe[0] = 0;
1387 swizzle_pipe[1] = 2;
1388 swizzle_pipe[2] = 4;
1389 swizzle_pipe[3] = 6;
1390 swizzle_pipe[4] = 1;
1391 swizzle_pipe[5] = 3;
1392 swizzle_pipe[6] = 5;
1393 swizzle_pipe[7] = 7;
1398 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1399 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1400 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1402 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1404 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1410 static void evergreen_program_channel_remap(struct radeon_device *rdev)
1412 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1414 tmp = RREG32(MC_SHARED_CHMAP);
1415 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1421 /* default mapping */
1422 mc_shared_chremap = 0x00fac688;
1426 switch (rdev->family) {
1429 tcp_chan_steer_lo = 0x54763210;
1430 tcp_chan_steer_hi = 0x0000ba98;
1437 tcp_chan_steer_lo = 0x76543210;
1438 tcp_chan_steer_hi = 0x0000ba98;
1442 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1443 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1444 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1447 static void evergreen_gpu_init(struct radeon_device *rdev)
1449 u32 cc_rb_backend_disable = 0;
1450 u32 cc_gc_shader_pipe_config;
1451 u32 gb_addr_config = 0;
1452 u32 mc_shared_chmap, mc_arb_ramcfg;
1458 u32 sq_lds_resource_mgmt;
1459 u32 sq_gpr_resource_mgmt_1;
1460 u32 sq_gpr_resource_mgmt_2;
1461 u32 sq_gpr_resource_mgmt_3;
1462 u32 sq_thread_resource_mgmt;
1463 u32 sq_thread_resource_mgmt_2;
1464 u32 sq_stack_resource_mgmt_1;
1465 u32 sq_stack_resource_mgmt_2;
1466 u32 sq_stack_resource_mgmt_3;
1467 u32 vgt_cache_invalidation;
1468 u32 hdp_host_path_cntl;
1469 int i, j, num_shader_engines, ps_thread_count;
1471 switch (rdev->family) {
1474 rdev->config.evergreen.num_ses = 2;
1475 rdev->config.evergreen.max_pipes = 4;
1476 rdev->config.evergreen.max_tile_pipes = 8;
1477 rdev->config.evergreen.max_simds = 10;
1478 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1479 rdev->config.evergreen.max_gprs = 256;
1480 rdev->config.evergreen.max_threads = 248;
1481 rdev->config.evergreen.max_gs_threads = 32;
1482 rdev->config.evergreen.max_stack_entries = 512;
1483 rdev->config.evergreen.sx_num_of_sets = 4;
1484 rdev->config.evergreen.sx_max_export_size = 256;
1485 rdev->config.evergreen.sx_max_export_pos_size = 64;
1486 rdev->config.evergreen.sx_max_export_smx_size = 192;
1487 rdev->config.evergreen.max_hw_contexts = 8;
1488 rdev->config.evergreen.sq_num_cf_insts = 2;
1490 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1491 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1492 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1495 rdev->config.evergreen.num_ses = 1;
1496 rdev->config.evergreen.max_pipes = 4;
1497 rdev->config.evergreen.max_tile_pipes = 4;
1498 rdev->config.evergreen.max_simds = 10;
1499 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1500 rdev->config.evergreen.max_gprs = 256;
1501 rdev->config.evergreen.max_threads = 248;
1502 rdev->config.evergreen.max_gs_threads = 32;
1503 rdev->config.evergreen.max_stack_entries = 512;
1504 rdev->config.evergreen.sx_num_of_sets = 4;
1505 rdev->config.evergreen.sx_max_export_size = 256;
1506 rdev->config.evergreen.sx_max_export_pos_size = 64;
1507 rdev->config.evergreen.sx_max_export_smx_size = 192;
1508 rdev->config.evergreen.max_hw_contexts = 8;
1509 rdev->config.evergreen.sq_num_cf_insts = 2;
1511 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1512 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1513 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1516 rdev->config.evergreen.num_ses = 1;
1517 rdev->config.evergreen.max_pipes = 4;
1518 rdev->config.evergreen.max_tile_pipes = 4;
1519 rdev->config.evergreen.max_simds = 5;
1520 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1521 rdev->config.evergreen.max_gprs = 256;
1522 rdev->config.evergreen.max_threads = 248;
1523 rdev->config.evergreen.max_gs_threads = 32;
1524 rdev->config.evergreen.max_stack_entries = 256;
1525 rdev->config.evergreen.sx_num_of_sets = 4;
1526 rdev->config.evergreen.sx_max_export_size = 256;
1527 rdev->config.evergreen.sx_max_export_pos_size = 64;
1528 rdev->config.evergreen.sx_max_export_smx_size = 192;
1529 rdev->config.evergreen.max_hw_contexts = 8;
1530 rdev->config.evergreen.sq_num_cf_insts = 2;
1532 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1533 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1534 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1538 rdev->config.evergreen.num_ses = 1;
1539 rdev->config.evergreen.max_pipes = 2;
1540 rdev->config.evergreen.max_tile_pipes = 2;
1541 rdev->config.evergreen.max_simds = 2;
1542 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1543 rdev->config.evergreen.max_gprs = 256;
1544 rdev->config.evergreen.max_threads = 192;
1545 rdev->config.evergreen.max_gs_threads = 16;
1546 rdev->config.evergreen.max_stack_entries = 256;
1547 rdev->config.evergreen.sx_num_of_sets = 4;
1548 rdev->config.evergreen.sx_max_export_size = 128;
1549 rdev->config.evergreen.sx_max_export_pos_size = 32;
1550 rdev->config.evergreen.sx_max_export_smx_size = 96;
1551 rdev->config.evergreen.max_hw_contexts = 4;
1552 rdev->config.evergreen.sq_num_cf_insts = 1;
1554 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1555 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1556 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1559 rdev->config.evergreen.num_ses = 1;
1560 rdev->config.evergreen.max_pipes = 2;
1561 rdev->config.evergreen.max_tile_pipes = 2;
1562 rdev->config.evergreen.max_simds = 2;
1563 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1564 rdev->config.evergreen.max_gprs = 256;
1565 rdev->config.evergreen.max_threads = 192;
1566 rdev->config.evergreen.max_gs_threads = 16;
1567 rdev->config.evergreen.max_stack_entries = 256;
1568 rdev->config.evergreen.sx_num_of_sets = 4;
1569 rdev->config.evergreen.sx_max_export_size = 128;
1570 rdev->config.evergreen.sx_max_export_pos_size = 32;
1571 rdev->config.evergreen.sx_max_export_smx_size = 96;
1572 rdev->config.evergreen.max_hw_contexts = 4;
1573 rdev->config.evergreen.sq_num_cf_insts = 1;
1575 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1576 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1577 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1581 /* Initialize HDP */
1582 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1583 WREG32((0x2c14 + j), 0x00000000);
1584 WREG32((0x2c18 + j), 0x00000000);
1585 WREG32((0x2c1c + j), 0x00000000);
1586 WREG32((0x2c20 + j), 0x00000000);
1587 WREG32((0x2c24 + j), 0x00000000);
1590 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1592 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1594 cc_gc_shader_pipe_config |=
1595 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1596 & EVERGREEN_MAX_PIPES_MASK);
1597 cc_gc_shader_pipe_config |=
1598 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1599 & EVERGREEN_MAX_SIMDS_MASK);
1601 cc_rb_backend_disable =
1602 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1603 & EVERGREEN_MAX_BACKENDS_MASK);
1606 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1607 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1609 switch (rdev->config.evergreen.max_tile_pipes) {
1612 gb_addr_config |= NUM_PIPES(0);
1615 gb_addr_config |= NUM_PIPES(1);
1618 gb_addr_config |= NUM_PIPES(2);
1621 gb_addr_config |= NUM_PIPES(3);
1625 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1626 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1627 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1628 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1629 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1630 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1632 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1633 gb_addr_config |= ROW_SIZE(2);
1635 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1637 if (rdev->ddev->pdev->device == 0x689e) {
1640 u8 efuse_box_bit_131_124;
1642 WREG32(RCU_IND_INDEX, 0x204);
1643 efuse_straps_4 = RREG32(RCU_IND_DATA);
1644 WREG32(RCU_IND_INDEX, 0x203);
1645 efuse_straps_3 = RREG32(RCU_IND_DATA);
1646 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1648 switch(efuse_box_bit_131_124) {
1650 gb_backend_map = 0x76543210;
1653 gb_backend_map = 0x77553311;
1656 gb_backend_map = 0x77553300;
1659 gb_backend_map = 0x77552211;
1662 gb_backend_map = 0x77443300;
1665 gb_backend_map = 0x66552211;
1668 gb_backend_map = 0x77552200;
1671 gb_backend_map = 0x66442200;
1674 gb_backend_map = 0x66553311;
1677 DRM_ERROR("bad backend map, using default\n");
1679 evergreen_get_tile_pipe_to_backend_map(rdev,
1680 rdev->config.evergreen.max_tile_pipes,
1681 rdev->config.evergreen.max_backends,
1682 ((EVERGREEN_MAX_BACKENDS_MASK <<
1683 rdev->config.evergreen.max_backends) &
1684 EVERGREEN_MAX_BACKENDS_MASK));
1687 } else if (rdev->ddev->pdev->device == 0x68b9) {
1689 u8 efuse_box_bit_127_124;
1691 WREG32(RCU_IND_INDEX, 0x203);
1692 efuse_straps_3 = RREG32(RCU_IND_DATA);
1693 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1695 switch(efuse_box_bit_127_124) {
1697 gb_backend_map = 0x00003210;
1703 gb_backend_map = 0x00003311;
1706 DRM_ERROR("bad backend map, using default\n");
1708 evergreen_get_tile_pipe_to_backend_map(rdev,
1709 rdev->config.evergreen.max_tile_pipes,
1710 rdev->config.evergreen.max_backends,
1711 ((EVERGREEN_MAX_BACKENDS_MASK <<
1712 rdev->config.evergreen.max_backends) &
1713 EVERGREEN_MAX_BACKENDS_MASK));
1717 switch (rdev->family) {
1720 gb_backend_map = 0x66442200;
1723 gb_backend_map = 0x00006420;
1727 evergreen_get_tile_pipe_to_backend_map(rdev,
1728 rdev->config.evergreen.max_tile_pipes,
1729 rdev->config.evergreen.max_backends,
1730 ((EVERGREEN_MAX_BACKENDS_MASK <<
1731 rdev->config.evergreen.max_backends) &
1732 EVERGREEN_MAX_BACKENDS_MASK));
1736 /* setup tiling info dword. gb_addr_config is not adequate since it does
1737 * not have bank info, so create a custom tiling dword.
1738 * bits 3:0 num_pipes
1739 * bits 7:4 num_banks
1740 * bits 11:8 group_size
1741 * bits 15:12 row_size
1743 rdev->config.evergreen.tile_config = 0;
1744 switch (rdev->config.evergreen.max_tile_pipes) {
1747 rdev->config.evergreen.tile_config |= (0 << 0);
1750 rdev->config.evergreen.tile_config |= (1 << 0);
1753 rdev->config.evergreen.tile_config |= (2 << 0);
1756 rdev->config.evergreen.tile_config |= (3 << 0);
1759 rdev->config.evergreen.tile_config |=
1760 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1761 rdev->config.evergreen.tile_config |=
1762 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1763 rdev->config.evergreen.tile_config |=
1764 ((gb_addr_config & 0x30000000) >> 28) << 12;
1766 WREG32(GB_BACKEND_MAP, gb_backend_map);
1767 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1768 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1769 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1771 evergreen_program_channel_remap(rdev);
1773 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1774 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1776 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1777 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1778 u32 sp = cc_gc_shader_pipe_config;
1779 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1781 if (i == num_shader_engines) {
1782 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1783 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1786 WREG32(GRBM_GFX_INDEX, gfx);
1787 WREG32(RLC_GFX_INDEX, gfx);
1789 WREG32(CC_RB_BACKEND_DISABLE, rb);
1790 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1791 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1792 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1795 grbm_gfx_index |= SE_BROADCAST_WRITES;
1796 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1797 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1799 WREG32(CGTS_SYS_TCC_DISABLE, 0);
1800 WREG32(CGTS_TCC_DISABLE, 0);
1801 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1802 WREG32(CGTS_USER_TCC_DISABLE, 0);
1804 /* set HW defaults for 3D engine */
1805 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1806 ROQ_IB2_START(0x2b)));
1808 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1810 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1815 sx_debug_1 = RREG32(SX_DEBUG_1);
1816 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1817 WREG32(SX_DEBUG_1, sx_debug_1);
1820 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1821 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1822 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1823 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1825 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1826 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1827 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1829 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1830 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1831 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1833 WREG32(VGT_NUM_INSTANCES, 1);
1834 WREG32(SPI_CONFIG_CNTL, 0);
1835 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1836 WREG32(CP_PERFMON_CNTL, 0);
1838 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1839 FETCH_FIFO_HIWATER(0x4) |
1840 DONE_FIFO_HIWATER(0xe0) |
1841 ALU_UPDATE_FIFO_HIWATER(0x8)));
1843 sq_config = RREG32(SQ_CONFIG);
1844 sq_config &= ~(PS_PRIO(3) |
1848 sq_config |= (VC_ENABLE |
1855 switch (rdev->family) {
1858 /* no vertex cache */
1859 sq_config &= ~VC_ENABLE;
1865 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1867 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1868 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1869 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1870 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1871 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1872 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1873 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1875 switch (rdev->family) {
1878 ps_thread_count = 96;
1881 ps_thread_count = 128;
1885 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1886 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1887 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1888 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1889 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1890 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1892 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1893 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1894 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1895 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1896 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1897 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1899 WREG32(SQ_CONFIG, sq_config);
1900 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1901 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1902 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1903 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1904 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1905 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1906 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1907 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1908 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1909 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1911 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1912 FORCE_EOV_MAX_REZ_CNT(255)));
1914 switch (rdev->family) {
1917 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1920 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1923 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1924 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1926 WREG32(VGT_GS_VERTEX_REUSE, 16);
1927 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1929 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
1930 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
1932 WREG32(CB_PERF_CTR0_SEL_0, 0);
1933 WREG32(CB_PERF_CTR0_SEL_1, 0);
1934 WREG32(CB_PERF_CTR1_SEL_0, 0);
1935 WREG32(CB_PERF_CTR1_SEL_1, 0);
1936 WREG32(CB_PERF_CTR2_SEL_0, 0);
1937 WREG32(CB_PERF_CTR2_SEL_1, 0);
1938 WREG32(CB_PERF_CTR3_SEL_0, 0);
1939 WREG32(CB_PERF_CTR3_SEL_1, 0);
1941 /* clear render buffer base addresses */
1942 WREG32(CB_COLOR0_BASE, 0);
1943 WREG32(CB_COLOR1_BASE, 0);
1944 WREG32(CB_COLOR2_BASE, 0);
1945 WREG32(CB_COLOR3_BASE, 0);
1946 WREG32(CB_COLOR4_BASE, 0);
1947 WREG32(CB_COLOR5_BASE, 0);
1948 WREG32(CB_COLOR6_BASE, 0);
1949 WREG32(CB_COLOR7_BASE, 0);
1950 WREG32(CB_COLOR8_BASE, 0);
1951 WREG32(CB_COLOR9_BASE, 0);
1952 WREG32(CB_COLOR10_BASE, 0);
1953 WREG32(CB_COLOR11_BASE, 0);
1955 /* set the shader const cache sizes to 0 */
1956 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
1958 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
1961 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1962 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1964 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1970 int evergreen_mc_init(struct radeon_device *rdev)
1973 int chansize, numchan;
1975 /* Get VRAM informations */
1976 rdev->mc.vram_is_ddr = true;
1977 tmp = RREG32(MC_ARB_RAMCFG);
1978 if (tmp & CHANSIZE_OVERRIDE) {
1980 } else if (tmp & CHANSIZE_MASK) {
1985 tmp = RREG32(MC_SHARED_CHMAP);
1986 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2001 rdev->mc.vram_width = numchan * chansize;
2002 /* Could aper size report 0 ? */
2003 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2004 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2005 /* Setup GPU memory space */
2006 if (rdev->flags & RADEON_IS_IGP) {
2007 /* size in bytes on fusion */
2008 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2009 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2011 /* size in MB on evergreen */
2012 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2013 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2015 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2016 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2017 r700_vram_gtt_location(rdev, &rdev->mc);
2018 radeon_update_bandwidth_info(rdev);
2023 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2025 /* FIXME: implement for evergreen */
2029 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2031 struct evergreen_mc_save save;
2035 dev_info(rdev->dev, "GPU softreset \n");
2036 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2037 RREG32(GRBM_STATUS));
2038 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2039 RREG32(GRBM_STATUS_SE0));
2040 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2041 RREG32(GRBM_STATUS_SE1));
2042 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2043 RREG32(SRBM_STATUS));
2044 evergreen_mc_stop(rdev, &save);
2045 if (evergreen_mc_wait_for_idle(rdev)) {
2046 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2048 /* Disable CP parsing/prefetching */
2049 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2051 /* reset all the gfx blocks */
2052 grbm_reset = (SOFT_RESET_CP |
2065 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2066 WREG32(GRBM_SOFT_RESET, grbm_reset);
2067 (void)RREG32(GRBM_SOFT_RESET);
2069 WREG32(GRBM_SOFT_RESET, 0);
2070 (void)RREG32(GRBM_SOFT_RESET);
2072 /* reset all the system blocks */
2073 srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
2075 dev_info(rdev->dev, " SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
2076 WREG32(SRBM_SOFT_RESET, srbm_reset);
2077 (void)RREG32(SRBM_SOFT_RESET);
2079 WREG32(SRBM_SOFT_RESET, 0);
2080 (void)RREG32(SRBM_SOFT_RESET);
2081 /* Wait a little for things to settle down */
2083 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2084 RREG32(GRBM_STATUS));
2085 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2086 RREG32(GRBM_STATUS_SE0));
2087 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2088 RREG32(GRBM_STATUS_SE1));
2089 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2090 RREG32(SRBM_STATUS));
2091 /* After reset we need to reinit the asic as GPU often endup in an
2094 atom_asic_init(rdev->mode_info.atom_context);
2095 evergreen_mc_resume(rdev, &save);
2099 int evergreen_asic_reset(struct radeon_device *rdev)
2101 return evergreen_gpu_soft_reset(rdev);
2106 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2110 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2112 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2114 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2116 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2118 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2120 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2126 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2130 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2131 WREG32(GRBM_INT_CNTL, 0);
2132 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2133 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2134 if (!(rdev->flags & RADEON_IS_IGP)) {
2135 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2136 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2137 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2138 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2141 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2142 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2143 if (!(rdev->flags & RADEON_IS_IGP)) {
2144 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2145 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2146 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2147 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2150 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2151 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2153 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2154 WREG32(DC_HPD1_INT_CONTROL, tmp);
2155 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2156 WREG32(DC_HPD2_INT_CONTROL, tmp);
2157 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2158 WREG32(DC_HPD3_INT_CONTROL, tmp);
2159 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2160 WREG32(DC_HPD4_INT_CONTROL, tmp);
2161 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2162 WREG32(DC_HPD5_INT_CONTROL, tmp);
2163 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2164 WREG32(DC_HPD6_INT_CONTROL, tmp);
2168 int evergreen_irq_set(struct radeon_device *rdev)
2170 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2171 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2172 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2173 u32 grbm_int_cntl = 0;
2175 if (!rdev->irq.installed) {
2176 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2179 /* don't enable anything if the ih is disabled */
2180 if (!rdev->ih.enabled) {
2181 r600_disable_interrupts(rdev);
2182 /* force the active interrupt state to all disabled */
2183 evergreen_disable_interrupt_state(rdev);
2187 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2188 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2189 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2190 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2191 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2192 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2194 if (rdev->irq.sw_int) {
2195 DRM_DEBUG("evergreen_irq_set: sw int\n");
2196 cp_int_cntl |= RB_INT_ENABLE;
2197 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2199 if (rdev->irq.crtc_vblank_int[0]) {
2200 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2201 crtc1 |= VBLANK_INT_MASK;
2203 if (rdev->irq.crtc_vblank_int[1]) {
2204 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2205 crtc2 |= VBLANK_INT_MASK;
2207 if (rdev->irq.crtc_vblank_int[2]) {
2208 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2209 crtc3 |= VBLANK_INT_MASK;
2211 if (rdev->irq.crtc_vblank_int[3]) {
2212 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2213 crtc4 |= VBLANK_INT_MASK;
2215 if (rdev->irq.crtc_vblank_int[4]) {
2216 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2217 crtc5 |= VBLANK_INT_MASK;
2219 if (rdev->irq.crtc_vblank_int[5]) {
2220 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2221 crtc6 |= VBLANK_INT_MASK;
2223 if (rdev->irq.hpd[0]) {
2224 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2225 hpd1 |= DC_HPDx_INT_EN;
2227 if (rdev->irq.hpd[1]) {
2228 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2229 hpd2 |= DC_HPDx_INT_EN;
2231 if (rdev->irq.hpd[2]) {
2232 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2233 hpd3 |= DC_HPDx_INT_EN;
2235 if (rdev->irq.hpd[3]) {
2236 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2237 hpd4 |= DC_HPDx_INT_EN;
2239 if (rdev->irq.hpd[4]) {
2240 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2241 hpd5 |= DC_HPDx_INT_EN;
2243 if (rdev->irq.hpd[5]) {
2244 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2245 hpd6 |= DC_HPDx_INT_EN;
2247 if (rdev->irq.gui_idle) {
2248 DRM_DEBUG("gui idle\n");
2249 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2252 WREG32(CP_INT_CNTL, cp_int_cntl);
2253 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2255 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2256 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2257 if (!(rdev->flags & RADEON_IS_IGP)) {
2258 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2259 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2260 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2261 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2264 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2265 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2266 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2267 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2268 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2269 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2274 static inline void evergreen_irq_ack(struct radeon_device *rdev,
2277 u32 *disp_int_cont2,
2278 u32 *disp_int_cont3,
2279 u32 *disp_int_cont4,
2280 u32 *disp_int_cont5)
2284 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2285 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2286 *disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2287 *disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2288 *disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2289 *disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2291 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2292 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2293 if (*disp_int & LB_D1_VLINE_INTERRUPT)
2294 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2296 if (*disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2297 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2298 if (*disp_int_cont & LB_D2_VLINE_INTERRUPT)
2299 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2301 if (*disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2302 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2303 if (*disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2304 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2306 if (*disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2307 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2308 if (*disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2309 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2311 if (*disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2312 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2313 if (*disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2314 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2316 if (*disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2317 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2318 if (*disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2319 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2321 if (*disp_int & DC_HPD1_INTERRUPT) {
2322 tmp = RREG32(DC_HPD1_INT_CONTROL);
2323 tmp |= DC_HPDx_INT_ACK;
2324 WREG32(DC_HPD1_INT_CONTROL, tmp);
2326 if (*disp_int_cont & DC_HPD2_INTERRUPT) {
2327 tmp = RREG32(DC_HPD2_INT_CONTROL);
2328 tmp |= DC_HPDx_INT_ACK;
2329 WREG32(DC_HPD2_INT_CONTROL, tmp);
2331 if (*disp_int_cont2 & DC_HPD3_INTERRUPT) {
2332 tmp = RREG32(DC_HPD3_INT_CONTROL);
2333 tmp |= DC_HPDx_INT_ACK;
2334 WREG32(DC_HPD3_INT_CONTROL, tmp);
2336 if (*disp_int_cont3 & DC_HPD4_INTERRUPT) {
2337 tmp = RREG32(DC_HPD4_INT_CONTROL);
2338 tmp |= DC_HPDx_INT_ACK;
2339 WREG32(DC_HPD4_INT_CONTROL, tmp);
2341 if (*disp_int_cont4 & DC_HPD5_INTERRUPT) {
2342 tmp = RREG32(DC_HPD5_INT_CONTROL);
2343 tmp |= DC_HPDx_INT_ACK;
2344 WREG32(DC_HPD5_INT_CONTROL, tmp);
2346 if (*disp_int_cont5 & DC_HPD6_INTERRUPT) {
2347 tmp = RREG32(DC_HPD5_INT_CONTROL);
2348 tmp |= DC_HPDx_INT_ACK;
2349 WREG32(DC_HPD6_INT_CONTROL, tmp);
2353 void evergreen_irq_disable(struct radeon_device *rdev)
2355 u32 disp_int, disp_int_cont, disp_int_cont2;
2356 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
2358 r600_disable_interrupts(rdev);
2359 /* Wait and acknowledge irq */
2361 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
2362 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
2363 evergreen_disable_interrupt_state(rdev);
2366 static void evergreen_irq_suspend(struct radeon_device *rdev)
2368 evergreen_irq_disable(rdev);
2369 r600_rlc_stop(rdev);
2372 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2376 if (rdev->wb.enabled)
2377 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2379 wptr = RREG32(IH_RB_WPTR);
2381 if (wptr & RB_OVERFLOW) {
2382 /* When a ring buffer overflow happen start parsing interrupt
2383 * from the last not overwritten vector (wptr + 16). Hopefully
2384 * this should allow us to catchup.
2386 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2387 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2388 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2389 tmp = RREG32(IH_RB_CNTL);
2390 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2391 WREG32(IH_RB_CNTL, tmp);
2393 return (wptr & rdev->ih.ptr_mask);
2396 int evergreen_irq_process(struct radeon_device *rdev)
2398 u32 wptr = evergreen_get_ih_wptr(rdev);
2399 u32 rptr = rdev->ih.rptr;
2400 u32 src_id, src_data;
2402 u32 disp_int, disp_int_cont, disp_int_cont2;
2403 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
2404 unsigned long flags;
2405 bool queue_hotplug = false;
2407 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2408 if (!rdev->ih.enabled)
2411 spin_lock_irqsave(&rdev->ih.lock, flags);
2414 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2417 if (rdev->shutdown) {
2418 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2423 /* display interrupts */
2424 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
2425 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
2427 rdev->ih.wptr = wptr;
2428 while (rptr != wptr) {
2429 /* wptr/rptr are in bytes! */
2430 ring_index = rptr / 4;
2431 src_id = rdev->ih.ring[ring_index] & 0xff;
2432 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2435 case 1: /* D1 vblank/vline */
2437 case 0: /* D1 vblank */
2438 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2439 drm_handle_vblank(rdev->ddev, 0);
2440 rdev->pm.vblank_sync = true;
2441 wake_up(&rdev->irq.vblank_queue);
2442 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2443 DRM_DEBUG("IH: D1 vblank\n");
2446 case 1: /* D1 vline */
2447 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2448 disp_int &= ~LB_D1_VLINE_INTERRUPT;
2449 DRM_DEBUG("IH: D1 vline\n");
2453 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2457 case 2: /* D2 vblank/vline */
2459 case 0: /* D2 vblank */
2460 if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2461 drm_handle_vblank(rdev->ddev, 1);
2462 rdev->pm.vblank_sync = true;
2463 wake_up(&rdev->irq.vblank_queue);
2464 disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2465 DRM_DEBUG("IH: D2 vblank\n");
2468 case 1: /* D2 vline */
2469 if (disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2470 disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2471 DRM_DEBUG("IH: D2 vline\n");
2475 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2479 case 3: /* D3 vblank/vline */
2481 case 0: /* D3 vblank */
2482 if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2483 drm_handle_vblank(rdev->ddev, 2);
2484 rdev->pm.vblank_sync = true;
2485 wake_up(&rdev->irq.vblank_queue);
2486 disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2487 DRM_DEBUG("IH: D3 vblank\n");
2490 case 1: /* D3 vline */
2491 if (disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2492 disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2493 DRM_DEBUG("IH: D3 vline\n");
2497 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2501 case 4: /* D4 vblank/vline */
2503 case 0: /* D4 vblank */
2504 if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2505 drm_handle_vblank(rdev->ddev, 3);
2506 rdev->pm.vblank_sync = true;
2507 wake_up(&rdev->irq.vblank_queue);
2508 disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2509 DRM_DEBUG("IH: D4 vblank\n");
2512 case 1: /* D4 vline */
2513 if (disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2514 disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2515 DRM_DEBUG("IH: D4 vline\n");
2519 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2523 case 5: /* D5 vblank/vline */
2525 case 0: /* D5 vblank */
2526 if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2527 drm_handle_vblank(rdev->ddev, 4);
2528 rdev->pm.vblank_sync = true;
2529 wake_up(&rdev->irq.vblank_queue);
2530 disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2531 DRM_DEBUG("IH: D5 vblank\n");
2534 case 1: /* D5 vline */
2535 if (disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2536 disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2537 DRM_DEBUG("IH: D5 vline\n");
2541 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2545 case 6: /* D6 vblank/vline */
2547 case 0: /* D6 vblank */
2548 if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2549 drm_handle_vblank(rdev->ddev, 5);
2550 rdev->pm.vblank_sync = true;
2551 wake_up(&rdev->irq.vblank_queue);
2552 disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2553 DRM_DEBUG("IH: D6 vblank\n");
2556 case 1: /* D6 vline */
2557 if (disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2558 disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2559 DRM_DEBUG("IH: D6 vline\n");
2563 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2567 case 42: /* HPD hotplug */
2570 if (disp_int & DC_HPD1_INTERRUPT) {
2571 disp_int &= ~DC_HPD1_INTERRUPT;
2572 queue_hotplug = true;
2573 DRM_DEBUG("IH: HPD1\n");
2577 if (disp_int_cont & DC_HPD2_INTERRUPT) {
2578 disp_int_cont &= ~DC_HPD2_INTERRUPT;
2579 queue_hotplug = true;
2580 DRM_DEBUG("IH: HPD2\n");
2584 if (disp_int_cont2 & DC_HPD3_INTERRUPT) {
2585 disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2586 queue_hotplug = true;
2587 DRM_DEBUG("IH: HPD3\n");
2591 if (disp_int_cont3 & DC_HPD4_INTERRUPT) {
2592 disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2593 queue_hotplug = true;
2594 DRM_DEBUG("IH: HPD4\n");
2598 if (disp_int_cont4 & DC_HPD5_INTERRUPT) {
2599 disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2600 queue_hotplug = true;
2601 DRM_DEBUG("IH: HPD5\n");
2605 if (disp_int_cont5 & DC_HPD6_INTERRUPT) {
2606 disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2607 queue_hotplug = true;
2608 DRM_DEBUG("IH: HPD6\n");
2612 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2616 case 176: /* CP_INT in ring buffer */
2617 case 177: /* CP_INT in IB1 */
2618 case 178: /* CP_INT in IB2 */
2619 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2620 radeon_fence_process(rdev);
2622 case 181: /* CP EOP event */
2623 DRM_DEBUG("IH: CP EOP\n");
2624 radeon_fence_process(rdev);
2626 case 233: /* GUI IDLE */
2627 DRM_DEBUG("IH: CP EOP\n");
2628 rdev->pm.gui_idle = true;
2629 wake_up(&rdev->irq.idle_queue);
2632 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2636 /* wptr/rptr are in bytes! */
2638 rptr &= rdev->ih.ptr_mask;
2640 /* make sure wptr hasn't changed while processing */
2641 wptr = evergreen_get_ih_wptr(rdev);
2642 if (wptr != rdev->ih.wptr)
2645 queue_work(rdev->wq, &rdev->hotplug_work);
2646 rdev->ih.rptr = rptr;
2647 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2648 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2652 static int evergreen_startup(struct radeon_device *rdev)
2656 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2657 r = r600_init_microcode(rdev);
2659 DRM_ERROR("Failed to load firmware!\n");
2664 evergreen_mc_program(rdev);
2665 if (rdev->flags & RADEON_IS_AGP) {
2666 evergreen_agp_enable(rdev);
2668 r = evergreen_pcie_gart_enable(rdev);
2672 evergreen_gpu_init(rdev);
2674 r = evergreen_blit_init(rdev);
2676 evergreen_blit_fini(rdev);
2677 rdev->asic->copy = NULL;
2678 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2681 /* allocate wb buffer */
2682 r = radeon_wb_init(rdev);
2687 r = r600_irq_init(rdev);
2689 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2690 radeon_irq_kms_fini(rdev);
2693 evergreen_irq_set(rdev);
2695 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2698 r = evergreen_cp_load_microcode(rdev);
2701 r = evergreen_cp_resume(rdev);
2708 int evergreen_resume(struct radeon_device *rdev)
2712 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2713 * posting will perform necessary task to bring back GPU into good
2717 atom_asic_init(rdev->mode_info.atom_context);
2719 r = evergreen_startup(rdev);
2721 DRM_ERROR("r600 startup failed on resume\n");
2725 r = r600_ib_test(rdev);
2727 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2735 int evergreen_suspend(struct radeon_device *rdev)
2739 /* FIXME: we should wait for ring to be empty */
2741 rdev->cp.ready = false;
2742 evergreen_irq_suspend(rdev);
2743 radeon_wb_disable(rdev);
2744 evergreen_pcie_gart_disable(rdev);
2746 /* unpin shaders bo */
2747 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2748 if (likely(r == 0)) {
2749 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2750 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2756 int evergreen_copy_blit(struct radeon_device *rdev,
2757 uint64_t src_offset, uint64_t dst_offset,
2758 unsigned num_pages, struct radeon_fence *fence)
2762 mutex_lock(&rdev->r600_blit.mutex);
2763 rdev->r600_blit.vb_ib = NULL;
2764 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2766 if (rdev->r600_blit.vb_ib)
2767 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2768 mutex_unlock(&rdev->r600_blit.mutex);
2771 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2772 evergreen_blit_done_copy(rdev, fence);
2773 mutex_unlock(&rdev->r600_blit.mutex);
2777 static bool evergreen_card_posted(struct radeon_device *rdev)
2781 /* first check CRTCs */
2782 if (rdev->flags & RADEON_IS_IGP)
2783 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2784 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2786 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2787 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2788 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2789 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2790 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2791 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2792 if (reg & EVERGREEN_CRTC_MASTER_EN)
2795 /* then check MEM_SIZE, in case the crtcs are off */
2796 if (RREG32(CONFIG_MEMSIZE))
2802 /* Plan is to move initialization in that function and use
2803 * helper function so that radeon_device_init pretty much
2804 * do nothing more than calling asic specific function. This
2805 * should also allow to remove a bunch of callback function
2808 int evergreen_init(struct radeon_device *rdev)
2812 r = radeon_dummy_page_init(rdev);
2815 /* This don't do much */
2816 r = radeon_gem_init(rdev);
2820 if (!radeon_get_bios(rdev)) {
2821 if (ASIC_IS_AVIVO(rdev))
2824 /* Must be an ATOMBIOS */
2825 if (!rdev->is_atom_bios) {
2826 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2829 r = radeon_atombios_init(rdev);
2832 /* Post card if necessary */
2833 if (!evergreen_card_posted(rdev)) {
2835 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2838 DRM_INFO("GPU not posted. posting now...\n");
2839 atom_asic_init(rdev->mode_info.atom_context);
2841 /* Initialize scratch registers */
2842 r600_scratch_init(rdev);
2843 /* Initialize surface registers */
2844 radeon_surface_init(rdev);
2845 /* Initialize clocks */
2846 radeon_get_clock_info(rdev->ddev);
2848 r = radeon_fence_driver_init(rdev);
2851 /* initialize AGP */
2852 if (rdev->flags & RADEON_IS_AGP) {
2853 r = radeon_agp_init(rdev);
2855 radeon_agp_disable(rdev);
2857 /* initialize memory controller */
2858 r = evergreen_mc_init(rdev);
2861 /* Memory manager */
2862 r = radeon_bo_init(rdev);
2866 r = radeon_irq_kms_init(rdev);
2870 rdev->cp.ring_obj = NULL;
2871 r600_ring_init(rdev, 1024 * 1024);
2873 rdev->ih.ring_obj = NULL;
2874 r600_ih_ring_init(rdev, 64 * 1024);
2876 r = r600_pcie_gart_init(rdev);
2880 rdev->accel_working = true;
2881 r = evergreen_startup(rdev);
2883 dev_err(rdev->dev, "disabling GPU acceleration\n");
2885 r600_irq_fini(rdev);
2886 radeon_wb_fini(rdev);
2887 radeon_irq_kms_fini(rdev);
2888 evergreen_pcie_gart_fini(rdev);
2889 rdev->accel_working = false;
2891 if (rdev->accel_working) {
2892 r = radeon_ib_pool_init(rdev);
2894 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
2895 rdev->accel_working = false;
2897 r = r600_ib_test(rdev);
2899 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2900 rdev->accel_working = false;
2906 void evergreen_fini(struct radeon_device *rdev)
2908 evergreen_blit_fini(rdev);
2910 r600_irq_fini(rdev);
2911 radeon_wb_fini(rdev);
2912 radeon_irq_kms_fini(rdev);
2913 evergreen_pcie_gart_fini(rdev);
2914 radeon_gem_fini(rdev);
2915 radeon_fence_driver_fini(rdev);
2916 radeon_agp_fini(rdev);
2917 radeon_bo_fini(rdev);
2918 radeon_atombios_fini(rdev);
2921 radeon_dummy_page_fini(rdev);