drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <drm/drmP.h>
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include <drm/radeon_drm.h>
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static const u32 crtc_offsets[6] =
  41 {
  42         EVERGREEN_CRTC0_REGISTER_OFFSET,
  43         EVERGREEN_CRTC1_REGISTER_OFFSET,
  44         EVERGREEN_CRTC2_REGISTER_OFFSET,
  45         EVERGREEN_CRTC3_REGISTER_OFFSET,
  46         EVERGREEN_CRTC4_REGISTER_OFFSET,
  47         EVERGREEN_CRTC5_REGISTER_OFFSET
  48 };
  49
  50 static void evergreen_gpu_init(struct radeon_device *rdev);
  51 void evergreen_fini(struct radeon_device *rdev);
  52 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  53 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
  54                                      int ring, u32 cp_int_cntl);
  55
  56 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
  57                              unsigned *bankh, unsigned *mtaspect,
  58                              unsigned *tile_split)
  59 {
  60         *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
  61         *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
  62         *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
  63         *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
  64         switch (*bankw) {
  65         default:
  66         case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
  67         case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
  68         case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
  69         case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
  70         }
  71         switch (*bankh) {
  72         default:
  73         case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
  74         case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
  75         case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
  76         case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
  77         }
  78         switch (*mtaspect) {
  79         default:
  80         case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
  81         case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
  82         case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
  83         case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
  84         }
  85 }
  86
  87 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
  88 {
  89         u16 ctl, v;
  90         int err;
  91
  92         err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
  93         if (err)
  94                 return;
  95
  96         v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
  97
  98         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
  99          * to avoid hangs or perfomance issues
 100          */
 101         if ((v == 0) || (v == 6) || (v == 7)) {
 102                 ctl &= ~PCI_EXP_DEVCTL_READRQ;
 103                 ctl |= (2 << 12);
 104                 pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
 105         }
 106 }
 107
 108 /**
 109  * dce4_wait_for_vblank - vblank wait asic callback.
 110  *
 111  * @rdev: radeon_device pointer
 112  * @crtc: crtc to wait for vblank on
 113  *
 114  * Wait for vblank on the requested crtc (evergreen+).
 115  */
 116 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
 117 {
 118         int i;
 119
 120         if (crtc >= rdev->num_crtc)
 121                 return;
 122
 123         if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
 124                 for (i = 0; i < rdev->usec_timeout; i++) {
 125                         if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
 126                                 break;
 127                         udelay(1);
 128                 }
 129                 for (i = 0; i < rdev->usec_timeout; i++) {
 130                         if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
 131                                 break;
 132                         udelay(1);
 133                 }
 134         }
 135 }
 136
 137 /**
 138  * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
 139  *
 140  * @rdev: radeon_device pointer
 141  * @crtc: crtc to prepare for pageflip on
 142  *
 143  * Pre-pageflip callback (evergreen+).
 144  * Enables the pageflip irq (vblank irq).
 145  */
 146 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
 147 {
 148         /* enable the pflip int */
 149         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 150 }
 151
 152 /**
 153  * evergreen_post_page_flip - pos-pageflip callback.
 154  *
 155  * @rdev: radeon_device pointer
 156  * @crtc: crtc to cleanup pageflip on
 157  *
 158  * Post-pageflip callback (evergreen+).
 159  * Disables the pageflip irq (vblank irq).
 160  */
 161 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
 162 {
 163         /* disable the pflip int */
 164         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 165 }
 166
 167 /**
 168  * evergreen_page_flip - pageflip callback.
 169  *
 170  * @rdev: radeon_device pointer
 171  * @crtc_id: crtc to cleanup pageflip on
 172  * @crtc_base: new address of the crtc (GPU MC address)
 173  *
 174  * Does the actual pageflip (evergreen+).
 175  * During vblank we take the crtc lock and wait for the update_pending
 176  * bit to go high, when it does, we release the lock, and allow the
 177  * double buffered update to take place.
 178  * Returns the current update pending status.
 179  */
 180 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 181 {
 182         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 183         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
 184         int i;
 185
 186         /* Lock the graphics update lock */
 187         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
 188         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 189
 190         /* update the scanout addresses */
 191         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 192                upper_32_bits(crtc_base));
 193         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 194                (u32)crtc_base);
 195
 196         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 197                upper_32_bits(crtc_base));
 198         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 199                (u32)crtc_base);
 200
 201         /* Wait for update_pending to go high. */
 202         for (i = 0; i < rdev->usec_timeout; i++) {
 203                 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
 204                         break;
 205                 udelay(1);
 206         }
 207         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 208
 209         /* Unlock the lock, so double-buffering can take place inside vblank */
 210         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
 211         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 212
 213         /* Return current update_pending status: */
 214         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
 215 }
 216
 217 /* get temperature in millidegrees */
 218 int evergreen_get_temp(struct radeon_device *rdev)
 219 {
 220         u32 temp, toffset;
 221         int actual_temp = 0;
 222
 223         if (rdev->family == CHIP_JUNIPER) {
 224                 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
 225                         TOFFSET_SHIFT;
 226                 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
 227                         TS0_ADC_DOUT_SHIFT;
 228
 229                 if (toffset & 0x100)
 230                         actual_temp = temp / 2 - (0x200 - toffset);
 231                 else
 232                         actual_temp = temp / 2 + toffset;
 233
 234                 actual_temp = actual_temp * 1000;
 235
 236         } else {
 237                 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 238                         ASIC_T_SHIFT;
 239
 240                 if (temp & 0x400)
 241                         actual_temp = -256;
 242                 else if (temp & 0x200)
 243                         actual_temp = 255;
 244                 else if (temp & 0x100) {
 245                         actual_temp = temp & 0x1ff;
 246                         actual_temp |= ~0x1ff;
 247                 } else
 248                         actual_temp = temp & 0xff;
 249
 250                 actual_temp = (actual_temp * 1000) / 2;
 251         }
 252
 253         return actual_temp;
 254 }
 255
 256 int sumo_get_temp(struct radeon_device *rdev)
 257 {
 258         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 259         int actual_temp = temp - 49;
 260
 261         return actual_temp * 1000;
 262 }
 263
 264 /**
 265  * sumo_pm_init_profile - Initialize power profiles callback.
 266  *
 267  * @rdev: radeon_device pointer
 268  *
 269  * Initialize the power states used in profile mode
 270  * (sumo, trinity, SI).
 271  * Used for profile mode only.
 272  */
 273 void sumo_pm_init_profile(struct radeon_device *rdev)
 274 {
 275         int idx;
 276
 277         /* default */
 278         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 279         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 280         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 281         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 282
 283         /* low,mid sh/mh */
 284         if (rdev->flags & RADEON_IS_MOBILITY)
 285                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 286         else
 287                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 288
 289         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 290         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 291         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 292         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 293
 294         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 295         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 296         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 297         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 298
 299         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 300         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 301         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 302         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 303
 304         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 305         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 306         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 307         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 308
 309         /* high sh/mh */
 310         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 311         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 312         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 313         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 314         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
 315                 rdev->pm.power_state[idx].num_clock_modes - 1;
 316
 317         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 318         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 319         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 320         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
 321                 rdev->pm.power_state[idx].num_clock_modes - 1;
 322 }
 323
 324 /**
 325  * btc_pm_init_profile - Initialize power profiles callback.
 326  *
 327  * @rdev: radeon_device pointer
 328  *
 329  * Initialize the power states used in profile mode
 330  * (BTC, cayman).
 331  * Used for profile mode only.
 332  */
 333 void btc_pm_init_profile(struct radeon_device *rdev)
 334 {
 335         int idx;
 336
 337         /* default */
 338         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 339         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 340         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 341         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 342         /* starting with BTC, there is one state that is used for both
 343          * MH and SH.  Difference is that we always use the high clock index for
 344          * mclk.
 345          */
 346         if (rdev->flags & RADEON_IS_MOBILITY)
 347                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 348         else
 349                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 350         /* low sh */
 351         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 352         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 353         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 354         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 355         /* mid sh */
 356         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 357         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 358         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 359         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 360         /* high sh */
 361         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 362         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 363         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 364         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 365         /* low mh */
 366         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 367         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 368         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 369         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 370         /* mid mh */
 371         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 372         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 373         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 374         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 375         /* high mh */
 376         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 377         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 378         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 379         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 380 }
 381
 382 /**
 383  * evergreen_pm_misc - set additional pm hw parameters callback.
 384  *
 385  * @rdev: radeon_device pointer
 386  *
 387  * Set non-clock parameters associated with a power state
 388  * (voltage, etc.) (evergreen+).
 389  */
 390 void evergreen_pm_misc(struct radeon_device *rdev)
 391 {
 392         int req_ps_idx = rdev->pm.requested_power_state_index;
 393         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 394         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 395         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 396
 397         if (voltage->type == VOLTAGE_SW) {
 398                 /* 0xff01 is a flag rather then an actual voltage */
 399                 if (voltage->voltage == 0xff01)
 400                         return;
 401                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
 402                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 403                         rdev->pm.current_vddc = voltage->voltage;
 404                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
 405                 }
 406                 /* 0xff01 is a flag rather then an actual voltage */
 407                 if (voltage->vddci == 0xff01)
 408                         return;
 409                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
 410                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
 411                         rdev->pm.current_vddci = voltage->vddci;
 412                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
 413                 }
 414         }
 415 }
 416
 417 /**
 418  * evergreen_pm_prepare - pre-power state change callback.
 419  *
 420  * @rdev: radeon_device pointer
 421  *
 422  * Prepare for a power state change (evergreen+).
 423  */
 424 void evergreen_pm_prepare(struct radeon_device *rdev)
 425 {
 426         struct drm_device *ddev = rdev->ddev;
 427         struct drm_crtc *crtc;
 428         struct radeon_crtc *radeon_crtc;
 429         u32 tmp;
 430
 431         /* disable any active CRTCs */
 432         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 433                 radeon_crtc = to_radeon_crtc(crtc);
 434                 if (radeon_crtc->enabled) {
 435                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 436                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 437                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 438                 }
 439         }
 440 }
 441
 442 /**
 443  * evergreen_pm_finish - post-power state change callback.
 444  *
 445  * @rdev: radeon_device pointer
 446  *
 447  * Clean up after a power state change (evergreen+).
 448  */
 449 void evergreen_pm_finish(struct radeon_device *rdev)
 450 {
 451         struct drm_device *ddev = rdev->ddev;
 452         struct drm_crtc *crtc;
 453         struct radeon_crtc *radeon_crtc;
 454         u32 tmp;
 455
 456         /* enable any active CRTCs */
 457         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 458                 radeon_crtc = to_radeon_crtc(crtc);
 459                 if (radeon_crtc->enabled) {
 460                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 461                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 462                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 463                 }
 464         }
 465 }
 466
 467 /**
 468  * evergreen_hpd_sense - hpd sense callback.
 469  *
 470  * @rdev: radeon_device pointer
 471  * @hpd: hpd (hotplug detect) pin
 472  *
 473  * Checks if a digital monitor is connected (evergreen+).
 474  * Returns true if connected, false if not connected.
 475  */
 476 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 477 {
 478         bool connected = false;
 479
 480         switch (hpd) {
 481         case RADEON_HPD_1:
 482                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 483                         connected = true;
 484                 break;
 485         case RADEON_HPD_2:
 486                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 487                         connected = true;
 488                 break;
 489         case RADEON_HPD_3:
 490                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 491                         connected = true;
 492                 break;
 493         case RADEON_HPD_4:
 494                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 495                         connected = true;
 496                 break;
 497         case RADEON_HPD_5:
 498                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 499                         connected = true;
 500                 break;
 501         case RADEON_HPD_6:
 502                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 503                         connected = true;
 504                         break;
 505         default:
 506                 break;
 507         }
 508
 509         return connected;
 510 }
 511
 512 /**
 513  * evergreen_hpd_set_polarity - hpd set polarity callback.
 514  *
 515  * @rdev: radeon_device pointer
 516  * @hpd: hpd (hotplug detect) pin
 517  *
 518  * Set the polarity of the hpd pin (evergreen+).
 519  */
 520 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 521                                 enum radeon_hpd_id hpd)
 522 {
 523         u32 tmp;
 524         bool connected = evergreen_hpd_sense(rdev, hpd);
 525
 526         switch (hpd) {
 527         case RADEON_HPD_1:
 528                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 529                 if (connected)
 530                         tmp &= ~DC_HPDx_INT_POLARITY;
 531                 else
 532                         tmp |= DC_HPDx_INT_POLARITY;
 533                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 534                 break;
 535         case RADEON_HPD_2:
 536                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 537                 if (connected)
 538                         tmp &= ~DC_HPDx_INT_POLARITY;
 539                 else
 540                         tmp |= DC_HPDx_INT_POLARITY;
 541                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 542                 break;
 543         case RADEON_HPD_3:
 544                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 545                 if (connected)
 546                         tmp &= ~DC_HPDx_INT_POLARITY;
 547                 else
 548                         tmp |= DC_HPDx_INT_POLARITY;
 549                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 550                 break;
 551         case RADEON_HPD_4:
 552                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 553                 if (connected)
 554                         tmp &= ~DC_HPDx_INT_POLARITY;
 555                 else
 556                         tmp |= DC_HPDx_INT_POLARITY;
 557                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 558                 break;
 559         case RADEON_HPD_5:
 560                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 561                 if (connected)
 562                         tmp &= ~DC_HPDx_INT_POLARITY;
 563                 else
 564                         tmp |= DC_HPDx_INT_POLARITY;
 565                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 566                         break;
 567         case RADEON_HPD_6:
 568                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 569                 if (connected)
 570                         tmp &= ~DC_HPDx_INT_POLARITY;
 571                 else
 572                         tmp |= DC_HPDx_INT_POLARITY;
 573                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 574                 break;
 575         default:
 576                 break;
 577         }
 578 }
 579
 580 /**
 581  * evergreen_hpd_init - hpd setup callback.
 582  *
 583  * @rdev: radeon_device pointer
 584  *
 585  * Setup the hpd pins used by the card (evergreen+).
 586  * Enable the pin, set the polarity, and enable the hpd interrupts.
 587  */
 588 void evergreen_hpd_init(struct radeon_device *rdev)
 589 {
 590         struct drm_device *dev = rdev->ddev;
 591         struct drm_connector *connector;
 592         unsigned enabled = 0;
 593         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 594                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 595
 596         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 597                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 598                 switch (radeon_connector->hpd.hpd) {
 599                 case RADEON_HPD_1:
 600                         WREG32(DC_HPD1_CONTROL, tmp);
 601                         break;
 602                 case RADEON_HPD_2:
 603                         WREG32(DC_HPD2_CONTROL, tmp);
 604                         break;
 605                 case RADEON_HPD_3:
 606                         WREG32(DC_HPD3_CONTROL, tmp);
 607                         break;
 608                 case RADEON_HPD_4:
 609                         WREG32(DC_HPD4_CONTROL, tmp);
 610                         break;
 611                 case RADEON_HPD_5:
 612                         WREG32(DC_HPD5_CONTROL, tmp);
 613                         break;
 614                 case RADEON_HPD_6:
 615                         WREG32(DC_HPD6_CONTROL, tmp);
 616                         break;
 617                 default:
 618                         break;
 619                 }
 620                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 621                 enabled |= 1 << radeon_connector->hpd.hpd;
 622         }
 623         radeon_irq_kms_enable_hpd(rdev, enabled);
 624 }
 625
 626 /**
 627  * evergreen_hpd_fini - hpd tear down callback.
 628  *
 629  * @rdev: radeon_device pointer
 630  *
 631  * Tear down the hpd pins used by the card (evergreen+).
 632  * Disable the hpd interrupts.
 633  */
 634 void evergreen_hpd_fini(struct radeon_device *rdev)
 635 {
 636         struct drm_device *dev = rdev->ddev;
 637         struct drm_connector *connector;
 638         unsigned disabled = 0;
 639
 640         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 641                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 642                 switch (radeon_connector->hpd.hpd) {
 643                 case RADEON_HPD_1:
 644                         WREG32(DC_HPD1_CONTROL, 0);
 645                         break;
 646                 case RADEON_HPD_2:
 647                         WREG32(DC_HPD2_CONTROL, 0);
 648                         break;
 649                 case RADEON_HPD_3:
 650                         WREG32(DC_HPD3_CONTROL, 0);
 651                         break;
 652                 case RADEON_HPD_4:
 653                         WREG32(DC_HPD4_CONTROL, 0);
 654                         break;
 655                 case RADEON_HPD_5:
 656                         WREG32(DC_HPD5_CONTROL, 0);
 657                         break;
 658                 case RADEON_HPD_6:
 659                         WREG32(DC_HPD6_CONTROL, 0);
 660                         break;
 661                 default:
 662                         break;
 663                 }
 664                 disabled |= 1 << radeon_connector->hpd.hpd;
 665         }
 666         radeon_irq_kms_disable_hpd(rdev, disabled);
 667 }
 668
 669 /* watermark setup */
 670
 671 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 672                                         struct radeon_crtc *radeon_crtc,
 673                                         struct drm_display_mode *mode,
 674                                         struct drm_display_mode *other_mode)
 675 {
 676         u32 tmp;
 677         /*
 678          * Line Buffer Setup
 679          * There are 3 line buffers, each one shared by 2 display controllers.
 680          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 681          * the display controllers.  The paritioning is done via one of four
 682          * preset allocations specified in bits 2:0:
 683          * first display controller
 684          *  0 - first half of lb (3840 * 2)
 685          *  1 - first 3/4 of lb (5760 * 2)
 686          *  2 - whole lb (7680 * 2), other crtc must be disabled
 687          *  3 - first 1/4 of lb (1920 * 2)
 688          * second display controller
 689          *  4 - second half of lb (3840 * 2)
 690          *  5 - second 3/4 of lb (5760 * 2)
 691          *  6 - whole lb (7680 * 2), other crtc must be disabled
 692          *  7 - last 1/4 of lb (1920 * 2)
 693          */
 694         /* this can get tricky if we have two large displays on a paired group
 695          * of crtcs.  Ideally for multiple large displays we'd assign them to
 696          * non-linked crtcs for maximum line buffer allocation.
 697          */
 698         if (radeon_crtc->base.enabled && mode) {
 699                 if (other_mode)
 700                         tmp = 0; /* 1/2 */
 701                 else
 702                         tmp = 2; /* whole */
 703         } else
 704                 tmp = 0;
 705
 706         /* second controller of the pair uses second half of the lb */
 707         if (radeon_crtc->crtc_id % 2)
 708                 tmp += 4;
 709         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 710
 711         if (radeon_crtc->base.enabled && mode) {
 712                 switch (tmp) {
 713                 case 0:
 714                 case 4:
 715                 default:
 716                         if (ASIC_IS_DCE5(rdev))
 717                                 return 4096 * 2;
 718                         else
 719                                 return 3840 * 2;
 720                 case 1:
 721                 case 5:
 722                         if (ASIC_IS_DCE5(rdev))
 723                                 return 6144 * 2;
 724                         else
 725                                 return 5760 * 2;
 726                 case 2:
 727                 case 6:
 728                         if (ASIC_IS_DCE5(rdev))
 729                                 return 8192 * 2;
 730                         else
 731                                 return 7680 * 2;
 732                 case 3:
 733                 case 7:
 734                         if (ASIC_IS_DCE5(rdev))
 735                                 return 2048 * 2;
 736                         else
 737                                 return 1920 * 2;
 738                 }
 739         }
 740
 741         /* controller not enabled, so no lb used */
 742         return 0;
 743 }
 744
 745 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 746 {
 747         u32 tmp = RREG32(MC_SHARED_CHMAP);
 748
 749         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 750         case 0:
 751         default:
 752                 return 1;
 753         case 1:
 754                 return 2;
 755         case 2:
 756                 return 4;
 757         case 3:
 758                 return 8;
 759         }
 760 }
 761
 762 struct evergreen_wm_params {
 763         u32 dram_channels; /* number of dram channels */
 764         u32 yclk;          /* bandwidth per dram data pin in kHz */
 765         u32 sclk;          /* engine clock in kHz */
 766         u32 disp_clk;      /* display clock in kHz */
 767         u32 src_width;     /* viewport width */
 768         u32 active_time;   /* active display time in ns */
 769         u32 blank_time;    /* blank time in ns */
 770         bool interlaced;    /* mode is interlaced */
 771         fixed20_12 vsc;    /* vertical scale ratio */
 772         u32 num_heads;     /* number of active crtcs */
 773         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 774         u32 lb_size;       /* line buffer allocated to pipe */
 775         u32 vtaps;         /* vertical scaler taps */
 776 };
 777
 778 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 779 {
 780         /* Calculate DRAM Bandwidth and the part allocated to display. */
 781         fixed20_12 dram_efficiency; /* 0.7 */
 782         fixed20_12 yclk, dram_channels, bandwidth;
 783         fixed20_12 a;
 784
 785         a.full = dfixed_const(1000);
 786         yclk.full = dfixed_const(wm->yclk);
 787         yclk.full = dfixed_div(yclk, a);
 788         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 789         a.full = dfixed_const(10);
 790         dram_efficiency.full = dfixed_const(7);
 791         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 792         bandwidth.full = dfixed_mul(dram_channels, yclk);
 793         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 794
 795         return dfixed_trunc(bandwidth);
 796 }
 797
 798 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 799 {
 800         /* Calculate DRAM Bandwidth and the part allocated to display. */
 801         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 802         fixed20_12 yclk, dram_channels, bandwidth;
 803         fixed20_12 a;
 804
 805         a.full = dfixed_const(1000);
 806         yclk.full = dfixed_const(wm->yclk);
 807         yclk.full = dfixed_div(yclk, a);
 808         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 809         a.full = dfixed_const(10);
 810         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 811         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 812         bandwidth.full = dfixed_mul(dram_channels, yclk);
 813         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 814
 815         return dfixed_trunc(bandwidth);
 816 }
 817
 818 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 819 {
 820         /* Calculate the display Data return Bandwidth */
 821         fixed20_12 return_efficiency; /* 0.8 */
 822         fixed20_12 sclk, bandwidth;
 823         fixed20_12 a;
 824
 825         a.full = dfixed_const(1000);
 826         sclk.full = dfixed_const(wm->sclk);
 827         sclk.full = dfixed_div(sclk, a);
 828         a.full = dfixed_const(10);
 829         return_efficiency.full = dfixed_const(8);
 830         return_efficiency.full = dfixed_div(return_efficiency, a);
 831         a.full = dfixed_const(32);
 832         bandwidth.full = dfixed_mul(a, sclk);
 833         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 834
 835         return dfixed_trunc(bandwidth);
 836 }
 837
 838 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 839 {
 840         /* Calculate the DMIF Request Bandwidth */
 841         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 842         fixed20_12 disp_clk, bandwidth;
 843         fixed20_12 a;
 844
 845         a.full = dfixed_const(1000);
 846         disp_clk.full = dfixed_const(wm->disp_clk);
 847         disp_clk.full = dfixed_div(disp_clk, a);
 848         a.full = dfixed_const(10);
 849         disp_clk_request_efficiency.full = dfixed_const(8);
 850         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 851         a.full = dfixed_const(32);
 852         bandwidth.full = dfixed_mul(a, disp_clk);
 853         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 854
 855         return dfixed_trunc(bandwidth);
 856 }
 857
 858 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 859 {
 860         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 861         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 862         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 863         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 864
 865         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 866 }
 867
 868 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 869 {
 870         /* Calculate the display mode Average Bandwidth
 871          * DisplayMode should contain the source and destination dimensions,
 872          * timing, etc.
 873          */
 874         fixed20_12 bpp;
 875         fixed20_12 line_time;
 876         fixed20_12 src_width;
 877         fixed20_12 bandwidth;
 878         fixed20_12 a;
 879
 880         a.full = dfixed_const(1000);
 881         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 882         line_time.full = dfixed_div(line_time, a);
 883         bpp.full = dfixed_const(wm->bytes_per_pixel);
 884         src_width.full = dfixed_const(wm->src_width);
 885         bandwidth.full = dfixed_mul(src_width, bpp);
 886         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 887         bandwidth.full = dfixed_div(bandwidth, line_time);
 888
 889         return dfixed_trunc(bandwidth);
 890 }
 891
 892 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 893 {
 894         /* First calcualte the latency in ns */
 895         u32 mc_latency = 2000; /* 2000 ns. */
 896         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 897         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 898         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 899         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 900         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 901                 (wm->num_heads * cursor_line_pair_return_time);
 902         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 903         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 904         fixed20_12 a, b, c;
 905
 906         if (wm->num_heads == 0)
 907                 return 0;
 908
 909         a.full = dfixed_const(2);
 910         b.full = dfixed_const(1);
 911         if ((wm->vsc.full > a.full) ||
 912             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 913             (wm->vtaps >= 5) ||
 914             ((wm->vsc.full >= a.full) && wm->interlaced))
 915                 max_src_lines_per_dst_line = 4;
 916         else
 917                 max_src_lines_per_dst_line = 2;
 918
 919         a.full = dfixed_const(available_bandwidth);
 920         b.full = dfixed_const(wm->num_heads);
 921         a.full = dfixed_div(a, b);
 922
 923         b.full = dfixed_const(1000);
 924         c.full = dfixed_const(wm->disp_clk);
 925         b.full = dfixed_div(c, b);
 926         c.full = dfixed_const(wm->bytes_per_pixel);
 927         b.full = dfixed_mul(b, c);
 928
 929         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 930
 931         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 932         b.full = dfixed_const(1000);
 933         c.full = dfixed_const(lb_fill_bw);
 934         b.full = dfixed_div(c, b);
 935         a.full = dfixed_div(a, b);
 936         line_fill_time = dfixed_trunc(a);
 937
 938         if (line_fill_time < wm->active_time)
 939                 return latency;
 940         else
 941                 return latency + (line_fill_time - wm->active_time);
 942
 943 }
 944
 945 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 946 {
 947         if (evergreen_average_bandwidth(wm) <=
 948             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 949                 return true;
 950         else
 951                 return false;
 952 };
 953
 954 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 955 {
 956         if (evergreen_average_bandwidth(wm) <=
 957             (evergreen_available_bandwidth(wm) / wm->num_heads))
 958                 return true;
 959         else
 960                 return false;
 961 };
 962
 963 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 964 {
 965         u32 lb_partitions = wm->lb_size / wm->src_width;
 966         u32 line_time = wm->active_time + wm->blank_time;
 967         u32 latency_tolerant_lines;
 968         u32 latency_hiding;
 969         fixed20_12 a;
 970
 971         a.full = dfixed_const(1);
 972         if (wm->vsc.full > a.full)
 973                 latency_tolerant_lines = 1;
 974         else {
 975                 if (lb_partitions <= (wm->vtaps + 1))
 976                         latency_tolerant_lines = 1;
 977                 else
 978                         latency_tolerant_lines = 2;
 979         }
 980
 981         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 982
 983         if (evergreen_latency_watermark(wm) <= latency_hiding)
 984                 return true;
 985         else
 986                 return false;
 987 }
 988
 989 static void evergreen_program_watermarks(struct radeon_device *rdev,
 990                                          struct radeon_crtc *radeon_crtc,
 991                                          u32 lb_size, u32 num_heads)
 992 {
 993         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 994         struct evergreen_wm_params wm;
 995         u32 pixel_period;
 996         u32 line_time = 0;
 997         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 998         u32 priority_a_mark = 0, priority_b_mark = 0;
 999         u32 priority_a_cnt = PRIORITY_OFF;
1000         u32 priority_b_cnt = PRIORITY_OFF;
1001         u32 pipe_offset = radeon_crtc->crtc_id * 16;
1002         u32 tmp, arb_control3;
1003         fixed20_12 a, b, c;
1004
1005         if (radeon_crtc->base.enabled && num_heads && mode) {
1006                 pixel_period = 1000000 / (u32)mode->clock;
1007                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1008                 priority_a_cnt = 0;
1009                 priority_b_cnt = 0;
1010
1011                 wm.yclk = rdev->pm.current_mclk * 10;
1012                 wm.sclk = rdev->pm.current_sclk * 10;
1013                 wm.disp_clk = mode->clock;
1014                 wm.src_width = mode->crtc_hdisplay;
1015                 wm.active_time = mode->crtc_hdisplay * pixel_period;
1016                 wm.blank_time = line_time - wm.active_time;
1017                 wm.interlaced = false;
1018                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1019                         wm.interlaced = true;
1020                 wm.vsc = radeon_crtc->vsc;
1021                 wm.vtaps = 1;
1022                 if (radeon_crtc->rmx_type != RMX_OFF)
1023                         wm.vtaps = 2;
1024                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
1025                 wm.lb_size = lb_size;
1026                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
1027                 wm.num_heads = num_heads;
1028
1029                 /* set for high clocks */
1030                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
1031                 /* set for low clocks */
1032                 /* wm.yclk = low clk; wm.sclk = low clk */
1033                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
1034
1035                 /* possibly force display priority to high */
1036                 /* should really do this at mode validation time... */
1037                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
1038                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
1039                     !evergreen_check_latency_hiding(&wm) ||
1040                     (rdev->disp_priority == 2)) {
1041                         DRM_DEBUG_KMS("force priority to high\n");
1042                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
1043                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
1044                 }
1045
1046                 a.full = dfixed_const(1000);
1047                 b.full = dfixed_const(mode->clock);
1048                 b.full = dfixed_div(b, a);
1049                 c.full = dfixed_const(latency_watermark_a);
1050                 c.full = dfixed_mul(c, b);
1051                 c.full = dfixed_mul(c, radeon_crtc->hsc);
1052                 c.full = dfixed_div(c, a);
1053                 a.full = dfixed_const(16);
1054                 c.full = dfixed_div(c, a);
1055                 priority_a_mark = dfixed_trunc(c);
1056                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1057
1058                 a.full = dfixed_const(1000);
1059                 b.full = dfixed_const(mode->clock);
1060                 b.full = dfixed_div(b, a);
1061                 c.full = dfixed_const(latency_watermark_b);
1062                 c.full = dfixed_mul(c, b);
1063                 c.full = dfixed_mul(c, radeon_crtc->hsc);
1064                 c.full = dfixed_div(c, a);
1065                 a.full = dfixed_const(16);
1066                 c.full = dfixed_div(c, a);
1067                 priority_b_mark = dfixed_trunc(c);
1068                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1069         }
1070
1071         /* select wm A */
1072         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1073         tmp = arb_control3;
1074         tmp &= ~LATENCY_WATERMARK_MASK(3);
1075         tmp |= LATENCY_WATERMARK_MASK(1);
1076         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1077         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1078                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1079                 LATENCY_HIGH_WATERMARK(line_time)));
1080         /* select wm B */
1081         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1082         tmp &= ~LATENCY_WATERMARK_MASK(3);
1083         tmp |= LATENCY_WATERMARK_MASK(2);
1084         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1085         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1086                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1087                 LATENCY_HIGH_WATERMARK(line_time)));
1088         /* restore original selection */
1089         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
1090
1091         /* write the priority marks */
1092         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
1093         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
1094
1095 }
1096
1097 /**
1098  * evergreen_bandwidth_update - update display watermarks callback.
1099  *
1100  * @rdev: radeon_device pointer
1101  *
1102  * Update the display watermarks based on the requested mode(s)
1103  * (evergreen+).
1104  */
1105 void evergreen_bandwidth_update(struct radeon_device *rdev)
1106 {
1107         struct drm_display_mode *mode0 = NULL;
1108         struct drm_display_mode *mode1 = NULL;
1109         u32 num_heads = 0, lb_size;
1110         int i;
1111
1112         radeon_update_display_priority(rdev);
1113
1114         for (i = 0; i < rdev->num_crtc; i++) {
1115                 if (rdev->mode_info.crtcs[i]->base.enabled)
1116                         num_heads++;
1117         }
1118         for (i = 0; i < rdev->num_crtc; i += 2) {
1119                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
1120                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
1121                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
1122                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
1123                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
1124                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
1125         }
1126 }
1127
1128 /**
1129  * evergreen_mc_wait_for_idle - wait for MC idle callback.
1130  *
1131  * @rdev: radeon_device pointer
1132  *
1133  * Wait for the MC (memory controller) to be idle.
1134  * (evergreen+).
1135  * Returns 0 if the MC is idle, -1 if not.
1136  */
1137 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
1138 {
1139         unsigned i;
1140         u32 tmp;
1141
1142         for (i = 0; i < rdev->usec_timeout; i++) {
1143                 /* read MC_STATUS */
1144                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1145                 if (!tmp)
1146                         return 0;
1147                 udelay(1);
1148         }
1149         return -1;
1150 }
1151
1152 /*
1153  * GART
1154  */
1155 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
1156 {
1157         unsigned i;
1158         u32 tmp;
1159
1160         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1161
1162         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1163         for (i = 0; i < rdev->usec_timeout; i++) {
1164                 /* read MC_STATUS */
1165                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1166                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1167                 if (tmp == 2) {
1168                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1169                         return;
1170                 }
1171                 if (tmp) {
1172                         return;
1173                 }
1174                 udelay(1);
1175         }
1176 }
1177
1178 static int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1179 {
1180         u32 tmp;
1181         int r;
1182
1183         if (rdev->gart.robj == NULL) {
1184                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1185                 return -EINVAL;
1186         }
1187         r = radeon_gart_table_vram_pin(rdev);
1188         if (r)
1189                 return r;
1190         radeon_gart_restore(rdev);
1191         /* Setup L2 cache */
1192         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1193                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1194                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1195         WREG32(VM_L2_CNTL2, 0);
1196         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1197         /* Setup TLB control */
1198         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1199                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1200                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1201                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1202         if (rdev->flags & RADEON_IS_IGP) {
1203                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1204                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1205                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1206         } else {
1207                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1208                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1209                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1210                 if ((rdev->family == CHIP_JUNIPER) ||
1211                     (rdev->family == CHIP_CYPRESS) ||
1212                     (rdev->family == CHIP_HEMLOCK) ||
1213                     (rdev->family == CHIP_BARTS))
1214                         WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1215         }
1216         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1217         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1218         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1219         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1220         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1221         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1222         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1223         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1224                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1225         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1226                         (u32)(rdev->dummy_page.addr >> 12));
1227         WREG32(VM_CONTEXT1_CNTL, 0);
1228
1229         evergreen_pcie_gart_tlb_flush(rdev);
1230         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1231                  (unsigned)(rdev->mc.gtt_size >> 20),
1232                  (unsigned long long)rdev->gart.table_addr);
1233         rdev->gart.ready = true;
1234         return 0;
1235 }
1236
1237 static void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1238 {
1239         u32 tmp;
1240
1241         /* Disable all tables */
1242         WREG32(VM_CONTEXT0_CNTL, 0);
1243         WREG32(VM_CONTEXT1_CNTL, 0);
1244
1245         /* Setup L2 cache */
1246         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1247                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1248         WREG32(VM_L2_CNTL2, 0);
1249         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1250         /* Setup TLB control */
1251         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1252         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1253         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1254         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1255         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1256         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1257         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1258         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1259         radeon_gart_table_vram_unpin(rdev);
1260 }
1261
1262 static void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1263 {
1264         evergreen_pcie_gart_disable(rdev);
1265         radeon_gart_table_vram_free(rdev);
1266         radeon_gart_fini(rdev);
1267 }
1268
1269
1270 static void evergreen_agp_enable(struct radeon_device *rdev)
1271 {
1272         u32 tmp;
1273
1274         /* Setup L2 cache */
1275         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1276                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1277                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1278         WREG32(VM_L2_CNTL2, 0);
1279         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1280         /* Setup TLB control */
1281         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1282                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1283                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1284                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1285         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1286         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1287         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1288         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1289         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1290         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1291         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1292         WREG32(VM_CONTEXT0_CNTL, 0);
1293         WREG32(VM_CONTEXT1_CNTL, 0);
1294 }
1295
1296 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1297 {
1298         u32 crtc_enabled, tmp, frame_count, blackout;
1299         int i, j;
1300
1301         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1302         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1303
1304         /* disable VGA render */
1305         WREG32(VGA_RENDER_CONTROL, 0);
1306         /* blank the display controllers */
1307         for (i = 0; i < rdev->num_crtc; i++) {
1308                 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1309                 if (crtc_enabled) {
1310                         save->crtc_enabled[i] = true;
1311                         if (ASIC_IS_DCE6(rdev)) {
1312                                 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1313                                 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1314                                         radeon_wait_for_vblank(rdev, i);
1315                                         tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1316                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1317                                         WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1318                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1319                                 }
1320                         } else {
1321                                 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1322                                 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1323                                         radeon_wait_for_vblank(rdev, i);
1324                                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1325                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1326                                         WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1327                                         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1328                                 }
1329                         }
1330                         /* wait for the next frame */
1331                         frame_count = radeon_get_vblank_counter(rdev, i);
1332                         for (j = 0; j < rdev->usec_timeout; j++) {
1333                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1334                                         break;
1335                                 udelay(1);
1336                         }
1337                 } else {
1338                         save->crtc_enabled[i] = false;
1339                 }
1340         }
1341
1342         radeon_mc_wait_for_idle(rdev);
1343
1344         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1345         if ((blackout & BLACKOUT_MODE_MASK) != 1) {
1346                 /* Block CPU access */
1347                 WREG32(BIF_FB_EN, 0);
1348                 /* blackout the MC */
1349                 blackout &= ~BLACKOUT_MODE_MASK;
1350                 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1351         }
1352 }
1353
1354 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1355 {
1356         u32 tmp, frame_count;
1357         int i, j;
1358
1359         /* update crtc base addresses */
1360         for (i = 0; i < rdev->num_crtc; i++) {
1361                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
1362                        upper_32_bits(rdev->mc.vram_start));
1363                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
1364                        upper_32_bits(rdev->mc.vram_start));
1365                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
1366                        (u32)rdev->mc.vram_start);
1367                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
1368                        (u32)rdev->mc.vram_start);
1369         }
1370         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1371         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1372
1373         /* unblackout the MC */
1374         tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1375         tmp &= ~BLACKOUT_MODE_MASK;
1376         WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1377         /* allow CPU access */
1378         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1379
1380         for (i = 0; i < rdev->num_crtc; i++) {
1381                 if (save->crtc_enabled[i]) {
1382                         if (ASIC_IS_DCE6(rdev)) {
1383                                 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1384                                 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1385                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1386                                 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1387                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1388                         } else {
1389                                 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1390                                 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1391                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
1392                                 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1393                                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
1394                         }
1395                         /* wait for the next frame */
1396                         frame_count = radeon_get_vblank_counter(rdev, i);
1397                         for (j = 0; j < rdev->usec_timeout; j++) {
1398                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1399                                         break;
1400                                 udelay(1);
1401                         }
1402                 }
1403         }
1404         /* Unlock vga access */
1405         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1406         mdelay(1);
1407         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1408 }
1409
1410 void evergreen_mc_program(struct radeon_device *rdev)
1411 {
1412         struct evergreen_mc_save save;
1413         u32 tmp;
1414         int i, j;
1415
1416         /* Initialize HDP */
1417         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1418                 WREG32((0x2c14 + j), 0x00000000);
1419                 WREG32((0x2c18 + j), 0x00000000);
1420                 WREG32((0x2c1c + j), 0x00000000);
1421                 WREG32((0x2c20 + j), 0x00000000);
1422                 WREG32((0x2c24 + j), 0x00000000);
1423         }
1424         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1425
1426         evergreen_mc_stop(rdev, &save);
1427         if (evergreen_mc_wait_for_idle(rdev)) {
1428                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1429         }
1430         /* Lockout access through VGA aperture*/
1431         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1432         /* Update configuration */
1433         if (rdev->flags & RADEON_IS_AGP) {
1434                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1435                         /* VRAM before AGP */
1436                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1437                                 rdev->mc.vram_start >> 12);
1438                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1439                                 rdev->mc.gtt_end >> 12);
1440                 } else {
1441                         /* VRAM after AGP */
1442                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1443                                 rdev->mc.gtt_start >> 12);
1444                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1445                                 rdev->mc.vram_end >> 12);
1446                 }
1447         } else {
1448                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1449                         rdev->mc.vram_start >> 12);
1450                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1451                         rdev->mc.vram_end >> 12);
1452         }
1453         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1454         /* llano/ontario only */
1455         if ((rdev->family == CHIP_PALM) ||
1456             (rdev->family == CHIP_SUMO) ||
1457             (rdev->family == CHIP_SUMO2)) {
1458                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1459                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1460                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1461                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1462         }
1463         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1464         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1465         WREG32(MC_VM_FB_LOCATION, tmp);
1466         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1467         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1468         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1469         if (rdev->flags & RADEON_IS_AGP) {
1470                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1471                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1472                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1473         } else {
1474                 WREG32(MC_VM_AGP_BASE, 0);
1475                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1476                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1477         }
1478         if (evergreen_mc_wait_for_idle(rdev)) {
1479                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1480         }
1481         evergreen_mc_resume(rdev, &save);
1482         /* we need to own VRAM, so turn off the VGA renderer here
1483          * to stop it overwriting our objects */
1484         rv515_vga_render_disable(rdev);
1485 }
1486
1487 /*
1488  * CP.
1489  */
1490 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1491 {
1492         struct radeon_ring *ring = &rdev->ring[ib->ring];
1493         u32 next_rptr;
1494
1495         /* set to DX10/11 mode */
1496         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1497         radeon_ring_write(ring, 1);
1498
1499         if (ring->rptr_save_reg) {
1500                 next_rptr = ring->wptr + 3 + 4;
1501                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1502                 radeon_ring_write(ring, ((ring->rptr_save_reg -
1503                                           PACKET3_SET_CONFIG_REG_START) >> 2));
1504                 radeon_ring_write(ring, next_rptr);
1505         } else if (rdev->wb.enabled) {
1506                 next_rptr = ring->wptr + 5 + 4;
1507                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1508                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1509                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1510                 radeon_ring_write(ring, next_rptr);
1511                 radeon_ring_write(ring, 0);
1512         }
1513
1514         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1515         radeon_ring_write(ring,
1516 #ifdef __BIG_ENDIAN
1517                           (2 << 0) |
1518 #endif
1519                           (ib->gpu_addr & 0xFFFFFFFC));
1520         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1521         radeon_ring_write(ring, ib->length_dw);
1522 }
1523
1524
1525 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1526 {
1527         const __be32 *fw_data;
1528         int i;
1529
1530         if (!rdev->me_fw || !rdev->pfp_fw)
1531                 return -EINVAL;
1532
1533         r700_cp_stop(rdev);
1534         WREG32(CP_RB_CNTL,
1535 #ifdef __BIG_ENDIAN
1536                BUF_SWAP_32BIT |
1537 #endif
1538                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1539
1540         fw_data = (const __be32 *)rdev->pfp_fw->data;
1541         WREG32(CP_PFP_UCODE_ADDR, 0);
1542         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1543                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1544         WREG32(CP_PFP_UCODE_ADDR, 0);
1545
1546         fw_data = (const __be32 *)rdev->me_fw->data;
1547         WREG32(CP_ME_RAM_WADDR, 0);
1548         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1549                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1550
1551         WREG32(CP_PFP_UCODE_ADDR, 0);
1552         WREG32(CP_ME_RAM_WADDR, 0);
1553         WREG32(CP_ME_RAM_RADDR, 0);
1554         return 0;
1555 }
1556
1557 static int evergreen_cp_start(struct radeon_device *rdev)
1558 {
1559         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1560         int r, i;
1561         uint32_t cp_me;
1562
1563         r = radeon_ring_lock(rdev, ring, 7);
1564         if (r) {
1565                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1566                 return r;
1567         }
1568         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1569         radeon_ring_write(ring, 0x1);
1570         radeon_ring_write(ring, 0x0);
1571         radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1572         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1573         radeon_ring_write(ring, 0);
1574         radeon_ring_write(ring, 0);
1575         radeon_ring_unlock_commit(rdev, ring);
1576
1577         cp_me = 0xff;
1578         WREG32(CP_ME_CNTL, cp_me);
1579
1580         r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
1581         if (r) {
1582                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1583                 return r;
1584         }
1585
1586         /* setup clear context state */
1587         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1588         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1589
1590         for (i = 0; i < evergreen_default_size; i++)
1591                 radeon_ring_write(ring, evergreen_default_state[i]);
1592
1593         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1594         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1595
1596         /* set clear context state */
1597         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1598         radeon_ring_write(ring, 0);
1599
1600         /* SQ_VTX_BASE_VTX_LOC */
1601         radeon_ring_write(ring, 0xc0026f00);
1602         radeon_ring_write(ring, 0x00000000);
1603         radeon_ring_write(ring, 0x00000000);
1604         radeon_ring_write(ring, 0x00000000);
1605
1606         /* Clear consts */
1607         radeon_ring_write(ring, 0xc0036f00);
1608         radeon_ring_write(ring, 0x00000bc4);
1609         radeon_ring_write(ring, 0xffffffff);
1610         radeon_ring_write(ring, 0xffffffff);
1611         radeon_ring_write(ring, 0xffffffff);
1612
1613         radeon_ring_write(ring, 0xc0026900);
1614         radeon_ring_write(ring, 0x00000316);
1615         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1616         radeon_ring_write(ring, 0x00000010); /*  */
1617
1618         radeon_ring_unlock_commit(rdev, ring);
1619
1620         return 0;
1621 }
1622
1623 static int evergreen_cp_resume(struct radeon_device *rdev)
1624 {
1625         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1626         u32 tmp;
1627         u32 rb_bufsz;
1628         int r;
1629
1630         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1631         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1632                                  SOFT_RESET_PA |
1633                                  SOFT_RESET_SH |
1634                                  SOFT_RESET_VGT |
1635                                  SOFT_RESET_SPI |
1636                                  SOFT_RESET_SX));
1637         RREG32(GRBM_SOFT_RESET);
1638         mdelay(15);
1639         WREG32(GRBM_SOFT_RESET, 0);
1640         RREG32(GRBM_SOFT_RESET);
1641
1642         /* Set ring buffer size */
1643         rb_bufsz = drm_order(ring->ring_size / 8);
1644         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1645 #ifdef __BIG_ENDIAN
1646         tmp |= BUF_SWAP_32BIT;
1647 #endif
1648         WREG32(CP_RB_CNTL, tmp);
1649         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1650         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1651
1652         /* Set the write pointer delay */
1653         WREG32(CP_RB_WPTR_DELAY, 0);
1654
1655         /* Initialize the ring buffer's read and write pointers */
1656         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1657         WREG32(CP_RB_RPTR_WR, 0);
1658         ring->wptr = 0;
1659         WREG32(CP_RB_WPTR, ring->wptr);
1660
1661         /* set the wb address whether it's enabled or not */
1662         WREG32(CP_RB_RPTR_ADDR,
1663                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1664         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1665         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1666
1667         if (rdev->wb.enabled)
1668                 WREG32(SCRATCH_UMSK, 0xff);
1669         else {
1670                 tmp |= RB_NO_UPDATE;
1671                 WREG32(SCRATCH_UMSK, 0);
1672         }
1673
1674         mdelay(1);
1675         WREG32(CP_RB_CNTL, tmp);
1676
1677         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1678         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1679
1680         ring->rptr = RREG32(CP_RB_RPTR);
1681
1682         evergreen_cp_start(rdev);
1683         ring->ready = true;
1684         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1685         if (r) {
1686                 ring->ready = false;
1687                 return r;
1688         }
1689         return 0;
1690 }
1691
1692 /*
1693  * Core functions
1694  */
1695 static void evergreen_gpu_init(struct radeon_device *rdev)
1696 {
1697         u32 gb_addr_config;
1698         u32 mc_shared_chmap, mc_arb_ramcfg;
1699         u32 sx_debug_1;
1700         u32 smx_dc_ctl0;
1701         u32 sq_config;
1702         u32 sq_lds_resource_mgmt;
1703         u32 sq_gpr_resource_mgmt_1;
1704         u32 sq_gpr_resource_mgmt_2;
1705         u32 sq_gpr_resource_mgmt_3;
1706         u32 sq_thread_resource_mgmt;
1707         u32 sq_thread_resource_mgmt_2;
1708         u32 sq_stack_resource_mgmt_1;
1709         u32 sq_stack_resource_mgmt_2;
1710         u32 sq_stack_resource_mgmt_3;
1711         u32 vgt_cache_invalidation;
1712         u32 hdp_host_path_cntl, tmp;
1713         u32 disabled_rb_mask;
1714         int i, j, num_shader_engines, ps_thread_count;
1715
1716         switch (rdev->family) {
1717         case CHIP_CYPRESS:
1718         case CHIP_HEMLOCK:
1719                 rdev->config.evergreen.num_ses = 2;
1720                 rdev->config.evergreen.max_pipes = 4;
1721                 rdev->config.evergreen.max_tile_pipes = 8;
1722                 rdev->config.evergreen.max_simds = 10;
1723                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1724                 rdev->config.evergreen.max_gprs = 256;
1725                 rdev->config.evergreen.max_threads = 248;
1726                 rdev->config.evergreen.max_gs_threads = 32;
1727                 rdev->config.evergreen.max_stack_entries = 512;
1728                 rdev->config.evergreen.sx_num_of_sets = 4;
1729                 rdev->config.evergreen.sx_max_export_size = 256;
1730                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1731                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1732                 rdev->config.evergreen.max_hw_contexts = 8;
1733                 rdev->config.evergreen.sq_num_cf_insts = 2;
1734
1735                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1736                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1737                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1738                 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
1739                 break;
1740         case CHIP_JUNIPER:
1741                 rdev->config.evergreen.num_ses = 1;
1742                 rdev->config.evergreen.max_pipes = 4;
1743                 rdev->config.evergreen.max_tile_pipes = 4;
1744                 rdev->config.evergreen.max_simds = 10;
1745                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1746                 rdev->config.evergreen.max_gprs = 256;
1747                 rdev->config.evergreen.max_threads = 248;
1748                 rdev->config.evergreen.max_gs_threads = 32;
1749                 rdev->config.evergreen.max_stack_entries = 512;
1750                 rdev->config.evergreen.sx_num_of_sets = 4;
1751                 rdev->config.evergreen.sx_max_export_size = 256;
1752                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1753                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1754                 rdev->config.evergreen.max_hw_contexts = 8;
1755                 rdev->config.evergreen.sq_num_cf_insts = 2;
1756
1757                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1758                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1759                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1760                 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
1761                 break;
1762         case CHIP_REDWOOD:
1763                 rdev->config.evergreen.num_ses = 1;
1764                 rdev->config.evergreen.max_pipes = 4;
1765                 rdev->config.evergreen.max_tile_pipes = 4;
1766                 rdev->config.evergreen.max_simds = 5;
1767                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1768                 rdev->config.evergreen.max_gprs = 256;
1769                 rdev->config.evergreen.max_threads = 248;
1770                 rdev->config.evergreen.max_gs_threads = 32;
1771                 rdev->config.evergreen.max_stack_entries = 256;
1772                 rdev->config.evergreen.sx_num_of_sets = 4;
1773                 rdev->config.evergreen.sx_max_export_size = 256;
1774                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1775                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1776                 rdev->config.evergreen.max_hw_contexts = 8;
1777                 rdev->config.evergreen.sq_num_cf_insts = 2;
1778
1779                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1780                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1781                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1782                 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1783                 break;
1784         case CHIP_CEDAR:
1785         default:
1786                 rdev->config.evergreen.num_ses = 1;
1787                 rdev->config.evergreen.max_pipes = 2;
1788                 rdev->config.evergreen.max_tile_pipes = 2;
1789                 rdev->config.evergreen.max_simds = 2;
1790                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1791                 rdev->config.evergreen.max_gprs = 256;
1792                 rdev->config.evergreen.max_threads = 192;
1793                 rdev->config.evergreen.max_gs_threads = 16;
1794                 rdev->config.evergreen.max_stack_entries = 256;
1795                 rdev->config.evergreen.sx_num_of_sets = 4;
1796                 rdev->config.evergreen.sx_max_export_size = 128;
1797                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1798                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1799                 rdev->config.evergreen.max_hw_contexts = 4;
1800                 rdev->config.evergreen.sq_num_cf_insts = 1;
1801
1802                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1803                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1804                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1805                 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1806                 break;
1807         case CHIP_PALM:
1808                 rdev->config.evergreen.num_ses = 1;
1809                 rdev->config.evergreen.max_pipes = 2;
1810                 rdev->config.evergreen.max_tile_pipes = 2;
1811                 rdev->config.evergreen.max_simds = 2;
1812                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1813                 rdev->config.evergreen.max_gprs = 256;
1814                 rdev->config.evergreen.max_threads = 192;
1815                 rdev->config.evergreen.max_gs_threads = 16;
1816                 rdev->config.evergreen.max_stack_entries = 256;
1817                 rdev->config.evergreen.sx_num_of_sets = 4;
1818                 rdev->config.evergreen.sx_max_export_size = 128;
1819                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1820                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1821                 rdev->config.evergreen.max_hw_contexts = 4;
1822                 rdev->config.evergreen.sq_num_cf_insts = 1;
1823
1824                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1825                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1826                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1827                 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1828                 break;
1829         case CHIP_SUMO:
1830                 rdev->config.evergreen.num_ses = 1;
1831                 rdev->config.evergreen.max_pipes = 4;
1832                 rdev->config.evergreen.max_tile_pipes = 4;
1833                 if (rdev->pdev->device == 0x9648)
1834                         rdev->config.evergreen.max_simds = 3;
1835                 else if ((rdev->pdev->device == 0x9647) ||
1836                          (rdev->pdev->device == 0x964a))
1837                         rdev->config.evergreen.max_simds = 4;
1838                 else
1839                         rdev->config.evergreen.max_simds = 5;
1840                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1841                 rdev->config.evergreen.max_gprs = 256;
1842                 rdev->config.evergreen.max_threads = 248;
1843                 rdev->config.evergreen.max_gs_threads = 32;
1844                 rdev->config.evergreen.max_stack_entries = 256;
1845                 rdev->config.evergreen.sx_num_of_sets = 4;
1846                 rdev->config.evergreen.sx_max_export_size = 256;
1847                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1848                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1849                 rdev->config.evergreen.max_hw_contexts = 8;
1850                 rdev->config.evergreen.sq_num_cf_insts = 2;
1851
1852                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1853                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1854                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1855                 gb_addr_config = SUMO_GB_ADDR_CONFIG_GOLDEN;
1856                 break;
1857         case CHIP_SUMO2:
1858                 rdev->config.evergreen.num_ses = 1;
1859                 rdev->config.evergreen.max_pipes = 4;
1860                 rdev->config.evergreen.max_tile_pipes = 4;
1861                 rdev->config.evergreen.max_simds = 2;
1862                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1863                 rdev->config.evergreen.max_gprs = 256;
1864                 rdev->config.evergreen.max_threads = 248;
1865                 rdev->config.evergreen.max_gs_threads = 32;
1866                 rdev->config.evergreen.max_stack_entries = 512;
1867                 rdev->config.evergreen.sx_num_of_sets = 4;
1868                 rdev->config.evergreen.sx_max_export_size = 256;
1869                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1870                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1871                 rdev->config.evergreen.max_hw_contexts = 8;
1872                 rdev->config.evergreen.sq_num_cf_insts = 2;
1873
1874                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1875                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1876                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1877                 gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;
1878                 break;
1879         case CHIP_BARTS:
1880                 rdev->config.evergreen.num_ses = 2;
1881                 rdev->config.evergreen.max_pipes = 4;
1882                 rdev->config.evergreen.max_tile_pipes = 8;
1883                 rdev->config.evergreen.max_simds = 7;
1884                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1885                 rdev->config.evergreen.max_gprs = 256;
1886                 rdev->config.evergreen.max_threads = 248;
1887                 rdev->config.evergreen.max_gs_threads = 32;
1888                 rdev->config.evergreen.max_stack_entries = 512;
1889                 rdev->config.evergreen.sx_num_of_sets = 4;
1890                 rdev->config.evergreen.sx_max_export_size = 256;
1891                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1892                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1893                 rdev->config.evergreen.max_hw_contexts = 8;
1894                 rdev->config.evergreen.sq_num_cf_insts = 2;
1895
1896                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1897                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1898                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1899                 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
1900                 break;
1901         case CHIP_TURKS:
1902                 rdev->config.evergreen.num_ses = 1;
1903                 rdev->config.evergreen.max_pipes = 4;
1904                 rdev->config.evergreen.max_tile_pipes = 4;
1905                 rdev->config.evergreen.max_simds = 6;
1906                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1907                 rdev->config.evergreen.max_gprs = 256;
1908                 rdev->config.evergreen.max_threads = 248;
1909                 rdev->config.evergreen.max_gs_threads = 32;
1910                 rdev->config.evergreen.max_stack_entries = 256;
1911                 rdev->config.evergreen.sx_num_of_sets = 4;
1912                 rdev->config.evergreen.sx_max_export_size = 256;
1913                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1914                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1915                 rdev->config.evergreen.max_hw_contexts = 8;
1916                 rdev->config.evergreen.sq_num_cf_insts = 2;
1917
1918                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1919                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1920                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1921                 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
1922                 break;
1923         case CHIP_CAICOS:
1924                 rdev->config.evergreen.num_ses = 1;
1925                 rdev->config.evergreen.max_pipes = 2;
1926                 rdev->config.evergreen.max_tile_pipes = 2;
1927                 rdev->config.evergreen.max_simds = 2;
1928                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1929                 rdev->config.evergreen.max_gprs = 256;
1930                 rdev->config.evergreen.max_threads = 192;
1931                 rdev->config.evergreen.max_gs_threads = 16;
1932                 rdev->config.evergreen.max_stack_entries = 256;
1933                 rdev->config.evergreen.sx_num_of_sets = 4;
1934                 rdev->config.evergreen.sx_max_export_size = 128;
1935                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1936                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1937                 rdev->config.evergreen.max_hw_contexts = 4;
1938                 rdev->config.evergreen.sq_num_cf_insts = 1;
1939
1940                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1941                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1942                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1943                 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
1944                 break;
1945         }
1946
1947         /* Initialize HDP */
1948         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1949                 WREG32((0x2c14 + j), 0x00000000);
1950                 WREG32((0x2c18 + j), 0x00000000);
1951                 WREG32((0x2c1c + j), 0x00000000);
1952                 WREG32((0x2c20 + j), 0x00000000);
1953                 WREG32((0x2c24 + j), 0x00000000);
1954         }
1955
1956         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1957
1958         evergreen_fix_pci_max_read_req_size(rdev);
1959
1960         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1961         if ((rdev->family == CHIP_PALM) ||
1962             (rdev->family == CHIP_SUMO) ||
1963             (rdev->family == CHIP_SUMO2))
1964                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1965         else
1966                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1967
1968         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1969          * not have bank info, so create a custom tiling dword.
1970          * bits 3:0   num_pipes
1971          * bits 7:4   num_banks
1972          * bits 11:8  group_size
1973          * bits 15:12 row_size
1974          */
1975         rdev->config.evergreen.tile_config = 0;
1976         switch (rdev->config.evergreen.max_tile_pipes) {
1977         case 1:
1978         default:
1979                 rdev->config.evergreen.tile_config |= (0 << 0);
1980                 break;
1981         case 2:
1982                 rdev->config.evergreen.tile_config |= (1 << 0);
1983                 break;
1984         case 4:
1985                 rdev->config.evergreen.tile_config |= (2 << 0);
1986                 break;
1987         case 8:
1988                 rdev->config.evergreen.tile_config |= (3 << 0);
1989                 break;
1990         }
1991         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1992         if (rdev->flags & RADEON_IS_IGP)
1993                 rdev->config.evergreen.tile_config |= 1 << 4;
1994         else {
1995                 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1996                 case 0: /* four banks */
1997                         rdev->config.evergreen.tile_config |= 0 << 4;
1998                         break;
1999                 case 1: /* eight banks */
2000                         rdev->config.evergreen.tile_config |= 1 << 4;
2001                         break;
2002                 case 2: /* sixteen banks */
2003                 default:
2004                         rdev->config.evergreen.tile_config |= 2 << 4;
2005                         break;
2006                 }
2007         }
2008         rdev->config.evergreen.tile_config |= 0 << 8;
2009         rdev->config.evergreen.tile_config |=
2010                 ((gb_addr_config & 0x30000000) >> 28) << 12;
2011
2012         num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
2013
2014         if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
2015                 u32 efuse_straps_4;
2016                 u32 efuse_straps_3;
2017
2018                 WREG32(RCU_IND_INDEX, 0x204);
2019                 efuse_straps_4 = RREG32(RCU_IND_DATA);
2020                 WREG32(RCU_IND_INDEX, 0x203);
2021                 efuse_straps_3 = RREG32(RCU_IND_DATA);
2022                 tmp = (((efuse_straps_4 & 0xf) << 4) |
2023                       ((efuse_straps_3 & 0xf0000000) >> 28));
2024         } else {
2025                 tmp = 0;
2026                 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
2027                         u32 rb_disable_bitmap;
2028
2029                         WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2030                         WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2031                         rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
2032                         tmp <<= 4;
2033                         tmp |= rb_disable_bitmap;
2034                 }
2035         }
2036         /* enabled rb are just the one not disabled :) */
2037         disabled_rb_mask = tmp;
2038
2039         WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2040         WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2041
2042         WREG32(GB_ADDR_CONFIG, gb_addr_config);
2043         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2044         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2045         WREG32(DMA_TILING_CONFIG, gb_addr_config);
2046
2047         if ((rdev->config.evergreen.max_backends == 1) &&
2048             (rdev->flags & RADEON_IS_IGP)) {
2049                 if ((disabled_rb_mask & 3) == 1) {
2050                         /* RB0 disabled, RB1 enabled */
2051                         tmp = 0x11111111;
2052                 } else {
2053                         /* RB1 disabled, RB0 enabled */
2054                         tmp = 0x00000000;
2055                 }
2056         } else {
2057                 tmp = gb_addr_config & NUM_PIPES_MASK;
2058                 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
2059                                                 EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
2060         }
2061         WREG32(GB_BACKEND_MAP, tmp);
2062
2063         WREG32(CGTS_SYS_TCC_DISABLE, 0);
2064         WREG32(CGTS_TCC_DISABLE, 0);
2065         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2066         WREG32(CGTS_USER_TCC_DISABLE, 0);
2067
2068         /* set HW defaults for 3D engine */
2069         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2070                                      ROQ_IB2_START(0x2b)));
2071
2072         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2073
2074         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2075                              SYNC_GRADIENT |
2076                              SYNC_WALKER |
2077                              SYNC_ALIGNER));
2078
2079         sx_debug_1 = RREG32(SX_DEBUG_1);
2080         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2081         WREG32(SX_DEBUG_1, sx_debug_1);
2082
2083
2084         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2085         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2086         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2087         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2088
2089         if (rdev->family <= CHIP_SUMO2)
2090                 WREG32(SMX_SAR_CTL0, 0x00010000);
2091
2092         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2093                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2094                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2095
2096         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2097                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2098                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2099
2100         WREG32(VGT_NUM_INSTANCES, 1);
2101         WREG32(SPI_CONFIG_CNTL, 0);
2102         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2103         WREG32(CP_PERFMON_CNTL, 0);
2104
2105         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2106                                   FETCH_FIFO_HIWATER(0x4) |
2107                                   DONE_FIFO_HIWATER(0xe0) |
2108                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2109
2110         sq_config = RREG32(SQ_CONFIG);
2111         sq_config &= ~(PS_PRIO(3) |
2112                        VS_PRIO(3) |
2113                        GS_PRIO(3) |
2114                        ES_PRIO(3));
2115         sq_config |= (VC_ENABLE |
2116                       EXPORT_SRC_C |
2117                       PS_PRIO(0) |
2118                       VS_PRIO(1) |
2119                       GS_PRIO(2) |
2120                       ES_PRIO(3));
2121
2122         switch (rdev->family) {
2123         case CHIP_CEDAR:
2124         case CHIP_PALM:
2125         case CHIP_SUMO:
2126         case CHIP_SUMO2:
2127         case CHIP_CAICOS:
2128                 /* no vertex cache */
2129                 sq_config &= ~VC_ENABLE;
2130                 break;
2131         default:
2132                 break;
2133         }
2134
2135         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2136
2137         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2138         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2139         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2140         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2141         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2142         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2143         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2144
2145         switch (rdev->family) {
2146         case CHIP_CEDAR:
2147         case CHIP_PALM:
2148         case CHIP_SUMO:
2149         case CHIP_SUMO2:
2150                 ps_thread_count = 96;
2151                 break;
2152         default:
2153                 ps_thread_count = 128;
2154                 break;
2155         }
2156
2157         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2158         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2159         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2160         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2161         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2162         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2163
2164         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2165         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2166         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2167         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2168         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2169         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2170
2171         WREG32(SQ_CONFIG, sq_config);
2172         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2173         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2174         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2175         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2176         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2177         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2178         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2179         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2180         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2181         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2182
2183         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2184                                           FORCE_EOV_MAX_REZ_CNT(255)));
2185
2186         switch (rdev->family) {
2187         case CHIP_CEDAR:
2188         case CHIP_PALM:
2189         case CHIP_SUMO:
2190         case CHIP_SUMO2:
2191         case CHIP_CAICOS:
2192                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2193                 break;
2194         default:
2195                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2196                 break;
2197         }
2198         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2199         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2200
2201         WREG32(VGT_GS_VERTEX_REUSE, 16);
2202         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2203         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2204
2205         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2206         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2207
2208         WREG32(CB_PERF_CTR0_SEL_0, 0);
2209         WREG32(CB_PERF_CTR0_SEL_1, 0);
2210         WREG32(CB_PERF_CTR1_SEL_0, 0);
2211         WREG32(CB_PERF_CTR1_SEL_1, 0);
2212         WREG32(CB_PERF_CTR2_SEL_0, 0);
2213         WREG32(CB_PERF_CTR2_SEL_1, 0);
2214         WREG32(CB_PERF_CTR3_SEL_0, 0);
2215         WREG32(CB_PERF_CTR3_SEL_1, 0);
2216
2217         /* clear render buffer base addresses */
2218         WREG32(CB_COLOR0_BASE, 0);
2219         WREG32(CB_COLOR1_BASE, 0);
2220         WREG32(CB_COLOR2_BASE, 0);
2221         WREG32(CB_COLOR3_BASE, 0);
2222         WREG32(CB_COLOR4_BASE, 0);
2223         WREG32(CB_COLOR5_BASE, 0);
2224         WREG32(CB_COLOR6_BASE, 0);
2225         WREG32(CB_COLOR7_BASE, 0);
2226         WREG32(CB_COLOR8_BASE, 0);
2227         WREG32(CB_COLOR9_BASE, 0);
2228         WREG32(CB_COLOR10_BASE, 0);
2229         WREG32(CB_COLOR11_BASE, 0);
2230
2231         /* set the shader const cache sizes to 0 */
2232         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2233                 WREG32(i, 0);
2234         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2235                 WREG32(i, 0);
2236
2237         tmp = RREG32(HDP_MISC_CNTL);
2238         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2239         WREG32(HDP_MISC_CNTL, tmp);
2240
2241         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2242         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2243
2244         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2245
2246         udelay(50);
2247
2248 }
2249
2250 int evergreen_mc_init(struct radeon_device *rdev)
2251 {
2252         u32 tmp;
2253         int chansize, numchan;
2254
2255         /* Get VRAM informations */
2256         rdev->mc.vram_is_ddr = true;
2257         if ((rdev->family == CHIP_PALM) ||
2258             (rdev->family == CHIP_SUMO) ||
2259             (rdev->family == CHIP_SUMO2))
2260                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2261         else
2262                 tmp = RREG32(MC_ARB_RAMCFG);
2263         if (tmp & CHANSIZE_OVERRIDE) {
2264                 chansize = 16;
2265         } else if (tmp & CHANSIZE_MASK) {
2266                 chansize = 64;
2267         } else {
2268                 chansize = 32;
2269         }
2270         tmp = RREG32(MC_SHARED_CHMAP);
2271         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2272         case 0:
2273         default:
2274                 numchan = 1;
2275                 break;
2276         case 1:
2277                 numchan = 2;
2278                 break;
2279         case 2:
2280                 numchan = 4;
2281                 break;
2282         case 3:
2283                 numchan = 8;
2284                 break;
2285         }
2286         rdev->mc.vram_width = numchan * chansize;
2287         /* Could aper size report 0 ? */
2288         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2289         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2290         /* Setup GPU memory space */
2291         if ((rdev->family == CHIP_PALM) ||
2292             (rdev->family == CHIP_SUMO) ||
2293             (rdev->family == CHIP_SUMO2)) {
2294                 /* size in bytes on fusion */
2295                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2296                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2297         } else {
2298                 /* size in MB on evergreen/cayman/tn */
2299                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2300                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2301         }
2302         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2303         r700_vram_gtt_location(rdev, &rdev->mc);
2304         radeon_update_bandwidth_info(rdev);
2305
2306         return 0;
2307 }
2308
2309 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2310 {
2311         u32 srbm_status;
2312         u32 grbm_status;
2313         u32 grbm_status_se0, grbm_status_se1;
2314
2315         srbm_status = RREG32(SRBM_STATUS);
2316         grbm_status = RREG32(GRBM_STATUS);
2317         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2318         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2319         if (!(grbm_status & GUI_ACTIVE)) {
2320                 radeon_ring_lockup_update(ring);
2321                 return false;
2322         }
2323         /* force CP activities */
2324         radeon_ring_force_activity(rdev, ring);
2325         return radeon_ring_test_lockup(rdev, ring);
2326 }
2327
2328 static void evergreen_gpu_soft_reset_gfx(struct radeon_device *rdev)
2329 {
2330         u32 grbm_reset = 0;
2331
2332         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2333                 return;
2334
2335         dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
2336                 RREG32(GRBM_STATUS));
2337         dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
2338                 RREG32(GRBM_STATUS_SE0));
2339         dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
2340                 RREG32(GRBM_STATUS_SE1));
2341         dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
2342                 RREG32(SRBM_STATUS));
2343         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2344                 RREG32(CP_STALLED_STAT1));
2345         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2346                 RREG32(CP_STALLED_STAT2));
2347         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
2348                 RREG32(CP_BUSY_STAT));
2349         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
2350                 RREG32(CP_STAT));
2351
2352         /* Disable CP parsing/prefetching */
2353         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2354
2355         /* reset all the gfx blocks */
2356         grbm_reset = (SOFT_RESET_CP |
2357                       SOFT_RESET_CB |
2358                       SOFT_RESET_DB |
2359                       SOFT_RESET_PA |
2360                       SOFT_RESET_SC |
2361                       SOFT_RESET_SPI |
2362                       SOFT_RESET_SH |
2363                       SOFT_RESET_SX |
2364                       SOFT_RESET_TC |
2365                       SOFT_RESET_TA |
2366                       SOFT_RESET_VC |
2367                       SOFT_RESET_VGT);
2368
2369         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2370         WREG32(GRBM_SOFT_RESET, grbm_reset);
2371         (void)RREG32(GRBM_SOFT_RESET);
2372         udelay(50);
2373         WREG32(GRBM_SOFT_RESET, 0);
2374         (void)RREG32(GRBM_SOFT_RESET);
2375
2376         dev_info(rdev->dev, "  GRBM_STATUS               = 0x%08X\n",
2377                 RREG32(GRBM_STATUS));
2378         dev_info(rdev->dev, "  GRBM_STATUS_SE0           = 0x%08X\n",
2379                 RREG32(GRBM_STATUS_SE0));
2380         dev_info(rdev->dev, "  GRBM_STATUS_SE1           = 0x%08X\n",
2381                 RREG32(GRBM_STATUS_SE1));
2382         dev_info(rdev->dev, "  SRBM_STATUS               = 0x%08X\n",
2383                 RREG32(SRBM_STATUS));
2384         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2385                 RREG32(CP_STALLED_STAT1));
2386         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2387                 RREG32(CP_STALLED_STAT2));
2388         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
2389                 RREG32(CP_BUSY_STAT));
2390         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
2391                 RREG32(CP_STAT));
2392 }
2393
2394 static void evergreen_gpu_soft_reset_dma(struct radeon_device *rdev)
2395 {
2396         u32 tmp;
2397
2398         if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
2399                 return;
2400
2401         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
2402                 RREG32(DMA_STATUS_REG));
2403
2404         /* Disable DMA */
2405         tmp = RREG32(DMA_RB_CNTL);
2406         tmp &= ~DMA_RB_ENABLE;
2407         WREG32(DMA_RB_CNTL, tmp);
2408
2409         /* Reset dma */
2410         WREG32(SRBM_SOFT_RESET, SOFT_RESET_DMA);
2411         RREG32(SRBM_SOFT_RESET);
2412         udelay(50);
2413         WREG32(SRBM_SOFT_RESET, 0);
2414
2415         dev_info(rdev->dev, "  R_00D034_DMA_STATUS_REG   = 0x%08X\n",
2416                 RREG32(DMA_STATUS_REG));
2417 }
2418
2419 static int evergreen_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
2420 {
2421         struct evergreen_mc_save save;
2422
2423         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2424                 reset_mask &= ~(RADEON_RESET_GFX | RADEON_RESET_COMPUTE);
2425
2426         if (RREG32(DMA_STATUS_REG) & DMA_IDLE)
2427                 reset_mask &= ~RADEON_RESET_DMA;
2428
2429         if (reset_mask == 0)
2430                 return 0;
2431
2432         dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
2433
2434         evergreen_mc_stop(rdev, &save);
2435         if (evergreen_mc_wait_for_idle(rdev)) {
2436                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2437         }
2438
2439         if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE))
2440                 evergreen_gpu_soft_reset_gfx(rdev);
2441
2442         if (reset_mask & RADEON_RESET_DMA)
2443                 evergreen_gpu_soft_reset_dma(rdev);
2444
2445         /* Wait a little for things to settle down */
2446         udelay(50);
2447
2448         evergreen_mc_resume(rdev, &save);
2449         return 0;
2450 }
2451
2452 int evergreen_asic_reset(struct radeon_device *rdev)
2453 {
2454         return evergreen_gpu_soft_reset(rdev, (RADEON_RESET_GFX |
2455                                                RADEON_RESET_COMPUTE |
2456                                                RADEON_RESET_DMA));
2457 }
2458
2459 /* Interrupts */
2460
2461 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2462 {
2463         if (crtc >= rdev->num_crtc)
2464                 return 0;
2465         else
2466                 return RREG32(CRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
2467 }
2468
2469 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2470 {
2471         u32 tmp;
2472
2473         if (rdev->family >= CHIP_CAYMAN) {
2474                 cayman_cp_int_cntl_setup(rdev, 0,
2475                                          CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2476                 cayman_cp_int_cntl_setup(rdev, 1, 0);
2477                 cayman_cp_int_cntl_setup(rdev, 2, 0);
2478                 tmp = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2479                 WREG32(CAYMAN_DMA1_CNTL, tmp);
2480         } else
2481                 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2482         tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2483         WREG32(DMA_CNTL, tmp);
2484         WREG32(GRBM_INT_CNTL, 0);
2485         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2486         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2487         if (rdev->num_crtc >= 4) {
2488                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2489                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2490         }
2491         if (rdev->num_crtc >= 6) {
2492                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2493                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2494         }
2495
2496         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2497         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2498         if (rdev->num_crtc >= 4) {
2499                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2500                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2501         }
2502         if (rdev->num_crtc >= 6) {
2503                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2504                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2505         }
2506
2507         /* only one DAC on DCE6 */
2508         if (!ASIC_IS_DCE6(rdev))
2509                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2510         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2511
2512         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2513         WREG32(DC_HPD1_INT_CONTROL, tmp);
2514         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2515         WREG32(DC_HPD2_INT_CONTROL, tmp);
2516         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2517         WREG32(DC_HPD3_INT_CONTROL, tmp);
2518         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2519         WREG32(DC_HPD4_INT_CONTROL, tmp);
2520         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2521         WREG32(DC_HPD5_INT_CONTROL, tmp);
2522         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2523         WREG32(DC_HPD6_INT_CONTROL, tmp);
2524
2525 }
2526
2527 int evergreen_irq_set(struct radeon_device *rdev)
2528 {
2529         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2530         u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
2531         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2532         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2533         u32 grbm_int_cntl = 0;
2534         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2535         u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
2536         u32 dma_cntl, dma_cntl1 = 0;
2537
2538         if (!rdev->irq.installed) {
2539                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2540                 return -EINVAL;
2541         }
2542         /* don't enable anything if the ih is disabled */
2543         if (!rdev->ih.enabled) {
2544                 r600_disable_interrupts(rdev);
2545                 /* force the active interrupt state to all disabled */
2546                 evergreen_disable_interrupt_state(rdev);
2547                 return 0;
2548         }
2549
2550         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2551         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2552         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2553         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2554         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2555         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2556
2557         afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2558         afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2559         afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2560         afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2561         afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2562         afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2563
2564         dma_cntl = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
2565
2566         if (rdev->family >= CHIP_CAYMAN) {
2567                 /* enable CP interrupts on all rings */
2568                 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2569                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2570                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2571                 }
2572                 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
2573                         DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2574                         cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2575                 }
2576                 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
2577                         DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2578                         cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2579                 }
2580         } else {
2581                 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2582                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2583                         cp_int_cntl |= RB_INT_ENABLE;
2584                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2585                 }
2586         }
2587
2588         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
2589                 DRM_DEBUG("r600_irq_set: sw int dma\n");
2590                 dma_cntl |= TRAP_ENABLE;
2591         }
2592
2593         if (rdev->family >= CHIP_CAYMAN) {
2594                 dma_cntl1 = RREG32(CAYMAN_DMA1_CNTL) & ~TRAP_ENABLE;
2595                 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
2596                         DRM_DEBUG("r600_irq_set: sw int dma1\n");
2597                         dma_cntl1 |= TRAP_ENABLE;
2598                 }
2599         }
2600
2601         if (rdev->irq.crtc_vblank_int[0] ||
2602             atomic_read(&rdev->irq.pflip[0])) {
2603                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2604                 crtc1 |= VBLANK_INT_MASK;
2605         }
2606         if (rdev->irq.crtc_vblank_int[1] ||
2607             atomic_read(&rdev->irq.pflip[1])) {
2608                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2609                 crtc2 |= VBLANK_INT_MASK;
2610         }
2611         if (rdev->irq.crtc_vblank_int[2] ||
2612             atomic_read(&rdev->irq.pflip[2])) {
2613                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2614                 crtc3 |= VBLANK_INT_MASK;
2615         }
2616         if (rdev->irq.crtc_vblank_int[3] ||
2617             atomic_read(&rdev->irq.pflip[3])) {
2618                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2619                 crtc4 |= VBLANK_INT_MASK;
2620         }
2621         if (rdev->irq.crtc_vblank_int[4] ||
2622             atomic_read(&rdev->irq.pflip[4])) {
2623                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2624                 crtc5 |= VBLANK_INT_MASK;
2625         }
2626         if (rdev->irq.crtc_vblank_int[5] ||
2627             atomic_read(&rdev->irq.pflip[5])) {
2628                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2629                 crtc6 |= VBLANK_INT_MASK;
2630         }
2631         if (rdev->irq.hpd[0]) {
2632                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2633                 hpd1 |= DC_HPDx_INT_EN;
2634         }
2635         if (rdev->irq.hpd[1]) {
2636                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2637                 hpd2 |= DC_HPDx_INT_EN;
2638         }
2639         if (rdev->irq.hpd[2]) {
2640                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2641                 hpd3 |= DC_HPDx_INT_EN;
2642         }
2643         if (rdev->irq.hpd[3]) {
2644                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2645                 hpd4 |= DC_HPDx_INT_EN;
2646         }
2647         if (rdev->irq.hpd[4]) {
2648                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2649                 hpd5 |= DC_HPDx_INT_EN;
2650         }
2651         if (rdev->irq.hpd[5]) {
2652                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2653                 hpd6 |= DC_HPDx_INT_EN;
2654         }
2655         if (rdev->irq.afmt[0]) {
2656                 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2657                 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2658         }
2659         if (rdev->irq.afmt[1]) {
2660                 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2661                 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2662         }
2663         if (rdev->irq.afmt[2]) {
2664                 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2665                 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2666         }
2667         if (rdev->irq.afmt[3]) {
2668                 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2669                 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2670         }
2671         if (rdev->irq.afmt[4]) {
2672                 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2673                 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2674         }
2675         if (rdev->irq.afmt[5]) {
2676                 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2677                 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2678         }
2679
2680         if (rdev->family >= CHIP_CAYMAN) {
2681                 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2682                 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2683                 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2684         } else
2685                 WREG32(CP_INT_CNTL, cp_int_cntl);
2686
2687         WREG32(DMA_CNTL, dma_cntl);
2688
2689         if (rdev->family >= CHIP_CAYMAN)
2690                 WREG32(CAYMAN_DMA1_CNTL, dma_cntl1);
2691
2692         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2693
2694         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2695         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2696         if (rdev->num_crtc >= 4) {
2697                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2698                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2699         }
2700         if (rdev->num_crtc >= 6) {
2701                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2702                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2703         }
2704
2705         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2706         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2707         if (rdev->num_crtc >= 4) {
2708                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2709                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2710         }
2711         if (rdev->num_crtc >= 6) {
2712                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2713                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2714         }
2715
2716         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2717         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2718         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2719         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2720         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2721         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2722
2723         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2724         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2725         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2726         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2727         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2728         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2729
2730         return 0;
2731 }
2732
2733 static void evergreen_irq_ack(struct radeon_device *rdev)
2734 {
2735         u32 tmp;
2736
2737         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2738         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2739         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2740         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2741         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2742         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2743         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2744         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2745         if (rdev->num_crtc >= 4) {
2746                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2747                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2748         }
2749         if (rdev->num_crtc >= 6) {
2750                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2751                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2752         }
2753
2754         rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2755         rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2756         rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2757         rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2758         rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2759         rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2760
2761         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2762                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2763         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2764                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2765         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2766                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2767         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2768                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2769         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2770                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2771         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2772                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2773
2774         if (rdev->num_crtc >= 4) {
2775                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2776                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2777                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2778                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2779                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2780                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2781                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2782                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2783                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2784                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2785                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2786                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2787         }
2788
2789         if (rdev->num_crtc >= 6) {
2790                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2791                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2792                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2793                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2794                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2795                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2796                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2797                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2798                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2799                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2800                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2801                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2802         }
2803
2804         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2805                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2806                 tmp |= DC_HPDx_INT_ACK;
2807                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2808         }
2809         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2810                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2811                 tmp |= DC_HPDx_INT_ACK;
2812                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2813         }
2814         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2815                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2816                 tmp |= DC_HPDx_INT_ACK;
2817                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2818         }
2819         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2820                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2821                 tmp |= DC_HPDx_INT_ACK;
2822                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2823         }
2824         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2825                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2826                 tmp |= DC_HPDx_INT_ACK;
2827                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2828         }
2829         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2830                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2831                 tmp |= DC_HPDx_INT_ACK;
2832                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2833         }
2834         if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2835                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2836                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2837                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2838         }
2839         if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2840                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2841                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2842                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2843         }
2844         if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2845                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2846                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2847                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2848         }
2849         if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2850                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
2851                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2852                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
2853         }
2854         if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2855                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
2856                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2857                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
2858         }
2859         if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2860                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2861                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2862                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2863         }
2864 }
2865
2866 static void evergreen_irq_disable(struct radeon_device *rdev)
2867 {
2868         r600_disable_interrupts(rdev);
2869         /* Wait and acknowledge irq */
2870         mdelay(1);
2871         evergreen_irq_ack(rdev);
2872         evergreen_disable_interrupt_state(rdev);
2873 }
2874
2875 void evergreen_irq_suspend(struct radeon_device *rdev)
2876 {
2877         evergreen_irq_disable(rdev);
2878         r600_rlc_stop(rdev);
2879 }
2880
2881 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2882 {
2883         u32 wptr, tmp;
2884
2885         if (rdev->wb.enabled)
2886                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2887         else
2888                 wptr = RREG32(IH_RB_WPTR);
2889
2890         if (wptr & RB_OVERFLOW) {
2891                 /* When a ring buffer overflow happen start parsing interrupt
2892                  * from the last not overwritten vector (wptr + 16). Hopefully
2893                  * this should allow us to catchup.
2894                  */
2895                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2896                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2897                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2898                 tmp = RREG32(IH_RB_CNTL);
2899                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2900                 WREG32(IH_RB_CNTL, tmp);
2901         }
2902         return (wptr & rdev->ih.ptr_mask);
2903 }
2904
2905 int evergreen_irq_process(struct radeon_device *rdev)
2906 {
2907         u32 wptr;
2908         u32 rptr;
2909         u32 src_id, src_data;
2910         u32 ring_index;
2911         bool queue_hotplug = false;
2912         bool queue_hdmi = false;
2913
2914         if (!rdev->ih.enabled || rdev->shutdown)
2915                 return IRQ_NONE;
2916
2917         wptr = evergreen_get_ih_wptr(rdev);
2918
2919 restart_ih:
2920         /* is somebody else already processing irqs? */
2921         if (atomic_xchg(&rdev->ih.lock, 1))
2922                 return IRQ_NONE;
2923
2924         rptr = rdev->ih.rptr;
2925         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2926
2927         /* Order reading of wptr vs. reading of IH ring data */
2928         rmb();
2929
2930         /* display interrupts */
2931         evergreen_irq_ack(rdev);
2932
2933         while (rptr != wptr) {
2934                 /* wptr/rptr are in bytes! */
2935                 ring_index = rptr / 4;
2936                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2937                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2938
2939                 switch (src_id) {
2940                 case 1: /* D1 vblank/vline */
2941                         switch (src_data) {
2942                         case 0: /* D1 vblank */
2943                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2944                                         if (rdev->irq.crtc_vblank_int[0]) {
2945                                                 drm_handle_vblank(rdev->ddev, 0);
2946                                                 rdev->pm.vblank_sync = true;
2947                                                 wake_up(&rdev->irq.vblank_queue);
2948                                         }
2949                                         if (atomic_read(&rdev->irq.pflip[0]))
2950                                                 radeon_crtc_handle_flip(rdev, 0);
2951                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2952                                         DRM_DEBUG("IH: D1 vblank\n");
2953                                 }
2954                                 break;
2955                         case 1: /* D1 vline */
2956                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2957                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2958                                         DRM_DEBUG("IH: D1 vline\n");
2959                                 }
2960                                 break;
2961                         default:
2962                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2963                                 break;
2964                         }
2965                         break;
2966                 case 2: /* D2 vblank/vline */
2967                         switch (src_data) {
2968                         case 0: /* D2 vblank */
2969                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2970                                         if (rdev->irq.crtc_vblank_int[1]) {
2971                                                 drm_handle_vblank(rdev->ddev, 1);
2972                                                 rdev->pm.vblank_sync = true;
2973                                                 wake_up(&rdev->irq.vblank_queue);
2974                                         }
2975                                         if (atomic_read(&rdev->irq.pflip[1]))
2976                                                 radeon_crtc_handle_flip(rdev, 1);
2977                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2978                                         DRM_DEBUG("IH: D2 vblank\n");
2979                                 }
2980                                 break;
2981                         case 1: /* D2 vline */
2982                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2983                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2984                                         DRM_DEBUG("IH: D2 vline\n");
2985                                 }
2986                                 break;
2987                         default:
2988                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2989                                 break;
2990                         }
2991                         break;
2992                 case 3: /* D3 vblank/vline */
2993                         switch (src_data) {
2994                         case 0: /* D3 vblank */
2995                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2996                                         if (rdev->irq.crtc_vblank_int[2]) {
2997                                                 drm_handle_vblank(rdev->ddev, 2);
2998                                                 rdev->pm.vblank_sync = true;
2999                                                 wake_up(&rdev->irq.vblank_queue);
3000                                         }
3001                                         if (atomic_read(&rdev->irq.pflip[2]))
3002                                                 radeon_crtc_handle_flip(rdev, 2);
3003                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
3004                                         DRM_DEBUG("IH: D3 vblank\n");
3005                                 }
3006                                 break;
3007                         case 1: /* D3 vline */
3008                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
3009                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
3010                                         DRM_DEBUG("IH: D3 vline\n");
3011                                 }
3012                                 break;
3013                         default:
3014                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3015                                 break;
3016                         }
3017                         break;
3018                 case 4: /* D4 vblank/vline */
3019                         switch (src_data) {
3020                         case 0: /* D4 vblank */
3021                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
3022                                         if (rdev->irq.crtc_vblank_int[3]) {
3023                                                 drm_handle_vblank(rdev->ddev, 3);
3024                                                 rdev->pm.vblank_sync = true;
3025                                                 wake_up(&rdev->irq.vblank_queue);
3026                                         }
3027                                         if (atomic_read(&rdev->irq.pflip[3]))
3028                                                 radeon_crtc_handle_flip(rdev, 3);
3029                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
3030                                         DRM_DEBUG("IH: D4 vblank\n");
3031                                 }
3032                                 break;
3033                         case 1: /* D4 vline */
3034                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
3035                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
3036                                         DRM_DEBUG("IH: D4 vline\n");
3037                                 }
3038                                 break;
3039                         default:
3040                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3041                                 break;
3042                         }
3043                         break;
3044                 case 5: /* D5 vblank/vline */
3045                         switch (src_data) {
3046                         case 0: /* D5 vblank */
3047                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
3048                                         if (rdev->irq.crtc_vblank_int[4]) {
3049                                                 drm_handle_vblank(rdev->ddev, 4);
3050                                                 rdev->pm.vblank_sync = true;
3051                                                 wake_up(&rdev->irq.vblank_queue);
3052                                         }
3053                                         if (atomic_read(&rdev->irq.pflip[4]))
3054                                                 radeon_crtc_handle_flip(rdev, 4);
3055                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
3056                                         DRM_DEBUG("IH: D5 vblank\n");
3057                                 }
3058                                 break;
3059                         case 1: /* D5 vline */
3060                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
3061                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
3062                                         DRM_DEBUG("IH: D5 vline\n");
3063                                 }
3064                                 break;
3065                         default:
3066                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3067                                 break;
3068                         }
3069                         break;
3070                 case 6: /* D6 vblank/vline */
3071                         switch (src_data) {
3072                         case 0: /* D6 vblank */
3073                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3074                                         if (rdev->irq.crtc_vblank_int[5]) {
3075                                                 drm_handle_vblank(rdev->ddev, 5);
3076                                                 rdev->pm.vblank_sync = true;
3077                                                 wake_up(&rdev->irq.vblank_queue);
3078                                         }
3079                                         if (atomic_read(&rdev->irq.pflip[5]))
3080                                                 radeon_crtc_handle_flip(rdev, 5);
3081                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3082                                         DRM_DEBUG("IH: D6 vblank\n");
3083                                 }
3084                                 break;
3085                         case 1: /* D6 vline */
3086                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3087                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3088                                         DRM_DEBUG("IH: D6 vline\n");
3089                                 }
3090                                 break;
3091                         default:
3092                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3093                                 break;
3094                         }
3095                         break;
3096                 case 42: /* HPD hotplug */
3097                         switch (src_data) {
3098                         case 0:
3099                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3100                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3101                                         queue_hotplug = true;
3102                                         DRM_DEBUG("IH: HPD1\n");
3103                                 }
3104                                 break;
3105                         case 1:
3106                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3107                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3108                                         queue_hotplug = true;
3109                                         DRM_DEBUG("IH: HPD2\n");
3110                                 }
3111                                 break;
3112                         case 2:
3113                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3114                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3115                                         queue_hotplug = true;
3116                                         DRM_DEBUG("IH: HPD3\n");
3117                                 }
3118                                 break;
3119                         case 3:
3120                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3121                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3122                                         queue_hotplug = true;
3123                                         DRM_DEBUG("IH: HPD4\n");
3124                                 }
3125                                 break;
3126                         case 4:
3127                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3128                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3129                                         queue_hotplug = true;
3130                                         DRM_DEBUG("IH: HPD5\n");
3131                                 }
3132                                 break;
3133                         case 5:
3134                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3135                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3136                                         queue_hotplug = true;
3137                                         DRM_DEBUG("IH: HPD6\n");
3138                                 }
3139                                 break;
3140                         default:
3141                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3142                                 break;
3143                         }
3144                         break;
3145                 case 44: /* hdmi */
3146                         switch (src_data) {
3147                         case 0:
3148                                 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3149                                         rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
3150                                         queue_hdmi = true;
3151                                         DRM_DEBUG("IH: HDMI0\n");
3152                                 }
3153                                 break;
3154                         case 1:
3155                                 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3156                                         rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
3157                                         queue_hdmi = true;
3158                                         DRM_DEBUG("IH: HDMI1\n");
3159                                 }
3160                                 break;
3161                         case 2:
3162                                 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3163                                         rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
3164                                         queue_hdmi = true;
3165                                         DRM_DEBUG("IH: HDMI2\n");
3166                                 }
3167                                 break;
3168                         case 3:
3169                                 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3170                                         rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
3171                                         queue_hdmi = true;
3172                                         DRM_DEBUG("IH: HDMI3\n");
3173                                 }
3174                                 break;
3175                         case 4:
3176                                 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3177                                         rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
3178                                         queue_hdmi = true;
3179                                         DRM_DEBUG("IH: HDMI4\n");
3180                                 }
3181                                 break;
3182                         case 5:
3183                                 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3184                                         rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
3185                                         queue_hdmi = true;
3186                                         DRM_DEBUG("IH: HDMI5\n");
3187                                 }
3188                                 break;
3189                         default:
3190                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3191                                 break;
3192                         }
3193                         break;
3194                 case 146:
3195                 case 147:
3196                         dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
3197                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
3198                                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
3199                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
3200                                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
3201                         /* reset addr and status */
3202                         WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
3203                         break;
3204                 case 176: /* CP_INT in ring buffer */
3205                 case 177: /* CP_INT in IB1 */
3206                 case 178: /* CP_INT in IB2 */
3207                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3208                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3209                         break;
3210                 case 181: /* CP EOP event */
3211                         DRM_DEBUG("IH: CP EOP\n");
3212                         if (rdev->family >= CHIP_CAYMAN) {
3213                                 switch (src_data) {
3214                                 case 0:
3215                                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3216                                         break;
3217                                 case 1:
3218                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3219                                         break;
3220                                 case 2:
3221                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3222                                         break;
3223                                 }
3224                         } else
3225                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3226                         break;
3227                 case 224: /* DMA trap event */
3228                         DRM_DEBUG("IH: DMA trap\n");
3229                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
3230                         break;
3231                 case 233: /* GUI IDLE */
3232                         DRM_DEBUG("IH: GUI idle\n");
3233                         break;
3234                 case 244: /* DMA trap event */
3235                         if (rdev->family >= CHIP_CAYMAN) {
3236                                 DRM_DEBUG("IH: DMA1 trap\n");
3237                                 radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
3238                         }
3239                         break;
3240                 default:
3241                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3242                         break;
3243                 }
3244
3245                 /* wptr/rptr are in bytes! */
3246                 rptr += 16;
3247                 rptr &= rdev->ih.ptr_mask;
3248         }
3249         if (queue_hotplug)
3250                 schedule_work(&rdev->hotplug_work);
3251         if (queue_hdmi)
3252                 schedule_work(&rdev->audio_work);
3253         rdev->ih.rptr = rptr;
3254         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3255         atomic_set(&rdev->ih.lock, 0);
3256
3257         /* make sure wptr hasn't changed while processing */
3258         wptr = evergreen_get_ih_wptr(rdev);
3259         if (wptr != rptr)
3260                 goto restart_ih;
3261
3262         return IRQ_HANDLED;
3263 }
3264
3265 /**
3266  * evergreen_dma_fence_ring_emit - emit a fence on the DMA ring
3267  *
3268  * @rdev: radeon_device pointer
3269  * @fence: radeon fence object
3270  *
3271  * Add a DMA fence packet to the ring to write
3272  * the fence seq number and DMA trap packet to generate
3273  * an interrupt if needed (evergreen-SI).
3274  */
3275 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
3276                                    struct radeon_fence *fence)
3277 {
3278         struct radeon_ring *ring = &rdev->ring[fence->ring];
3279         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
3280         /* write the fence */
3281         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_FENCE, 0, 0, 0));
3282         radeon_ring_write(ring, addr & 0xfffffffc);
3283         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff));
3284         radeon_ring_write(ring, fence->seq);
3285         /* generate an interrupt */
3286         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_TRAP, 0, 0, 0));
3287         /* flush HDP */
3288         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0));
3289         radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2));
3290         radeon_ring_write(ring, 1);
3291 }
3292
3293 /**
3294  * evergreen_dma_ring_ib_execute - schedule an IB on the DMA engine
3295  *
3296  * @rdev: radeon_device pointer
3297  * @ib: IB object to schedule
3298  *
3299  * Schedule an IB in the DMA ring (evergreen).
3300  */
3301 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
3302                                    struct radeon_ib *ib)
3303 {
3304         struct radeon_ring *ring = &rdev->ring[ib->ring];
3305
3306         if (rdev->wb.enabled) {
3307                 u32 next_rptr = ring->wptr + 4;
3308                 while ((next_rptr & 7) != 5)
3309                         next_rptr++;
3310                 next_rptr += 3;
3311                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1));
3312                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
3313                 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff);
3314                 radeon_ring_write(ring, next_rptr);
3315         }
3316
3317         /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
3318          * Pad as necessary with NOPs.
3319          */
3320         while ((ring->wptr & 7) != 5)
3321                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3322         radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_INDIRECT_BUFFER, 0, 0, 0));
3323         radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
3324         radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
3325
3326 }
3327
3328 /**
3329  * evergreen_copy_dma - copy pages using the DMA engine
3330  *
3331  * @rdev: radeon_device pointer
3332  * @src_offset: src GPU address
3333  * @dst_offset: dst GPU address
3334  * @num_gpu_pages: number of GPU pages to xfer
3335  * @fence: radeon fence object
3336  *
3337  * Copy GPU paging using the DMA engine (evergreen-cayman).
3338  * Used by the radeon ttm implementation to move pages if
3339  * registered as the asic copy callback.
3340  */
3341 int evergreen_copy_dma(struct radeon_device *rdev,
3342                        uint64_t src_offset, uint64_t dst_offset,
3343                        unsigned num_gpu_pages,
3344                        struct radeon_fence **fence)
3345 {
3346         struct radeon_semaphore *sem = NULL;
3347         int ring_index = rdev->asic->copy.dma_ring_index;
3348         struct radeon_ring *ring = &rdev->ring[ring_index];
3349         u32 size_in_dw, cur_size_in_dw;
3350         int i, num_loops;
3351         int r = 0;
3352
3353         r = radeon_semaphore_create(rdev, &sem);
3354         if (r) {
3355                 DRM_ERROR("radeon: moving bo (%d).\n", r);
3356                 return r;
3357         }
3358
3359         size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
3360         num_loops = DIV_ROUND_UP(size_in_dw, 0xfffff);
3361         r = radeon_ring_lock(rdev, ring, num_loops * 5 + 11);
3362         if (r) {
3363                 DRM_ERROR("radeon: moving bo (%d).\n", r);
3364                 radeon_semaphore_free(rdev, &sem, NULL);
3365                 return r;
3366         }
3367
3368         if (radeon_fence_need_sync(*fence, ring->idx)) {
3369                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
3370                                             ring->idx);
3371                 radeon_fence_note_sync(*fence, ring->idx);
3372         } else {
3373                 radeon_semaphore_free(rdev, &sem, NULL);
3374         }
3375
3376         for (i = 0; i < num_loops; i++) {
3377                 cur_size_in_dw = size_in_dw;
3378                 if (cur_size_in_dw > 0xFFFFF)
3379                         cur_size_in_dw = 0xFFFFF;
3380                 size_in_dw -= cur_size_in_dw;
3381                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
3382                 radeon_ring_write(ring, dst_offset & 0xfffffffc);
3383                 radeon_ring_write(ring, src_offset & 0xfffffffc);
3384                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
3385                 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
3386                 src_offset += cur_size_in_dw * 4;
3387                 dst_offset += cur_size_in_dw * 4;
3388         }
3389
3390         r = radeon_fence_emit(rdev, fence, ring->idx);
3391         if (r) {
3392                 radeon_ring_unlock_undo(rdev, ring);
3393                 return r;
3394         }
3395
3396         radeon_ring_unlock_commit(rdev, ring);
3397         radeon_semaphore_free(rdev, &sem, *fence);
3398
3399         return r;
3400 }
3401
3402 static int evergreen_startup(struct radeon_device *rdev)
3403 {
3404         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3405         int r;
3406
3407         /* enable pcie gen2 link */
3408         evergreen_pcie_gen2_enable(rdev);
3409
3410         if (ASIC_IS_DCE5(rdev)) {
3411                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3412                         r = ni_init_microcode(rdev);
3413                         if (r) {
3414                                 DRM_ERROR("Failed to load firmware!\n");
3415                                 return r;
3416                         }
3417                 }
3418                 r = ni_mc_load_microcode(rdev);
3419                 if (r) {
3420                         DRM_ERROR("Failed to load MC firmware!\n");
3421                         return r;
3422                 }
3423         } else {
3424                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3425                         r = r600_init_microcode(rdev);
3426                         if (r) {
3427                                 DRM_ERROR("Failed to load firmware!\n");
3428                                 return r;
3429                         }
3430                 }
3431         }
3432
3433         r = r600_vram_scratch_init(rdev);
3434         if (r)
3435                 return r;
3436
3437         evergreen_mc_program(rdev);
3438         if (rdev->flags & RADEON_IS_AGP) {
3439                 evergreen_agp_enable(rdev);
3440         } else {
3441                 r = evergreen_pcie_gart_enable(rdev);
3442                 if (r)
3443                         return r;
3444         }
3445         evergreen_gpu_init(rdev);
3446
3447         r = evergreen_blit_init(rdev);
3448         if (r) {
3449                 r600_blit_fini(rdev);
3450                 rdev->asic->copy.copy = NULL;
3451                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3452         }
3453
3454         /* allocate wb buffer */
3455         r = radeon_wb_init(rdev);
3456         if (r)
3457                 return r;
3458
3459         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3460         if (r) {
3461                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3462                 return r;
3463         }
3464
3465         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
3466         if (r) {
3467                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
3468                 return r;
3469         }
3470
3471         /* Enable IRQ */
3472         r = r600_irq_init(rdev);
3473         if (r) {
3474                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3475                 radeon_irq_kms_fini(rdev);
3476                 return r;
3477         }
3478         evergreen_irq_set(rdev);
3479
3480         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3481                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3482                              0, 0xfffff, RADEON_CP_PACKET2);
3483         if (r)
3484                 return r;
3485
3486         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3487         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3488                              DMA_RB_RPTR, DMA_RB_WPTR,
3489                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3490         if (r)
3491                 return r;
3492
3493         r = evergreen_cp_load_microcode(rdev);
3494         if (r)
3495                 return r;
3496         r = evergreen_cp_resume(rdev);
3497         if (r)
3498                 return r;
3499         r = r600_dma_resume(rdev);
3500         if (r)
3501                 return r;
3502
3503         r = radeon_ib_pool_init(rdev);
3504         if (r) {
3505                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3506                 return r;
3507         }
3508
3509         r = r600_audio_init(rdev);
3510         if (r) {
3511                 DRM_ERROR("radeon: audio init failed\n");
3512                 return r;
3513         }
3514
3515         return 0;
3516 }
3517
3518 int evergreen_resume(struct radeon_device *rdev)
3519 {
3520         int r;
3521
3522         /* reset the asic, the gfx blocks are often in a bad state
3523          * after the driver is unloaded or after a resume
3524          */
3525         if (radeon_asic_reset(rdev))
3526                 dev_warn(rdev->dev, "GPU reset failed !\n");
3527         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3528          * posting will perform necessary task to bring back GPU into good
3529          * shape.
3530          */
3531         /* post card */
3532         atom_asic_init(rdev->mode_info.atom_context);
3533
3534         rdev->accel_working = true;
3535         r = evergreen_startup(rdev);
3536         if (r) {
3537                 DRM_ERROR("evergreen startup failed on resume\n");
3538                 rdev->accel_working = false;
3539                 return r;
3540         }
3541
3542         return r;
3543
3544 }
3545
3546 int evergreen_suspend(struct radeon_device *rdev)
3547 {
3548         r600_audio_fini(rdev);
3549         r700_cp_stop(rdev);
3550         r600_dma_stop(rdev);
3551         evergreen_irq_suspend(rdev);
3552         radeon_wb_disable(rdev);
3553         evergreen_pcie_gart_disable(rdev);
3554
3555         return 0;
3556 }
3557
3558 /* Plan is to move initialization in that function and use
3559  * helper function so that radeon_device_init pretty much
3560  * do nothing more than calling asic specific function. This
3561  * should also allow to remove a bunch of callback function
3562  * like vram_info.
3563  */
3564 int evergreen_init(struct radeon_device *rdev)
3565 {
3566         int r;
3567
3568         /* Read BIOS */
3569         if (!radeon_get_bios(rdev)) {
3570                 if (ASIC_IS_AVIVO(rdev))
3571                         return -EINVAL;
3572         }
3573         /* Must be an ATOMBIOS */
3574         if (!rdev->is_atom_bios) {
3575                 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3576                 return -EINVAL;
3577         }
3578         r = radeon_atombios_init(rdev);
3579         if (r)
3580                 return r;
3581         /* reset the asic, the gfx blocks are often in a bad state
3582          * after the driver is unloaded or after a resume
3583          */
3584         if (radeon_asic_reset(rdev))
3585                 dev_warn(rdev->dev, "GPU reset failed !\n");
3586         /* Post card if necessary */
3587         if (!radeon_card_posted(rdev)) {
3588                 if (!rdev->bios) {
3589                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3590                         return -EINVAL;
3591                 }
3592                 DRM_INFO("GPU not posted. posting now...\n");
3593                 atom_asic_init(rdev->mode_info.atom_context);
3594         }
3595         /* Initialize scratch registers */
3596         r600_scratch_init(rdev);
3597         /* Initialize surface registers */
3598         radeon_surface_init(rdev);
3599         /* Initialize clocks */
3600         radeon_get_clock_info(rdev->ddev);
3601         /* Fence driver */
3602         r = radeon_fence_driver_init(rdev);
3603         if (r)
3604                 return r;
3605         /* initialize AGP */
3606         if (rdev->flags & RADEON_IS_AGP) {
3607                 r = radeon_agp_init(rdev);
3608                 if (r)
3609                         radeon_agp_disable(rdev);
3610         }
3611         /* initialize memory controller */
3612         r = evergreen_mc_init(rdev);
3613         if (r)
3614                 return r;
3615         /* Memory manager */
3616         r = radeon_bo_init(rdev);
3617         if (r)
3618                 return r;
3619
3620         r = radeon_irq_kms_init(rdev);
3621         if (r)
3622                 return r;
3623
3624         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3625         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3626
3627         rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
3628         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
3629
3630         rdev->ih.ring_obj = NULL;
3631         r600_ih_ring_init(rdev, 64 * 1024);
3632
3633         r = r600_pcie_gart_init(rdev);
3634         if (r)
3635                 return r;
3636
3637         rdev->accel_working = true;
3638         r = evergreen_startup(rdev);
3639         if (r) {
3640                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3641                 r700_cp_fini(rdev);
3642                 r600_dma_fini(rdev);
3643                 r600_irq_fini(rdev);
3644                 radeon_wb_fini(rdev);
3645                 radeon_ib_pool_fini(rdev);
3646                 radeon_irq_kms_fini(rdev);
3647                 evergreen_pcie_gart_fini(rdev);
3648                 rdev->accel_working = false;
3649         }
3650
3651         /* Don't start up if the MC ucode is missing on BTC parts.
3652          * The default clocks and voltages before the MC ucode
3653          * is loaded are not suffient for advanced operations.
3654          */
3655         if (ASIC_IS_DCE5(rdev)) {
3656                 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3657                         DRM_ERROR("radeon: MC ucode required for NI+.\n");
3658                         return -EINVAL;
3659                 }
3660         }
3661
3662         return 0;
3663 }
3664
3665 void evergreen_fini(struct radeon_device *rdev)
3666 {
3667         r600_audio_fini(rdev);
3668         r600_blit_fini(rdev);
3669         r700_cp_fini(rdev);
3670         r600_dma_fini(rdev);
3671         r600_irq_fini(rdev);
3672         radeon_wb_fini(rdev);
3673         radeon_ib_pool_fini(rdev);
3674         radeon_irq_kms_fini(rdev);
3675         evergreen_pcie_gart_fini(rdev);
3676         r600_vram_scratch_fini(rdev);
3677         radeon_gem_fini(rdev);
3678         radeon_fence_driver_fini(rdev);
3679         radeon_agp_fini(rdev);
3680         radeon_bo_fini(rdev);
3681         radeon_atombios_fini(rdev);
3682         kfree(rdev->bios);
3683         rdev->bios = NULL;
3684 }
3685
3686 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3687 {
3688         u32 link_width_cntl, speed_cntl, mask;
3689         int ret;
3690
3691         if (radeon_pcie_gen2 == 0)
3692                 return;
3693
3694         if (rdev->flags & RADEON_IS_IGP)
3695                 return;
3696
3697         if (!(rdev->flags & RADEON_IS_PCIE))
3698                 return;
3699
3700         /* x2 cards have a special sequence */
3701         if (ASIC_IS_X2(rdev))
3702                 return;
3703
3704         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
3705         if (ret != 0)
3706                 return;
3707
3708         if (!(mask & DRM_PCIE_SPEED_50))
3709                 return;
3710
3711         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3712         if (speed_cntl & LC_CURRENT_DATA_RATE) {
3713                 DRM_INFO("PCIE gen 2 link speeds already enabled\n");
3714                 return;
3715         }
3716
3717         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3718
3719         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3720             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3721
3722                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3723                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3724                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3725
3726                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3727                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3728                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3729
3730                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3731                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3732                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3733
3734                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3735                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3736                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3737
3738                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3739                 speed_cntl |= LC_GEN2_EN_STRAP;
3740                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3741
3742         } else {
3743                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3744                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3745                 if (1)
3746                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3747                 else
3748                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3749                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3750         }
3751 }