drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35 #include "evergreen_blit_shaders.h"
  36
  37 #define EVERGREEN_PFP_UCODE_SIZE 1120
  38 #define EVERGREEN_PM4_UCODE_SIZE 1376
  39
  40 static void evergreen_gpu_init(struct radeon_device *rdev);
  41 void evergreen_fini(struct radeon_device *rdev);
  42 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  43 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
  44                                      int ring, u32 cp_int_cntl);
  45
  46 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
  47                              unsigned *bankh, unsigned *mtaspect,
  48                              unsigned *tile_split)
  49 {
  50         *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
  51         *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
  52         *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
  53         *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
  54         switch (*bankw) {
  55         default:
  56         case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
  57         case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
  58         case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
  59         case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
  60         }
  61         switch (*bankh) {
  62         default:
  63         case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
  64         case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
  65         case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
  66         case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
  67         }
  68         switch (*mtaspect) {
  69         default:
  70         case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
  71         case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
  72         case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
  73         case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
  74         }
  75 }
  76
  77 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
  78 {
  79         u16 ctl, v;
  80         int err;
  81
  82         err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
  83         if (err)
  84                 return;
  85
  86         v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
  87
  88         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
  89          * to avoid hangs or perfomance issues
  90          */
  91         if ((v == 0) || (v == 6) || (v == 7)) {
  92                 ctl &= ~PCI_EXP_DEVCTL_READRQ;
  93                 ctl |= (2 << 12);
  94                 pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
  95         }
  96 }
  97
  98 /**
  99  * dce4_wait_for_vblank - vblank wait asic callback.
 100  *
 101  * @rdev: radeon_device pointer
 102  * @crtc: crtc to wait for vblank on
 103  *
 104  * Wait for vblank on the requested crtc (evergreen+).
 105  */
 106 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
 107 {
 108         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
 109         int i;
 110
 111         if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) {
 112                 for (i = 0; i < rdev->usec_timeout; i++) {
 113                         if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK))
 114                                 break;
 115                         udelay(1);
 116                 }
 117                 for (i = 0; i < rdev->usec_timeout; i++) {
 118                         if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)
 119                                 break;
 120                         udelay(1);
 121                 }
 122         }
 123 }
 124
 125 /**
 126  * radeon_irq_kms_pflip_irq_get - pre-pageflip callback.
 127  *
 128  * @rdev: radeon_device pointer
 129  * @crtc: crtc to prepare for pageflip on
 130  *
 131  * Pre-pageflip callback (evergreen+).
 132  * Enables the pageflip irq (vblank irq).
 133  */
 134 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
 135 {
 136         /* enable the pflip int */
 137         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 138 }
 139
 140 /**
 141  * evergreen_post_page_flip - pos-pageflip callback.
 142  *
 143  * @rdev: radeon_device pointer
 144  * @crtc: crtc to cleanup pageflip on
 145  *
 146  * Post-pageflip callback (evergreen+).
 147  * Disables the pageflip irq (vblank irq).
 148  */
 149 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
 150 {
 151         /* disable the pflip int */
 152         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 153 }
 154
 155 /**
 156  * evergreen_page_flip - pageflip callback.
 157  *
 158  * @rdev: radeon_device pointer
 159  * @crtc_id: crtc to cleanup pageflip on
 160  * @crtc_base: new address of the crtc (GPU MC address)
 161  *
 162  * Does the actual pageflip (evergreen+).
 163  * During vblank we take the crtc lock and wait for the update_pending
 164  * bit to go high, when it does, we release the lock, and allow the
 165  * double buffered update to take place.
 166  * Returns the current update pending status.
 167  */
 168 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 169 {
 170         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 171         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
 172         int i;
 173
 174         /* Lock the graphics update lock */
 175         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
 176         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 177
 178         /* update the scanout addresses */
 179         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 180                upper_32_bits(crtc_base));
 181         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 182                (u32)crtc_base);
 183
 184         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
 185                upper_32_bits(crtc_base));
 186         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 187                (u32)crtc_base);
 188
 189         /* Wait for update_pending to go high. */
 190         for (i = 0; i < rdev->usec_timeout; i++) {
 191                 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
 192                         break;
 193                 udelay(1);
 194         }
 195         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 196
 197         /* Unlock the lock, so double-buffering can take place inside vblank */
 198         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
 199         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 200
 201         /* Return current update_pending status: */
 202         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
 203 }
 204
 205 /* get temperature in millidegrees */
 206 int evergreen_get_temp(struct radeon_device *rdev)
 207 {
 208         u32 temp, toffset;
 209         int actual_temp = 0;
 210
 211         if (rdev->family == CHIP_JUNIPER) {
 212                 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
 213                         TOFFSET_SHIFT;
 214                 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
 215                         TS0_ADC_DOUT_SHIFT;
 216
 217                 if (toffset & 0x100)
 218                         actual_temp = temp / 2 - (0x200 - toffset);
 219                 else
 220                         actual_temp = temp / 2 + toffset;
 221
 222                 actual_temp = actual_temp * 1000;
 223
 224         } else {
 225                 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 226                         ASIC_T_SHIFT;
 227
 228                 if (temp & 0x400)
 229                         actual_temp = -256;
 230                 else if (temp & 0x200)
 231                         actual_temp = 255;
 232                 else if (temp & 0x100) {
 233                         actual_temp = temp & 0x1ff;
 234                         actual_temp |= ~0x1ff;
 235                 } else
 236                         actual_temp = temp & 0xff;
 237
 238                 actual_temp = (actual_temp * 1000) / 2;
 239         }
 240
 241         return actual_temp;
 242 }
 243
 244 int sumo_get_temp(struct radeon_device *rdev)
 245 {
 246         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
 247         int actual_temp = temp - 49;
 248
 249         return actual_temp * 1000;
 250 }
 251
 252 /**
 253  * sumo_pm_init_profile - Initialize power profiles callback.
 254  *
 255  * @rdev: radeon_device pointer
 256  *
 257  * Initialize the power states used in profile mode
 258  * (sumo, trinity, SI).
 259  * Used for profile mode only.
 260  */
 261 void sumo_pm_init_profile(struct radeon_device *rdev)
 262 {
 263         int idx;
 264
 265         /* default */
 266         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 267         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 268         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 269         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 270
 271         /* low,mid sh/mh */
 272         if (rdev->flags & RADEON_IS_MOBILITY)
 273                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 274         else
 275                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 276
 277         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
 278         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
 279         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 280         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 281
 282         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
 283         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
 284         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 285         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 286
 287         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
 288         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
 289         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 290         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 291
 292         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
 293         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
 294         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 295         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 296
 297         /* high sh/mh */
 298         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 299         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
 300         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
 301         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 302         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
 303                 rdev->pm.power_state[idx].num_clock_modes - 1;
 304
 305         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
 306         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
 307         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 308         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
 309                 rdev->pm.power_state[idx].num_clock_modes - 1;
 310 }
 311
 312 /**
 313  * evergreen_pm_misc - set additional pm hw parameters callback.
 314  *
 315  * @rdev: radeon_device pointer
 316  *
 317  * Set non-clock parameters associated with a power state
 318  * (voltage, etc.) (evergreen+).
 319  */
 320 void evergreen_pm_misc(struct radeon_device *rdev)
 321 {
 322         int req_ps_idx = rdev->pm.requested_power_state_index;
 323         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 324         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 325         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 326
 327         if (voltage->type == VOLTAGE_SW) {
 328                 /* 0xff01 is a flag rather then an actual voltage */
 329                 if (voltage->voltage == 0xff01)
 330                         return;
 331                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
 332                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 333                         rdev->pm.current_vddc = voltage->voltage;
 334                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
 335                 }
 336                 /* 0xff01 is a flag rather then an actual voltage */
 337                 if (voltage->vddci == 0xff01)
 338                         return;
 339                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
 340                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
 341                         rdev->pm.current_vddci = voltage->vddci;
 342                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
 343                 }
 344         }
 345 }
 346
 347 /**
 348  * evergreen_pm_prepare - pre-power state change callback.
 349  *
 350  * @rdev: radeon_device pointer
 351  *
 352  * Prepare for a power state change (evergreen+).
 353  */
 354 void evergreen_pm_prepare(struct radeon_device *rdev)
 355 {
 356         struct drm_device *ddev = rdev->ddev;
 357         struct drm_crtc *crtc;
 358         struct radeon_crtc *radeon_crtc;
 359         u32 tmp;
 360
 361         /* disable any active CRTCs */
 362         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 363                 radeon_crtc = to_radeon_crtc(crtc);
 364                 if (radeon_crtc->enabled) {
 365                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 366                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 367                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 368                 }
 369         }
 370 }
 371
 372 /**
 373  * evergreen_pm_finish - post-power state change callback.
 374  *
 375  * @rdev: radeon_device pointer
 376  *
 377  * Clean up after a power state change (evergreen+).
 378  */
 379 void evergreen_pm_finish(struct radeon_device *rdev)
 380 {
 381         struct drm_device *ddev = rdev->ddev;
 382         struct drm_crtc *crtc;
 383         struct radeon_crtc *radeon_crtc;
 384         u32 tmp;
 385
 386         /* enable any active CRTCs */
 387         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 388                 radeon_crtc = to_radeon_crtc(crtc);
 389                 if (radeon_crtc->enabled) {
 390                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
 391                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
 392                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
 393                 }
 394         }
 395 }
 396
 397 /**
 398  * evergreen_hpd_sense - hpd sense callback.
 399  *
 400  * @rdev: radeon_device pointer
 401  * @hpd: hpd (hotplug detect) pin
 402  *
 403  * Checks if a digital monitor is connected (evergreen+).
 404  * Returns true if connected, false if not connected.
 405  */
 406 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 407 {
 408         bool connected = false;
 409
 410         switch (hpd) {
 411         case RADEON_HPD_1:
 412                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 413                         connected = true;
 414                 break;
 415         case RADEON_HPD_2:
 416                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 417                         connected = true;
 418                 break;
 419         case RADEON_HPD_3:
 420                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 421                         connected = true;
 422                 break;
 423         case RADEON_HPD_4:
 424                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 425                         connected = true;
 426                 break;
 427         case RADEON_HPD_5:
 428                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 429                         connected = true;
 430                 break;
 431         case RADEON_HPD_6:
 432                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 433                         connected = true;
 434                         break;
 435         default:
 436                 break;
 437         }
 438
 439         return connected;
 440 }
 441
 442 /**
 443  * evergreen_hpd_set_polarity - hpd set polarity callback.
 444  *
 445  * @rdev: radeon_device pointer
 446  * @hpd: hpd (hotplug detect) pin
 447  *
 448  * Set the polarity of the hpd pin (evergreen+).
 449  */
 450 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 451                                 enum radeon_hpd_id hpd)
 452 {
 453         u32 tmp;
 454         bool connected = evergreen_hpd_sense(rdev, hpd);
 455
 456         switch (hpd) {
 457         case RADEON_HPD_1:
 458                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 459                 if (connected)
 460                         tmp &= ~DC_HPDx_INT_POLARITY;
 461                 else
 462                         tmp |= DC_HPDx_INT_POLARITY;
 463                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 464                 break;
 465         case RADEON_HPD_2:
 466                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 467                 if (connected)
 468                         tmp &= ~DC_HPDx_INT_POLARITY;
 469                 else
 470                         tmp |= DC_HPDx_INT_POLARITY;
 471                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 472                 break;
 473         case RADEON_HPD_3:
 474                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 475                 if (connected)
 476                         tmp &= ~DC_HPDx_INT_POLARITY;
 477                 else
 478                         tmp |= DC_HPDx_INT_POLARITY;
 479                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 480                 break;
 481         case RADEON_HPD_4:
 482                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 483                 if (connected)
 484                         tmp &= ~DC_HPDx_INT_POLARITY;
 485                 else
 486                         tmp |= DC_HPDx_INT_POLARITY;
 487                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 488                 break;
 489         case RADEON_HPD_5:
 490                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 491                 if (connected)
 492                         tmp &= ~DC_HPDx_INT_POLARITY;
 493                 else
 494                         tmp |= DC_HPDx_INT_POLARITY;
 495                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 496                         break;
 497         case RADEON_HPD_6:
 498                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 499                 if (connected)
 500                         tmp &= ~DC_HPDx_INT_POLARITY;
 501                 else
 502                         tmp |= DC_HPDx_INT_POLARITY;
 503                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 504                 break;
 505         default:
 506                 break;
 507         }
 508 }
 509
 510 /**
 511  * evergreen_hpd_init - hpd setup callback.
 512  *
 513  * @rdev: radeon_device pointer
 514  *
 515  * Setup the hpd pins used by the card (evergreen+).
 516  * Enable the pin, set the polarity, and enable the hpd interrupts.
 517  */
 518 void evergreen_hpd_init(struct radeon_device *rdev)
 519 {
 520         struct drm_device *dev = rdev->ddev;
 521         struct drm_connector *connector;
 522         unsigned enabled = 0;
 523         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 524                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 525
 526         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 527                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 528                 switch (radeon_connector->hpd.hpd) {
 529                 case RADEON_HPD_1:
 530                         WREG32(DC_HPD1_CONTROL, tmp);
 531                         break;
 532                 case RADEON_HPD_2:
 533                         WREG32(DC_HPD2_CONTROL, tmp);
 534                         break;
 535                 case RADEON_HPD_3:
 536                         WREG32(DC_HPD3_CONTROL, tmp);
 537                         break;
 538                 case RADEON_HPD_4:
 539                         WREG32(DC_HPD4_CONTROL, tmp);
 540                         break;
 541                 case RADEON_HPD_5:
 542                         WREG32(DC_HPD5_CONTROL, tmp);
 543                         break;
 544                 case RADEON_HPD_6:
 545                         WREG32(DC_HPD6_CONTROL, tmp);
 546                         break;
 547                 default:
 548                         break;
 549                 }
 550                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 551                 enabled |= 1 << radeon_connector->hpd.hpd;
 552         }
 553         radeon_irq_kms_enable_hpd(rdev, enabled);
 554 }
 555
 556 /**
 557  * evergreen_hpd_fini - hpd tear down callback.
 558  *
 559  * @rdev: radeon_device pointer
 560  *
 561  * Tear down the hpd pins used by the card (evergreen+).
 562  * Disable the hpd interrupts.
 563  */
 564 void evergreen_hpd_fini(struct radeon_device *rdev)
 565 {
 566         struct drm_device *dev = rdev->ddev;
 567         struct drm_connector *connector;
 568         unsigned disabled = 0;
 569
 570         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 571                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 572                 switch (radeon_connector->hpd.hpd) {
 573                 case RADEON_HPD_1:
 574                         WREG32(DC_HPD1_CONTROL, 0);
 575                         break;
 576                 case RADEON_HPD_2:
 577                         WREG32(DC_HPD2_CONTROL, 0);
 578                         break;
 579                 case RADEON_HPD_3:
 580                         WREG32(DC_HPD3_CONTROL, 0);
 581                         break;
 582                 case RADEON_HPD_4:
 583                         WREG32(DC_HPD4_CONTROL, 0);
 584                         break;
 585                 case RADEON_HPD_5:
 586                         WREG32(DC_HPD5_CONTROL, 0);
 587                         break;
 588                 case RADEON_HPD_6:
 589                         WREG32(DC_HPD6_CONTROL, 0);
 590                         break;
 591                 default:
 592                         break;
 593                 }
 594                 disabled |= 1 << radeon_connector->hpd.hpd;
 595         }
 596         radeon_irq_kms_disable_hpd(rdev, disabled);
 597 }
 598
 599 /* watermark setup */
 600
 601 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
 602                                         struct radeon_crtc *radeon_crtc,
 603                                         struct drm_display_mode *mode,
 604                                         struct drm_display_mode *other_mode)
 605 {
 606         u32 tmp;
 607         /*
 608          * Line Buffer Setup
 609          * There are 3 line buffers, each one shared by 2 display controllers.
 610          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
 611          * the display controllers.  The paritioning is done via one of four
 612          * preset allocations specified in bits 2:0:
 613          * first display controller
 614          *  0 - first half of lb (3840 * 2)
 615          *  1 - first 3/4 of lb (5760 * 2)
 616          *  2 - whole lb (7680 * 2), other crtc must be disabled
 617          *  3 - first 1/4 of lb (1920 * 2)
 618          * second display controller
 619          *  4 - second half of lb (3840 * 2)
 620          *  5 - second 3/4 of lb (5760 * 2)
 621          *  6 - whole lb (7680 * 2), other crtc must be disabled
 622          *  7 - last 1/4 of lb (1920 * 2)
 623          */
 624         /* this can get tricky if we have two large displays on a paired group
 625          * of crtcs.  Ideally for multiple large displays we'd assign them to
 626          * non-linked crtcs for maximum line buffer allocation.
 627          */
 628         if (radeon_crtc->base.enabled && mode) {
 629                 if (other_mode)
 630                         tmp = 0; /* 1/2 */
 631                 else
 632                         tmp = 2; /* whole */
 633         } else
 634                 tmp = 0;
 635
 636         /* second controller of the pair uses second half of the lb */
 637         if (radeon_crtc->crtc_id % 2)
 638                 tmp += 4;
 639         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
 640
 641         if (radeon_crtc->base.enabled && mode) {
 642                 switch (tmp) {
 643                 case 0:
 644                 case 4:
 645                 default:
 646                         if (ASIC_IS_DCE5(rdev))
 647                                 return 4096 * 2;
 648                         else
 649                                 return 3840 * 2;
 650                 case 1:
 651                 case 5:
 652                         if (ASIC_IS_DCE5(rdev))
 653                                 return 6144 * 2;
 654                         else
 655                                 return 5760 * 2;
 656                 case 2:
 657                 case 6:
 658                         if (ASIC_IS_DCE5(rdev))
 659                                 return 8192 * 2;
 660                         else
 661                                 return 7680 * 2;
 662                 case 3:
 663                 case 7:
 664                         if (ASIC_IS_DCE5(rdev))
 665                                 return 2048 * 2;
 666                         else
 667                                 return 1920 * 2;
 668                 }
 669         }
 670
 671         /* controller not enabled, so no lb used */
 672         return 0;
 673 }
 674
 675 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 676 {
 677         u32 tmp = RREG32(MC_SHARED_CHMAP);
 678
 679         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 680         case 0:
 681         default:
 682                 return 1;
 683         case 1:
 684                 return 2;
 685         case 2:
 686                 return 4;
 687         case 3:
 688                 return 8;
 689         }
 690 }
 691
 692 struct evergreen_wm_params {
 693         u32 dram_channels; /* number of dram channels */
 694         u32 yclk;          /* bandwidth per dram data pin in kHz */
 695         u32 sclk;          /* engine clock in kHz */
 696         u32 disp_clk;      /* display clock in kHz */
 697         u32 src_width;     /* viewport width */
 698         u32 active_time;   /* active display time in ns */
 699         u32 blank_time;    /* blank time in ns */
 700         bool interlaced;    /* mode is interlaced */
 701         fixed20_12 vsc;    /* vertical scale ratio */
 702         u32 num_heads;     /* number of active crtcs */
 703         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
 704         u32 lb_size;       /* line buffer allocated to pipe */
 705         u32 vtaps;         /* vertical scaler taps */
 706 };
 707
 708 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
 709 {
 710         /* Calculate DRAM Bandwidth and the part allocated to display. */
 711         fixed20_12 dram_efficiency; /* 0.7 */
 712         fixed20_12 yclk, dram_channels, bandwidth;
 713         fixed20_12 a;
 714
 715         a.full = dfixed_const(1000);
 716         yclk.full = dfixed_const(wm->yclk);
 717         yclk.full = dfixed_div(yclk, a);
 718         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 719         a.full = dfixed_const(10);
 720         dram_efficiency.full = dfixed_const(7);
 721         dram_efficiency.full = dfixed_div(dram_efficiency, a);
 722         bandwidth.full = dfixed_mul(dram_channels, yclk);
 723         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
 724
 725         return dfixed_trunc(bandwidth);
 726 }
 727
 728 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 729 {
 730         /* Calculate DRAM Bandwidth and the part allocated to display. */
 731         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
 732         fixed20_12 yclk, dram_channels, bandwidth;
 733         fixed20_12 a;
 734
 735         a.full = dfixed_const(1000);
 736         yclk.full = dfixed_const(wm->yclk);
 737         yclk.full = dfixed_div(yclk, a);
 738         dram_channels.full = dfixed_const(wm->dram_channels * 4);
 739         a.full = dfixed_const(10);
 740         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
 741         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
 742         bandwidth.full = dfixed_mul(dram_channels, yclk);
 743         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
 744
 745         return dfixed_trunc(bandwidth);
 746 }
 747
 748 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
 749 {
 750         /* Calculate the display Data return Bandwidth */
 751         fixed20_12 return_efficiency; /* 0.8 */
 752         fixed20_12 sclk, bandwidth;
 753         fixed20_12 a;
 754
 755         a.full = dfixed_const(1000);
 756         sclk.full = dfixed_const(wm->sclk);
 757         sclk.full = dfixed_div(sclk, a);
 758         a.full = dfixed_const(10);
 759         return_efficiency.full = dfixed_const(8);
 760         return_efficiency.full = dfixed_div(return_efficiency, a);
 761         a.full = dfixed_const(32);
 762         bandwidth.full = dfixed_mul(a, sclk);
 763         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
 764
 765         return dfixed_trunc(bandwidth);
 766 }
 767
 768 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
 769 {
 770         /* Calculate the DMIF Request Bandwidth */
 771         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
 772         fixed20_12 disp_clk, bandwidth;
 773         fixed20_12 a;
 774
 775         a.full = dfixed_const(1000);
 776         disp_clk.full = dfixed_const(wm->disp_clk);
 777         disp_clk.full = dfixed_div(disp_clk, a);
 778         a.full = dfixed_const(10);
 779         disp_clk_request_efficiency.full = dfixed_const(8);
 780         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
 781         a.full = dfixed_const(32);
 782         bandwidth.full = dfixed_mul(a, disp_clk);
 783         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
 784
 785         return dfixed_trunc(bandwidth);
 786 }
 787
 788 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
 789 {
 790         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
 791         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
 792         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
 793         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
 794
 795         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
 796 }
 797
 798 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
 799 {
 800         /* Calculate the display mode Average Bandwidth
 801          * DisplayMode should contain the source and destination dimensions,
 802          * timing, etc.
 803          */
 804         fixed20_12 bpp;
 805         fixed20_12 line_time;
 806         fixed20_12 src_width;
 807         fixed20_12 bandwidth;
 808         fixed20_12 a;
 809
 810         a.full = dfixed_const(1000);
 811         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
 812         line_time.full = dfixed_div(line_time, a);
 813         bpp.full = dfixed_const(wm->bytes_per_pixel);
 814         src_width.full = dfixed_const(wm->src_width);
 815         bandwidth.full = dfixed_mul(src_width, bpp);
 816         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
 817         bandwidth.full = dfixed_div(bandwidth, line_time);
 818
 819         return dfixed_trunc(bandwidth);
 820 }
 821
 822 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
 823 {
 824         /* First calcualte the latency in ns */
 825         u32 mc_latency = 2000; /* 2000 ns. */
 826         u32 available_bandwidth = evergreen_available_bandwidth(wm);
 827         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
 828         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
 829         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
 830         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
 831                 (wm->num_heads * cursor_line_pair_return_time);
 832         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
 833         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
 834         fixed20_12 a, b, c;
 835
 836         if (wm->num_heads == 0)
 837                 return 0;
 838
 839         a.full = dfixed_const(2);
 840         b.full = dfixed_const(1);
 841         if ((wm->vsc.full > a.full) ||
 842             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
 843             (wm->vtaps >= 5) ||
 844             ((wm->vsc.full >= a.full) && wm->interlaced))
 845                 max_src_lines_per_dst_line = 4;
 846         else
 847                 max_src_lines_per_dst_line = 2;
 848
 849         a.full = dfixed_const(available_bandwidth);
 850         b.full = dfixed_const(wm->num_heads);
 851         a.full = dfixed_div(a, b);
 852
 853         b.full = dfixed_const(1000);
 854         c.full = dfixed_const(wm->disp_clk);
 855         b.full = dfixed_div(c, b);
 856         c.full = dfixed_const(wm->bytes_per_pixel);
 857         b.full = dfixed_mul(b, c);
 858
 859         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
 860
 861         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
 862         b.full = dfixed_const(1000);
 863         c.full = dfixed_const(lb_fill_bw);
 864         b.full = dfixed_div(c, b);
 865         a.full = dfixed_div(a, b);
 866         line_fill_time = dfixed_trunc(a);
 867
 868         if (line_fill_time < wm->active_time)
 869                 return latency;
 870         else
 871                 return latency + (line_fill_time - wm->active_time);
 872
 873 }
 874
 875 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
 876 {
 877         if (evergreen_average_bandwidth(wm) <=
 878             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
 879                 return true;
 880         else
 881                 return false;
 882 };
 883
 884 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
 885 {
 886         if (evergreen_average_bandwidth(wm) <=
 887             (evergreen_available_bandwidth(wm) / wm->num_heads))
 888                 return true;
 889         else
 890                 return false;
 891 };
 892
 893 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
 894 {
 895         u32 lb_partitions = wm->lb_size / wm->src_width;
 896         u32 line_time = wm->active_time + wm->blank_time;
 897         u32 latency_tolerant_lines;
 898         u32 latency_hiding;
 899         fixed20_12 a;
 900
 901         a.full = dfixed_const(1);
 902         if (wm->vsc.full > a.full)
 903                 latency_tolerant_lines = 1;
 904         else {
 905                 if (lb_partitions <= (wm->vtaps + 1))
 906                         latency_tolerant_lines = 1;
 907                 else
 908                         latency_tolerant_lines = 2;
 909         }
 910
 911         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
 912
 913         if (evergreen_latency_watermark(wm) <= latency_hiding)
 914                 return true;
 915         else
 916                 return false;
 917 }
 918
 919 static void evergreen_program_watermarks(struct radeon_device *rdev,
 920                                          struct radeon_crtc *radeon_crtc,
 921                                          u32 lb_size, u32 num_heads)
 922 {
 923         struct drm_display_mode *mode = &radeon_crtc->base.mode;
 924         struct evergreen_wm_params wm;
 925         u32 pixel_period;
 926         u32 line_time = 0;
 927         u32 latency_watermark_a = 0, latency_watermark_b = 0;
 928         u32 priority_a_mark = 0, priority_b_mark = 0;
 929         u32 priority_a_cnt = PRIORITY_OFF;
 930         u32 priority_b_cnt = PRIORITY_OFF;
 931         u32 pipe_offset = radeon_crtc->crtc_id * 16;
 932         u32 tmp, arb_control3;
 933         fixed20_12 a, b, c;
 934
 935         if (radeon_crtc->base.enabled && num_heads && mode) {
 936                 pixel_period = 1000000 / (u32)mode->clock;
 937                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
 938                 priority_a_cnt = 0;
 939                 priority_b_cnt = 0;
 940
 941                 wm.yclk = rdev->pm.current_mclk * 10;
 942                 wm.sclk = rdev->pm.current_sclk * 10;
 943                 wm.disp_clk = mode->clock;
 944                 wm.src_width = mode->crtc_hdisplay;
 945                 wm.active_time = mode->crtc_hdisplay * pixel_period;
 946                 wm.blank_time = line_time - wm.active_time;
 947                 wm.interlaced = false;
 948                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 949                         wm.interlaced = true;
 950                 wm.vsc = radeon_crtc->vsc;
 951                 wm.vtaps = 1;
 952                 if (radeon_crtc->rmx_type != RMX_OFF)
 953                         wm.vtaps = 2;
 954                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
 955                 wm.lb_size = lb_size;
 956                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
 957                 wm.num_heads = num_heads;
 958
 959                 /* set for high clocks */
 960                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
 961                 /* set for low clocks */
 962                 /* wm.yclk = low clk; wm.sclk = low clk */
 963                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
 964
 965                 /* possibly force display priority to high */
 966                 /* should really do this at mode validation time... */
 967                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
 968                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
 969                     !evergreen_check_latency_hiding(&wm) ||
 970                     (rdev->disp_priority == 2)) {
 971                         DRM_DEBUG_KMS("force priority to high\n");
 972                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
 973                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
 974                 }
 975
 976                 a.full = dfixed_const(1000);
 977                 b.full = dfixed_const(mode->clock);
 978                 b.full = dfixed_div(b, a);
 979                 c.full = dfixed_const(latency_watermark_a);
 980                 c.full = dfixed_mul(c, b);
 981                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 982                 c.full = dfixed_div(c, a);
 983                 a.full = dfixed_const(16);
 984                 c.full = dfixed_div(c, a);
 985                 priority_a_mark = dfixed_trunc(c);
 986                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
 987
 988                 a.full = dfixed_const(1000);
 989                 b.full = dfixed_const(mode->clock);
 990                 b.full = dfixed_div(b, a);
 991                 c.full = dfixed_const(latency_watermark_b);
 992                 c.full = dfixed_mul(c, b);
 993                 c.full = dfixed_mul(c, radeon_crtc->hsc);
 994                 c.full = dfixed_div(c, a);
 995                 a.full = dfixed_const(16);
 996                 c.full = dfixed_div(c, a);
 997                 priority_b_mark = dfixed_trunc(c);
 998                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
 999         }
1000
1001         /* select wm A */
1002         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1003         tmp = arb_control3;
1004         tmp &= ~LATENCY_WATERMARK_MASK(3);
1005         tmp |= LATENCY_WATERMARK_MASK(1);
1006         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1007         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1008                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
1009                 LATENCY_HIGH_WATERMARK(line_time)));
1010         /* select wm B */
1011         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
1012         tmp &= ~LATENCY_WATERMARK_MASK(3);
1013         tmp |= LATENCY_WATERMARK_MASK(2);
1014         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
1015         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
1016                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
1017                 LATENCY_HIGH_WATERMARK(line_time)));
1018         /* restore original selection */
1019         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
1020
1021         /* write the priority marks */
1022         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
1023         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
1024
1025 }
1026
1027 /**
1028  * evergreen_bandwidth_update - update display watermarks callback.
1029  *
1030  * @rdev: radeon_device pointer
1031  *
1032  * Update the display watermarks based on the requested mode(s)
1033  * (evergreen+).
1034  */
1035 void evergreen_bandwidth_update(struct radeon_device *rdev)
1036 {
1037         struct drm_display_mode *mode0 = NULL;
1038         struct drm_display_mode *mode1 = NULL;
1039         u32 num_heads = 0, lb_size;
1040         int i;
1041
1042         radeon_update_display_priority(rdev);
1043
1044         for (i = 0; i < rdev->num_crtc; i++) {
1045                 if (rdev->mode_info.crtcs[i]->base.enabled)
1046                         num_heads++;
1047         }
1048         for (i = 0; i < rdev->num_crtc; i += 2) {
1049                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
1050                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
1051                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
1052                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
1053                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
1054                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
1055         }
1056 }
1057
1058 /**
1059  * evergreen_mc_wait_for_idle - wait for MC idle callback.
1060  *
1061  * @rdev: radeon_device pointer
1062  *
1063  * Wait for the MC (memory controller) to be idle.
1064  * (evergreen+).
1065  * Returns 0 if the MC is idle, -1 if not.
1066  */
1067 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
1068 {
1069         unsigned i;
1070         u32 tmp;
1071
1072         for (i = 0; i < rdev->usec_timeout; i++) {
1073                 /* read MC_STATUS */
1074                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
1075                 if (!tmp)
1076                         return 0;
1077                 udelay(1);
1078         }
1079         return -1;
1080 }
1081
1082 /*
1083  * GART
1084  */
1085 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
1086 {
1087         unsigned i;
1088         u32 tmp;
1089
1090         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1091
1092         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
1093         for (i = 0; i < rdev->usec_timeout; i++) {
1094                 /* read MC_STATUS */
1095                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1096                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1097                 if (tmp == 2) {
1098                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1099                         return;
1100                 }
1101                 if (tmp) {
1102                         return;
1103                 }
1104                 udelay(1);
1105         }
1106 }
1107
1108 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1109 {
1110         u32 tmp;
1111         int r;
1112
1113         if (rdev->gart.robj == NULL) {
1114                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1115                 return -EINVAL;
1116         }
1117         r = radeon_gart_table_vram_pin(rdev);
1118         if (r)
1119                 return r;
1120         radeon_gart_restore(rdev);
1121         /* Setup L2 cache */
1122         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1123                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1124                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1125         WREG32(VM_L2_CNTL2, 0);
1126         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1127         /* Setup TLB control */
1128         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1129                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1130                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1131                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1132         if (rdev->flags & RADEON_IS_IGP) {
1133                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1134                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1135                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1136         } else {
1137                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1138                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1139                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1140                 if ((rdev->family == CHIP_JUNIPER) ||
1141                     (rdev->family == CHIP_CYPRESS) ||
1142                     (rdev->family == CHIP_HEMLOCK) ||
1143                     (rdev->family == CHIP_BARTS))
1144                         WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1145         }
1146         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1147         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1148         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1149         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1150         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1151         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1152         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1153         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1154                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1155         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1156                         (u32)(rdev->dummy_page.addr >> 12));
1157         WREG32(VM_CONTEXT1_CNTL, 0);
1158
1159         evergreen_pcie_gart_tlb_flush(rdev);
1160         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1161                  (unsigned)(rdev->mc.gtt_size >> 20),
1162                  (unsigned long long)rdev->gart.table_addr);
1163         rdev->gart.ready = true;
1164         return 0;
1165 }
1166
1167 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1168 {
1169         u32 tmp;
1170
1171         /* Disable all tables */
1172         WREG32(VM_CONTEXT0_CNTL, 0);
1173         WREG32(VM_CONTEXT1_CNTL, 0);
1174
1175         /* Setup L2 cache */
1176         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1177                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1178         WREG32(VM_L2_CNTL2, 0);
1179         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1180         /* Setup TLB control */
1181         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1182         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1183         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1184         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1185         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1186         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1187         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1188         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1189         radeon_gart_table_vram_unpin(rdev);
1190 }
1191
1192 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1193 {
1194         evergreen_pcie_gart_disable(rdev);
1195         radeon_gart_table_vram_free(rdev);
1196         radeon_gart_fini(rdev);
1197 }
1198
1199
1200 void evergreen_agp_enable(struct radeon_device *rdev)
1201 {
1202         u32 tmp;
1203
1204         /* Setup L2 cache */
1205         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1206                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1207                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1208         WREG32(VM_L2_CNTL2, 0);
1209         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1210         /* Setup TLB control */
1211         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1212                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1213                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1214                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1215         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1216         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1217         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1218         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1219         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1220         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1221         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1222         WREG32(VM_CONTEXT0_CNTL, 0);
1223         WREG32(VM_CONTEXT1_CNTL, 0);
1224 }
1225
1226 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1227 {
1228         save->vga_control[0] = RREG32(D1VGA_CONTROL);
1229         save->vga_control[1] = RREG32(D2VGA_CONTROL);
1230         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1231         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1232         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1233         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1234         if (rdev->num_crtc >= 4) {
1235                 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1236                 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1237                 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1238                 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1239         }
1240         if (rdev->num_crtc >= 6) {
1241                 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1242                 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1243                 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1244                 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1245         }
1246
1247         /* Stop all video */
1248         WREG32(VGA_RENDER_CONTROL, 0);
1249         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1250         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1251         if (rdev->num_crtc >= 4) {
1252                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1253                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1254         }
1255         if (rdev->num_crtc >= 6) {
1256                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1257                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1258         }
1259         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1260         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1261         if (rdev->num_crtc >= 4) {
1262                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1263                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1264         }
1265         if (rdev->num_crtc >= 6) {
1266                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1267                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1268         }
1269         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1270         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1271         if (rdev->num_crtc >= 4) {
1272                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1273                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1274         }
1275         if (rdev->num_crtc >= 6) {
1276                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1277                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1278         }
1279
1280         WREG32(D1VGA_CONTROL, 0);
1281         WREG32(D2VGA_CONTROL, 0);
1282         if (rdev->num_crtc >= 4) {
1283                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1284                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1285         }
1286         if (rdev->num_crtc >= 6) {
1287                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1288                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1289         }
1290 }
1291
1292 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1293 {
1294         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1295                upper_32_bits(rdev->mc.vram_start));
1296         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1297                upper_32_bits(rdev->mc.vram_start));
1298         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1299                (u32)rdev->mc.vram_start);
1300         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1301                (u32)rdev->mc.vram_start);
1302
1303         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1304                upper_32_bits(rdev->mc.vram_start));
1305         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1306                upper_32_bits(rdev->mc.vram_start));
1307         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1308                (u32)rdev->mc.vram_start);
1309         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1310                (u32)rdev->mc.vram_start);
1311
1312         if (rdev->num_crtc >= 4) {
1313                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1314                        upper_32_bits(rdev->mc.vram_start));
1315                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1316                        upper_32_bits(rdev->mc.vram_start));
1317                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1318                        (u32)rdev->mc.vram_start);
1319                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1320                        (u32)rdev->mc.vram_start);
1321
1322                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1323                        upper_32_bits(rdev->mc.vram_start));
1324                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1325                        upper_32_bits(rdev->mc.vram_start));
1326                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1327                        (u32)rdev->mc.vram_start);
1328                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1329                        (u32)rdev->mc.vram_start);
1330         }
1331         if (rdev->num_crtc >= 6) {
1332                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1333                        upper_32_bits(rdev->mc.vram_start));
1334                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1335                        upper_32_bits(rdev->mc.vram_start));
1336                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1337                        (u32)rdev->mc.vram_start);
1338                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1339                        (u32)rdev->mc.vram_start);
1340
1341                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1342                        upper_32_bits(rdev->mc.vram_start));
1343                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1344                        upper_32_bits(rdev->mc.vram_start));
1345                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1346                        (u32)rdev->mc.vram_start);
1347                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1348                        (u32)rdev->mc.vram_start);
1349         }
1350
1351         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1352         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1353         /* Unlock host access */
1354         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1355         mdelay(1);
1356         /* Restore video state */
1357         WREG32(D1VGA_CONTROL, save->vga_control[0]);
1358         WREG32(D2VGA_CONTROL, save->vga_control[1]);
1359         if (rdev->num_crtc >= 4) {
1360                 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1361                 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1362         }
1363         if (rdev->num_crtc >= 6) {
1364                 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1365                 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1366         }
1367         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1368         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1369         if (rdev->num_crtc >= 4) {
1370                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1371                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1372         }
1373         if (rdev->num_crtc >= 6) {
1374                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1375                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1376         }
1377         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1378         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1379         if (rdev->num_crtc >= 4) {
1380                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1381                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1382         }
1383         if (rdev->num_crtc >= 6) {
1384                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1385                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1386         }
1387         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1388         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1389         if (rdev->num_crtc >= 4) {
1390                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1391                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1392         }
1393         if (rdev->num_crtc >= 6) {
1394                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1395                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1396         }
1397         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1398 }
1399
1400 void evergreen_mc_program(struct radeon_device *rdev)
1401 {
1402         struct evergreen_mc_save save;
1403         u32 tmp;
1404         int i, j;
1405
1406         /* Initialize HDP */
1407         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1408                 WREG32((0x2c14 + j), 0x00000000);
1409                 WREG32((0x2c18 + j), 0x00000000);
1410                 WREG32((0x2c1c + j), 0x00000000);
1411                 WREG32((0x2c20 + j), 0x00000000);
1412                 WREG32((0x2c24 + j), 0x00000000);
1413         }
1414         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1415
1416         evergreen_mc_stop(rdev, &save);
1417         if (evergreen_mc_wait_for_idle(rdev)) {
1418                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1419         }
1420         /* Lockout access through VGA aperture*/
1421         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1422         /* Update configuration */
1423         if (rdev->flags & RADEON_IS_AGP) {
1424                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1425                         /* VRAM before AGP */
1426                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1427                                 rdev->mc.vram_start >> 12);
1428                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1429                                 rdev->mc.gtt_end >> 12);
1430                 } else {
1431                         /* VRAM after AGP */
1432                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1433                                 rdev->mc.gtt_start >> 12);
1434                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1435                                 rdev->mc.vram_end >> 12);
1436                 }
1437         } else {
1438                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1439                         rdev->mc.vram_start >> 12);
1440                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1441                         rdev->mc.vram_end >> 12);
1442         }
1443         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1444         /* llano/ontario only */
1445         if ((rdev->family == CHIP_PALM) ||
1446             (rdev->family == CHIP_SUMO) ||
1447             (rdev->family == CHIP_SUMO2)) {
1448                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1449                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1450                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1451                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1452         }
1453         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1454         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1455         WREG32(MC_VM_FB_LOCATION, tmp);
1456         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1457         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1458         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1459         if (rdev->flags & RADEON_IS_AGP) {
1460                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1461                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1462                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1463         } else {
1464                 WREG32(MC_VM_AGP_BASE, 0);
1465                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1466                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1467         }
1468         if (evergreen_mc_wait_for_idle(rdev)) {
1469                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1470         }
1471         evergreen_mc_resume(rdev, &save);
1472         /* we need to own VRAM, so turn off the VGA renderer here
1473          * to stop it overwriting our objects */
1474         rv515_vga_render_disable(rdev);
1475 }
1476
1477 /*
1478  * CP.
1479  */
1480 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1481 {
1482         struct radeon_ring *ring = &rdev->ring[ib->ring];
1483         u32 next_rptr;
1484
1485         /* set to DX10/11 mode */
1486         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1487         radeon_ring_write(ring, 1);
1488
1489         if (ring->rptr_save_reg) {
1490                 next_rptr = ring->wptr + 3 + 4;
1491                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1492                 radeon_ring_write(ring, ((ring->rptr_save_reg -
1493                                           PACKET3_SET_CONFIG_REG_START) >> 2));
1494                 radeon_ring_write(ring, next_rptr);
1495         } else if (rdev->wb.enabled) {
1496                 next_rptr = ring->wptr + 5 + 4;
1497                 radeon_ring_write(ring, PACKET3(PACKET3_MEM_WRITE, 3));
1498                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1499                 radeon_ring_write(ring, (upper_32_bits(ring->next_rptr_gpu_addr) & 0xff) | (1 << 18));
1500                 radeon_ring_write(ring, next_rptr);
1501                 radeon_ring_write(ring, 0);
1502         }
1503
1504         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1505         radeon_ring_write(ring,
1506 #ifdef __BIG_ENDIAN
1507                           (2 << 0) |
1508 #endif
1509                           (ib->gpu_addr & 0xFFFFFFFC));
1510         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1511         radeon_ring_write(ring, ib->length_dw);
1512 }
1513
1514
1515 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1516 {
1517         const __be32 *fw_data;
1518         int i;
1519
1520         if (!rdev->me_fw || !rdev->pfp_fw)
1521                 return -EINVAL;
1522
1523         r700_cp_stop(rdev);
1524         WREG32(CP_RB_CNTL,
1525 #ifdef __BIG_ENDIAN
1526                BUF_SWAP_32BIT |
1527 #endif
1528                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1529
1530         fw_data = (const __be32 *)rdev->pfp_fw->data;
1531         WREG32(CP_PFP_UCODE_ADDR, 0);
1532         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1533                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1534         WREG32(CP_PFP_UCODE_ADDR, 0);
1535
1536         fw_data = (const __be32 *)rdev->me_fw->data;
1537         WREG32(CP_ME_RAM_WADDR, 0);
1538         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1539                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1540
1541         WREG32(CP_PFP_UCODE_ADDR, 0);
1542         WREG32(CP_ME_RAM_WADDR, 0);
1543         WREG32(CP_ME_RAM_RADDR, 0);
1544         return 0;
1545 }
1546
1547 static int evergreen_cp_start(struct radeon_device *rdev)
1548 {
1549         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1550         int r, i;
1551         uint32_t cp_me;
1552
1553         r = radeon_ring_lock(rdev, ring, 7);
1554         if (r) {
1555                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1556                 return r;
1557         }
1558         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1559         radeon_ring_write(ring, 0x1);
1560         radeon_ring_write(ring, 0x0);
1561         radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1562         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1563         radeon_ring_write(ring, 0);
1564         radeon_ring_write(ring, 0);
1565         radeon_ring_unlock_commit(rdev, ring);
1566
1567         cp_me = 0xff;
1568         WREG32(CP_ME_CNTL, cp_me);
1569
1570         r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
1571         if (r) {
1572                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1573                 return r;
1574         }
1575
1576         /* setup clear context state */
1577         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1578         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1579
1580         for (i = 0; i < evergreen_default_size; i++)
1581                 radeon_ring_write(ring, evergreen_default_state[i]);
1582
1583         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1584         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1585
1586         /* set clear context state */
1587         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1588         radeon_ring_write(ring, 0);
1589
1590         /* SQ_VTX_BASE_VTX_LOC */
1591         radeon_ring_write(ring, 0xc0026f00);
1592         radeon_ring_write(ring, 0x00000000);
1593         radeon_ring_write(ring, 0x00000000);
1594         radeon_ring_write(ring, 0x00000000);
1595
1596         /* Clear consts */
1597         radeon_ring_write(ring, 0xc0036f00);
1598         radeon_ring_write(ring, 0x00000bc4);
1599         radeon_ring_write(ring, 0xffffffff);
1600         radeon_ring_write(ring, 0xffffffff);
1601         radeon_ring_write(ring, 0xffffffff);
1602
1603         radeon_ring_write(ring, 0xc0026900);
1604         radeon_ring_write(ring, 0x00000316);
1605         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1606         radeon_ring_write(ring, 0x00000010); /*  */
1607
1608         radeon_ring_unlock_commit(rdev, ring);
1609
1610         return 0;
1611 }
1612
1613 int evergreen_cp_resume(struct radeon_device *rdev)
1614 {
1615         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1616         u32 tmp;
1617         u32 rb_bufsz;
1618         int r;
1619
1620         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1621         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1622                                  SOFT_RESET_PA |
1623                                  SOFT_RESET_SH |
1624                                  SOFT_RESET_VGT |
1625                                  SOFT_RESET_SPI |
1626                                  SOFT_RESET_SX));
1627         RREG32(GRBM_SOFT_RESET);
1628         mdelay(15);
1629         WREG32(GRBM_SOFT_RESET, 0);
1630         RREG32(GRBM_SOFT_RESET);
1631
1632         /* Set ring buffer size */
1633         rb_bufsz = drm_order(ring->ring_size / 8);
1634         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1635 #ifdef __BIG_ENDIAN
1636         tmp |= BUF_SWAP_32BIT;
1637 #endif
1638         WREG32(CP_RB_CNTL, tmp);
1639         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1640         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1641
1642         /* Set the write pointer delay */
1643         WREG32(CP_RB_WPTR_DELAY, 0);
1644
1645         /* Initialize the ring buffer's read and write pointers */
1646         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1647         WREG32(CP_RB_RPTR_WR, 0);
1648         ring->wptr = 0;
1649         WREG32(CP_RB_WPTR, ring->wptr);
1650
1651         /* set the wb address wether it's enabled or not */
1652         WREG32(CP_RB_RPTR_ADDR,
1653                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1654         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1655         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1656
1657         if (rdev->wb.enabled)
1658                 WREG32(SCRATCH_UMSK, 0xff);
1659         else {
1660                 tmp |= RB_NO_UPDATE;
1661                 WREG32(SCRATCH_UMSK, 0);
1662         }
1663
1664         mdelay(1);
1665         WREG32(CP_RB_CNTL, tmp);
1666
1667         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1668         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1669
1670         ring->rptr = RREG32(CP_RB_RPTR);
1671
1672         evergreen_cp_start(rdev);
1673         ring->ready = true;
1674         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1675         if (r) {
1676                 ring->ready = false;
1677                 return r;
1678         }
1679         return 0;
1680 }
1681
1682 /*
1683  * Core functions
1684  */
1685 static void evergreen_gpu_init(struct radeon_device *rdev)
1686 {
1687         u32 gb_addr_config;
1688         u32 mc_shared_chmap, mc_arb_ramcfg;
1689         u32 sx_debug_1;
1690         u32 smx_dc_ctl0;
1691         u32 sq_config;
1692         u32 sq_lds_resource_mgmt;
1693         u32 sq_gpr_resource_mgmt_1;
1694         u32 sq_gpr_resource_mgmt_2;
1695         u32 sq_gpr_resource_mgmt_3;
1696         u32 sq_thread_resource_mgmt;
1697         u32 sq_thread_resource_mgmt_2;
1698         u32 sq_stack_resource_mgmt_1;
1699         u32 sq_stack_resource_mgmt_2;
1700         u32 sq_stack_resource_mgmt_3;
1701         u32 vgt_cache_invalidation;
1702         u32 hdp_host_path_cntl, tmp;
1703         u32 disabled_rb_mask;
1704         int i, j, num_shader_engines, ps_thread_count;
1705
1706         switch (rdev->family) {
1707         case CHIP_CYPRESS:
1708         case CHIP_HEMLOCK:
1709                 rdev->config.evergreen.num_ses = 2;
1710                 rdev->config.evergreen.max_pipes = 4;
1711                 rdev->config.evergreen.max_tile_pipes = 8;
1712                 rdev->config.evergreen.max_simds = 10;
1713                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1714                 rdev->config.evergreen.max_gprs = 256;
1715                 rdev->config.evergreen.max_threads = 248;
1716                 rdev->config.evergreen.max_gs_threads = 32;
1717                 rdev->config.evergreen.max_stack_entries = 512;
1718                 rdev->config.evergreen.sx_num_of_sets = 4;
1719                 rdev->config.evergreen.sx_max_export_size = 256;
1720                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1721                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1722                 rdev->config.evergreen.max_hw_contexts = 8;
1723                 rdev->config.evergreen.sq_num_cf_insts = 2;
1724
1725                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1726                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1727                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1728                 gb_addr_config = CYPRESS_GB_ADDR_CONFIG_GOLDEN;
1729                 break;
1730         case CHIP_JUNIPER:
1731                 rdev->config.evergreen.num_ses = 1;
1732                 rdev->config.evergreen.max_pipes = 4;
1733                 rdev->config.evergreen.max_tile_pipes = 4;
1734                 rdev->config.evergreen.max_simds = 10;
1735                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1736                 rdev->config.evergreen.max_gprs = 256;
1737                 rdev->config.evergreen.max_threads = 248;
1738                 rdev->config.evergreen.max_gs_threads = 32;
1739                 rdev->config.evergreen.max_stack_entries = 512;
1740                 rdev->config.evergreen.sx_num_of_sets = 4;
1741                 rdev->config.evergreen.sx_max_export_size = 256;
1742                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1743                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1744                 rdev->config.evergreen.max_hw_contexts = 8;
1745                 rdev->config.evergreen.sq_num_cf_insts = 2;
1746
1747                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1748                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1749                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1750                 gb_addr_config = JUNIPER_GB_ADDR_CONFIG_GOLDEN;
1751                 break;
1752         case CHIP_REDWOOD:
1753                 rdev->config.evergreen.num_ses = 1;
1754                 rdev->config.evergreen.max_pipes = 4;
1755                 rdev->config.evergreen.max_tile_pipes = 4;
1756                 rdev->config.evergreen.max_simds = 5;
1757                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1758                 rdev->config.evergreen.max_gprs = 256;
1759                 rdev->config.evergreen.max_threads = 248;
1760                 rdev->config.evergreen.max_gs_threads = 32;
1761                 rdev->config.evergreen.max_stack_entries = 256;
1762                 rdev->config.evergreen.sx_num_of_sets = 4;
1763                 rdev->config.evergreen.sx_max_export_size = 256;
1764                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1765                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1766                 rdev->config.evergreen.max_hw_contexts = 8;
1767                 rdev->config.evergreen.sq_num_cf_insts = 2;
1768
1769                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1770                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1771                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1772                 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1773                 break;
1774         case CHIP_CEDAR:
1775         default:
1776                 rdev->config.evergreen.num_ses = 1;
1777                 rdev->config.evergreen.max_pipes = 2;
1778                 rdev->config.evergreen.max_tile_pipes = 2;
1779                 rdev->config.evergreen.max_simds = 2;
1780                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1781                 rdev->config.evergreen.max_gprs = 256;
1782                 rdev->config.evergreen.max_threads = 192;
1783                 rdev->config.evergreen.max_gs_threads = 16;
1784                 rdev->config.evergreen.max_stack_entries = 256;
1785                 rdev->config.evergreen.sx_num_of_sets = 4;
1786                 rdev->config.evergreen.sx_max_export_size = 128;
1787                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1788                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1789                 rdev->config.evergreen.max_hw_contexts = 4;
1790                 rdev->config.evergreen.sq_num_cf_insts = 1;
1791
1792                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1793                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1794                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1795                 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1796                 break;
1797         case CHIP_PALM:
1798                 rdev->config.evergreen.num_ses = 1;
1799                 rdev->config.evergreen.max_pipes = 2;
1800                 rdev->config.evergreen.max_tile_pipes = 2;
1801                 rdev->config.evergreen.max_simds = 2;
1802                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1803                 rdev->config.evergreen.max_gprs = 256;
1804                 rdev->config.evergreen.max_threads = 192;
1805                 rdev->config.evergreen.max_gs_threads = 16;
1806                 rdev->config.evergreen.max_stack_entries = 256;
1807                 rdev->config.evergreen.sx_num_of_sets = 4;
1808                 rdev->config.evergreen.sx_max_export_size = 128;
1809                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1810                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1811                 rdev->config.evergreen.max_hw_contexts = 4;
1812                 rdev->config.evergreen.sq_num_cf_insts = 1;
1813
1814                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1815                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1816                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1817                 gb_addr_config = CEDAR_GB_ADDR_CONFIG_GOLDEN;
1818                 break;
1819         case CHIP_SUMO:
1820                 rdev->config.evergreen.num_ses = 1;
1821                 rdev->config.evergreen.max_pipes = 4;
1822                 rdev->config.evergreen.max_tile_pipes = 2;
1823                 if (rdev->pdev->device == 0x9648)
1824                         rdev->config.evergreen.max_simds = 3;
1825                 else if ((rdev->pdev->device == 0x9647) ||
1826                          (rdev->pdev->device == 0x964a))
1827                         rdev->config.evergreen.max_simds = 4;
1828                 else
1829                         rdev->config.evergreen.max_simds = 5;
1830                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1831                 rdev->config.evergreen.max_gprs = 256;
1832                 rdev->config.evergreen.max_threads = 248;
1833                 rdev->config.evergreen.max_gs_threads = 32;
1834                 rdev->config.evergreen.max_stack_entries = 256;
1835                 rdev->config.evergreen.sx_num_of_sets = 4;
1836                 rdev->config.evergreen.sx_max_export_size = 256;
1837                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1838                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1839                 rdev->config.evergreen.max_hw_contexts = 8;
1840                 rdev->config.evergreen.sq_num_cf_insts = 2;
1841
1842                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1843                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1844                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1845                 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1846                 break;
1847         case CHIP_SUMO2:
1848                 rdev->config.evergreen.num_ses = 1;
1849                 rdev->config.evergreen.max_pipes = 4;
1850                 rdev->config.evergreen.max_tile_pipes = 4;
1851                 rdev->config.evergreen.max_simds = 2;
1852                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1853                 rdev->config.evergreen.max_gprs = 256;
1854                 rdev->config.evergreen.max_threads = 248;
1855                 rdev->config.evergreen.max_gs_threads = 32;
1856                 rdev->config.evergreen.max_stack_entries = 512;
1857                 rdev->config.evergreen.sx_num_of_sets = 4;
1858                 rdev->config.evergreen.sx_max_export_size = 256;
1859                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1860                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1861                 rdev->config.evergreen.max_hw_contexts = 8;
1862                 rdev->config.evergreen.sq_num_cf_insts = 2;
1863
1864                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1865                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1866                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1867                 gb_addr_config = REDWOOD_GB_ADDR_CONFIG_GOLDEN;
1868                 break;
1869         case CHIP_BARTS:
1870                 rdev->config.evergreen.num_ses = 2;
1871                 rdev->config.evergreen.max_pipes = 4;
1872                 rdev->config.evergreen.max_tile_pipes = 8;
1873                 rdev->config.evergreen.max_simds = 7;
1874                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1875                 rdev->config.evergreen.max_gprs = 256;
1876                 rdev->config.evergreen.max_threads = 248;
1877                 rdev->config.evergreen.max_gs_threads = 32;
1878                 rdev->config.evergreen.max_stack_entries = 512;
1879                 rdev->config.evergreen.sx_num_of_sets = 4;
1880                 rdev->config.evergreen.sx_max_export_size = 256;
1881                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1882                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1883                 rdev->config.evergreen.max_hw_contexts = 8;
1884                 rdev->config.evergreen.sq_num_cf_insts = 2;
1885
1886                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1887                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1888                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1889                 gb_addr_config = BARTS_GB_ADDR_CONFIG_GOLDEN;
1890                 break;
1891         case CHIP_TURKS:
1892                 rdev->config.evergreen.num_ses = 1;
1893                 rdev->config.evergreen.max_pipes = 4;
1894                 rdev->config.evergreen.max_tile_pipes = 4;
1895                 rdev->config.evergreen.max_simds = 6;
1896                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1897                 rdev->config.evergreen.max_gprs = 256;
1898                 rdev->config.evergreen.max_threads = 248;
1899                 rdev->config.evergreen.max_gs_threads = 32;
1900                 rdev->config.evergreen.max_stack_entries = 256;
1901                 rdev->config.evergreen.sx_num_of_sets = 4;
1902                 rdev->config.evergreen.sx_max_export_size = 256;
1903                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1904                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1905                 rdev->config.evergreen.max_hw_contexts = 8;
1906                 rdev->config.evergreen.sq_num_cf_insts = 2;
1907
1908                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1909                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1910                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1911                 gb_addr_config = TURKS_GB_ADDR_CONFIG_GOLDEN;
1912                 break;
1913         case CHIP_CAICOS:
1914                 rdev->config.evergreen.num_ses = 1;
1915                 rdev->config.evergreen.max_pipes = 4;
1916                 rdev->config.evergreen.max_tile_pipes = 2;
1917                 rdev->config.evergreen.max_simds = 2;
1918                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1919                 rdev->config.evergreen.max_gprs = 256;
1920                 rdev->config.evergreen.max_threads = 192;
1921                 rdev->config.evergreen.max_gs_threads = 16;
1922                 rdev->config.evergreen.max_stack_entries = 256;
1923                 rdev->config.evergreen.sx_num_of_sets = 4;
1924                 rdev->config.evergreen.sx_max_export_size = 128;
1925                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1926                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1927                 rdev->config.evergreen.max_hw_contexts = 4;
1928                 rdev->config.evergreen.sq_num_cf_insts = 1;
1929
1930                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1931                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1932                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1933                 gb_addr_config = CAICOS_GB_ADDR_CONFIG_GOLDEN;
1934                 break;
1935         }
1936
1937         /* Initialize HDP */
1938         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1939                 WREG32((0x2c14 + j), 0x00000000);
1940                 WREG32((0x2c18 + j), 0x00000000);
1941                 WREG32((0x2c1c + j), 0x00000000);
1942                 WREG32((0x2c20 + j), 0x00000000);
1943                 WREG32((0x2c24 + j), 0x00000000);
1944         }
1945
1946         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1947
1948         evergreen_fix_pci_max_read_req_size(rdev);
1949
1950         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1951         if ((rdev->family == CHIP_PALM) ||
1952             (rdev->family == CHIP_SUMO) ||
1953             (rdev->family == CHIP_SUMO2))
1954                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1955         else
1956                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1957
1958         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1959          * not have bank info, so create a custom tiling dword.
1960          * bits 3:0   num_pipes
1961          * bits 7:4   num_banks
1962          * bits 11:8  group_size
1963          * bits 15:12 row_size
1964          */
1965         rdev->config.evergreen.tile_config = 0;
1966         switch (rdev->config.evergreen.max_tile_pipes) {
1967         case 1:
1968         default:
1969                 rdev->config.evergreen.tile_config |= (0 << 0);
1970                 break;
1971         case 2:
1972                 rdev->config.evergreen.tile_config |= (1 << 0);
1973                 break;
1974         case 4:
1975                 rdev->config.evergreen.tile_config |= (2 << 0);
1976                 break;
1977         case 8:
1978                 rdev->config.evergreen.tile_config |= (3 << 0);
1979                 break;
1980         }
1981         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1982         if (rdev->flags & RADEON_IS_IGP)
1983                 rdev->config.evergreen.tile_config |= 1 << 4;
1984         else {
1985                 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1986                         rdev->config.evergreen.tile_config |= 1 << 4;
1987                 else
1988                         rdev->config.evergreen.tile_config |= 0 << 4;
1989         }
1990         rdev->config.evergreen.tile_config |= 0 << 8;
1991         rdev->config.evergreen.tile_config |=
1992                 ((gb_addr_config & 0x30000000) >> 28) << 12;
1993
1994         num_shader_engines = (gb_addr_config & NUM_SHADER_ENGINES(3) >> 12) + 1;
1995
1996         if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK)) {
1997                 u32 efuse_straps_4;
1998                 u32 efuse_straps_3;
1999
2000                 WREG32(RCU_IND_INDEX, 0x204);
2001                 efuse_straps_4 = RREG32(RCU_IND_DATA);
2002                 WREG32(RCU_IND_INDEX, 0x203);
2003                 efuse_straps_3 = RREG32(RCU_IND_DATA);
2004                 tmp = (((efuse_straps_4 & 0xf) << 4) |
2005                       ((efuse_straps_3 & 0xf0000000) >> 28));
2006         } else {
2007                 tmp = 0;
2008                 for (i = (rdev->config.evergreen.num_ses - 1); i >= 0; i--) {
2009                         u32 rb_disable_bitmap;
2010
2011                         WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2012                         WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
2013                         rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
2014                         tmp <<= 4;
2015                         tmp |= rb_disable_bitmap;
2016                 }
2017         }
2018         /* enabled rb are just the one not disabled :) */
2019         disabled_rb_mask = tmp;
2020
2021         WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2022         WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
2023
2024         WREG32(GB_ADDR_CONFIG, gb_addr_config);
2025         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2026         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2027
2028         tmp = gb_addr_config & NUM_PIPES_MASK;
2029         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.evergreen.max_backends,
2030                                         EVERGREEN_MAX_BACKENDS, disabled_rb_mask);
2031         WREG32(GB_BACKEND_MAP, tmp);
2032
2033         WREG32(CGTS_SYS_TCC_DISABLE, 0);
2034         WREG32(CGTS_TCC_DISABLE, 0);
2035         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2036         WREG32(CGTS_USER_TCC_DISABLE, 0);
2037
2038         /* set HW defaults for 3D engine */
2039         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2040                                      ROQ_IB2_START(0x2b)));
2041
2042         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2043
2044         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2045                              SYNC_GRADIENT |
2046                              SYNC_WALKER |
2047                              SYNC_ALIGNER));
2048
2049         sx_debug_1 = RREG32(SX_DEBUG_1);
2050         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2051         WREG32(SX_DEBUG_1, sx_debug_1);
2052
2053
2054         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2055         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2056         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2057         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2058
2059         if (rdev->family <= CHIP_SUMO2)
2060                 WREG32(SMX_SAR_CTL0, 0x00010000);
2061
2062         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2063                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2064                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2065
2066         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2067                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2068                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2069
2070         WREG32(VGT_NUM_INSTANCES, 1);
2071         WREG32(SPI_CONFIG_CNTL, 0);
2072         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2073         WREG32(CP_PERFMON_CNTL, 0);
2074
2075         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2076                                   FETCH_FIFO_HIWATER(0x4) |
2077                                   DONE_FIFO_HIWATER(0xe0) |
2078                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2079
2080         sq_config = RREG32(SQ_CONFIG);
2081         sq_config &= ~(PS_PRIO(3) |
2082                        VS_PRIO(3) |
2083                        GS_PRIO(3) |
2084                        ES_PRIO(3));
2085         sq_config |= (VC_ENABLE |
2086                       EXPORT_SRC_C |
2087                       PS_PRIO(0) |
2088                       VS_PRIO(1) |
2089                       GS_PRIO(2) |
2090                       ES_PRIO(3));
2091
2092         switch (rdev->family) {
2093         case CHIP_CEDAR:
2094         case CHIP_PALM:
2095         case CHIP_SUMO:
2096         case CHIP_SUMO2:
2097         case CHIP_CAICOS:
2098                 /* no vertex cache */
2099                 sq_config &= ~VC_ENABLE;
2100                 break;
2101         default:
2102                 break;
2103         }
2104
2105         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2106
2107         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2108         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2109         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2110         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2111         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2112         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2113         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2114
2115         switch (rdev->family) {
2116         case CHIP_CEDAR:
2117         case CHIP_PALM:
2118         case CHIP_SUMO:
2119         case CHIP_SUMO2:
2120                 ps_thread_count = 96;
2121                 break;
2122         default:
2123                 ps_thread_count = 128;
2124                 break;
2125         }
2126
2127         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2128         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2129         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2130         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2131         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2132         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2133
2134         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2135         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2136         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2137         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2138         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2139         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2140
2141         WREG32(SQ_CONFIG, sq_config);
2142         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2143         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2144         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2145         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2146         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2147         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2148         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2149         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2150         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2151         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2152
2153         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2154                                           FORCE_EOV_MAX_REZ_CNT(255)));
2155
2156         switch (rdev->family) {
2157         case CHIP_CEDAR:
2158         case CHIP_PALM:
2159         case CHIP_SUMO:
2160         case CHIP_SUMO2:
2161         case CHIP_CAICOS:
2162                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2163                 break;
2164         default:
2165                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2166                 break;
2167         }
2168         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2169         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2170
2171         WREG32(VGT_GS_VERTEX_REUSE, 16);
2172         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2173         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2174
2175         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2176         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2177
2178         WREG32(CB_PERF_CTR0_SEL_0, 0);
2179         WREG32(CB_PERF_CTR0_SEL_1, 0);
2180         WREG32(CB_PERF_CTR1_SEL_0, 0);
2181         WREG32(CB_PERF_CTR1_SEL_1, 0);
2182         WREG32(CB_PERF_CTR2_SEL_0, 0);
2183         WREG32(CB_PERF_CTR2_SEL_1, 0);
2184         WREG32(CB_PERF_CTR3_SEL_0, 0);
2185         WREG32(CB_PERF_CTR3_SEL_1, 0);
2186
2187         /* clear render buffer base addresses */
2188         WREG32(CB_COLOR0_BASE, 0);
2189         WREG32(CB_COLOR1_BASE, 0);
2190         WREG32(CB_COLOR2_BASE, 0);
2191         WREG32(CB_COLOR3_BASE, 0);
2192         WREG32(CB_COLOR4_BASE, 0);
2193         WREG32(CB_COLOR5_BASE, 0);
2194         WREG32(CB_COLOR6_BASE, 0);
2195         WREG32(CB_COLOR7_BASE, 0);
2196         WREG32(CB_COLOR8_BASE, 0);
2197         WREG32(CB_COLOR9_BASE, 0);
2198         WREG32(CB_COLOR10_BASE, 0);
2199         WREG32(CB_COLOR11_BASE, 0);
2200
2201         /* set the shader const cache sizes to 0 */
2202         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2203                 WREG32(i, 0);
2204         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2205                 WREG32(i, 0);
2206
2207         tmp = RREG32(HDP_MISC_CNTL);
2208         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2209         WREG32(HDP_MISC_CNTL, tmp);
2210
2211         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2212         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2213
2214         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2215
2216         udelay(50);
2217
2218 }
2219
2220 int evergreen_mc_init(struct radeon_device *rdev)
2221 {
2222         u32 tmp;
2223         int chansize, numchan;
2224
2225         /* Get VRAM informations */
2226         rdev->mc.vram_is_ddr = true;
2227         if ((rdev->family == CHIP_PALM) ||
2228             (rdev->family == CHIP_SUMO) ||
2229             (rdev->family == CHIP_SUMO2))
2230                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2231         else
2232                 tmp = RREG32(MC_ARB_RAMCFG);
2233         if (tmp & CHANSIZE_OVERRIDE) {
2234                 chansize = 16;
2235         } else if (tmp & CHANSIZE_MASK) {
2236                 chansize = 64;
2237         } else {
2238                 chansize = 32;
2239         }
2240         tmp = RREG32(MC_SHARED_CHMAP);
2241         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2242         case 0:
2243         default:
2244                 numchan = 1;
2245                 break;
2246         case 1:
2247                 numchan = 2;
2248                 break;
2249         case 2:
2250                 numchan = 4;
2251                 break;
2252         case 3:
2253                 numchan = 8;
2254                 break;
2255         }
2256         rdev->mc.vram_width = numchan * chansize;
2257         /* Could aper size report 0 ? */
2258         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2259         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2260         /* Setup GPU memory space */
2261         if ((rdev->family == CHIP_PALM) ||
2262             (rdev->family == CHIP_SUMO) ||
2263             (rdev->family == CHIP_SUMO2)) {
2264                 /* size in bytes on fusion */
2265                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2266                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2267         } else {
2268                 /* size in MB on evergreen/cayman/tn */
2269                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2270                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2271         }
2272         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2273         r700_vram_gtt_location(rdev, &rdev->mc);
2274         radeon_update_bandwidth_info(rdev);
2275
2276         return 0;
2277 }
2278
2279 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2280 {
2281         u32 srbm_status;
2282         u32 grbm_status;
2283         u32 grbm_status_se0, grbm_status_se1;
2284
2285         srbm_status = RREG32(SRBM_STATUS);
2286         grbm_status = RREG32(GRBM_STATUS);
2287         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2288         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2289         if (!(grbm_status & GUI_ACTIVE)) {
2290                 radeon_ring_lockup_update(ring);
2291                 return false;
2292         }
2293         /* force CP activities */
2294         radeon_ring_force_activity(rdev, ring);
2295         return radeon_ring_test_lockup(rdev, ring);
2296 }
2297
2298 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2299 {
2300         struct evergreen_mc_save save;
2301         u32 grbm_reset = 0;
2302
2303         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2304                 return 0;
2305
2306         dev_info(rdev->dev, "GPU softreset \n");
2307         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2308                 RREG32(GRBM_STATUS));
2309         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2310                 RREG32(GRBM_STATUS_SE0));
2311         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2312                 RREG32(GRBM_STATUS_SE1));
2313         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2314                 RREG32(SRBM_STATUS));
2315         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2316                 RREG32(CP_STALLED_STAT1));
2317         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2318                 RREG32(CP_STALLED_STAT2));
2319         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
2320                 RREG32(CP_BUSY_STAT));
2321         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
2322                 RREG32(CP_STAT));
2323         evergreen_mc_stop(rdev, &save);
2324         if (evergreen_mc_wait_for_idle(rdev)) {
2325                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2326         }
2327         /* Disable CP parsing/prefetching */
2328         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2329
2330         /* reset all the gfx blocks */
2331         grbm_reset = (SOFT_RESET_CP |
2332                       SOFT_RESET_CB |
2333                       SOFT_RESET_DB |
2334                       SOFT_RESET_PA |
2335                       SOFT_RESET_SC |
2336                       SOFT_RESET_SPI |
2337                       SOFT_RESET_SH |
2338                       SOFT_RESET_SX |
2339                       SOFT_RESET_TC |
2340                       SOFT_RESET_TA |
2341                       SOFT_RESET_VC |
2342                       SOFT_RESET_VGT);
2343
2344         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2345         WREG32(GRBM_SOFT_RESET, grbm_reset);
2346         (void)RREG32(GRBM_SOFT_RESET);
2347         udelay(50);
2348         WREG32(GRBM_SOFT_RESET, 0);
2349         (void)RREG32(GRBM_SOFT_RESET);
2350         /* Wait a little for things to settle down */
2351         udelay(50);
2352         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2353                 RREG32(GRBM_STATUS));
2354         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2355                 RREG32(GRBM_STATUS_SE0));
2356         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2357                 RREG32(GRBM_STATUS_SE1));
2358         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2359                 RREG32(SRBM_STATUS));
2360         dev_info(rdev->dev, "  R_008674_CP_STALLED_STAT1 = 0x%08X\n",
2361                 RREG32(CP_STALLED_STAT1));
2362         dev_info(rdev->dev, "  R_008678_CP_STALLED_STAT2 = 0x%08X\n",
2363                 RREG32(CP_STALLED_STAT2));
2364         dev_info(rdev->dev, "  R_00867C_CP_BUSY_STAT     = 0x%08X\n",
2365                 RREG32(CP_BUSY_STAT));
2366         dev_info(rdev->dev, "  R_008680_CP_STAT          = 0x%08X\n",
2367                 RREG32(CP_STAT));
2368         evergreen_mc_resume(rdev, &save);
2369         return 0;
2370 }
2371
2372 int evergreen_asic_reset(struct radeon_device *rdev)
2373 {
2374         return evergreen_gpu_soft_reset(rdev);
2375 }
2376
2377 /* Interrupts */
2378
2379 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2380 {
2381         switch (crtc) {
2382         case 0:
2383                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2384         case 1:
2385                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2386         case 2:
2387                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2388         case 3:
2389                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2390         case 4:
2391                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2392         case 5:
2393                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2394         default:
2395                 return 0;
2396         }
2397 }
2398
2399 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2400 {
2401         u32 tmp;
2402
2403         if (rdev->family >= CHIP_CAYMAN) {
2404                 cayman_cp_int_cntl_setup(rdev, 0,
2405                                          CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2406                 cayman_cp_int_cntl_setup(rdev, 1, 0);
2407                 cayman_cp_int_cntl_setup(rdev, 2, 0);
2408         } else
2409                 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2410         WREG32(GRBM_INT_CNTL, 0);
2411         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2412         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2413         if (rdev->num_crtc >= 4) {
2414                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2415                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2416         }
2417         if (rdev->num_crtc >= 6) {
2418                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2419                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2420         }
2421
2422         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2423         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2424         if (rdev->num_crtc >= 4) {
2425                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2426                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2427         }
2428         if (rdev->num_crtc >= 6) {
2429                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2430                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2431         }
2432
2433         /* only one DAC on DCE6 */
2434         if (!ASIC_IS_DCE6(rdev))
2435                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2436         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2437
2438         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2439         WREG32(DC_HPD1_INT_CONTROL, tmp);
2440         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2441         WREG32(DC_HPD2_INT_CONTROL, tmp);
2442         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2443         WREG32(DC_HPD3_INT_CONTROL, tmp);
2444         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2445         WREG32(DC_HPD4_INT_CONTROL, tmp);
2446         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2447         WREG32(DC_HPD5_INT_CONTROL, tmp);
2448         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2449         WREG32(DC_HPD6_INT_CONTROL, tmp);
2450
2451 }
2452
2453 int evergreen_irq_set(struct radeon_device *rdev)
2454 {
2455         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2456         u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
2457         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2458         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2459         u32 grbm_int_cntl = 0;
2460         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2461         u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0;
2462
2463         if (!rdev->irq.installed) {
2464                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2465                 return -EINVAL;
2466         }
2467         /* don't enable anything if the ih is disabled */
2468         if (!rdev->ih.enabled) {
2469                 r600_disable_interrupts(rdev);
2470                 /* force the active interrupt state to all disabled */
2471                 evergreen_disable_interrupt_state(rdev);
2472                 return 0;
2473         }
2474
2475         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2476         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2477         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2478         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2479         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2480         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2481
2482         afmt1 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2483         afmt2 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2484         afmt3 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2485         afmt4 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2486         afmt5 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2487         afmt6 = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET) & ~AFMT_AZ_FORMAT_WTRIG_MASK;
2488
2489         if (rdev->family >= CHIP_CAYMAN) {
2490                 /* enable CP interrupts on all rings */
2491                 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2492                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2493                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2494                 }
2495                 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
2496                         DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2497                         cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2498                 }
2499                 if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
2500                         DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2501                         cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2502                 }
2503         } else {
2504                 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
2505                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2506                         cp_int_cntl |= RB_INT_ENABLE;
2507                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2508                 }
2509         }
2510
2511         if (rdev->irq.crtc_vblank_int[0] ||
2512             atomic_read(&rdev->irq.pflip[0])) {
2513                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2514                 crtc1 |= VBLANK_INT_MASK;
2515         }
2516         if (rdev->irq.crtc_vblank_int[1] ||
2517             atomic_read(&rdev->irq.pflip[1])) {
2518                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2519                 crtc2 |= VBLANK_INT_MASK;
2520         }
2521         if (rdev->irq.crtc_vblank_int[2] ||
2522             atomic_read(&rdev->irq.pflip[2])) {
2523                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2524                 crtc3 |= VBLANK_INT_MASK;
2525         }
2526         if (rdev->irq.crtc_vblank_int[3] ||
2527             atomic_read(&rdev->irq.pflip[3])) {
2528                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2529                 crtc4 |= VBLANK_INT_MASK;
2530         }
2531         if (rdev->irq.crtc_vblank_int[4] ||
2532             atomic_read(&rdev->irq.pflip[4])) {
2533                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2534                 crtc5 |= VBLANK_INT_MASK;
2535         }
2536         if (rdev->irq.crtc_vblank_int[5] ||
2537             atomic_read(&rdev->irq.pflip[5])) {
2538                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2539                 crtc6 |= VBLANK_INT_MASK;
2540         }
2541         if (rdev->irq.hpd[0]) {
2542                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2543                 hpd1 |= DC_HPDx_INT_EN;
2544         }
2545         if (rdev->irq.hpd[1]) {
2546                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2547                 hpd2 |= DC_HPDx_INT_EN;
2548         }
2549         if (rdev->irq.hpd[2]) {
2550                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2551                 hpd3 |= DC_HPDx_INT_EN;
2552         }
2553         if (rdev->irq.hpd[3]) {
2554                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2555                 hpd4 |= DC_HPDx_INT_EN;
2556         }
2557         if (rdev->irq.hpd[4]) {
2558                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2559                 hpd5 |= DC_HPDx_INT_EN;
2560         }
2561         if (rdev->irq.hpd[5]) {
2562                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2563                 hpd6 |= DC_HPDx_INT_EN;
2564         }
2565         if (rdev->irq.afmt[0]) {
2566                 DRM_DEBUG("evergreen_irq_set: hdmi 0\n");
2567                 afmt1 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2568         }
2569         if (rdev->irq.afmt[1]) {
2570                 DRM_DEBUG("evergreen_irq_set: hdmi 1\n");
2571                 afmt2 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2572         }
2573         if (rdev->irq.afmt[2]) {
2574                 DRM_DEBUG("evergreen_irq_set: hdmi 2\n");
2575                 afmt3 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2576         }
2577         if (rdev->irq.afmt[3]) {
2578                 DRM_DEBUG("evergreen_irq_set: hdmi 3\n");
2579                 afmt4 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2580         }
2581         if (rdev->irq.afmt[4]) {
2582                 DRM_DEBUG("evergreen_irq_set: hdmi 4\n");
2583                 afmt5 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2584         }
2585         if (rdev->irq.afmt[5]) {
2586                 DRM_DEBUG("evergreen_irq_set: hdmi 5\n");
2587                 afmt6 |= AFMT_AZ_FORMAT_WTRIG_MASK;
2588         }
2589         if (rdev->irq.gui_idle) {
2590                 DRM_DEBUG("gui idle\n");
2591                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2592         }
2593
2594         if (rdev->family >= CHIP_CAYMAN) {
2595                 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2596                 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2597                 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2598         } else
2599                 WREG32(CP_INT_CNTL, cp_int_cntl);
2600         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2601
2602         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2603         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2604         if (rdev->num_crtc >= 4) {
2605                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2606                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2607         }
2608         if (rdev->num_crtc >= 6) {
2609                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2610                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2611         }
2612
2613         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2614         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2615         if (rdev->num_crtc >= 4) {
2616                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2617                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2618         }
2619         if (rdev->num_crtc >= 6) {
2620                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2621                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2622         }
2623
2624         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2625         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2626         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2627         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2628         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2629         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2630
2631         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, afmt1);
2632         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, afmt2);
2633         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, afmt3);
2634         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, afmt4);
2635         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, afmt5);
2636         WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, afmt6);
2637
2638         return 0;
2639 }
2640
2641 static void evergreen_irq_ack(struct radeon_device *rdev)
2642 {
2643         u32 tmp;
2644
2645         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2646         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2647         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2648         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2649         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2650         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2651         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2652         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2653         if (rdev->num_crtc >= 4) {
2654                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2655                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2656         }
2657         if (rdev->num_crtc >= 6) {
2658                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2659                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2660         }
2661
2662         rdev->irq.stat_regs.evergreen.afmt_status1 = RREG32(AFMT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2663         rdev->irq.stat_regs.evergreen.afmt_status2 = RREG32(AFMT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2664         rdev->irq.stat_regs.evergreen.afmt_status3 = RREG32(AFMT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2665         rdev->irq.stat_regs.evergreen.afmt_status4 = RREG32(AFMT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2666         rdev->irq.stat_regs.evergreen.afmt_status5 = RREG32(AFMT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2667         rdev->irq.stat_regs.evergreen.afmt_status6 = RREG32(AFMT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2668
2669         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2670                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2671         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2672                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2673         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2674                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2675         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2676                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2677         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2678                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2679         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2680                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2681
2682         if (rdev->num_crtc >= 4) {
2683                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2684                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2685                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2686                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2687                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2688                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2689                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2690                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2691                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2692                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2693                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2694                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2695         }
2696
2697         if (rdev->num_crtc >= 6) {
2698                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2699                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2700                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2701                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2702                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2703                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2704                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2705                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2706                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2707                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2708                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2709                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2710         }
2711
2712         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2713                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2714                 tmp |= DC_HPDx_INT_ACK;
2715                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2716         }
2717         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2718                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2719                 tmp |= DC_HPDx_INT_ACK;
2720                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2721         }
2722         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2723                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2724                 tmp |= DC_HPDx_INT_ACK;
2725                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2726         }
2727         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2728                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2729                 tmp |= DC_HPDx_INT_ACK;
2730                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2731         }
2732         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2733                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2734                 tmp |= DC_HPDx_INT_ACK;
2735                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2736         }
2737         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2738                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2739                 tmp |= DC_HPDx_INT_ACK;
2740                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2741         }
2742         if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
2743                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
2744                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2745                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, tmp);
2746         }
2747         if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
2748                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2749                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2750                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, tmp);
2751         }
2752         if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
2753                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
2754                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2755                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, tmp);
2756         }
2757         if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
2758                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
2759                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2760                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, tmp);
2761         }
2762         if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
2763                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
2764                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2765                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, tmp);
2766         }
2767         if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
2768                 tmp = RREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2769                 tmp |= AFMT_AZ_FORMAT_WTRIG_ACK;
2770                 WREG32(AFMT_AUDIO_PACKET_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, tmp);
2771         }
2772 }
2773
2774 void evergreen_irq_disable(struct radeon_device *rdev)
2775 {
2776         r600_disable_interrupts(rdev);
2777         /* Wait and acknowledge irq */
2778         mdelay(1);
2779         evergreen_irq_ack(rdev);
2780         evergreen_disable_interrupt_state(rdev);
2781 }
2782
2783 void evergreen_irq_suspend(struct radeon_device *rdev)
2784 {
2785         evergreen_irq_disable(rdev);
2786         r600_rlc_stop(rdev);
2787 }
2788
2789 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2790 {
2791         u32 wptr, tmp;
2792
2793         if (rdev->wb.enabled)
2794                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2795         else
2796                 wptr = RREG32(IH_RB_WPTR);
2797
2798         if (wptr & RB_OVERFLOW) {
2799                 /* When a ring buffer overflow happen start parsing interrupt
2800                  * from the last not overwritten vector (wptr + 16). Hopefully
2801                  * this should allow us to catchup.
2802                  */
2803                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2804                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2805                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2806                 tmp = RREG32(IH_RB_CNTL);
2807                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2808                 WREG32(IH_RB_CNTL, tmp);
2809         }
2810         return (wptr & rdev->ih.ptr_mask);
2811 }
2812
2813 int evergreen_irq_process(struct radeon_device *rdev)
2814 {
2815         u32 wptr;
2816         u32 rptr;
2817         u32 src_id, src_data;
2818         u32 ring_index;
2819         bool queue_hotplug = false;
2820         bool queue_hdmi = false;
2821
2822         if (!rdev->ih.enabled || rdev->shutdown)
2823                 return IRQ_NONE;
2824
2825         wptr = evergreen_get_ih_wptr(rdev);
2826
2827 restart_ih:
2828         /* is somebody else already processing irqs? */
2829         if (atomic_xchg(&rdev->ih.lock, 1))
2830                 return IRQ_NONE;
2831
2832         rptr = rdev->ih.rptr;
2833         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2834
2835         /* Order reading of wptr vs. reading of IH ring data */
2836         rmb();
2837
2838         /* display interrupts */
2839         evergreen_irq_ack(rdev);
2840
2841         while (rptr != wptr) {
2842                 /* wptr/rptr are in bytes! */
2843                 ring_index = rptr / 4;
2844                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2845                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2846
2847                 switch (src_id) {
2848                 case 1: /* D1 vblank/vline */
2849                         switch (src_data) {
2850                         case 0: /* D1 vblank */
2851                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2852                                         if (rdev->irq.crtc_vblank_int[0]) {
2853                                                 drm_handle_vblank(rdev->ddev, 0);
2854                                                 rdev->pm.vblank_sync = true;
2855                                                 wake_up(&rdev->irq.vblank_queue);
2856                                         }
2857                                         if (atomic_read(&rdev->irq.pflip[0]))
2858                                                 radeon_crtc_handle_flip(rdev, 0);
2859                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2860                                         DRM_DEBUG("IH: D1 vblank\n");
2861                                 }
2862                                 break;
2863                         case 1: /* D1 vline */
2864                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2865                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2866                                         DRM_DEBUG("IH: D1 vline\n");
2867                                 }
2868                                 break;
2869                         default:
2870                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2871                                 break;
2872                         }
2873                         break;
2874                 case 2: /* D2 vblank/vline */
2875                         switch (src_data) {
2876                         case 0: /* D2 vblank */
2877                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2878                                         if (rdev->irq.crtc_vblank_int[1]) {
2879                                                 drm_handle_vblank(rdev->ddev, 1);
2880                                                 rdev->pm.vblank_sync = true;
2881                                                 wake_up(&rdev->irq.vblank_queue);
2882                                         }
2883                                         if (atomic_read(&rdev->irq.pflip[1]))
2884                                                 radeon_crtc_handle_flip(rdev, 1);
2885                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2886                                         DRM_DEBUG("IH: D2 vblank\n");
2887                                 }
2888                                 break;
2889                         case 1: /* D2 vline */
2890                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2891                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2892                                         DRM_DEBUG("IH: D2 vline\n");
2893                                 }
2894                                 break;
2895                         default:
2896                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2897                                 break;
2898                         }
2899                         break;
2900                 case 3: /* D3 vblank/vline */
2901                         switch (src_data) {
2902                         case 0: /* D3 vblank */
2903                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2904                                         if (rdev->irq.crtc_vblank_int[2]) {
2905                                                 drm_handle_vblank(rdev->ddev, 2);
2906                                                 rdev->pm.vblank_sync = true;
2907                                                 wake_up(&rdev->irq.vblank_queue);
2908                                         }
2909                                         if (atomic_read(&rdev->irq.pflip[2]))
2910                                                 radeon_crtc_handle_flip(rdev, 2);
2911                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2912                                         DRM_DEBUG("IH: D3 vblank\n");
2913                                 }
2914                                 break;
2915                         case 1: /* D3 vline */
2916                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2917                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2918                                         DRM_DEBUG("IH: D3 vline\n");
2919                                 }
2920                                 break;
2921                         default:
2922                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2923                                 break;
2924                         }
2925                         break;
2926                 case 4: /* D4 vblank/vline */
2927                         switch (src_data) {
2928                         case 0: /* D4 vblank */
2929                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2930                                         if (rdev->irq.crtc_vblank_int[3]) {
2931                                                 drm_handle_vblank(rdev->ddev, 3);
2932                                                 rdev->pm.vblank_sync = true;
2933                                                 wake_up(&rdev->irq.vblank_queue);
2934                                         }
2935                                         if (atomic_read(&rdev->irq.pflip[3]))
2936                                                 radeon_crtc_handle_flip(rdev, 3);
2937                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2938                                         DRM_DEBUG("IH: D4 vblank\n");
2939                                 }
2940                                 break;
2941                         case 1: /* D4 vline */
2942                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2943                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2944                                         DRM_DEBUG("IH: D4 vline\n");
2945                                 }
2946                                 break;
2947                         default:
2948                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2949                                 break;
2950                         }
2951                         break;
2952                 case 5: /* D5 vblank/vline */
2953                         switch (src_data) {
2954                         case 0: /* D5 vblank */
2955                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2956                                         if (rdev->irq.crtc_vblank_int[4]) {
2957                                                 drm_handle_vblank(rdev->ddev, 4);
2958                                                 rdev->pm.vblank_sync = true;
2959                                                 wake_up(&rdev->irq.vblank_queue);
2960                                         }
2961                                         if (atomic_read(&rdev->irq.pflip[4]))
2962                                                 radeon_crtc_handle_flip(rdev, 4);
2963                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2964                                         DRM_DEBUG("IH: D5 vblank\n");
2965                                 }
2966                                 break;
2967                         case 1: /* D5 vline */
2968                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2969                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2970                                         DRM_DEBUG("IH: D5 vline\n");
2971                                 }
2972                                 break;
2973                         default:
2974                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2975                                 break;
2976                         }
2977                         break;
2978                 case 6: /* D6 vblank/vline */
2979                         switch (src_data) {
2980                         case 0: /* D6 vblank */
2981                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2982                                         if (rdev->irq.crtc_vblank_int[5]) {
2983                                                 drm_handle_vblank(rdev->ddev, 5);
2984                                                 rdev->pm.vblank_sync = true;
2985                                                 wake_up(&rdev->irq.vblank_queue);
2986                                         }
2987                                         if (atomic_read(&rdev->irq.pflip[5]))
2988                                                 radeon_crtc_handle_flip(rdev, 5);
2989                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2990                                         DRM_DEBUG("IH: D6 vblank\n");
2991                                 }
2992                                 break;
2993                         case 1: /* D6 vline */
2994                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2995                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2996                                         DRM_DEBUG("IH: D6 vline\n");
2997                                 }
2998                                 break;
2999                         default:
3000                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3001                                 break;
3002                         }
3003                         break;
3004                 case 42: /* HPD hotplug */
3005                         switch (src_data) {
3006                         case 0:
3007                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3008                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3009                                         queue_hotplug = true;
3010                                         DRM_DEBUG("IH: HPD1\n");
3011                                 }
3012                                 break;
3013                         case 1:
3014                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3015                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3016                                         queue_hotplug = true;
3017                                         DRM_DEBUG("IH: HPD2\n");
3018                                 }
3019                                 break;
3020                         case 2:
3021                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3022                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3023                                         queue_hotplug = true;
3024                                         DRM_DEBUG("IH: HPD3\n");
3025                                 }
3026                                 break;
3027                         case 3:
3028                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3029                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3030                                         queue_hotplug = true;
3031                                         DRM_DEBUG("IH: HPD4\n");
3032                                 }
3033                                 break;
3034                         case 4:
3035                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3036                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3037                                         queue_hotplug = true;
3038                                         DRM_DEBUG("IH: HPD5\n");
3039                                 }
3040                                 break;
3041                         case 5:
3042                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3043                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3044                                         queue_hotplug = true;
3045                                         DRM_DEBUG("IH: HPD6\n");
3046                                 }
3047                                 break;
3048                         default:
3049                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3050                                 break;
3051                         }
3052                         break;
3053                 case 44: /* hdmi */
3054                         switch (src_data) {
3055                         case 0:
3056                                 if (rdev->irq.stat_regs.evergreen.afmt_status1 & AFMT_AZ_FORMAT_WTRIG) {
3057                                         rdev->irq.stat_regs.evergreen.afmt_status1 &= ~AFMT_AZ_FORMAT_WTRIG;
3058                                         queue_hdmi = true;
3059                                         DRM_DEBUG("IH: HDMI0\n");
3060                                 }
3061                                 break;
3062                         case 1:
3063                                 if (rdev->irq.stat_regs.evergreen.afmt_status2 & AFMT_AZ_FORMAT_WTRIG) {
3064                                         rdev->irq.stat_regs.evergreen.afmt_status2 &= ~AFMT_AZ_FORMAT_WTRIG;
3065                                         queue_hdmi = true;
3066                                         DRM_DEBUG("IH: HDMI1\n");
3067                                 }
3068                                 break;
3069                         case 2:
3070                                 if (rdev->irq.stat_regs.evergreen.afmt_status3 & AFMT_AZ_FORMAT_WTRIG) {
3071                                         rdev->irq.stat_regs.evergreen.afmt_status3 &= ~AFMT_AZ_FORMAT_WTRIG;
3072                                         queue_hdmi = true;
3073                                         DRM_DEBUG("IH: HDMI2\n");
3074                                 }
3075                                 break;
3076                         case 3:
3077                                 if (rdev->irq.stat_regs.evergreen.afmt_status4 & AFMT_AZ_FORMAT_WTRIG) {
3078                                         rdev->irq.stat_regs.evergreen.afmt_status4 &= ~AFMT_AZ_FORMAT_WTRIG;
3079                                         queue_hdmi = true;
3080                                         DRM_DEBUG("IH: HDMI3\n");
3081                                 }
3082                                 break;
3083                         case 4:
3084                                 if (rdev->irq.stat_regs.evergreen.afmt_status5 & AFMT_AZ_FORMAT_WTRIG) {
3085                                         rdev->irq.stat_regs.evergreen.afmt_status5 &= ~AFMT_AZ_FORMAT_WTRIG;
3086                                         queue_hdmi = true;
3087                                         DRM_DEBUG("IH: HDMI4\n");
3088                                 }
3089                                 break;
3090                         case 5:
3091                                 if (rdev->irq.stat_regs.evergreen.afmt_status6 & AFMT_AZ_FORMAT_WTRIG) {
3092                                         rdev->irq.stat_regs.evergreen.afmt_status6 &= ~AFMT_AZ_FORMAT_WTRIG;
3093                                         queue_hdmi = true;
3094                                         DRM_DEBUG("IH: HDMI5\n");
3095                                 }
3096                                 break;
3097                         default:
3098                                 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
3099                                 break;
3100                         }
3101                         break;
3102                 case 176: /* CP_INT in ring buffer */
3103                 case 177: /* CP_INT in IB1 */
3104                 case 178: /* CP_INT in IB2 */
3105                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3106                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3107                         break;
3108                 case 181: /* CP EOP event */
3109                         DRM_DEBUG("IH: CP EOP\n");
3110                         if (rdev->family >= CHIP_CAYMAN) {
3111                                 switch (src_data) {
3112                                 case 0:
3113                                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3114                                         break;
3115                                 case 1:
3116                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3117                                         break;
3118                                 case 2:
3119                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3120                                         break;
3121                                 }
3122                         } else
3123                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3124                         break;
3125                 case 233: /* GUI IDLE */
3126                         DRM_DEBUG("IH: GUI idle\n");
3127                         wake_up(&rdev->irq.idle_queue);
3128                         break;
3129                 default:
3130                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3131                         break;
3132                 }
3133
3134                 /* wptr/rptr are in bytes! */
3135                 rptr += 16;
3136                 rptr &= rdev->ih.ptr_mask;
3137         }
3138         if (queue_hotplug)
3139                 schedule_work(&rdev->hotplug_work);
3140         if (queue_hdmi)
3141                 schedule_work(&rdev->audio_work);
3142         rdev->ih.rptr = rptr;
3143         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3144         atomic_set(&rdev->ih.lock, 0);
3145
3146         /* make sure wptr hasn't changed while processing */
3147         wptr = evergreen_get_ih_wptr(rdev);
3148         if (wptr != rptr)
3149                 goto restart_ih;
3150
3151         return IRQ_HANDLED;
3152 }
3153
3154 static int evergreen_startup(struct radeon_device *rdev)
3155 {
3156         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3157         int r;
3158
3159         /* enable pcie gen2 link */
3160         evergreen_pcie_gen2_enable(rdev);
3161
3162         if (ASIC_IS_DCE5(rdev)) {
3163                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3164                         r = ni_init_microcode(rdev);
3165                         if (r) {
3166                                 DRM_ERROR("Failed to load firmware!\n");
3167                                 return r;
3168                         }
3169                 }
3170                 r = ni_mc_load_microcode(rdev);
3171                 if (r) {
3172                         DRM_ERROR("Failed to load MC firmware!\n");
3173                         return r;
3174                 }
3175         } else {
3176                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3177                         r = r600_init_microcode(rdev);
3178                         if (r) {
3179                                 DRM_ERROR("Failed to load firmware!\n");
3180                                 return r;
3181                         }
3182                 }
3183         }
3184
3185         r = r600_vram_scratch_init(rdev);
3186         if (r)
3187                 return r;
3188
3189         evergreen_mc_program(rdev);
3190         if (rdev->flags & RADEON_IS_AGP) {
3191                 evergreen_agp_enable(rdev);
3192         } else {
3193                 r = evergreen_pcie_gart_enable(rdev);
3194                 if (r)
3195                         return r;
3196         }
3197         evergreen_gpu_init(rdev);
3198
3199         r = evergreen_blit_init(rdev);
3200         if (r) {
3201                 r600_blit_fini(rdev);
3202                 rdev->asic->copy.copy = NULL;
3203                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3204         }
3205
3206         /* allocate wb buffer */
3207         r = radeon_wb_init(rdev);
3208         if (r)
3209                 return r;
3210
3211         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3212         if (r) {
3213                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3214                 return r;
3215         }
3216
3217         /* Enable IRQ */
3218         r = r600_irq_init(rdev);
3219         if (r) {
3220                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3221                 radeon_irq_kms_fini(rdev);
3222                 return r;
3223         }
3224         evergreen_irq_set(rdev);
3225
3226         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3227                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3228                              0, 0xfffff, RADEON_CP_PACKET2);
3229         if (r)
3230                 return r;
3231         r = evergreen_cp_load_microcode(rdev);
3232         if (r)
3233                 return r;
3234         r = evergreen_cp_resume(rdev);
3235         if (r)
3236                 return r;
3237
3238         r = radeon_ib_pool_init(rdev);
3239         if (r) {
3240                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3241                 return r;
3242         }
3243
3244         r = r600_audio_init(rdev);
3245         if (r) {
3246                 DRM_ERROR("radeon: audio init failed\n");
3247                 return r;
3248         }
3249
3250         return 0;
3251 }
3252
3253 int evergreen_resume(struct radeon_device *rdev)
3254 {
3255         int r;
3256
3257         /* reset the asic, the gfx blocks are often in a bad state
3258          * after the driver is unloaded or after a resume
3259          */
3260         if (radeon_asic_reset(rdev))
3261                 dev_warn(rdev->dev, "GPU reset failed !\n");
3262         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3263          * posting will perform necessary task to bring back GPU into good
3264          * shape.
3265          */
3266         /* post card */
3267         atom_asic_init(rdev->mode_info.atom_context);
3268
3269         rdev->accel_working = true;
3270         r = evergreen_startup(rdev);
3271         if (r) {
3272                 DRM_ERROR("evergreen startup failed on resume\n");
3273                 rdev->accel_working = false;
3274                 return r;
3275         }
3276
3277         return r;
3278
3279 }
3280
3281 int evergreen_suspend(struct radeon_device *rdev)
3282 {
3283         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3284
3285         r600_audio_fini(rdev);
3286         r700_cp_stop(rdev);
3287         ring->ready = false;
3288         evergreen_irq_suspend(rdev);
3289         radeon_wb_disable(rdev);
3290         evergreen_pcie_gart_disable(rdev);
3291
3292         return 0;
3293 }
3294
3295 /* Plan is to move initialization in that function and use
3296  * helper function so that radeon_device_init pretty much
3297  * do nothing more than calling asic specific function. This
3298  * should also allow to remove a bunch of callback function
3299  * like vram_info.
3300  */
3301 int evergreen_init(struct radeon_device *rdev)
3302 {
3303         int r;
3304
3305         /* Read BIOS */
3306         if (!radeon_get_bios(rdev)) {
3307                 if (ASIC_IS_AVIVO(rdev))
3308                         return -EINVAL;
3309         }
3310         /* Must be an ATOMBIOS */
3311         if (!rdev->is_atom_bios) {
3312                 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3313                 return -EINVAL;
3314         }
3315         r = radeon_atombios_init(rdev);
3316         if (r)
3317                 return r;
3318         /* reset the asic, the gfx blocks are often in a bad state
3319          * after the driver is unloaded or after a resume
3320          */
3321         if (radeon_asic_reset(rdev))
3322                 dev_warn(rdev->dev, "GPU reset failed !\n");
3323         /* Post card if necessary */
3324         if (!radeon_card_posted(rdev)) {
3325                 if (!rdev->bios) {
3326                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3327                         return -EINVAL;
3328                 }
3329                 DRM_INFO("GPU not posted. posting now...\n");
3330                 atom_asic_init(rdev->mode_info.atom_context);
3331         }
3332         /* Initialize scratch registers */
3333         r600_scratch_init(rdev);
3334         /* Initialize surface registers */
3335         radeon_surface_init(rdev);
3336         /* Initialize clocks */
3337         radeon_get_clock_info(rdev->ddev);
3338         /* Fence driver */
3339         r = radeon_fence_driver_init(rdev);
3340         if (r)
3341                 return r;
3342         /* initialize AGP */
3343         if (rdev->flags & RADEON_IS_AGP) {
3344                 r = radeon_agp_init(rdev);
3345                 if (r)
3346                         radeon_agp_disable(rdev);
3347         }
3348         /* initialize memory controller */
3349         r = evergreen_mc_init(rdev);
3350         if (r)
3351                 return r;
3352         /* Memory manager */
3353         r = radeon_bo_init(rdev);
3354         if (r)
3355                 return r;
3356
3357         r = radeon_irq_kms_init(rdev);
3358         if (r)
3359                 return r;
3360
3361         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3362         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3363
3364         rdev->ih.ring_obj = NULL;
3365         r600_ih_ring_init(rdev, 64 * 1024);
3366
3367         r = r600_pcie_gart_init(rdev);
3368         if (r)
3369                 return r;
3370
3371         rdev->accel_working = true;
3372         r = evergreen_startup(rdev);
3373         if (r) {
3374                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3375                 r700_cp_fini(rdev);
3376                 r600_irq_fini(rdev);
3377                 radeon_wb_fini(rdev);
3378                 radeon_ib_pool_fini(rdev);
3379                 radeon_irq_kms_fini(rdev);
3380                 evergreen_pcie_gart_fini(rdev);
3381                 rdev->accel_working = false;
3382         }
3383
3384         /* Don't start up if the MC ucode is missing on BTC parts.
3385          * The default clocks and voltages before the MC ucode
3386          * is loaded are not suffient for advanced operations.
3387          */
3388         if (ASIC_IS_DCE5(rdev)) {
3389                 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3390                         DRM_ERROR("radeon: MC ucode required for NI+.\n");
3391                         return -EINVAL;
3392                 }
3393         }
3394
3395         return 0;
3396 }
3397
3398 void evergreen_fini(struct radeon_device *rdev)
3399 {
3400         r600_audio_fini(rdev);
3401         r600_blit_fini(rdev);
3402         r700_cp_fini(rdev);
3403         r600_irq_fini(rdev);
3404         radeon_wb_fini(rdev);
3405         radeon_ib_pool_fini(rdev);
3406         radeon_irq_kms_fini(rdev);
3407         evergreen_pcie_gart_fini(rdev);
3408         r600_vram_scratch_fini(rdev);
3409         radeon_gem_fini(rdev);
3410         radeon_fence_driver_fini(rdev);
3411         radeon_agp_fini(rdev);
3412         radeon_bo_fini(rdev);
3413         radeon_atombios_fini(rdev);
3414         kfree(rdev->bios);
3415         rdev->bios = NULL;
3416 }
3417
3418 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3419 {
3420         u32 link_width_cntl, speed_cntl, mask;
3421         int ret;
3422
3423         if (radeon_pcie_gen2 == 0)
3424                 return;
3425
3426         if (rdev->flags & RADEON_IS_IGP)
3427                 return;
3428
3429         if (!(rdev->flags & RADEON_IS_PCIE))
3430                 return;
3431
3432         /* x2 cards have a special sequence */
3433         if (ASIC_IS_X2(rdev))
3434                 return;
3435
3436         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
3437         if (ret != 0)
3438                 return;
3439
3440         if (!(mask & DRM_PCIE_SPEED_50))
3441                 return;
3442
3443         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
3444
3445         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3446         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3447             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3448
3449                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3450                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3451                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3452
3453                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3454                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3455                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3456
3457                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3458                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3459                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3460
3461                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3462                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3463                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3464
3465                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3466                 speed_cntl |= LC_GEN2_EN_STRAP;
3467                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3468
3469         } else {
3470                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3471                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3472                 if (1)
3473                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3474                 else
3475                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3476                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3477         }
3478 }