drivers/gpu/drm/radeon/evergreen_hdmi.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Christian König.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Christian König
  25  *          Rafał Miłecki
  26  */
  27 #include <linux/hdmi.h>
  28 #include <drm/drmP.h>
  29 #include <drm/radeon_drm.h>
  30 #include "radeon.h"
  31 #include "radeon_asic.h"
  32 #include "radeon_audio.h"
  33 #include "evergreend.h"
  34 #include "atom.h"
  35
  36 extern void dce6_afmt_select_pin(struct drm_encoder *encoder);
  37
  38 /* enable the audio stream */
  39 static void dce4_audio_enable(struct radeon_device *rdev,
  40                               struct r600_audio_pin *pin,
  41                               u8 enable_mask)
  42 {
  43         u32 tmp = RREG32(AZ_HOT_PLUG_CONTROL);
  44
  45         if (!pin)
  46                 return;
  47
  48         if (enable_mask) {
  49                 tmp |= AUDIO_ENABLED;
  50                 if (enable_mask & 1)
  51                         tmp |= PIN0_AUDIO_ENABLED;
  52                 if (enable_mask & 2)
  53                         tmp |= PIN1_AUDIO_ENABLED;
  54                 if (enable_mask & 4)
  55                         tmp |= PIN2_AUDIO_ENABLED;
  56                 if (enable_mask & 8)
  57                         tmp |= PIN3_AUDIO_ENABLED;
  58         } else {
  59                 tmp &= ~(AUDIO_ENABLED |
  60                          PIN0_AUDIO_ENABLED |
  61                          PIN1_AUDIO_ENABLED |
  62                          PIN2_AUDIO_ENABLED |
  63                          PIN3_AUDIO_ENABLED);
  64         }
  65
  66         WREG32(AZ_HOT_PLUG_CONTROL, tmp);
  67 }
  68
  69 /*
  70  * update the N and CTS parameters for a given pixel clock rate
  71  */
  72 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
  73 {
  74         struct drm_device *dev = encoder->dev;
  75         struct radeon_device *rdev = dev->dev_private;
  76         struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
  77         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  78         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
  79         uint32_t offset = dig->afmt->offset;
  80
  81         WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
  82         WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
  83
  84         WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
  85         WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
  86
  87         WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
  88         WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
  89 }
  90
  91 void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
  92                 struct drm_connector *connector, struct drm_display_mode *mode)
  93 {
  94         struct radeon_device *rdev = encoder->dev->dev_private;
  95         u32 tmp = 0;
  96
  97         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
  98                 if (connector->latency_present[1])
  99                         tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
 100                                 AUDIO_LIPSYNC(connector->audio_latency[1]);
 101                 else
 102                         tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
 103         } else {
 104                 if (connector->latency_present[0])
 105                         tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
 106                                 AUDIO_LIPSYNC(connector->audio_latency[0]);
 107                 else
 108                         tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
 109         }
 110         WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
 111 }
 112
 113 void dce4_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder,
 114         u8 *sadb, int sad_count)
 115 {
 116         struct radeon_device *rdev = encoder->dev->dev_private;
 117         u32 tmp;
 118
 119         /* program the speaker allocation */
 120         tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
 121         tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
 122         /* set HDMI mode */
 123         tmp |= HDMI_CONNECTION;
 124         if (sad_count)
 125                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
 126         else
 127                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
 128         WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
 129 }
 130
 131 void dce4_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder,
 132         u8 *sadb, int sad_count)
 133 {
 134         struct radeon_device *rdev = encoder->dev->dev_private;
 135         u32 tmp;
 136
 137         /* program the speaker allocation */
 138         tmp = RREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER);
 139         tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK);
 140         /* set DP mode */
 141         tmp |= DP_CONNECTION;
 142         if (sad_count)
 143                 tmp |= SPEAKER_ALLOCATION(sadb[0]);
 144         else
 145                 tmp |= SPEAKER_ALLOCATION(5); /* stereo */
 146         WREG32_ENDPOINT(0, AZ_F0_CODEC_PIN0_CONTROL_CHANNEL_SPEAKER, tmp);
 147 }
 148
 149 void evergreen_hdmi_write_sad_regs(struct drm_encoder *encoder,
 150         struct cea_sad *sads, int sad_count)
 151 {
 152         int i;
 153         struct radeon_device *rdev = encoder->dev->dev_private;
 154         static const u16 eld_reg_to_type[][2] = {
 155                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
 156                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
 157                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
 158                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
 159                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
 160                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
 161                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
 162                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
 163                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
 164                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
 165                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
 166                 { AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
 167         };
 168
 169         for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
 170                 u32 value = 0;
 171                 u8 stereo_freqs = 0;
 172                 int max_channels = -1;
 173                 int j;
 174
 175                 for (j = 0; j < sad_count; j++) {
 176                         struct cea_sad *sad = &sads[j];
 177
 178                         if (sad->format == eld_reg_to_type[i][1]) {
 179                                 if (sad->channels > max_channels) {
 180                                         value = MAX_CHANNELS(sad->channels) |
 181                                                 DESCRIPTOR_BYTE_2(sad->byte2) |
 182                                                 SUPPORTED_FREQUENCIES(sad->freq);
 183                                         max_channels = sad->channels;
 184                                 }
 185
 186                                 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
 187                                         stereo_freqs |= sad->freq;
 188                                 else
 189                                         break;
 190                         }
 191                 }
 192
 193                 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
 194
 195                 WREG32_ENDPOINT(0, eld_reg_to_type[i][0], value);
 196         }
 197 }
 198
 199 /*
 200  * build a HDMI Video Info Frame
 201  */
 202 static void evergreen_hdmi_update_avi_infoframe(struct drm_encoder *encoder,
 203                                                 void *buffer, size_t size)
 204 {
 205         struct drm_device *dev = encoder->dev;
 206         struct radeon_device *rdev = dev->dev_private;
 207         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 208         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 209         uint32_t offset = dig->afmt->offset;
 210         uint8_t *frame = buffer + 3;
 211         uint8_t *header = buffer;
 212
 213         WREG32(AFMT_AVI_INFO0 + offset,
 214                 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
 215         WREG32(AFMT_AVI_INFO1 + offset,
 216                 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
 217         WREG32(AFMT_AVI_INFO2 + offset,
 218                 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
 219         WREG32(AFMT_AVI_INFO3 + offset,
 220                 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
 221 }
 222
 223 static void evergreen_audio_set_dto(struct drm_encoder *encoder, u32 clock)
 224 {
 225         struct drm_device *dev = encoder->dev;
 226         struct radeon_device *rdev = dev->dev_private;
 227         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 228         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 229         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 230         u32 base_rate = 24000;
 231         u32 max_ratio = clock / base_rate;
 232         u32 dto_phase;
 233         u32 dto_modulo = clock;
 234         u32 wallclock_ratio;
 235         u32 dto_cntl;
 236
 237         if (!dig || !dig->afmt)
 238                 return;
 239
 240         if (ASIC_IS_DCE6(rdev)) {
 241                 dto_phase = 24 * 1000;
 242         } else {
 243                 if (max_ratio >= 8) {
 244                         dto_phase = 192 * 1000;
 245                         wallclock_ratio = 3;
 246                 } else if (max_ratio >= 4) {
 247                         dto_phase = 96 * 1000;
 248                         wallclock_ratio = 2;
 249                 } else if (max_ratio >= 2) {
 250                         dto_phase = 48 * 1000;
 251                         wallclock_ratio = 1;
 252                 } else {
 253                         dto_phase = 24 * 1000;
 254                         wallclock_ratio = 0;
 255                 }
 256                 dto_cntl = RREG32(DCCG_AUDIO_DTO0_CNTL) & ~DCCG_AUDIO_DTO_WALLCLOCK_RATIO_MASK;
 257                 dto_cntl |= DCCG_AUDIO_DTO_WALLCLOCK_RATIO(wallclock_ratio);
 258                 WREG32(DCCG_AUDIO_DTO0_CNTL, dto_cntl);
 259         }
 260
 261         /* XXX two dtos; generally use dto0 for hdmi */
 262         /* Express [24MHz / target pixel clock] as an exact rational
 263          * number (coefficient of two integer numbers.  DCCG_AUDIO_DTOx_PHASE
 264          * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
 265          */
 266         WREG32(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL(radeon_crtc->crtc_id));
 267         WREG32(DCCG_AUDIO_DTO0_PHASE, dto_phase);
 268         WREG32(DCCG_AUDIO_DTO0_MODULE, dto_modulo);
 269 }
 270
 271
 272 /*
 273  * update the info frames with the data from the current display mode
 274  */
 275 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
 276 {
 277         struct drm_device *dev = encoder->dev;
 278         struct radeon_device *rdev = dev->dev_private;
 279         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 280         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 281         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 282         u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
 283         struct hdmi_avi_infoframe frame;
 284         uint32_t offset;
 285         ssize_t err;
 286         uint32_t val;
 287         int bpc = 8;
 288
 289         if (!dig || !dig->afmt)
 290                 return;
 291
 292         /* Silent, r600_hdmi_enable will raise WARN for us */
 293         if (!dig->afmt->enabled)
 294                 return;
 295         offset = dig->afmt->offset;
 296
 297         /* hdmi deep color mode general control packets setup, if bpc > 8 */
 298         if (encoder->crtc) {
 299                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 300                 bpc = radeon_crtc->bpc;
 301         }
 302
 303         /* disable audio prior to setting up hw */
 304         if (ASIC_IS_DCE6(rdev)) {
 305                 dig->afmt->pin = dce6_audio_get_pin(rdev);
 306                 dce6_audio_enable(rdev, dig->afmt->pin, 0);
 307         } else {
 308                 dig->afmt->pin = r600_audio_get_pin(rdev);
 309                 dce4_audio_enable(rdev, dig->afmt->pin, 0);
 310         }
 311
 312         evergreen_audio_set_dto(encoder, mode->clock);
 313
 314         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 315                HDMI_NULL_SEND); /* send null packets when required */
 316
 317         WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
 318
 319         val = RREG32(HDMI_CONTROL + offset);
 320         val &= ~HDMI_DEEP_COLOR_ENABLE;
 321         val &= ~HDMI_DEEP_COLOR_DEPTH_MASK;
 322
 323         switch (bpc) {
 324                 case 0:
 325                 case 6:
 326                 case 8:
 327                 case 16:
 328                 default:
 329                         DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
 330                                          connector->name, bpc);
 331                         break;
 332                 case 10:
 333                         val |= HDMI_DEEP_COLOR_ENABLE;
 334                         val |= HDMI_DEEP_COLOR_DEPTH(HDMI_30BIT_DEEP_COLOR);
 335                         DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
 336                                          connector->name);
 337                         break;
 338                 case 12:
 339                         val |= HDMI_DEEP_COLOR_ENABLE;
 340                         val |= HDMI_DEEP_COLOR_DEPTH(HDMI_36BIT_DEEP_COLOR);
 341                         DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
 342                                          connector->name);
 343                         break;
 344         }
 345
 346         WREG32(HDMI_CONTROL + offset, val);
 347
 348         WREG32(HDMI_VBI_PACKET_CONTROL + offset,
 349                HDMI_NULL_SEND | /* send null packets when required */
 350                HDMI_GC_SEND | /* send general control packets */
 351                HDMI_GC_CONT); /* send general control packets every frame */
 352
 353         WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
 354                HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
 355                HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
 356
 357         WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
 358                AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
 359
 360         WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
 361                HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
 362
 363         WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
 364
 365         WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
 366                HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
 367                HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
 368
 369         WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
 370                AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
 371
 372         /* fglrx clears sth in AFMT_AUDIO_PACKET_CONTROL2 here */
 373
 374         if (bpc > 8)
 375                 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
 376                        HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
 377         else
 378                 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
 379                        HDMI_ACR_SOURCE | /* select SW CTS value */
 380                        HDMI_ACR_AUTO_SEND); /* allow hw to sent ACR packets when required */
 381
 382         evergreen_hdmi_update_ACR(encoder, mode->clock);
 383
 384         WREG32(AFMT_60958_0 + offset,
 385                AFMT_60958_CS_CHANNEL_NUMBER_L(1));
 386
 387         WREG32(AFMT_60958_1 + offset,
 388                AFMT_60958_CS_CHANNEL_NUMBER_R(2));
 389
 390         WREG32(AFMT_60958_2 + offset,
 391                AFMT_60958_CS_CHANNEL_NUMBER_2(3) |
 392                AFMT_60958_CS_CHANNEL_NUMBER_3(4) |
 393                AFMT_60958_CS_CHANNEL_NUMBER_4(5) |
 394                AFMT_60958_CS_CHANNEL_NUMBER_5(6) |
 395                AFMT_60958_CS_CHANNEL_NUMBER_6(7) |
 396                AFMT_60958_CS_CHANNEL_NUMBER_7(8));
 397
 398         radeon_audio_write_speaker_allocation(encoder);
 399
 400         WREG32(AFMT_AUDIO_PACKET_CONTROL2 + offset,
 401                AFMT_AUDIO_CHANNEL_ENABLE(0xff));
 402
 403         /* fglrx sets 0x40 in 0x5f80 here */
 404
 405         if (ASIC_IS_DCE6(rdev))
 406                 dce6_afmt_select_pin(encoder);
 407
 408         radeon_audio_write_sad_regs(encoder);
 409         radeon_audio_write_latency_fields(encoder, mode);
 410
 411         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
 412         if (err < 0) {
 413                 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
 414                 return;
 415         }
 416
 417         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
 418         if (err < 0) {
 419                 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
 420                 return;
 421         }
 422
 423         evergreen_hdmi_update_avi_infoframe(encoder, buffer, sizeof(buffer));
 424
 425         WREG32_OR(HDMI_INFOFRAME_CONTROL0 + offset,
 426                   HDMI_AVI_INFO_SEND | /* enable AVI info frames */
 427                   HDMI_AVI_INFO_CONT); /* required for audio info values to be updated */
 428
 429         WREG32_P(HDMI_INFOFRAME_CONTROL1 + offset,
 430                  HDMI_AVI_INFO_LINE(2), /* anything other than 0 */
 431                  ~HDMI_AVI_INFO_LINE_MASK);
 432
 433         WREG32_OR(AFMT_AUDIO_PACKET_CONTROL + offset,
 434                   AFMT_AUDIO_SAMPLE_SEND); /* send audio packets */
 435
 436         /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
 437         WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
 438         WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
 439         WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
 440         WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);
 441
 442         /* enable audio after to setting up hw */
 443         if (ASIC_IS_DCE6(rdev))
 444                 dce6_audio_enable(rdev, dig->afmt->pin, 1);
 445         else
 446                 dce4_audio_enable(rdev, dig->afmt->pin, 0xf);
 447 }
 448
 449 void evergreen_hdmi_enable(struct drm_encoder *encoder, bool enable)
 450 {
 451         struct drm_device *dev = encoder->dev;
 452         struct radeon_device *rdev = dev->dev_private;
 453         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 454         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 455
 456         if (!dig || !dig->afmt)
 457                 return;
 458
 459         /* Silent, r600_hdmi_enable will raise WARN for us */
 460         if (enable && dig->afmt->enabled)
 461                 return;
 462         if (!enable && !dig->afmt->enabled)
 463                 return;
 464
 465         if (!enable && dig->afmt->pin) {
 466                 if (ASIC_IS_DCE6(rdev))
 467                         dce6_audio_enable(rdev, dig->afmt->pin, 0);
 468                 else
 469                         dce4_audio_enable(rdev, dig->afmt->pin, 0);
 470                 dig->afmt->pin = NULL;
 471         }
 472
 473         dig->afmt->enabled = enable;
 474
 475         DRM_DEBUG("%sabling HDMI interface @ 0x%04X for encoder 0x%x\n",
 476                   enable ? "En" : "Dis", dig->afmt->offset, radeon_encoder->encoder_id);
 477 }