2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Christian König.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Christian König
28 #include "radeon_drm.h"
30 #include "radeon_asic.h"
31 #include "evergreend.h"
35 * update the N and CTS parameters for a given pixel clock rate
37 static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock)
39 struct drm_device *dev = encoder->dev;
40 struct radeon_device *rdev = dev->dev_private;
41 struct radeon_hdmi_acr acr = r600_hdmi_acr(clock);
42 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
44 WREG32(HDMI_ACR_32_0 + offset, HDMI_ACR_CTS_32(acr.cts_32khz));
45 WREG32(HDMI_ACR_32_1 + offset, acr.n_32khz);
47 WREG32(HDMI_ACR_44_0 + offset, HDMI_ACR_CTS_44(acr.cts_44_1khz));
48 WREG32(HDMI_ACR_44_1 + offset, acr.n_44_1khz);
50 WREG32(HDMI_ACR_48_0 + offset, HDMI_ACR_CTS_48(acr.cts_48khz));
51 WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
55 * calculate the crc for a given info frame
57 static void evergreen_hdmi_infoframe_checksum(uint8_t packetType,
58 uint8_t versionNumber,
63 frame[0] = packetType + versionNumber + length;
64 for (i = 1; i <= length; i++)
66 frame[0] = 0x100 - frame[0];
70 * build a HDMI Video Info Frame
72 static void evergreen_hdmi_videoinfoframe(
73 struct drm_encoder *encoder,
75 int active_information_present,
76 uint8_t active_format_aspect_ratio,
77 uint8_t scan_information,
79 uint8_t ex_colorimetry,
82 uint8_t picture_aspect_ratio,
83 uint8_t video_format_identification,
84 uint8_t pixel_repetition,
85 uint8_t non_uniform_picture_scaling,
86 uint8_t bar_info_data_valid,
93 struct drm_device *dev = encoder->dev;
94 struct radeon_device *rdev = dev->dev_private;
95 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
101 (scan_information & 0x3) |
102 ((bar_info_data_valid & 0x3) << 2) |
103 ((active_information_present & 0x1) << 4) |
104 ((color_format & 0x3) << 5);
106 (active_format_aspect_ratio & 0xF) |
107 ((picture_aspect_ratio & 0x3) << 4) |
108 ((colorimetry & 0x3) << 6);
110 (non_uniform_picture_scaling & 0x3) |
111 ((quantization & 0x3) << 2) |
112 ((ex_colorimetry & 0x7) << 4) |
114 frame[0x4] = (video_format_identification & 0x7F);
115 frame[0x5] = (pixel_repetition & 0xF);
116 frame[0x6] = (top_bar & 0xFF);
117 frame[0x7] = (top_bar >> 8);
118 frame[0x8] = (bottom_bar & 0xFF);
119 frame[0x9] = (bottom_bar >> 8);
120 frame[0xA] = (left_bar & 0xFF);
121 frame[0xB] = (left_bar >> 8);
122 frame[0xC] = (right_bar & 0xFF);
123 frame[0xD] = (right_bar >> 8);
125 evergreen_hdmi_infoframe_checksum(0x82, 0x02, 0x0D, frame);
126 /* Our header values (type, version, length) should be alright, Intel
127 * is using the same. Checksum function also seems to be OK, it works
128 * fine for audio infoframe. However calculated value is always lower
129 * by 2 in comparison to fglrx. It breaks displaying anything in case
130 * of TVs that strictly check the checksum. Hack it manually here to
131 * workaround this issue. */
134 WREG32(AFMT_AVI_INFO0 + offset,
135 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
136 WREG32(AFMT_AVI_INFO1 + offset,
137 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
138 WREG32(AFMT_AVI_INFO2 + offset,
139 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
140 WREG32(AFMT_AVI_INFO3 + offset,
141 frame[0xC] | (frame[0xD] << 8));
145 * update the info frames with the data from the current display mode
147 void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode)
149 struct drm_device *dev = encoder->dev;
150 struct radeon_device *rdev = dev->dev_private;
151 uint32_t offset = to_radeon_encoder(encoder)->hdmi_offset;
153 if (ASIC_IS_DCE5(rdev))
156 if (!to_radeon_encoder(encoder)->hdmi_enabled)
159 r600_audio_set_clock(encoder, mode->clock);
161 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
162 HDMI_NULL_SEND); /* send null packets when required */
164 WREG32(AFMT_AUDIO_CRC_CONTROL + offset, 0x1000);
166 WREG32(HDMI_AUDIO_PACKET_CONTROL + offset,
167 HDMI_AUDIO_DELAY_EN(1) | /* set the default audio delay */
168 HDMI_AUDIO_PACKETS_PER_LINE(3)); /* should be suffient for all audio modes and small enough for all hblanks */
170 WREG32(AFMT_AUDIO_PACKET_CONTROL + offset,
171 AFMT_AUDIO_SAMPLE_SEND | /* send audio packets */
172 AFMT_60958_CS_UPDATE); /* allow 60958 channel status fields to be updated */
174 WREG32(HDMI_ACR_PACKET_CONTROL + offset,
175 HDMI_ACR_AUTO_SEND | /* allow hw to sent ACR packets when required */
176 HDMI_ACR_SOURCE); /* select SW CTS value */
178 WREG32(HDMI_VBI_PACKET_CONTROL + offset,
179 HDMI_NULL_SEND | /* send null packets when required */
180 HDMI_GC_SEND | /* send general control packets */
181 HDMI_GC_CONT); /* send general control packets every frame */
183 WREG32(HDMI_INFOFRAME_CONTROL0 + offset,
184 HDMI_AVI_INFO_SEND | /* enable AVI info frames */
185 HDMI_AVI_INFO_CONT | /* send AVI info frames every frame/field */
186 HDMI_AUDIO_INFO_SEND | /* enable audio info frames (frames won't be set until audio is enabled) */
187 HDMI_AUDIO_INFO_CONT); /* required for audio info values to be updated */
189 WREG32(AFMT_INFOFRAME_CONTROL0 + offset,
190 AFMT_AUDIO_INFO_UPDATE); /* required for audio info values to be updated */
192 WREG32(HDMI_INFOFRAME_CONTROL1 + offset,
193 HDMI_AVI_INFO_LINE(2) | /* anything other than 0 */
194 HDMI_AUDIO_INFO_LINE(2)); /* anything other than 0 */
196 WREG32(HDMI_GC + offset, 0); /* unset HDMI_GC_AVMUTE */
198 evergreen_hdmi_videoinfoframe(encoder, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
201 evergreen_hdmi_update_ACR(encoder, mode->clock);
203 /* it's unknown what these bits do excatly, but it's indeed quite useful for debugging */
204 WREG32(AFMT_RAMP_CONTROL0 + offset, 0x00FFFFFF);
205 WREG32(AFMT_RAMP_CONTROL1 + offset, 0x007FFFFF);
206 WREG32(AFMT_RAMP_CONTROL2 + offset, 0x00000001);
207 WREG32(AFMT_RAMP_CONTROL3 + offset, 0x00000001);