drivers/gpu/drm/radeon/kv_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "cikd.h"
  27 #include "r600_dpm.h"
  28 #include "kv_dpm.h"
  29 #include "radeon_asic.h"
  30 #include <linux/seq_file.h>
  31
  32 #define KV_MAX_DEEPSLEEP_DIVIDER_ID     5
  33 #define KV_MINIMUM_ENGINE_CLOCK         800
  34 #define SMC_RAM_END                     0x40000
  35
  36 static void kv_init_graphics_levels(struct radeon_device *rdev);
  37 static int kv_calculate_ds_divider(struct radeon_device *rdev);
  38 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev);
  39 static int kv_calculate_dpm_settings(struct radeon_device *rdev);
  40 static void kv_enable_new_levels(struct radeon_device *rdev);
  41 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
  42                                            struct radeon_ps *new_rps);
  43 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level);
  44 static int kv_set_enabled_levels(struct radeon_device *rdev);
  45 static int kv_force_dpm_highest(struct radeon_device *rdev);
  46 static int kv_force_dpm_lowest(struct radeon_device *rdev);
  47 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
  48                                         struct radeon_ps *new_rps,
  49                                         struct radeon_ps *old_rps);
  50 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
  51                                             int min_temp, int max_temp);
  52 static int kv_init_fps_limits(struct radeon_device *rdev);
  53
  54 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
  55 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate);
  56 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate);
  57 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate);
  58
  59 extern void cik_enter_rlc_safe_mode(struct radeon_device *rdev);
  60 extern void cik_exit_rlc_safe_mode(struct radeon_device *rdev);
  61 extern void cik_update_cg(struct radeon_device *rdev,
  62                           u32 block, bool enable);
  63
  64 static const struct kv_lcac_config_values sx_local_cac_cfg_kv[] =
  65 {
  66         {  0,       4,        1    },
  67         {  1,       4,        1    },
  68         {  2,       5,        1    },
  69         {  3,       4,        2    },
  70         {  4,       1,        1    },
  71         {  5,       5,        2    },
  72         {  6,       6,        1    },
  73         {  7,       9,        2    },
  74         { 0xffffffff }
  75 };
  76
  77 static const struct kv_lcac_config_values mc0_local_cac_cfg_kv[] =
  78 {
  79         {  0,       4,        1    },
  80         { 0xffffffff }
  81 };
  82
  83 static const struct kv_lcac_config_values mc1_local_cac_cfg_kv[] =
  84 {
  85         {  0,       4,        1    },
  86         { 0xffffffff }
  87 };
  88
  89 static const struct kv_lcac_config_values mc2_local_cac_cfg_kv[] =
  90 {
  91         {  0,       4,        1    },
  92         { 0xffffffff }
  93 };
  94
  95 static const struct kv_lcac_config_values mc3_local_cac_cfg_kv[] =
  96 {
  97         {  0,       4,        1    },
  98         { 0xffffffff }
  99 };
 100
 101 static const struct kv_lcac_config_values cpl_local_cac_cfg_kv[] =
 102 {
 103         {  0,       4,        1    },
 104         {  1,       4,        1    },
 105         {  2,       5,        1    },
 106         {  3,       4,        1    },
 107         {  4,       1,        1    },
 108         {  5,       5,        1    },
 109         {  6,       6,        1    },
 110         {  7,       9,        1    },
 111         {  8,       4,        1    },
 112         {  9,       2,        1    },
 113         {  10,      3,        1    },
 114         {  11,      6,        1    },
 115         {  12,      8,        2    },
 116         {  13,      1,        1    },
 117         {  14,      2,        1    },
 118         {  15,      3,        1    },
 119         {  16,      1,        1    },
 120         {  17,      4,        1    },
 121         {  18,      3,        1    },
 122         {  19,      1,        1    },
 123         {  20,      8,        1    },
 124         {  21,      5,        1    },
 125         {  22,      1,        1    },
 126         {  23,      1,        1    },
 127         {  24,      4,        1    },
 128         {  27,      6,        1    },
 129         {  28,      1,        1    },
 130         { 0xffffffff }
 131 };
 132
 133 static const struct kv_lcac_config_reg sx0_cac_config_reg[] =
 134 {
 135         { 0xc0400d00, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 136 };
 137
 138 static const struct kv_lcac_config_reg mc0_cac_config_reg[] =
 139 {
 140         { 0xc0400d30, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 141 };
 142
 143 static const struct kv_lcac_config_reg mc1_cac_config_reg[] =
 144 {
 145         { 0xc0400d3c, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 146 };
 147
 148 static const struct kv_lcac_config_reg mc2_cac_config_reg[] =
 149 {
 150         { 0xc0400d48, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 151 };
 152
 153 static const struct kv_lcac_config_reg mc3_cac_config_reg[] =
 154 {
 155         { 0xc0400d54, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 156 };
 157
 158 static const struct kv_lcac_config_reg cpl_cac_config_reg[] =
 159 {
 160         { 0xc0400d80, 0x003e0000, 17, 0x3fc00000, 22, 0x0001fffe, 1, 0x00000001, 0 }
 161 };
 162
 163 static const struct kv_pt_config_reg didt_config_kv[] =
 164 {
 165         { 0x10, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 166         { 0x10, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 167         { 0x10, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 168         { 0x10, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 169         { 0x11, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 170         { 0x11, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 171         { 0x11, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 172         { 0x11, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 173         { 0x12, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 174         { 0x12, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 175         { 0x12, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 176         { 0x12, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 177         { 0x2, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 178         { 0x2, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 179         { 0x2, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 180         { 0x1, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 181         { 0x1, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 182         { 0x0, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 183         { 0x30, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 184         { 0x30, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 185         { 0x30, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 186         { 0x30, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 187         { 0x31, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 188         { 0x31, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 189         { 0x31, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 190         { 0x31, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 191         { 0x32, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 192         { 0x32, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 193         { 0x32, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 194         { 0x32, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 195         { 0x22, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 196         { 0x22, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 197         { 0x22, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 198         { 0x21, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 199         { 0x21, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 200         { 0x20, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 201         { 0x50, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 202         { 0x50, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 203         { 0x50, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 204         { 0x50, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 205         { 0x51, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 206         { 0x51, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 207         { 0x51, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 208         { 0x51, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 209         { 0x52, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 210         { 0x52, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 211         { 0x52, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 212         { 0x52, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 213         { 0x42, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 214         { 0x42, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 215         { 0x42, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 216         { 0x41, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 217         { 0x41, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 218         { 0x40, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 219         { 0x70, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 220         { 0x70, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 221         { 0x70, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 222         { 0x70, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 223         { 0x71, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 224         { 0x71, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 225         { 0x71, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 226         { 0x71, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 227         { 0x72, 0x000000ff, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 228         { 0x72, 0x0000ff00, 8, 0x0, KV_CONFIGREG_DIDT_IND },
 229         { 0x72, 0x00ff0000, 16, 0x0, KV_CONFIGREG_DIDT_IND },
 230         { 0x72, 0xff000000, 24, 0x0, KV_CONFIGREG_DIDT_IND },
 231         { 0x62, 0x00003fff, 0, 0x4, KV_CONFIGREG_DIDT_IND },
 232         { 0x62, 0x03ff0000, 16, 0x80, KV_CONFIGREG_DIDT_IND },
 233         { 0x62, 0x78000000, 27, 0x3, KV_CONFIGREG_DIDT_IND },
 234         { 0x61, 0x0000ffff, 0, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 235         { 0x61, 0xffff0000, 16, 0x3FFF, KV_CONFIGREG_DIDT_IND },
 236         { 0x60, 0x00000001, 0, 0x0, KV_CONFIGREG_DIDT_IND },
 237         { 0xFFFFFFFF }
 238 };
 239
 240 static struct kv_ps *kv_get_ps(struct radeon_ps *rps)
 241 {
 242         struct kv_ps *ps = rps->ps_priv;
 243
 244         return ps;
 245 }
 246
 247 static struct kv_power_info *kv_get_pi(struct radeon_device *rdev)
 248 {
 249         struct kv_power_info *pi = rdev->pm.dpm.priv;
 250
 251         return pi;
 252 }
 253
 254 #if 0
 255 static void kv_program_local_cac_table(struct radeon_device *rdev,
 256                                        const struct kv_lcac_config_values *local_cac_table,
 257                                        const struct kv_lcac_config_reg *local_cac_reg)
 258 {
 259         u32 i, count, data;
 260         const struct kv_lcac_config_values *values = local_cac_table;
 261
 262         while (values->block_id != 0xffffffff) {
 263                 count = values->signal_id;
 264                 for (i = 0; i < count; i++) {
 265                         data = ((values->block_id << local_cac_reg->block_shift) &
 266                                 local_cac_reg->block_mask);
 267                         data |= ((i << local_cac_reg->signal_shift) &
 268                                  local_cac_reg->signal_mask);
 269                         data |= ((values->t << local_cac_reg->t_shift) &
 270                                  local_cac_reg->t_mask);
 271                         data |= ((1 << local_cac_reg->enable_shift) &
 272                                  local_cac_reg->enable_mask);
 273                         WREG32_SMC(local_cac_reg->cntl, data);
 274                 }
 275                 values++;
 276         }
 277 }
 278 #endif
 279
 280 static int kv_program_pt_config_registers(struct radeon_device *rdev,
 281                                           const struct kv_pt_config_reg *cac_config_regs)
 282 {
 283         const struct kv_pt_config_reg *config_regs = cac_config_regs;
 284         u32 data;
 285         u32 cache = 0;
 286
 287         if (config_regs == NULL)
 288                 return -EINVAL;
 289
 290         while (config_regs->offset != 0xFFFFFFFF) {
 291                 if (config_regs->type == KV_CONFIGREG_CACHE) {
 292                         cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 293                 } else {
 294                         switch (config_regs->type) {
 295                         case KV_CONFIGREG_SMC_IND:
 296                                 data = RREG32_SMC(config_regs->offset);
 297                                 break;
 298                         case KV_CONFIGREG_DIDT_IND:
 299                                 data = RREG32_DIDT(config_regs->offset);
 300                                 break;
 301                         default:
 302                                 data = RREG32(config_regs->offset << 2);
 303                                 break;
 304                         }
 305
 306                         data &= ~config_regs->mask;
 307                         data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
 308                         data |= cache;
 309                         cache = 0;
 310
 311                         switch (config_regs->type) {
 312                         case KV_CONFIGREG_SMC_IND:
 313                                 WREG32_SMC(config_regs->offset, data);
 314                                 break;
 315                         case KV_CONFIGREG_DIDT_IND:
 316                                 WREG32_DIDT(config_regs->offset, data);
 317                                 break;
 318                         default:
 319                                 WREG32(config_regs->offset << 2, data);
 320                                 break;
 321                         }
 322                 }
 323                 config_regs++;
 324         }
 325
 326         return 0;
 327 }
 328
 329 static void kv_do_enable_didt(struct radeon_device *rdev, bool enable)
 330 {
 331         struct kv_power_info *pi = kv_get_pi(rdev);
 332         u32 data;
 333
 334         if (pi->caps_sq_ramping) {
 335                 data = RREG32_DIDT(DIDT_SQ_CTRL0);
 336                 if (enable)
 337                         data |= DIDT_CTRL_EN;
 338                 else
 339                         data &= ~DIDT_CTRL_EN;
 340                 WREG32_DIDT(DIDT_SQ_CTRL0, data);
 341         }
 342
 343         if (pi->caps_db_ramping) {
 344                 data = RREG32_DIDT(DIDT_DB_CTRL0);
 345                 if (enable)
 346                         data |= DIDT_CTRL_EN;
 347                 else
 348                         data &= ~DIDT_CTRL_EN;
 349                 WREG32_DIDT(DIDT_DB_CTRL0, data);
 350         }
 351
 352         if (pi->caps_td_ramping) {
 353                 data = RREG32_DIDT(DIDT_TD_CTRL0);
 354                 if (enable)
 355                         data |= DIDT_CTRL_EN;
 356                 else
 357                         data &= ~DIDT_CTRL_EN;
 358                 WREG32_DIDT(DIDT_TD_CTRL0, data);
 359         }
 360
 361         if (pi->caps_tcp_ramping) {
 362                 data = RREG32_DIDT(DIDT_TCP_CTRL0);
 363                 if (enable)
 364                         data |= DIDT_CTRL_EN;
 365                 else
 366                         data &= ~DIDT_CTRL_EN;
 367                 WREG32_DIDT(DIDT_TCP_CTRL0, data);
 368         }
 369 }
 370
 371 static int kv_enable_didt(struct radeon_device *rdev, bool enable)
 372 {
 373         struct kv_power_info *pi = kv_get_pi(rdev);
 374         int ret;
 375
 376         if (pi->caps_sq_ramping ||
 377             pi->caps_db_ramping ||
 378             pi->caps_td_ramping ||
 379             pi->caps_tcp_ramping) {
 380                 cik_enter_rlc_safe_mode(rdev);
 381
 382                 if (enable) {
 383                         ret = kv_program_pt_config_registers(rdev, didt_config_kv);
 384                         if (ret) {
 385                                 cik_exit_rlc_safe_mode(rdev);
 386                                 return ret;
 387                         }
 388                 }
 389
 390                 kv_do_enable_didt(rdev, enable);
 391
 392                 cik_exit_rlc_safe_mode(rdev);
 393         }
 394
 395         return 0;
 396 }
 397
 398 #if 0
 399 static void kv_initialize_hardware_cac_manager(struct radeon_device *rdev)
 400 {
 401         struct kv_power_info *pi = kv_get_pi(rdev);
 402
 403         if (pi->caps_cac) {
 404                 WREG32_SMC(LCAC_SX0_OVR_SEL, 0);
 405                 WREG32_SMC(LCAC_SX0_OVR_VAL, 0);
 406                 kv_program_local_cac_table(rdev, sx_local_cac_cfg_kv, sx0_cac_config_reg);
 407
 408                 WREG32_SMC(LCAC_MC0_OVR_SEL, 0);
 409                 WREG32_SMC(LCAC_MC0_OVR_VAL, 0);
 410                 kv_program_local_cac_table(rdev, mc0_local_cac_cfg_kv, mc0_cac_config_reg);
 411
 412                 WREG32_SMC(LCAC_MC1_OVR_SEL, 0);
 413                 WREG32_SMC(LCAC_MC1_OVR_VAL, 0);
 414                 kv_program_local_cac_table(rdev, mc1_local_cac_cfg_kv, mc1_cac_config_reg);
 415
 416                 WREG32_SMC(LCAC_MC2_OVR_SEL, 0);
 417                 WREG32_SMC(LCAC_MC2_OVR_VAL, 0);
 418                 kv_program_local_cac_table(rdev, mc2_local_cac_cfg_kv, mc2_cac_config_reg);
 419
 420                 WREG32_SMC(LCAC_MC3_OVR_SEL, 0);
 421                 WREG32_SMC(LCAC_MC3_OVR_VAL, 0);
 422                 kv_program_local_cac_table(rdev, mc3_local_cac_cfg_kv, mc3_cac_config_reg);
 423
 424                 WREG32_SMC(LCAC_CPL_OVR_SEL, 0);
 425                 WREG32_SMC(LCAC_CPL_OVR_VAL, 0);
 426                 kv_program_local_cac_table(rdev, cpl_local_cac_cfg_kv, cpl_cac_config_reg);
 427         }
 428 }
 429 #endif
 430
 431 static int kv_enable_smc_cac(struct radeon_device *rdev, bool enable)
 432 {
 433         struct kv_power_info *pi = kv_get_pi(rdev);
 434         int ret = 0;
 435
 436         if (pi->caps_cac) {
 437                 if (enable) {
 438                         ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableCac);
 439                         if (ret)
 440                                 pi->cac_enabled = false;
 441                         else
 442                                 pi->cac_enabled = true;
 443                 } else if (pi->cac_enabled) {
 444                         kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableCac);
 445                         pi->cac_enabled = false;
 446                 }
 447         }
 448
 449         return ret;
 450 }
 451
 452 static int kv_process_firmware_header(struct radeon_device *rdev)
 453 {
 454         struct kv_power_info *pi = kv_get_pi(rdev);
 455         u32 tmp;
 456         int ret;
 457
 458         ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
 459                                      offsetof(SMU7_Firmware_Header, DpmTable),
 460                                      &tmp, pi->sram_end);
 461
 462         if (ret == 0)
 463                 pi->dpm_table_start = tmp;
 464
 465         ret = kv_read_smc_sram_dword(rdev, SMU7_FIRMWARE_HEADER_LOCATION +
 466                                      offsetof(SMU7_Firmware_Header, SoftRegisters),
 467                                      &tmp, pi->sram_end);
 468
 469         if (ret == 0)
 470                 pi->soft_regs_start = tmp;
 471
 472         return ret;
 473 }
 474
 475 static int kv_enable_dpm_voltage_scaling(struct radeon_device *rdev)
 476 {
 477         struct kv_power_info *pi = kv_get_pi(rdev);
 478         int ret;
 479
 480         pi->graphics_voltage_change_enable = 1;
 481
 482         ret = kv_copy_bytes_to_smc(rdev,
 483                                    pi->dpm_table_start +
 484                                    offsetof(SMU7_Fusion_DpmTable, GraphicsVoltageChangeEnable),
 485                                    &pi->graphics_voltage_change_enable,
 486                                    sizeof(u8), pi->sram_end);
 487
 488         return ret;
 489 }
 490
 491 static int kv_set_dpm_interval(struct radeon_device *rdev)
 492 {
 493         struct kv_power_info *pi = kv_get_pi(rdev);
 494         int ret;
 495
 496         pi->graphics_interval = 1;
 497
 498         ret = kv_copy_bytes_to_smc(rdev,
 499                                    pi->dpm_table_start +
 500                                    offsetof(SMU7_Fusion_DpmTable, GraphicsInterval),
 501                                    &pi->graphics_interval,
 502                                    sizeof(u8), pi->sram_end);
 503
 504         return ret;
 505 }
 506
 507 static int kv_set_dpm_boot_state(struct radeon_device *rdev)
 508 {
 509         struct kv_power_info *pi = kv_get_pi(rdev);
 510         int ret;
 511
 512         ret = kv_copy_bytes_to_smc(rdev,
 513                                    pi->dpm_table_start +
 514                                    offsetof(SMU7_Fusion_DpmTable, GraphicsBootLevel),
 515                                    &pi->graphics_boot_level,
 516                                    sizeof(u8), pi->sram_end);
 517
 518         return ret;
 519 }
 520
 521 static void kv_program_vc(struct radeon_device *rdev)
 522 {
 523         WREG32_SMC(CG_FTV_0, 0x3FFFC100);
 524 }
 525
 526 static void kv_clear_vc(struct radeon_device *rdev)
 527 {
 528         WREG32_SMC(CG_FTV_0, 0);
 529 }
 530
 531 static int kv_set_divider_value(struct radeon_device *rdev,
 532                                 u32 index, u32 sclk)
 533 {
 534         struct kv_power_info *pi = kv_get_pi(rdev);
 535         struct atom_clock_dividers dividers;
 536         int ret;
 537
 538         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 539                                              sclk, false, &dividers);
 540         if (ret)
 541                 return ret;
 542
 543         pi->graphics_level[index].SclkDid = (u8)dividers.post_div;
 544         pi->graphics_level[index].SclkFrequency = cpu_to_be32(sclk);
 545
 546         return 0;
 547 }
 548
 549 static u16 kv_convert_8bit_index_to_voltage(struct radeon_device *rdev,
 550                                             u16 voltage)
 551 {
 552         return 6200 - (voltage * 25);
 553 }
 554
 555 static u16 kv_convert_2bit_index_to_voltage(struct radeon_device *rdev,
 556                                             u32 vid_2bit)
 557 {
 558         struct kv_power_info *pi = kv_get_pi(rdev);
 559         u32 vid_8bit = sumo_convert_vid2_to_vid7(rdev,
 560                                                  &pi->sys_info.vid_mapping_table,
 561                                                  vid_2bit);
 562
 563         return kv_convert_8bit_index_to_voltage(rdev, (u16)vid_8bit);
 564 }
 565
 566
 567 static int kv_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
 568 {
 569         struct kv_power_info *pi = kv_get_pi(rdev);
 570
 571         pi->graphics_level[index].VoltageDownH = (u8)pi->voltage_drop_t;
 572         pi->graphics_level[index].MinVddNb =
 573                 cpu_to_be32(kv_convert_2bit_index_to_voltage(rdev, vid));
 574
 575         return 0;
 576 }
 577
 578 static int kv_set_at(struct radeon_device *rdev, u32 index, u32 at)
 579 {
 580         struct kv_power_info *pi = kv_get_pi(rdev);
 581
 582         pi->graphics_level[index].AT = cpu_to_be16((u16)at);
 583
 584         return 0;
 585 }
 586
 587 static void kv_dpm_power_level_enable(struct radeon_device *rdev,
 588                                       u32 index, bool enable)
 589 {
 590         struct kv_power_info *pi = kv_get_pi(rdev);
 591
 592         pi->graphics_level[index].EnabledForActivity = enable ? 1 : 0;
 593 }
 594
 595 static void kv_start_dpm(struct radeon_device *rdev)
 596 {
 597         u32 tmp = RREG32_SMC(GENERAL_PWRMGT);
 598
 599         tmp |= GLOBAL_PWRMGT_EN;
 600         WREG32_SMC(GENERAL_PWRMGT, tmp);
 601
 602         kv_smc_dpm_enable(rdev, true);
 603 }
 604
 605 static void kv_stop_dpm(struct radeon_device *rdev)
 606 {
 607         kv_smc_dpm_enable(rdev, false);
 608 }
 609
 610 static void kv_start_am(struct radeon_device *rdev)
 611 {
 612         u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
 613
 614         sclk_pwrmgt_cntl &= ~(RESET_SCLK_CNT | RESET_BUSY_CNT);
 615         sclk_pwrmgt_cntl |= DYNAMIC_PM_EN;
 616
 617         WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 618 }
 619
 620 static void kv_reset_am(struct radeon_device *rdev)
 621 {
 622         u32 sclk_pwrmgt_cntl = RREG32_SMC(SCLK_PWRMGT_CNTL);
 623
 624         sclk_pwrmgt_cntl |= (RESET_SCLK_CNT | RESET_BUSY_CNT);
 625
 626         WREG32_SMC(SCLK_PWRMGT_CNTL, sclk_pwrmgt_cntl);
 627 }
 628
 629 static int kv_freeze_sclk_dpm(struct radeon_device *rdev, bool freeze)
 630 {
 631         return kv_notify_message_to_smu(rdev, freeze ?
 632                                         PPSMC_MSG_SCLKDPM_FreezeLevel : PPSMC_MSG_SCLKDPM_UnfreezeLevel);
 633 }
 634
 635 static int kv_force_lowest_valid(struct radeon_device *rdev)
 636 {
 637         return kv_force_dpm_lowest(rdev);
 638 }
 639
 640 static int kv_unforce_levels(struct radeon_device *rdev)
 641 {
 642         if (rdev->family == CHIP_KABINI)
 643                 return kv_notify_message_to_smu(rdev, PPSMC_MSG_NoForcedLevel);
 644         else
 645                 return kv_set_enabled_levels(rdev);
 646 }
 647
 648 static int kv_update_sclk_t(struct radeon_device *rdev)
 649 {
 650         struct kv_power_info *pi = kv_get_pi(rdev);
 651         u32 low_sclk_interrupt_t = 0;
 652         int ret = 0;
 653
 654         if (pi->caps_sclk_throttle_low_notification) {
 655                 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t);
 656
 657                 ret = kv_copy_bytes_to_smc(rdev,
 658                                            pi->dpm_table_start +
 659                                            offsetof(SMU7_Fusion_DpmTable, LowSclkInterruptT),
 660                                            (u8 *)&low_sclk_interrupt_t,
 661                                            sizeof(u32), pi->sram_end);
 662         }
 663         return ret;
 664 }
 665
 666 static int kv_program_bootup_state(struct radeon_device *rdev)
 667 {
 668         struct kv_power_info *pi = kv_get_pi(rdev);
 669         u32 i;
 670         struct radeon_clock_voltage_dependency_table *table =
 671                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
 672
 673         if (table && table->count) {
 674                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
 675                         if (table->entries[i].clk == pi->boot_pl.sclk)
 676                                 break;
 677                 }
 678
 679                 pi->graphics_boot_level = (u8)i;
 680                 kv_dpm_power_level_enable(rdev, i, true);
 681         } else {
 682                 struct sumo_sclk_voltage_mapping_table *table =
 683                         &pi->sys_info.sclk_voltage_mapping_table;
 684
 685                 if (table->num_max_dpm_entries == 0)
 686                         return -EINVAL;
 687
 688                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
 689                         if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
 690                                 break;
 691                 }
 692
 693                 pi->graphics_boot_level = (u8)i;
 694                 kv_dpm_power_level_enable(rdev, i, true);
 695         }
 696         return 0;
 697 }
 698
 699 static int kv_enable_auto_thermal_throttling(struct radeon_device *rdev)
 700 {
 701         struct kv_power_info *pi = kv_get_pi(rdev);
 702         int ret;
 703
 704         pi->graphics_therm_throttle_enable = 1;
 705
 706         ret = kv_copy_bytes_to_smc(rdev,
 707                                    pi->dpm_table_start +
 708                                    offsetof(SMU7_Fusion_DpmTable, GraphicsThermThrottleEnable),
 709                                    &pi->graphics_therm_throttle_enable,
 710                                    sizeof(u8), pi->sram_end);
 711
 712         return ret;
 713 }
 714
 715 static int kv_upload_dpm_settings(struct radeon_device *rdev)
 716 {
 717         struct kv_power_info *pi = kv_get_pi(rdev);
 718         int ret;
 719
 720         ret = kv_copy_bytes_to_smc(rdev,
 721                                    pi->dpm_table_start +
 722                                    offsetof(SMU7_Fusion_DpmTable, GraphicsLevel),
 723                                    (u8 *)&pi->graphics_level,
 724                                    sizeof(SMU7_Fusion_GraphicsLevel) * SMU7_MAX_LEVELS_GRAPHICS,
 725                                    pi->sram_end);
 726
 727         if (ret)
 728                 return ret;
 729
 730         ret = kv_copy_bytes_to_smc(rdev,
 731                                    pi->dpm_table_start +
 732                                    offsetof(SMU7_Fusion_DpmTable, GraphicsDpmLevelCount),
 733                                    &pi->graphics_dpm_level_count,
 734                                    sizeof(u8), pi->sram_end);
 735
 736         return ret;
 737 }
 738
 739 static u32 kv_get_clock_difference(u32 a, u32 b)
 740 {
 741         return (a >= b) ? a - b : b - a;
 742 }
 743
 744 static u32 kv_get_clk_bypass(struct radeon_device *rdev, u32 clk)
 745 {
 746         struct kv_power_info *pi = kv_get_pi(rdev);
 747         u32 value;
 748
 749         if (pi->caps_enable_dfs_bypass) {
 750                 if (kv_get_clock_difference(clk, 40000) < 200)
 751                         value = 3;
 752                 else if (kv_get_clock_difference(clk, 30000) < 200)
 753                         value = 2;
 754                 else if (kv_get_clock_difference(clk, 20000) < 200)
 755                         value = 7;
 756                 else if (kv_get_clock_difference(clk, 15000) < 200)
 757                         value = 6;
 758                 else if (kv_get_clock_difference(clk, 10000) < 200)
 759                         value = 8;
 760                 else
 761                         value = 0;
 762         } else {
 763                 value = 0;
 764         }
 765
 766         return value;
 767 }
 768
 769 static int kv_populate_uvd_table(struct radeon_device *rdev)
 770 {
 771         struct kv_power_info *pi = kv_get_pi(rdev);
 772         struct radeon_uvd_clock_voltage_dependency_table *table =
 773                 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
 774         struct atom_clock_dividers dividers;
 775         int ret;
 776         u32 i;
 777
 778         if (table == NULL || table->count == 0)
 779                 return 0;
 780
 781         pi->uvd_level_count = 0;
 782         for (i = 0; i < table->count; i++) {
 783                 if (pi->high_voltage_t &&
 784                     (pi->high_voltage_t < table->entries[i].v))
 785                         break;
 786
 787                 pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
 788                 pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
 789                 pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
 790
 791                 pi->uvd_level[i].VClkBypassCntl =
 792                         (u8)kv_get_clk_bypass(rdev, table->entries[i].vclk);
 793                 pi->uvd_level[i].DClkBypassCntl =
 794                         (u8)kv_get_clk_bypass(rdev, table->entries[i].dclk);
 795
 796                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 797                                                      table->entries[i].vclk, false, &dividers);
 798                 if (ret)
 799                         return ret;
 800                 pi->uvd_level[i].VclkDivider = (u8)dividers.post_div;
 801
 802                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 803                                                      table->entries[i].dclk, false, &dividers);
 804                 if (ret)
 805                         return ret;
 806                 pi->uvd_level[i].DclkDivider = (u8)dividers.post_div;
 807
 808                 pi->uvd_level_count++;
 809         }
 810
 811         ret = kv_copy_bytes_to_smc(rdev,
 812                                    pi->dpm_table_start +
 813                                    offsetof(SMU7_Fusion_DpmTable, UvdLevelCount),
 814                                    (u8 *)&pi->uvd_level_count,
 815                                    sizeof(u8), pi->sram_end);
 816         if (ret)
 817                 return ret;
 818
 819         pi->uvd_interval = 1;
 820
 821         ret = kv_copy_bytes_to_smc(rdev,
 822                                    pi->dpm_table_start +
 823                                    offsetof(SMU7_Fusion_DpmTable, UVDInterval),
 824                                    &pi->uvd_interval,
 825                                    sizeof(u8), pi->sram_end);
 826         if (ret)
 827                 return ret;
 828
 829         ret = kv_copy_bytes_to_smc(rdev,
 830                                    pi->dpm_table_start +
 831                                    offsetof(SMU7_Fusion_DpmTable, UvdLevel),
 832                                    (u8 *)&pi->uvd_level,
 833                                    sizeof(SMU7_Fusion_UvdLevel) * SMU7_MAX_LEVELS_UVD,
 834                                    pi->sram_end);
 835
 836         return ret;
 837
 838 }
 839
 840 static int kv_populate_vce_table(struct radeon_device *rdev)
 841 {
 842         struct kv_power_info *pi = kv_get_pi(rdev);
 843         int ret;
 844         u32 i;
 845         struct radeon_vce_clock_voltage_dependency_table *table =
 846                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
 847         struct atom_clock_dividers dividers;
 848
 849         if (table == NULL || table->count == 0)
 850                 return 0;
 851
 852         pi->vce_level_count = 0;
 853         for (i = 0; i < table->count; i++) {
 854                 if (pi->high_voltage_t &&
 855                     pi->high_voltage_t < table->entries[i].v)
 856                         break;
 857
 858                 pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
 859                 pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 860
 861                 pi->vce_level[i].ClkBypassCntl =
 862                         (u8)kv_get_clk_bypass(rdev, table->entries[i].evclk);
 863
 864                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 865                                                      table->entries[i].evclk, false, &dividers);
 866                 if (ret)
 867                         return ret;
 868                 pi->vce_level[i].Divider = (u8)dividers.post_div;
 869
 870                 pi->vce_level_count++;
 871         }
 872
 873         ret = kv_copy_bytes_to_smc(rdev,
 874                                    pi->dpm_table_start +
 875                                    offsetof(SMU7_Fusion_DpmTable, VceLevelCount),
 876                                    (u8 *)&pi->vce_level_count,
 877                                    sizeof(u8),
 878                                    pi->sram_end);
 879         if (ret)
 880                 return ret;
 881
 882         pi->vce_interval = 1;
 883
 884         ret = kv_copy_bytes_to_smc(rdev,
 885                                    pi->dpm_table_start +
 886                                    offsetof(SMU7_Fusion_DpmTable, VCEInterval),
 887                                    (u8 *)&pi->vce_interval,
 888                                    sizeof(u8),
 889                                    pi->sram_end);
 890         if (ret)
 891                 return ret;
 892
 893         ret = kv_copy_bytes_to_smc(rdev,
 894                                    pi->dpm_table_start +
 895                                    offsetof(SMU7_Fusion_DpmTable, VceLevel),
 896                                    (u8 *)&pi->vce_level,
 897                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_VCE,
 898                                    pi->sram_end);
 899
 900         return ret;
 901 }
 902
 903 static int kv_populate_samu_table(struct radeon_device *rdev)
 904 {
 905         struct kv_power_info *pi = kv_get_pi(rdev);
 906         struct radeon_clock_voltage_dependency_table *table =
 907                 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
 908         struct atom_clock_dividers dividers;
 909         int ret;
 910         u32 i;
 911
 912         if (table == NULL || table->count == 0)
 913                 return 0;
 914
 915         pi->samu_level_count = 0;
 916         for (i = 0; i < table->count; i++) {
 917                 if (pi->high_voltage_t &&
 918                     pi->high_voltage_t < table->entries[i].v)
 919                         break;
 920
 921                 pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
 922                 pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 923
 924                 pi->samu_level[i].ClkBypassCntl =
 925                         (u8)kv_get_clk_bypass(rdev, table->entries[i].clk);
 926
 927                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 928                                                      table->entries[i].clk, false, &dividers);
 929                 if (ret)
 930                         return ret;
 931                 pi->samu_level[i].Divider = (u8)dividers.post_div;
 932
 933                 pi->samu_level_count++;
 934         }
 935
 936         ret = kv_copy_bytes_to_smc(rdev,
 937                                    pi->dpm_table_start +
 938                                    offsetof(SMU7_Fusion_DpmTable, SamuLevelCount),
 939                                    (u8 *)&pi->samu_level_count,
 940                                    sizeof(u8),
 941                                    pi->sram_end);
 942         if (ret)
 943                 return ret;
 944
 945         pi->samu_interval = 1;
 946
 947         ret = kv_copy_bytes_to_smc(rdev,
 948                                    pi->dpm_table_start +
 949                                    offsetof(SMU7_Fusion_DpmTable, SAMUInterval),
 950                                    (u8 *)&pi->samu_interval,
 951                                    sizeof(u8),
 952                                    pi->sram_end);
 953         if (ret)
 954                 return ret;
 955
 956         ret = kv_copy_bytes_to_smc(rdev,
 957                                    pi->dpm_table_start +
 958                                    offsetof(SMU7_Fusion_DpmTable, SamuLevel),
 959                                    (u8 *)&pi->samu_level,
 960                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_SAMU,
 961                                    pi->sram_end);
 962         if (ret)
 963                 return ret;
 964
 965         return ret;
 966 }
 967
 968
 969 static int kv_populate_acp_table(struct radeon_device *rdev)
 970 {
 971         struct kv_power_info *pi = kv_get_pi(rdev);
 972         struct radeon_clock_voltage_dependency_table *table =
 973                 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
 974         struct atom_clock_dividers dividers;
 975         int ret;
 976         u32 i;
 977
 978         if (table == NULL || table->count == 0)
 979                 return 0;
 980
 981         pi->acp_level_count = 0;
 982         for (i = 0; i < table->count; i++) {
 983                 pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
 984                 pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
 985
 986                 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
 987                                                      table->entries[i].clk, false, &dividers);
 988                 if (ret)
 989                         return ret;
 990                 pi->acp_level[i].Divider = (u8)dividers.post_div;
 991
 992                 pi->acp_level_count++;
 993         }
 994
 995         ret = kv_copy_bytes_to_smc(rdev,
 996                                    pi->dpm_table_start +
 997                                    offsetof(SMU7_Fusion_DpmTable, AcpLevelCount),
 998                                    (u8 *)&pi->acp_level_count,
 999                                    sizeof(u8),
1000                                    pi->sram_end);
1001         if (ret)
1002                 return ret;
1003
1004         pi->acp_interval = 1;
1005
1006         ret = kv_copy_bytes_to_smc(rdev,
1007                                    pi->dpm_table_start +
1008                                    offsetof(SMU7_Fusion_DpmTable, ACPInterval),
1009                                    (u8 *)&pi->acp_interval,
1010                                    sizeof(u8),
1011                                    pi->sram_end);
1012         if (ret)
1013                 return ret;
1014
1015         ret = kv_copy_bytes_to_smc(rdev,
1016                                    pi->dpm_table_start +
1017                                    offsetof(SMU7_Fusion_DpmTable, AcpLevel),
1018                                    (u8 *)&pi->acp_level,
1019                                    sizeof(SMU7_Fusion_ExtClkLevel) * SMU7_MAX_LEVELS_ACP,
1020                                    pi->sram_end);
1021         if (ret)
1022                 return ret;
1023
1024         return ret;
1025 }
1026
1027 static void kv_calculate_dfs_bypass_settings(struct radeon_device *rdev)
1028 {
1029         struct kv_power_info *pi = kv_get_pi(rdev);
1030         u32 i;
1031         struct radeon_clock_voltage_dependency_table *table =
1032                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1033
1034         if (table && table->count) {
1035                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1036                         if (pi->caps_enable_dfs_bypass) {
1037                                 if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1038                                         pi->graphics_level[i].ClkBypassCntl = 3;
1039                                 else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1040                                         pi->graphics_level[i].ClkBypassCntl = 2;
1041                                 else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1042                                         pi->graphics_level[i].ClkBypassCntl = 7;
1043                                 else if (kv_get_clock_difference(table->entries[i].clk , 20000) < 200)
1044                                         pi->graphics_level[i].ClkBypassCntl = 6;
1045                                 else if (kv_get_clock_difference(table->entries[i].clk , 10000) < 200)
1046                                         pi->graphics_level[i].ClkBypassCntl = 8;
1047                                 else
1048                                         pi->graphics_level[i].ClkBypassCntl = 0;
1049                         } else {
1050                                 pi->graphics_level[i].ClkBypassCntl = 0;
1051                         }
1052                 }
1053         } else {
1054                 struct sumo_sclk_voltage_mapping_table *table =
1055                         &pi->sys_info.sclk_voltage_mapping_table;
1056                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1057                         if (pi->caps_enable_dfs_bypass) {
1058                                 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1059                                         pi->graphics_level[i].ClkBypassCntl = 3;
1060                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1061                                         pi->graphics_level[i].ClkBypassCntl = 2;
1062                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1063                                         pi->graphics_level[i].ClkBypassCntl = 7;
1064                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1065                                         pi->graphics_level[i].ClkBypassCntl = 6;
1066                                 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1067                                         pi->graphics_level[i].ClkBypassCntl = 8;
1068                                 else
1069                                         pi->graphics_level[i].ClkBypassCntl = 0;
1070                         } else {
1071                                 pi->graphics_level[i].ClkBypassCntl = 0;
1072                         }
1073                 }
1074         }
1075 }
1076
1077 static int kv_enable_ulv(struct radeon_device *rdev, bool enable)
1078 {
1079         return kv_notify_message_to_smu(rdev, enable ?
1080                                         PPSMC_MSG_EnableULV : PPSMC_MSG_DisableULV);
1081 }
1082
1083 static void kv_reset_acp_boot_level(struct radeon_device *rdev)
1084 {
1085         struct kv_power_info *pi = kv_get_pi(rdev);
1086
1087         pi->acp_boot_level = 0xff;
1088 }
1089
1090 static void kv_update_current_ps(struct radeon_device *rdev,
1091                                  struct radeon_ps *rps)
1092 {
1093         struct kv_ps *new_ps = kv_get_ps(rps);
1094         struct kv_power_info *pi = kv_get_pi(rdev);
1095
1096         pi->current_rps = *rps;
1097         pi->current_ps = *new_ps;
1098         pi->current_rps.ps_priv = &pi->current_ps;
1099 }
1100
1101 static void kv_update_requested_ps(struct radeon_device *rdev,
1102                                    struct radeon_ps *rps)
1103 {
1104         struct kv_ps *new_ps = kv_get_ps(rps);
1105         struct kv_power_info *pi = kv_get_pi(rdev);
1106
1107         pi->requested_rps = *rps;
1108         pi->requested_ps = *new_ps;
1109         pi->requested_rps.ps_priv = &pi->requested_ps;
1110 }
1111
1112 void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable)
1113 {
1114         struct kv_power_info *pi = kv_get_pi(rdev);
1115         int ret;
1116
1117         if (pi->bapm_enable) {
1118                 ret = kv_smc_bapm_enable(rdev, enable);
1119                 if (ret)
1120                         DRM_ERROR("kv_smc_bapm_enable failed\n");
1121         }
1122 }
1123
1124 int kv_dpm_enable(struct radeon_device *rdev)
1125 {
1126         struct kv_power_info *pi = kv_get_pi(rdev);
1127         int ret;
1128
1129         ret = kv_process_firmware_header(rdev);
1130         if (ret) {
1131                 DRM_ERROR("kv_process_firmware_header failed\n");
1132                 return ret;
1133         }
1134         kv_init_fps_limits(rdev);
1135         kv_init_graphics_levels(rdev);
1136         ret = kv_program_bootup_state(rdev);
1137         if (ret) {
1138                 DRM_ERROR("kv_program_bootup_state failed\n");
1139                 return ret;
1140         }
1141         kv_calculate_dfs_bypass_settings(rdev);
1142         ret = kv_upload_dpm_settings(rdev);
1143         if (ret) {
1144                 DRM_ERROR("kv_upload_dpm_settings failed\n");
1145                 return ret;
1146         }
1147         ret = kv_populate_uvd_table(rdev);
1148         if (ret) {
1149                 DRM_ERROR("kv_populate_uvd_table failed\n");
1150                 return ret;
1151         }
1152         ret = kv_populate_vce_table(rdev);
1153         if (ret) {
1154                 DRM_ERROR("kv_populate_vce_table failed\n");
1155                 return ret;
1156         }
1157         ret = kv_populate_samu_table(rdev);
1158         if (ret) {
1159                 DRM_ERROR("kv_populate_samu_table failed\n");
1160                 return ret;
1161         }
1162         ret = kv_populate_acp_table(rdev);
1163         if (ret) {
1164                 DRM_ERROR("kv_populate_acp_table failed\n");
1165                 return ret;
1166         }
1167         kv_program_vc(rdev);
1168 #if 0
1169         kv_initialize_hardware_cac_manager(rdev);
1170 #endif
1171         kv_start_am(rdev);
1172         if (pi->enable_auto_thermal_throttling) {
1173                 ret = kv_enable_auto_thermal_throttling(rdev);
1174                 if (ret) {
1175                         DRM_ERROR("kv_enable_auto_thermal_throttling failed\n");
1176                         return ret;
1177                 }
1178         }
1179         ret = kv_enable_dpm_voltage_scaling(rdev);
1180         if (ret) {
1181                 DRM_ERROR("kv_enable_dpm_voltage_scaling failed\n");
1182                 return ret;
1183         }
1184         ret = kv_set_dpm_interval(rdev);
1185         if (ret) {
1186                 DRM_ERROR("kv_set_dpm_interval failed\n");
1187                 return ret;
1188         }
1189         ret = kv_set_dpm_boot_state(rdev);
1190         if (ret) {
1191                 DRM_ERROR("kv_set_dpm_boot_state failed\n");
1192                 return ret;
1193         }
1194         ret = kv_enable_ulv(rdev, true);
1195         if (ret) {
1196                 DRM_ERROR("kv_enable_ulv failed\n");
1197                 return ret;
1198         }
1199         kv_start_dpm(rdev);
1200         ret = kv_enable_didt(rdev, true);
1201         if (ret) {
1202                 DRM_ERROR("kv_enable_didt failed\n");
1203                 return ret;
1204         }
1205         ret = kv_enable_smc_cac(rdev, true);
1206         if (ret) {
1207                 DRM_ERROR("kv_enable_smc_cac failed\n");
1208                 return ret;
1209         }
1210
1211         kv_reset_acp_boot_level(rdev);
1212
1213         if (rdev->irq.installed &&
1214             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1215                 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1216                 if (ret) {
1217                         DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1218                         return ret;
1219                 }
1220                 rdev->irq.dpm_thermal = true;
1221                 radeon_irq_set(rdev);
1222         }
1223
1224         ret = kv_smc_bapm_enable(rdev, false);
1225         if (ret) {
1226                 DRM_ERROR("kv_smc_bapm_enable failed\n");
1227                 return ret;
1228         }
1229
1230         /* powerdown unused blocks for now */
1231         kv_dpm_powergate_acp(rdev, true);
1232         kv_dpm_powergate_samu(rdev, true);
1233         kv_dpm_powergate_vce(rdev, true);
1234         kv_dpm_powergate_uvd(rdev, true);
1235
1236         kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1237
1238         return ret;
1239 }
1240
1241 int kv_dpm_late_enable(struct radeon_device *rdev)
1242 {
1243         int ret;
1244
1245         if (rdev->irq.installed &&
1246             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1247                 ret = kv_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1248                 if (ret) {
1249                         DRM_ERROR("kv_set_thermal_temperature_range failed\n");
1250                         return ret;
1251                 }
1252                 rdev->irq.dpm_thermal = true;
1253                 radeon_irq_set(rdev);
1254         }
1255
1256         /* powerdown unused blocks for now */
1257         kv_dpm_powergate_acp(rdev, true);
1258         kv_dpm_powergate_samu(rdev, true);
1259         kv_dpm_powergate_vce(rdev, true);
1260         kv_dpm_powergate_uvd(rdev, true);
1261
1262         return ret;
1263 }
1264
1265 void kv_dpm_disable(struct radeon_device *rdev)
1266 {
1267         kv_smc_bapm_enable(rdev, false);
1268
1269         /* powerup blocks */
1270         kv_dpm_powergate_acp(rdev, false);
1271         kv_dpm_powergate_samu(rdev, false);
1272         kv_dpm_powergate_vce(rdev, false);
1273         kv_dpm_powergate_uvd(rdev, false);
1274
1275         kv_enable_smc_cac(rdev, false);
1276         kv_enable_didt(rdev, false);
1277         kv_clear_vc(rdev);
1278         kv_stop_dpm(rdev);
1279         kv_enable_ulv(rdev, false);
1280         kv_reset_am(rdev);
1281
1282         kv_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1283 }
1284
1285 #if 0
1286 static int kv_write_smc_soft_register(struct radeon_device *rdev,
1287                                       u16 reg_offset, u32 value)
1288 {
1289         struct kv_power_info *pi = kv_get_pi(rdev);
1290
1291         return kv_copy_bytes_to_smc(rdev, pi->soft_regs_start + reg_offset,
1292                                     (u8 *)&value, sizeof(u16), pi->sram_end);
1293 }
1294
1295 static int kv_read_smc_soft_register(struct radeon_device *rdev,
1296                                      u16 reg_offset, u32 *value)
1297 {
1298         struct kv_power_info *pi = kv_get_pi(rdev);
1299
1300         return kv_read_smc_sram_dword(rdev, pi->soft_regs_start + reg_offset,
1301                                       value, pi->sram_end);
1302 }
1303 #endif
1304
1305 static void kv_init_sclk_t(struct radeon_device *rdev)
1306 {
1307         struct kv_power_info *pi = kv_get_pi(rdev);
1308
1309         pi->low_sclk_interrupt_t = 0;
1310 }
1311
1312 static int kv_init_fps_limits(struct radeon_device *rdev)
1313 {
1314         struct kv_power_info *pi = kv_get_pi(rdev);
1315         int ret = 0;
1316
1317         if (pi->caps_fps) {
1318                 u16 tmp;
1319
1320                 tmp = 45;
1321                 pi->fps_high_t = cpu_to_be16(tmp);
1322                 ret = kv_copy_bytes_to_smc(rdev,
1323                                            pi->dpm_table_start +
1324                                            offsetof(SMU7_Fusion_DpmTable, FpsHighT),
1325                                            (u8 *)&pi->fps_high_t,
1326                                            sizeof(u16), pi->sram_end);
1327
1328                 tmp = 30;
1329                 pi->fps_low_t = cpu_to_be16(tmp);
1330
1331                 ret = kv_copy_bytes_to_smc(rdev,
1332                                            pi->dpm_table_start +
1333                                            offsetof(SMU7_Fusion_DpmTable, FpsLowT),
1334                                            (u8 *)&pi->fps_low_t,
1335                                            sizeof(u16), pi->sram_end);
1336
1337         }
1338         return ret;
1339 }
1340
1341 static void kv_init_powergate_state(struct radeon_device *rdev)
1342 {
1343         struct kv_power_info *pi = kv_get_pi(rdev);
1344
1345         pi->uvd_power_gated = false;
1346         pi->vce_power_gated = false;
1347         pi->samu_power_gated = false;
1348         pi->acp_power_gated = false;
1349
1350 }
1351
1352 static int kv_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
1353 {
1354         return kv_notify_message_to_smu(rdev, enable ?
1355                                         PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable);
1356 }
1357
1358 #if 0
1359 static int kv_enable_vce_dpm(struct radeon_device *rdev, bool enable)
1360 {
1361         return kv_notify_message_to_smu(rdev, enable ?
1362                                         PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable);
1363 }
1364 #endif
1365
1366 static int kv_enable_samu_dpm(struct radeon_device *rdev, bool enable)
1367 {
1368         return kv_notify_message_to_smu(rdev, enable ?
1369                                         PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable);
1370 }
1371
1372 static int kv_enable_acp_dpm(struct radeon_device *rdev, bool enable)
1373 {
1374         return kv_notify_message_to_smu(rdev, enable ?
1375                                         PPSMC_MSG_ACPDPM_Enable : PPSMC_MSG_ACPDPM_Disable);
1376 }
1377
1378 static int kv_update_uvd_dpm(struct radeon_device *rdev, bool gate)
1379 {
1380         struct kv_power_info *pi = kv_get_pi(rdev);
1381         struct radeon_uvd_clock_voltage_dependency_table *table =
1382                 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1383         int ret;
1384
1385         if (!gate) {
1386                 if (!pi->caps_uvd_dpm || table->count || pi->caps_stable_p_state)
1387                         pi->uvd_boot_level = table->count - 1;
1388                 else
1389                         pi->uvd_boot_level = 0;
1390
1391                 ret = kv_copy_bytes_to_smc(rdev,
1392                                            pi->dpm_table_start +
1393                                            offsetof(SMU7_Fusion_DpmTable, UvdBootLevel),
1394                                            (uint8_t *)&pi->uvd_boot_level,
1395                                            sizeof(u8), pi->sram_end);
1396                 if (ret)
1397                         return ret;
1398
1399                 if (!pi->caps_uvd_dpm ||
1400                     pi->caps_stable_p_state)
1401                         kv_send_msg_to_smc_with_parameter(rdev,
1402                                                           PPSMC_MSG_UVDDPM_SetEnabledMask,
1403                                                           (1 << pi->uvd_boot_level));
1404         }
1405
1406         return kv_enable_uvd_dpm(rdev, !gate);
1407 }
1408
1409 #if 0
1410 static u8 kv_get_vce_boot_level(struct radeon_device *rdev)
1411 {
1412         u8 i;
1413         struct radeon_vce_clock_voltage_dependency_table *table =
1414                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1415
1416         for (i = 0; i < table->count; i++) {
1417                 if (table->entries[i].evclk >= 0) /* XXX */
1418                         break;
1419         }
1420
1421         return i;
1422 }
1423
1424 static int kv_update_vce_dpm(struct radeon_device *rdev,
1425                              struct radeon_ps *radeon_new_state,
1426                              struct radeon_ps *radeon_current_state)
1427 {
1428         struct kv_power_info *pi = kv_get_pi(rdev);
1429         struct radeon_vce_clock_voltage_dependency_table *table =
1430                 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
1431         int ret;
1432
1433         if (radeon_new_state->evclk > 0 && radeon_current_state->evclk == 0) {
1434                 if (pi->caps_stable_p_state)
1435                         pi->vce_boot_level = table->count - 1;
1436                 else
1437                         pi->vce_boot_level = kv_get_vce_boot_level(rdev);
1438
1439                 ret = kv_copy_bytes_to_smc(rdev,
1440                                            pi->dpm_table_start +
1441                                            offsetof(SMU7_Fusion_DpmTable, VceBootLevel),
1442                                            (u8 *)&pi->vce_boot_level,
1443                                            sizeof(u8),
1444                                            pi->sram_end);
1445                 if (ret)
1446                         return ret;
1447
1448                 if (pi->caps_stable_p_state)
1449                         kv_send_msg_to_smc_with_parameter(rdev,
1450                                                           PPSMC_MSG_VCEDPM_SetEnabledMask,
1451                                                           (1 << pi->vce_boot_level));
1452
1453                 kv_enable_vce_dpm(rdev, true);
1454         } else if (radeon_new_state->evclk == 0 && radeon_current_state->evclk > 0) {
1455                 kv_enable_vce_dpm(rdev, false);
1456         }
1457
1458         return 0;
1459 }
1460 #endif
1461
1462 static int kv_update_samu_dpm(struct radeon_device *rdev, bool gate)
1463 {
1464         struct kv_power_info *pi = kv_get_pi(rdev);
1465         struct radeon_clock_voltage_dependency_table *table =
1466                 &rdev->pm.dpm.dyn_state.samu_clock_voltage_dependency_table;
1467         int ret;
1468
1469         if (!gate) {
1470                 if (pi->caps_stable_p_state)
1471                         pi->samu_boot_level = table->count - 1;
1472                 else
1473                         pi->samu_boot_level = 0;
1474
1475                 ret = kv_copy_bytes_to_smc(rdev,
1476                                            pi->dpm_table_start +
1477                                            offsetof(SMU7_Fusion_DpmTable, SamuBootLevel),
1478                                            (u8 *)&pi->samu_boot_level,
1479                                            sizeof(u8),
1480                                            pi->sram_end);
1481                 if (ret)
1482                         return ret;
1483
1484                 if (pi->caps_stable_p_state)
1485                         kv_send_msg_to_smc_with_parameter(rdev,
1486                                                           PPSMC_MSG_SAMUDPM_SetEnabledMask,
1487                                                           (1 << pi->samu_boot_level));
1488         }
1489
1490         return kv_enable_samu_dpm(rdev, !gate);
1491 }
1492
1493 static u8 kv_get_acp_boot_level(struct radeon_device *rdev)
1494 {
1495         u8 i;
1496         struct radeon_clock_voltage_dependency_table *table =
1497                 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1498
1499         for (i = 0; i < table->count; i++) {
1500                 if (table->entries[i].clk >= 0) /* XXX */
1501                         break;
1502         }
1503
1504         if (i >= table->count)
1505                 i = table->count - 1;
1506
1507         return i;
1508 }
1509
1510 static void kv_update_acp_boot_level(struct radeon_device *rdev)
1511 {
1512         struct kv_power_info *pi = kv_get_pi(rdev);
1513         u8 acp_boot_level;
1514
1515         if (!pi->caps_stable_p_state) {
1516                 acp_boot_level = kv_get_acp_boot_level(rdev);
1517                 if (acp_boot_level != pi->acp_boot_level) {
1518                         pi->acp_boot_level = acp_boot_level;
1519                         kv_send_msg_to_smc_with_parameter(rdev,
1520                                                           PPSMC_MSG_ACPDPM_SetEnabledMask,
1521                                                           (1 << pi->acp_boot_level));
1522                 }
1523         }
1524 }
1525
1526 static int kv_update_acp_dpm(struct radeon_device *rdev, bool gate)
1527 {
1528         struct kv_power_info *pi = kv_get_pi(rdev);
1529         struct radeon_clock_voltage_dependency_table *table =
1530                 &rdev->pm.dpm.dyn_state.acp_clock_voltage_dependency_table;
1531         int ret;
1532
1533         if (!gate) {
1534                 if (pi->caps_stable_p_state)
1535                         pi->acp_boot_level = table->count - 1;
1536                 else
1537                         pi->acp_boot_level = kv_get_acp_boot_level(rdev);
1538
1539                 ret = kv_copy_bytes_to_smc(rdev,
1540                                            pi->dpm_table_start +
1541                                            offsetof(SMU7_Fusion_DpmTable, AcpBootLevel),
1542                                            (u8 *)&pi->acp_boot_level,
1543                                            sizeof(u8),
1544                                            pi->sram_end);
1545                 if (ret)
1546                         return ret;
1547
1548                 if (pi->caps_stable_p_state)
1549                         kv_send_msg_to_smc_with_parameter(rdev,
1550                                                           PPSMC_MSG_ACPDPM_SetEnabledMask,
1551                                                           (1 << pi->acp_boot_level));
1552         }
1553
1554         return kv_enable_acp_dpm(rdev, !gate);
1555 }
1556
1557 void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate)
1558 {
1559         struct kv_power_info *pi = kv_get_pi(rdev);
1560
1561         if (pi->uvd_power_gated == gate)
1562                 return;
1563
1564         pi->uvd_power_gated = gate;
1565
1566         if (gate) {
1567                 if (pi->caps_uvd_pg) {
1568                         uvd_v1_0_stop(rdev);
1569                         cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, false);
1570                 }
1571                 kv_update_uvd_dpm(rdev, gate);
1572                 if (pi->caps_uvd_pg)
1573                         kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerOFF);
1574         } else {
1575                 if (pi->caps_uvd_pg) {
1576                         kv_notify_message_to_smu(rdev, PPSMC_MSG_UVDPowerON);
1577                         uvd_v4_2_resume(rdev);
1578                         uvd_v1_0_start(rdev);
1579                         cik_update_cg(rdev, RADEON_CG_BLOCK_UVD, true);
1580                 }
1581                 kv_update_uvd_dpm(rdev, gate);
1582         }
1583 }
1584
1585 static void kv_dpm_powergate_vce(struct radeon_device *rdev, bool gate)
1586 {
1587         struct kv_power_info *pi = kv_get_pi(rdev);
1588
1589         if (pi->vce_power_gated == gate)
1590                 return;
1591
1592         pi->vce_power_gated = gate;
1593
1594         if (gate) {
1595                 if (pi->caps_vce_pg)
1596                         kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerOFF);
1597         } else {
1598                 if (pi->caps_vce_pg)
1599                         kv_notify_message_to_smu(rdev, PPSMC_MSG_VCEPowerON);
1600         }
1601 }
1602
1603 static void kv_dpm_powergate_samu(struct radeon_device *rdev, bool gate)
1604 {
1605         struct kv_power_info *pi = kv_get_pi(rdev);
1606
1607         if (pi->samu_power_gated == gate)
1608                 return;
1609
1610         pi->samu_power_gated = gate;
1611
1612         if (gate) {
1613                 kv_update_samu_dpm(rdev, true);
1614                 if (pi->caps_samu_pg)
1615                         kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerOFF);
1616         } else {
1617                 if (pi->caps_samu_pg)
1618                         kv_notify_message_to_smu(rdev, PPSMC_MSG_SAMPowerON);
1619                 kv_update_samu_dpm(rdev, false);
1620         }
1621 }
1622
1623 static void kv_dpm_powergate_acp(struct radeon_device *rdev, bool gate)
1624 {
1625         struct kv_power_info *pi = kv_get_pi(rdev);
1626
1627         if (pi->acp_power_gated == gate)
1628                 return;
1629
1630         if (rdev->family == CHIP_KABINI)
1631                 return;
1632
1633         pi->acp_power_gated = gate;
1634
1635         if (gate) {
1636                 kv_update_acp_dpm(rdev, true);
1637                 if (pi->caps_acp_pg)
1638                         kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerOFF);
1639         } else {
1640                 if (pi->caps_acp_pg)
1641                         kv_notify_message_to_smu(rdev, PPSMC_MSG_ACPPowerON);
1642                 kv_update_acp_dpm(rdev, false);
1643         }
1644 }
1645
1646 static void kv_set_valid_clock_range(struct radeon_device *rdev,
1647                                      struct radeon_ps *new_rps)
1648 {
1649         struct kv_ps *new_ps = kv_get_ps(new_rps);
1650         struct kv_power_info *pi = kv_get_pi(rdev);
1651         u32 i;
1652         struct radeon_clock_voltage_dependency_table *table =
1653                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
1654
1655         if (table && table->count) {
1656                 for (i = 0; i < pi->graphics_dpm_level_count; i++) {
1657                         if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1658                             (i == (pi->graphics_dpm_level_count - 1))) {
1659                                 pi->lowest_valid = i;
1660                                 break;
1661                         }
1662                 }
1663
1664                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1665                         if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1666                                 break;
1667                 }
1668                 pi->highest_valid = i;
1669
1670                 if (pi->lowest_valid > pi->highest_valid) {
1671                         if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1672                             (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1673                                 pi->highest_valid = pi->lowest_valid;
1674                         else
1675                                 pi->lowest_valid =  pi->highest_valid;
1676                 }
1677         } else {
1678                 struct sumo_sclk_voltage_mapping_table *table =
1679                         &pi->sys_info.sclk_voltage_mapping_table;
1680
1681                 for (i = 0; i < (int)pi->graphics_dpm_level_count; i++) {
1682                         if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1683                             i == (int)(pi->graphics_dpm_level_count - 1)) {
1684                                 pi->lowest_valid = i;
1685                                 break;
1686                         }
1687                 }
1688
1689                 for (i = pi->graphics_dpm_level_count - 1; i > 0; i--) {
1690                         if (table->entries[i].sclk_frequency <=
1691                             new_ps->levels[new_ps->num_levels - 1].sclk)
1692                                 break;
1693                 }
1694                 pi->highest_valid = i;
1695
1696                 if (pi->lowest_valid > pi->highest_valid) {
1697                         if ((new_ps->levels[0].sclk -
1698                              table->entries[pi->highest_valid].sclk_frequency) >
1699                             (table->entries[pi->lowest_valid].sclk_frequency -
1700                              new_ps->levels[new_ps->num_levels -1].sclk))
1701                                 pi->highest_valid = pi->lowest_valid;
1702                         else
1703                                 pi->lowest_valid =  pi->highest_valid;
1704                 }
1705         }
1706 }
1707
1708 static int kv_update_dfs_bypass_settings(struct radeon_device *rdev,
1709                                          struct radeon_ps *new_rps)
1710 {
1711         struct kv_ps *new_ps = kv_get_ps(new_rps);
1712         struct kv_power_info *pi = kv_get_pi(rdev);
1713         int ret = 0;
1714         u8 clk_bypass_cntl;
1715
1716         if (pi->caps_enable_dfs_bypass) {
1717                 clk_bypass_cntl = new_ps->need_dfs_bypass ?
1718                         pi->graphics_level[pi->graphics_boot_level].ClkBypassCntl : 0;
1719                 ret = kv_copy_bytes_to_smc(rdev,
1720                                            (pi->dpm_table_start +
1721                                             offsetof(SMU7_Fusion_DpmTable, GraphicsLevel) +
1722                                             (pi->graphics_boot_level * sizeof(SMU7_Fusion_GraphicsLevel)) +
1723                                             offsetof(SMU7_Fusion_GraphicsLevel, ClkBypassCntl)),
1724                                            &clk_bypass_cntl,
1725                                            sizeof(u8), pi->sram_end);
1726         }
1727
1728         return ret;
1729 }
1730
1731 static int kv_enable_nb_dpm(struct radeon_device *rdev)
1732 {
1733         struct kv_power_info *pi = kv_get_pi(rdev);
1734         int ret = 0;
1735
1736         if (pi->enable_nb_dpm && !pi->nb_dpm_enabled) {
1737                 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_NBDPM_Enable);
1738                 if (ret == 0)
1739                         pi->nb_dpm_enabled = true;
1740         }
1741
1742         return ret;
1743 }
1744
1745 int kv_dpm_force_performance_level(struct radeon_device *rdev,
1746                                    enum radeon_dpm_forced_level level)
1747 {
1748         int ret;
1749
1750         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1751                 ret = kv_force_dpm_highest(rdev);
1752                 if (ret)
1753                         return ret;
1754         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1755                 ret = kv_force_dpm_lowest(rdev);
1756                 if (ret)
1757                         return ret;
1758         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
1759                 ret = kv_unforce_levels(rdev);
1760                 if (ret)
1761                         return ret;
1762         }
1763
1764         rdev->pm.dpm.forced_level = level;
1765
1766         return 0;
1767 }
1768
1769 int kv_dpm_pre_set_power_state(struct radeon_device *rdev)
1770 {
1771         struct kv_power_info *pi = kv_get_pi(rdev);
1772         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1773         struct radeon_ps *new_ps = &requested_ps;
1774
1775         kv_update_requested_ps(rdev, new_ps);
1776
1777         kv_apply_state_adjust_rules(rdev,
1778                                     &pi->requested_rps,
1779                                     &pi->current_rps);
1780
1781         return 0;
1782 }
1783
1784 int kv_dpm_set_power_state(struct radeon_device *rdev)
1785 {
1786         struct kv_power_info *pi = kv_get_pi(rdev);
1787         struct radeon_ps *new_ps = &pi->requested_rps;
1788         /*struct radeon_ps *old_ps = &pi->current_rps;*/
1789         int ret;
1790
1791         if (pi->bapm_enable) {
1792                 ret = kv_smc_bapm_enable(rdev, rdev->pm.dpm.ac_power);
1793                 if (ret) {
1794                         DRM_ERROR("kv_smc_bapm_enable failed\n");
1795                         return ret;
1796                 }
1797         }
1798
1799         if (rdev->family == CHIP_KABINI) {
1800                 if (pi->enable_dpm) {
1801                         kv_set_valid_clock_range(rdev, new_ps);
1802                         kv_update_dfs_bypass_settings(rdev, new_ps);
1803                         ret = kv_calculate_ds_divider(rdev);
1804                         if (ret) {
1805                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1806                                 return ret;
1807                         }
1808                         kv_calculate_nbps_level_settings(rdev);
1809                         kv_calculate_dpm_settings(rdev);
1810                         kv_force_lowest_valid(rdev);
1811                         kv_enable_new_levels(rdev);
1812                         kv_upload_dpm_settings(rdev);
1813                         kv_program_nbps_index_settings(rdev, new_ps);
1814                         kv_unforce_levels(rdev);
1815                         kv_set_enabled_levels(rdev);
1816                         kv_force_lowest_valid(rdev);
1817                         kv_unforce_levels(rdev);
1818 #if 0
1819                         ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1820                         if (ret) {
1821                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1822                                 return ret;
1823                         }
1824 #endif
1825                         kv_update_sclk_t(rdev);
1826                 }
1827         } else {
1828                 if (pi->enable_dpm) {
1829                         kv_set_valid_clock_range(rdev, new_ps);
1830                         kv_update_dfs_bypass_settings(rdev, new_ps);
1831                         ret = kv_calculate_ds_divider(rdev);
1832                         if (ret) {
1833                                 DRM_ERROR("kv_calculate_ds_divider failed\n");
1834                                 return ret;
1835                         }
1836                         kv_calculate_nbps_level_settings(rdev);
1837                         kv_calculate_dpm_settings(rdev);
1838                         kv_freeze_sclk_dpm(rdev, true);
1839                         kv_upload_dpm_settings(rdev);
1840                         kv_program_nbps_index_settings(rdev, new_ps);
1841                         kv_freeze_sclk_dpm(rdev, false);
1842                         kv_set_enabled_levels(rdev);
1843 #if 0
1844                         ret = kv_update_vce_dpm(rdev, new_ps, old_ps);
1845                         if (ret) {
1846                                 DRM_ERROR("kv_update_vce_dpm failed\n");
1847                                 return ret;
1848                         }
1849 #endif
1850                         kv_update_acp_boot_level(rdev);
1851                         kv_update_sclk_t(rdev);
1852                         kv_enable_nb_dpm(rdev);
1853                 }
1854         }
1855
1856         return 0;
1857 }
1858
1859 void kv_dpm_post_set_power_state(struct radeon_device *rdev)
1860 {
1861         struct kv_power_info *pi = kv_get_pi(rdev);
1862         struct radeon_ps *new_ps = &pi->requested_rps;
1863
1864         kv_update_current_ps(rdev, new_ps);
1865 }
1866
1867 void kv_dpm_setup_asic(struct radeon_device *rdev)
1868 {
1869         sumo_take_smu_control(rdev, true);
1870         kv_init_powergate_state(rdev);
1871         kv_init_sclk_t(rdev);
1872 }
1873
1874 void kv_dpm_reset_asic(struct radeon_device *rdev)
1875 {
1876         struct kv_power_info *pi = kv_get_pi(rdev);
1877
1878         if (rdev->family == CHIP_KABINI) {
1879                 kv_force_lowest_valid(rdev);
1880                 kv_init_graphics_levels(rdev);
1881                 kv_program_bootup_state(rdev);
1882                 kv_upload_dpm_settings(rdev);
1883                 kv_force_lowest_valid(rdev);
1884                 kv_unforce_levels(rdev);
1885         } else {
1886                 kv_init_graphics_levels(rdev);
1887                 kv_program_bootup_state(rdev);
1888                 kv_freeze_sclk_dpm(rdev, true);
1889                 kv_upload_dpm_settings(rdev);
1890                 kv_freeze_sclk_dpm(rdev, false);
1891                 kv_set_enabled_level(rdev, pi->graphics_boot_level);
1892         }
1893 }
1894
1895 //XXX use sumo_dpm_display_configuration_changed
1896
1897 static void kv_construct_max_power_limits_table(struct radeon_device *rdev,
1898                                                 struct radeon_clock_and_voltage_limits *table)
1899 {
1900         struct kv_power_info *pi = kv_get_pi(rdev);
1901
1902         if (pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries > 0) {
1903                 int idx = pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1;
1904                 table->sclk =
1905                         pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency;
1906                 table->vddc =
1907                         kv_convert_2bit_index_to_voltage(rdev,
1908                                                          pi->sys_info.sclk_voltage_mapping_table.entries[idx].vid_2bit);
1909         }
1910
1911         table->mclk = pi->sys_info.nbp_memory_clock[0];
1912 }
1913
1914 static void kv_patch_voltage_values(struct radeon_device *rdev)
1915 {
1916         int i;
1917         struct radeon_uvd_clock_voltage_dependency_table *table =
1918                 &rdev->pm.dpm.dyn_state.uvd_clock_voltage_dependency_table;
1919
1920         if (table->count) {
1921                 for (i = 0; i < table->count; i++)
1922                         table->entries[i].v =
1923                                 kv_convert_8bit_index_to_voltage(rdev,
1924                                                                  table->entries[i].v);
1925         }
1926
1927 }
1928
1929 static void kv_construct_boot_state(struct radeon_device *rdev)
1930 {
1931         struct kv_power_info *pi = kv_get_pi(rdev);
1932
1933         pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1934         pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1935         pi->boot_pl.ds_divider_index = 0;
1936         pi->boot_pl.ss_divider_index = 0;
1937         pi->boot_pl.allow_gnb_slow = 1;
1938         pi->boot_pl.force_nbp_state = 0;
1939         pi->boot_pl.display_wm = 0;
1940         pi->boot_pl.vce_wm = 0;
1941 }
1942
1943 static int kv_force_dpm_highest(struct radeon_device *rdev)
1944 {
1945         int ret;
1946         u32 enable_mask, i;
1947
1948         ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1949         if (ret)
1950                 return ret;
1951
1952         for (i = SMU7_MAX_LEVELS_GRAPHICS - 1; i > 0; i--) {
1953                 if (enable_mask & (1 << i))
1954                         break;
1955         }
1956
1957         if (rdev->family == CHIP_KABINI)
1958                 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1959         else
1960                 return kv_set_enabled_level(rdev, i);
1961 }
1962
1963 static int kv_force_dpm_lowest(struct radeon_device *rdev)
1964 {
1965         int ret;
1966         u32 enable_mask, i;
1967
1968         ret = kv_dpm_get_enable_mask(rdev, &enable_mask);
1969         if (ret)
1970                 return ret;
1971
1972         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
1973                 if (enable_mask & (1 << i))
1974                         break;
1975         }
1976
1977         if (rdev->family == CHIP_KABINI)
1978                 return kv_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_DPM_ForceState, i);
1979         else
1980                 return kv_set_enabled_level(rdev, i);
1981 }
1982
1983 static u8 kv_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1984                                              u32 sclk, u32 min_sclk_in_sr)
1985 {
1986         struct kv_power_info *pi = kv_get_pi(rdev);
1987         u32 i;
1988         u32 temp;
1989         u32 min = (min_sclk_in_sr > KV_MINIMUM_ENGINE_CLOCK) ?
1990                 min_sclk_in_sr : KV_MINIMUM_ENGINE_CLOCK;
1991
1992         if (sclk < min)
1993                 return 0;
1994
1995         if (!pi->caps_sclk_ds)
1996                 return 0;
1997
1998         for (i = KV_MAX_DEEPSLEEP_DIVIDER_ID; i > 0; i--) {
1999                 temp = sclk / sumo_get_sleep_divider_from_id(i);
2000                 if (temp >= min)
2001                         break;
2002         }
2003
2004         return (u8)i;
2005 }
2006
2007 static int kv_get_high_voltage_limit(struct radeon_device *rdev, int *limit)
2008 {
2009         struct kv_power_info *pi = kv_get_pi(rdev);
2010         struct radeon_clock_voltage_dependency_table *table =
2011                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2012         int i;
2013
2014         if (table && table->count) {
2015                 for (i = table->count - 1; i >= 0; i--) {
2016                         if (pi->high_voltage_t &&
2017                             (kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v) <=
2018                              pi->high_voltage_t)) {
2019                                 *limit = i;
2020                                 return 0;
2021                         }
2022                 }
2023         } else {
2024                 struct sumo_sclk_voltage_mapping_table *table =
2025                         &pi->sys_info.sclk_voltage_mapping_table;
2026
2027                 for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
2028                         if (pi->high_voltage_t &&
2029                             (kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit) <=
2030                              pi->high_voltage_t)) {
2031                                 *limit = i;
2032                                 return 0;
2033                         }
2034                 }
2035         }
2036
2037         *limit = 0;
2038         return 0;
2039 }
2040
2041 static void kv_apply_state_adjust_rules(struct radeon_device *rdev,
2042                                         struct radeon_ps *new_rps,
2043                                         struct radeon_ps *old_rps)
2044 {
2045         struct kv_ps *ps = kv_get_ps(new_rps);
2046         struct kv_power_info *pi = kv_get_pi(rdev);
2047         u32 min_sclk = 10000; /* ??? */
2048         u32 sclk, mclk = 0;
2049         int i, limit;
2050         bool force_high;
2051         struct radeon_clock_voltage_dependency_table *table =
2052                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2053         u32 stable_p_state_sclk = 0;
2054         struct radeon_clock_and_voltage_limits *max_limits =
2055                 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2056
2057         mclk = max_limits->mclk;
2058         sclk = min_sclk;
2059
2060         if (pi->caps_stable_p_state) {
2061                 stable_p_state_sclk = (max_limits->sclk * 75) / 100;
2062
2063                 for (i = table->count - 1; i >= 0; i++) {
2064                         if (stable_p_state_sclk >= table->entries[i].clk) {
2065                                 stable_p_state_sclk = table->entries[i].clk;
2066                                 break;
2067                         }
2068                 }
2069
2070                 if (i > 0)
2071                         stable_p_state_sclk = table->entries[0].clk;
2072
2073                 sclk = stable_p_state_sclk;
2074         }
2075
2076         ps->need_dfs_bypass = true;
2077
2078         for (i = 0; i < ps->num_levels; i++) {
2079                 if (ps->levels[i].sclk < sclk)
2080                         ps->levels[i].sclk = sclk;
2081         }
2082
2083         if (table && table->count) {
2084                 for (i = 0; i < ps->num_levels; i++) {
2085                         if (pi->high_voltage_t &&
2086                             (pi->high_voltage_t <
2087                              kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2088                                 kv_get_high_voltage_limit(rdev, &limit);
2089                                 ps->levels[i].sclk = table->entries[limit].clk;
2090                         }
2091                 }
2092         } else {
2093                 struct sumo_sclk_voltage_mapping_table *table =
2094                         &pi->sys_info.sclk_voltage_mapping_table;
2095
2096                 for (i = 0; i < ps->num_levels; i++) {
2097                         if (pi->high_voltage_t &&
2098                             (pi->high_voltage_t <
2099                              kv_convert_8bit_index_to_voltage(rdev, ps->levels[i].vddc_index))) {
2100                                 kv_get_high_voltage_limit(rdev, &limit);
2101                                 ps->levels[i].sclk = table->entries[limit].sclk_frequency;
2102                         }
2103                 }
2104         }
2105
2106         if (pi->caps_stable_p_state) {
2107                 for (i = 0; i < ps->num_levels; i++) {
2108                         ps->levels[i].sclk = stable_p_state_sclk;
2109                 }
2110         }
2111
2112         pi->video_start = new_rps->dclk || new_rps->vclk;
2113
2114         if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
2115             ATOM_PPLIB_CLASSIFICATION_UI_BATTERY)
2116                 pi->battery_state = true;
2117         else
2118                 pi->battery_state = false;
2119
2120         if (rdev->family == CHIP_KABINI) {
2121                 ps->dpm0_pg_nb_ps_lo = 0x1;
2122                 ps->dpm0_pg_nb_ps_hi = 0x0;
2123                 ps->dpmx_nb_ps_lo = 0x1;
2124                 ps->dpmx_nb_ps_hi = 0x0;
2125         } else {
2126                 ps->dpm0_pg_nb_ps_lo = 0x3;
2127                 ps->dpm0_pg_nb_ps_hi = 0x0;
2128                 ps->dpmx_nb_ps_lo = 0x3;
2129                 ps->dpmx_nb_ps_hi = 0x0;
2130
2131                 if (pi->sys_info.nb_dpm_enable) {
2132                         force_high = (mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2133                                 pi->video_start || (rdev->pm.dpm.new_active_crtc_count >= 3) ||
2134                                 pi->disable_nb_ps3_in_battery;
2135                         ps->dpm0_pg_nb_ps_lo = force_high ? 0x2 : 0x3;
2136                         ps->dpm0_pg_nb_ps_hi = 0x2;
2137                         ps->dpmx_nb_ps_lo = force_high ? 0x2 : 0x3;
2138                         ps->dpmx_nb_ps_hi = 0x2;
2139                 }
2140         }
2141 }
2142
2143 static void kv_dpm_power_level_enabled_for_throttle(struct radeon_device *rdev,
2144                                                     u32 index, bool enable)
2145 {
2146         struct kv_power_info *pi = kv_get_pi(rdev);
2147
2148         pi->graphics_level[index].EnabledForThrottle = enable ? 1 : 0;
2149 }
2150
2151 static int kv_calculate_ds_divider(struct radeon_device *rdev)
2152 {
2153         struct kv_power_info *pi = kv_get_pi(rdev);
2154         u32 sclk_in_sr = 10000; /* ??? */
2155         u32 i;
2156
2157         if (pi->lowest_valid > pi->highest_valid)
2158                 return -EINVAL;
2159
2160         for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2161                 pi->graphics_level[i].DeepSleepDivId =
2162                         kv_get_sleep_divider_id_from_clock(rdev,
2163                                                            be32_to_cpu(pi->graphics_level[i].SclkFrequency),
2164                                                            sclk_in_sr);
2165         }
2166         return 0;
2167 }
2168
2169 static int kv_calculate_nbps_level_settings(struct radeon_device *rdev)
2170 {
2171         struct kv_power_info *pi = kv_get_pi(rdev);
2172         u32 i;
2173         bool force_high;
2174         struct radeon_clock_and_voltage_limits *max_limits =
2175                 &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2176         u32 mclk = max_limits->mclk;
2177
2178         if (pi->lowest_valid > pi->highest_valid)
2179                 return -EINVAL;
2180
2181         if (rdev->family == CHIP_KABINI) {
2182                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2183                         pi->graphics_level[i].GnbSlow = 1;
2184                         pi->graphics_level[i].ForceNbPs1 = 0;
2185                         pi->graphics_level[i].UpH = 0;
2186                 }
2187
2188                 if (!pi->sys_info.nb_dpm_enable)
2189                         return 0;
2190
2191                 force_high = ((mclk >= pi->sys_info.nbp_memory_clock[3]) ||
2192                               (rdev->pm.dpm.new_active_crtc_count >= 3) || pi->video_start);
2193
2194                 if (force_high) {
2195                         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2196                                 pi->graphics_level[i].GnbSlow = 0;
2197                 } else {
2198                         if (pi->battery_state)
2199                                 pi->graphics_level[0].ForceNbPs1 = 1;
2200
2201                         pi->graphics_level[1].GnbSlow = 0;
2202                         pi->graphics_level[2].GnbSlow = 0;
2203                         pi->graphics_level[3].GnbSlow = 0;
2204                         pi->graphics_level[4].GnbSlow = 0;
2205                 }
2206         } else {
2207                 for (i = pi->lowest_valid; i <= pi->highest_valid; i++) {
2208                         pi->graphics_level[i].GnbSlow = 1;
2209                         pi->graphics_level[i].ForceNbPs1 = 0;
2210                         pi->graphics_level[i].UpH = 0;
2211                 }
2212
2213                 if (pi->sys_info.nb_dpm_enable && pi->battery_state) {
2214                         pi->graphics_level[pi->lowest_valid].UpH = 0x28;
2215                         pi->graphics_level[pi->lowest_valid].GnbSlow = 0;
2216                         if (pi->lowest_valid != pi->highest_valid)
2217                                 pi->graphics_level[pi->lowest_valid].ForceNbPs1 = 1;
2218                 }
2219         }
2220         return 0;
2221 }
2222
2223 static int kv_calculate_dpm_settings(struct radeon_device *rdev)
2224 {
2225         struct kv_power_info *pi = kv_get_pi(rdev);
2226         u32 i;
2227
2228         if (pi->lowest_valid > pi->highest_valid)
2229                 return -EINVAL;
2230
2231         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2232                 pi->graphics_level[i].DisplayWatermark = (i == pi->highest_valid) ? 1 : 0;
2233
2234         return 0;
2235 }
2236
2237 static void kv_init_graphics_levels(struct radeon_device *rdev)
2238 {
2239         struct kv_power_info *pi = kv_get_pi(rdev);
2240         u32 i;
2241         struct radeon_clock_voltage_dependency_table *table =
2242                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk;
2243
2244         if (table && table->count) {
2245                 u32 vid_2bit;
2246
2247                 pi->graphics_dpm_level_count = 0;
2248                 for (i = 0; i < table->count; i++) {
2249                         if (pi->high_voltage_t &&
2250                             (pi->high_voltage_t <
2251                              kv_convert_8bit_index_to_voltage(rdev, table->entries[i].v)))
2252                                 break;
2253
2254                         kv_set_divider_value(rdev, i, table->entries[i].clk);
2255                         vid_2bit = sumo_convert_vid7_to_vid2(rdev,
2256                                                              &pi->sys_info.vid_mapping_table,
2257                                                              table->entries[i].v);
2258                         kv_set_vid(rdev, i, vid_2bit);
2259                         kv_set_at(rdev, i, pi->at[i]);
2260                         kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2261                         pi->graphics_dpm_level_count++;
2262                 }
2263         } else {
2264                 struct sumo_sclk_voltage_mapping_table *table =
2265                         &pi->sys_info.sclk_voltage_mapping_table;
2266
2267                 pi->graphics_dpm_level_count = 0;
2268                 for (i = 0; i < table->num_max_dpm_entries; i++) {
2269                         if (pi->high_voltage_t &&
2270                             pi->high_voltage_t <
2271                             kv_convert_2bit_index_to_voltage(rdev, table->entries[i].vid_2bit))
2272                                 break;
2273
2274                         kv_set_divider_value(rdev, i, table->entries[i].sclk_frequency);
2275                         kv_set_vid(rdev, i, table->entries[i].vid_2bit);
2276                         kv_set_at(rdev, i, pi->at[i]);
2277                         kv_dpm_power_level_enabled_for_throttle(rdev, i, true);
2278                         pi->graphics_dpm_level_count++;
2279                 }
2280         }
2281
2282         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++)
2283                 kv_dpm_power_level_enable(rdev, i, false);
2284 }
2285
2286 static void kv_enable_new_levels(struct radeon_device *rdev)
2287 {
2288         struct kv_power_info *pi = kv_get_pi(rdev);
2289         u32 i;
2290
2291         for (i = 0; i < SMU7_MAX_LEVELS_GRAPHICS; i++) {
2292                 if (i >= pi->lowest_valid && i <= pi->highest_valid)
2293                         kv_dpm_power_level_enable(rdev, i, true);
2294         }
2295 }
2296
2297 static int kv_set_enabled_level(struct radeon_device *rdev, u32 level)
2298 {
2299         u32 new_mask = (1 << level);
2300
2301         return kv_send_msg_to_smc_with_parameter(rdev,
2302                                                  PPSMC_MSG_SCLKDPM_SetEnabledMask,
2303                                                  new_mask);
2304 }
2305
2306 static int kv_set_enabled_levels(struct radeon_device *rdev)
2307 {
2308         struct kv_power_info *pi = kv_get_pi(rdev);
2309         u32 i, new_mask = 0;
2310
2311         for (i = pi->lowest_valid; i <= pi->highest_valid; i++)
2312                 new_mask |= (1 << i);
2313
2314         return kv_send_msg_to_smc_with_parameter(rdev,
2315                                                  PPSMC_MSG_SCLKDPM_SetEnabledMask,
2316                                                  new_mask);
2317 }
2318
2319 static void kv_program_nbps_index_settings(struct radeon_device *rdev,
2320                                            struct radeon_ps *new_rps)
2321 {
2322         struct kv_ps *new_ps = kv_get_ps(new_rps);
2323         struct kv_power_info *pi = kv_get_pi(rdev);
2324         u32 nbdpmconfig1;
2325
2326         if (rdev->family == CHIP_KABINI)
2327                 return;
2328
2329         if (pi->sys_info.nb_dpm_enable) {
2330                 nbdpmconfig1 = RREG32_SMC(NB_DPM_CONFIG_1);
2331                 nbdpmconfig1 &= ~(Dpm0PgNbPsLo_MASK | Dpm0PgNbPsHi_MASK |
2332                                   DpmXNbPsLo_MASK | DpmXNbPsHi_MASK);
2333                 nbdpmconfig1 |= (Dpm0PgNbPsLo(new_ps->dpm0_pg_nb_ps_lo) |
2334                                  Dpm0PgNbPsHi(new_ps->dpm0_pg_nb_ps_hi) |
2335                                  DpmXNbPsLo(new_ps->dpmx_nb_ps_lo) |
2336                                  DpmXNbPsHi(new_ps->dpmx_nb_ps_hi));
2337                 WREG32_SMC(NB_DPM_CONFIG_1, nbdpmconfig1);
2338         }
2339 }
2340
2341 static int kv_set_thermal_temperature_range(struct radeon_device *rdev,
2342                                             int min_temp, int max_temp)
2343 {
2344         int low_temp = 0 * 1000;
2345         int high_temp = 255 * 1000;
2346         u32 tmp;
2347
2348         if (low_temp < min_temp)
2349                 low_temp = min_temp;
2350         if (high_temp > max_temp)
2351                 high_temp = max_temp;
2352         if (high_temp < low_temp) {
2353                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
2354                 return -EINVAL;
2355         }
2356
2357         tmp = RREG32_SMC(CG_THERMAL_INT_CTRL);
2358         tmp &= ~(DIG_THERM_INTH_MASK | DIG_THERM_INTL_MASK);
2359         tmp |= (DIG_THERM_INTH(49 + (high_temp / 1000)) |
2360                 DIG_THERM_INTL(49 + (low_temp / 1000)));
2361         WREG32_SMC(CG_THERMAL_INT_CTRL, tmp);
2362
2363         rdev->pm.dpm.thermal.min_temp = low_temp;
2364         rdev->pm.dpm.thermal.max_temp = high_temp;
2365
2366         return 0;
2367 }
2368
2369 union igp_info {
2370         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
2371         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
2372         struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
2373         struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
2374         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
2375         struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
2376 };
2377
2378 static int kv_parse_sys_info_table(struct radeon_device *rdev)
2379 {
2380         struct kv_power_info *pi = kv_get_pi(rdev);
2381         struct radeon_mode_info *mode_info = &rdev->mode_info;
2382         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
2383         union igp_info *igp_info;
2384         u8 frev, crev;
2385         u16 data_offset;
2386         int i;
2387
2388         if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2389                                    &frev, &crev, &data_offset)) {
2390                 igp_info = (union igp_info *)(mode_info->atom_context->bios +
2391                                               data_offset);
2392
2393                 if (crev != 8) {
2394                         DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
2395                         return -EINVAL;
2396                 }
2397                 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_8.ulBootUpEngineClock);
2398                 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_8.ulBootUpUMAClock);
2399                 pi->sys_info.bootup_nb_voltage_index =
2400                         le16_to_cpu(igp_info->info_8.usBootUpNBVoltage);
2401                 if (igp_info->info_8.ucHtcTmpLmt == 0)
2402                         pi->sys_info.htc_tmp_lmt = 203;
2403                 else
2404                         pi->sys_info.htc_tmp_lmt = igp_info->info_8.ucHtcTmpLmt;
2405                 if (igp_info->info_8.ucHtcHystLmt == 0)
2406                         pi->sys_info.htc_hyst_lmt = 5;
2407                 else
2408                         pi->sys_info.htc_hyst_lmt = igp_info->info_8.ucHtcHystLmt;
2409                 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
2410                         DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
2411                 }
2412
2413                 if (le32_to_cpu(igp_info->info_8.ulSystemConfig) & (1 << 3))
2414                         pi->sys_info.nb_dpm_enable = true;
2415                 else
2416                         pi->sys_info.nb_dpm_enable = false;
2417
2418                 for (i = 0; i < KV_NUM_NBPSTATES; i++) {
2419                         pi->sys_info.nbp_memory_clock[i] =
2420                                 le32_to_cpu(igp_info->info_8.ulNbpStateMemclkFreq[i]);
2421                         pi->sys_info.nbp_n_clock[i] =
2422                                 le32_to_cpu(igp_info->info_8.ulNbpStateNClkFreq[i]);
2423                 }
2424                 if (le32_to_cpu(igp_info->info_8.ulGPUCapInfo) &
2425                     SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS)
2426                         pi->caps_enable_dfs_bypass = true;
2427
2428                 sumo_construct_sclk_voltage_mapping_table(rdev,
2429                                                           &pi->sys_info.sclk_voltage_mapping_table,
2430                                                           igp_info->info_8.sAvail_SCLK);
2431
2432                 sumo_construct_vid_mapping_table(rdev,
2433                                                  &pi->sys_info.vid_mapping_table,
2434                                                  igp_info->info_8.sAvail_SCLK);
2435
2436                 kv_construct_max_power_limits_table(rdev,
2437                                                     &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac);
2438         }
2439         return 0;
2440 }
2441
2442 union power_info {
2443         struct _ATOM_POWERPLAY_INFO info;
2444         struct _ATOM_POWERPLAY_INFO_V2 info_2;
2445         struct _ATOM_POWERPLAY_INFO_V3 info_3;
2446         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2447         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2448         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2449 };
2450
2451 union pplib_clock_info {
2452         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2453         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2454         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2455         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2456 };
2457
2458 union pplib_power_state {
2459         struct _ATOM_PPLIB_STATE v1;
2460         struct _ATOM_PPLIB_STATE_V2 v2;
2461 };
2462
2463 static void kv_patch_boot_state(struct radeon_device *rdev,
2464                                 struct kv_ps *ps)
2465 {
2466         struct kv_power_info *pi = kv_get_pi(rdev);
2467
2468         ps->num_levels = 1;
2469         ps->levels[0] = pi->boot_pl;
2470 }
2471
2472 static void kv_parse_pplib_non_clock_info(struct radeon_device *rdev,
2473                                           struct radeon_ps *rps,
2474                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
2475                                           u8 table_rev)
2476 {
2477         struct kv_ps *ps = kv_get_ps(rps);
2478
2479         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2480         rps->class = le16_to_cpu(non_clock_info->usClassification);
2481         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
2482
2483         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
2484                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
2485                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
2486         } else {
2487                 rps->vclk = 0;
2488                 rps->dclk = 0;
2489         }
2490
2491         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2492                 rdev->pm.dpm.boot_ps = rps;
2493                 kv_patch_boot_state(rdev, ps);
2494         }
2495         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
2496                 rdev->pm.dpm.uvd_ps = rps;
2497 }
2498
2499 static void kv_parse_pplib_clock_info(struct radeon_device *rdev,
2500                                       struct radeon_ps *rps, int index,
2501                                         union pplib_clock_info *clock_info)
2502 {
2503         struct kv_power_info *pi = kv_get_pi(rdev);
2504         struct kv_ps *ps = kv_get_ps(rps);
2505         struct kv_pl *pl = &ps->levels[index];
2506         u32 sclk;
2507
2508         sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2509         sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2510         pl->sclk = sclk;
2511         pl->vddc_index = clock_info->sumo.vddcIndex;
2512
2513         ps->num_levels = index + 1;
2514
2515         if (pi->caps_sclk_ds) {
2516                 pl->ds_divider_index = 5;
2517                 pl->ss_divider_index = 5;
2518         }
2519 }
2520
2521 static int kv_parse_power_table(struct radeon_device *rdev)
2522 {
2523         struct radeon_mode_info *mode_info = &rdev->mode_info;
2524         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2525         union pplib_power_state *power_state;
2526         int i, j, k, non_clock_array_index, clock_array_index;
2527         union pplib_clock_info *clock_info;
2528         struct _StateArray *state_array;
2529         struct _ClockInfoArray *clock_info_array;
2530         struct _NonClockInfoArray *non_clock_info_array;
2531         union power_info *power_info;
2532         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2533         u16 data_offset;
2534         u8 frev, crev;
2535         u8 *power_state_offset;
2536         struct kv_ps *ps;
2537
2538         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2539                                    &frev, &crev, &data_offset))
2540                 return -EINVAL;
2541         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2542
2543         state_array = (struct _StateArray *)
2544                 (mode_info->atom_context->bios + data_offset +
2545                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
2546         clock_info_array = (struct _ClockInfoArray *)
2547                 (mode_info->atom_context->bios + data_offset +
2548                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2549         non_clock_info_array = (struct _NonClockInfoArray *)
2550                 (mode_info->atom_context->bios + data_offset +
2551                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2552
2553         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
2554                                   state_array->ucNumEntries, GFP_KERNEL);
2555         if (!rdev->pm.dpm.ps)
2556                 return -ENOMEM;
2557         power_state_offset = (u8 *)state_array->states;
2558         rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
2559         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
2560         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
2561         for (i = 0; i < state_array->ucNumEntries; i++) {
2562                 u8 *idx;
2563                 power_state = (union pplib_power_state *)power_state_offset;
2564                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2565                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2566                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
2567                 if (!rdev->pm.power_state[i].clock_info)
2568                         return -EINVAL;
2569                 ps = kzalloc(sizeof(struct kv_ps), GFP_KERNEL);
2570                 if (ps == NULL) {
2571                         kfree(rdev->pm.dpm.ps);
2572                         return -ENOMEM;
2573                 }
2574                 rdev->pm.dpm.ps[i].ps_priv = ps;
2575                 k = 0;
2576                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
2577                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2578                         clock_array_index = idx[j];
2579                         if (clock_array_index >= clock_info_array->ucNumEntries)
2580                                 continue;
2581                         if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
2582                                 break;
2583                         clock_info = (union pplib_clock_info *)
2584                                 ((u8 *)&clock_info_array->clockInfo[0] +
2585                                  (clock_array_index * clock_info_array->ucEntrySize));
2586                         kv_parse_pplib_clock_info(rdev,
2587                                                   &rdev->pm.dpm.ps[i], k,
2588                                                   clock_info);
2589                         k++;
2590                 }
2591                 kv_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
2592                                               non_clock_info,
2593                                               non_clock_info_array->ucEntrySize);
2594                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2595         }
2596         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
2597         return 0;
2598 }
2599
2600 int kv_dpm_init(struct radeon_device *rdev)
2601 {
2602         struct kv_power_info *pi;
2603         int ret, i;
2604
2605         pi = kzalloc(sizeof(struct kv_power_info), GFP_KERNEL);
2606         if (pi == NULL)
2607                 return -ENOMEM;
2608         rdev->pm.dpm.priv = pi;
2609
2610         ret = r600_parse_extended_power_table(rdev);
2611         if (ret)
2612                 return ret;
2613
2614         for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++)
2615                 pi->at[i] = TRINITY_AT_DFLT;
2616
2617         pi->sram_end = SMC_RAM_END;
2618
2619         if (rdev->family == CHIP_KABINI)
2620                 pi->high_voltage_t = 4001;
2621
2622         pi->enable_nb_dpm = true;
2623
2624         pi->caps_power_containment = true;
2625         pi->caps_cac = true;
2626         pi->enable_didt = false;
2627         if (pi->enable_didt) {
2628                 pi->caps_sq_ramping = true;
2629                 pi->caps_db_ramping = true;
2630                 pi->caps_td_ramping = true;
2631                 pi->caps_tcp_ramping = true;
2632         }
2633
2634         pi->caps_sclk_ds = true;
2635         pi->enable_auto_thermal_throttling = true;
2636         pi->disable_nb_ps3_in_battery = false;
2637         pi->bapm_enable = false;
2638         pi->voltage_drop_t = 0;
2639         pi->caps_sclk_throttle_low_notification = false;
2640         pi->caps_fps = false; /* true? */
2641         pi->caps_uvd_pg = true;
2642         pi->caps_uvd_dpm = true;
2643         pi->caps_vce_pg = false;
2644         pi->caps_samu_pg = false;
2645         pi->caps_acp_pg = false;
2646         pi->caps_stable_p_state = false;
2647
2648         ret = kv_parse_sys_info_table(rdev);
2649         if (ret)
2650                 return ret;
2651
2652         kv_patch_voltage_values(rdev);
2653         kv_construct_boot_state(rdev);
2654
2655         ret = kv_parse_power_table(rdev);
2656         if (ret)
2657                 return ret;
2658
2659         pi->enable_dpm = true;
2660
2661         return 0;
2662 }
2663
2664 void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
2665                                                     struct seq_file *m)
2666 {
2667         struct kv_power_info *pi = kv_get_pi(rdev);
2668         u32 current_index =
2669                 (RREG32_SMC(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) >>
2670                 CURR_SCLK_INDEX_SHIFT;
2671         u32 sclk, tmp;
2672         u16 vddc;
2673
2674         if (current_index >= SMU__NUM_SCLK_DPM_STATE) {
2675                 seq_printf(m, "invalid dpm profile %d\n", current_index);
2676         } else {
2677                 sclk = be32_to_cpu(pi->graphics_level[current_index].SclkFrequency);
2678                 tmp = (RREG32_SMC(SMU_VOLTAGE_STATUS) & SMU_VOLTAGE_CURRENT_LEVEL_MASK) >>
2679                         SMU_VOLTAGE_CURRENT_LEVEL_SHIFT;
2680                 vddc = kv_convert_8bit_index_to_voltage(rdev, (u16)tmp);
2681                 seq_printf(m, "power level %d    sclk: %u vddc: %u\n",
2682                            current_index, sclk, vddc);
2683         }
2684 }
2685
2686 void kv_dpm_print_power_state(struct radeon_device *rdev,
2687                               struct radeon_ps *rps)
2688 {
2689         int i;
2690         struct kv_ps *ps = kv_get_ps(rps);
2691
2692         r600_dpm_print_class_info(rps->class, rps->class2);
2693         r600_dpm_print_cap_info(rps->caps);
2694         printk("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
2695         for (i = 0; i < ps->num_levels; i++) {
2696                 struct kv_pl *pl = &ps->levels[i];
2697                 printk("\t\tpower level %d    sclk: %u vddc: %u\n",
2698                        i, pl->sclk,
2699                        kv_convert_8bit_index_to_voltage(rdev, pl->vddc_index));
2700         }
2701         r600_dpm_print_ps_status(rdev, rps);
2702 }
2703
2704 void kv_dpm_fini(struct radeon_device *rdev)
2705 {
2706         int i;
2707
2708         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
2709                 kfree(rdev->pm.dpm.ps[i].ps_priv);
2710         }
2711         kfree(rdev->pm.dpm.ps);
2712         kfree(rdev->pm.dpm.priv);
2713         r600_free_extended_power_table(rdev);
2714 }
2715
2716 void kv_dpm_display_configuration_changed(struct radeon_device *rdev)
2717 {
2718
2719 }
2720
2721 u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low)
2722 {
2723         struct kv_power_info *pi = kv_get_pi(rdev);
2724         struct kv_ps *requested_state = kv_get_ps(&pi->requested_rps);
2725
2726         if (low)
2727                 return requested_state->levels[0].sclk;
2728         else
2729                 return requested_state->levels[requested_state->num_levels - 1].sclk;
2730 }
2731
2732 u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low)
2733 {
2734         struct kv_power_info *pi = kv_get_pi(rdev);
2735
2736         return pi->sys_info.bootup_uma_clk;
2737 }
2738