2 * Copyright 2013 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #define SMU__NUM_SCLK_DPM_STATE 8
27 #define SMU__NUM_MCLK_DPM_LEVELS 4
28 #define SMU__NUM_LCLK_DPM_LEVELS 8
29 #define SMU__NUM_PCIE_DPM_LEVELS 0 /* ??? */
30 #include "smu7_fusion.h"
31 #include "trinity_dpm.h"
34 #define KV_NUM_NBPSTATES 4
36 enum kv_pt_config_reg_type {
39 KV_CONFIGREG_DIDT_IND,
44 struct kv_pt_config_reg {
49 enum kv_pt_config_reg_type type;
52 struct kv_lcac_config_values {
58 struct kv_lcac_config_reg {
82 struct kv_pl levels[SUMO_MAX_HARDWARE_POWERLEVELS];
96 u32 nbp_memory_clock[KV_NUM_NBPSTATES];
97 u32 nbp_n_clock[KV_NUM_NBPSTATES];
98 u16 bootup_nb_voltage_index;
101 struct sumo_sclk_voltage_mapping_table sclk_voltage_mapping_table;
102 struct sumo_vid_mapping_table vid_mapping_table;
103 u32 uma_channel_number;
106 struct kv_power_info {
107 u32 at[SUMO_MAX_HARDWARE_POWERLEVELS];
109 struct kv_sys_info sys_info;
110 struct kv_pl boot_pl;
111 bool enable_nb_ps_policy;
112 bool disable_nb_ps3_in_battery;
125 u8 graphics_dpm_level_count;
131 SMU7_Fusion_GraphicsLevel graphics_level[SMU__NUM_SCLK_DPM_STATE];
132 SMU7_Fusion_ACPILevel acpi_level;
133 SMU7_Fusion_UvdLevel uvd_level[SMU7_MAX_LEVELS_UVD];
134 SMU7_Fusion_ExtClkLevel vce_level[SMU7_MAX_LEVELS_VCE];
135 SMU7_Fusion_ExtClkLevel acp_level[SMU7_MAX_LEVELS_ACP];
136 SMU7_Fusion_ExtClkLevel samu_level[SMU7_MAX_LEVELS_SAMU];
145 u8 graphics_boot_level;
146 u8 graphics_interval;
147 u8 graphics_therm_throttle_enable;
148 u8 graphics_voltage_change_enable;
149 u8 graphics_clk_slow_enable;
150 u8 graphics_clk_slow_divider;
152 u32 low_sclk_interrupt_t;
153 bool uvd_power_gated;
154 bool vce_power_gated;
155 bool acp_power_gated;
156 bool samu_power_gated;
161 bool enable_auto_thermal_throttling;
165 bool caps_power_containment;
166 bool caps_sq_ramping;
167 bool caps_db_ramping;
168 bool caps_td_ramping;
169 bool caps_tcp_ramping;
170 bool caps_sclk_throttle_low_notification;
177 bool caps_stable_p_state;
178 bool caps_enable_dfs_bypass;
180 struct radeon_ps current_rps;
181 struct kv_ps current_ps;
182 struct radeon_ps requested_rps;
183 struct kv_ps requested_ps;
188 int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id);
189 int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask);
190 int kv_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
191 PPSMC_Msg msg, u32 parameter);
192 int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
193 u32 *value, u32 limit);
194 int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable);
195 int kv_copy_bytes_to_smc(struct radeon_device *rdev,
196 u32 smc_start_address,
197 const u8 *src, u32 byte_count, u32 limit);