2 * Copyright 2013 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
30 int kv_notify_message_to_smu(struct radeon_device *rdev, u32 id)
35 WREG32(SMC_MESSAGE_0, id & SMC_MSG_MASK);
37 for (i = 0; i < rdev->usec_timeout; i++) {
38 if ((RREG32(SMC_RESP_0) & SMC_RESP_MASK) != 0)
42 tmp = RREG32(SMC_RESP_0) & SMC_RESP_MASK;
54 int kv_dpm_get_enable_mask(struct radeon_device *rdev, u32 *enable_mask)
58 ret = kv_notify_message_to_smu(rdev, PPSMC_MSG_SCLKDPM_GetEnabledMask);
61 *enable_mask = RREG32_SMC(SMC_SYSCON_MSG_ARG_0);
66 int kv_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
67 PPSMC_Msg msg, u32 parameter)
70 WREG32(SMC_MSG_ARG_0, parameter);
72 return kv_notify_message_to_smu(rdev, msg);
75 static int kv_set_smc_sram_address(struct radeon_device *rdev,
76 u32 smc_address, u32 limit)
80 if ((smc_address + 3) > limit)
83 WREG32(SMC_IND_INDEX_0, smc_address);
84 WREG32_P(SMC_IND_ACCESS_CNTL, 0, ~AUTO_INCREMENT_IND_0);
89 int kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address,
90 u32 *value, u32 limit)
94 ret = kv_set_smc_sram_address(rdev, smc_address, limit);
98 *value = RREG32(SMC_IND_DATA_0);
102 int kv_smc_dpm_enable(struct radeon_device *rdev, bool enable)
105 return kv_notify_message_to_smu(rdev, PPSMC_MSG_DPM_Enable);
107 return kv_notify_message_to_smu(rdev, PPSMC_MSG_DPM_Disable);
110 int kv_smc_bapm_enable(struct radeon_device *rdev, bool enable)
113 return kv_notify_message_to_smu(rdev, PPSMC_MSG_EnableBAPM);
115 return kv_notify_message_to_smu(rdev, PPSMC_MSG_DisableBAPM);
118 int kv_copy_bytes_to_smc(struct radeon_device *rdev,
119 u32 smc_start_address,
120 const u8 *src, u32 byte_count, u32 limit)
123 u32 data, original_data, addr, extra_shift, t_byte, count, mask;
125 if ((smc_start_address + byte_count) > limit)
128 addr = smc_start_address;
131 /* RMW for the initial bytes */
135 ret = kv_set_smc_sram_address(rdev, addr, limit);
139 original_data = RREG32(SMC_IND_DATA_0);
146 mask = (mask << 8) | 0xff;
148 } else if (byte_count > 0) {
149 data = (data << 8) + *src++;
154 mask = (mask << 8) | 0xff;
159 data |= original_data & mask;
161 ret = kv_set_smc_sram_address(rdev, addr, limit);
165 WREG32(SMC_IND_DATA_0, data);
170 while (byte_count >= 4) {
171 /* SMC address space is BE */
172 data = (src[0] << 24) + (src[1] << 16) + (src[2] << 8) + src[3];
174 ret = kv_set_smc_sram_address(rdev, addr, limit);
178 WREG32(SMC_IND_DATA_0, data);
185 /* RMW for the final bytes */
186 if (byte_count > 0) {
189 ret = kv_set_smc_sram_address(rdev, addr, limit);
193 original_data= RREG32(SMC_IND_DATA_0);
195 extra_shift = 8 * (4 - byte_count);
197 while (byte_count > 0) {
198 /* SMC address space is BE */
199 data = (data << 8) + *src++;
203 data <<= extra_shift;
205 data |= (original_data & ~((~0UL) << extra_shift));
207 ret = kv_set_smc_sram_address(rdev, addr, limit);
211 WREG32(SMC_IND_DATA_0, data);