2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
24 #include <linux/firmware.h>
25 #include <linux/slab.h>
26 #include <linux/module.h>
29 #include "radeon_asic.h"
30 #include <drm/radeon_drm.h>
34 #include "cayman_blit_shaders.h"
35 #include "radeon_ucode.h"
36 #include "clearstate_cayman.h"
38 static const u32 tn_rlc_save_restore_register_list[] =
164 extern bool evergreen_is_display_hung(struct radeon_device *rdev);
165 extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
166 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
167 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
168 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
169 extern void evergreen_mc_program(struct radeon_device *rdev);
170 extern void evergreen_irq_suspend(struct radeon_device *rdev);
171 extern int evergreen_mc_init(struct radeon_device *rdev);
172 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
173 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
174 extern void evergreen_program_aspm(struct radeon_device *rdev);
175 extern void sumo_rlc_fini(struct radeon_device *rdev);
176 extern int sumo_rlc_init(struct radeon_device *rdev);
177 extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev);
180 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
181 MODULE_FIRMWARE("radeon/BARTS_me.bin");
182 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
183 MODULE_FIRMWARE("radeon/BARTS_smc.bin");
184 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
185 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
186 MODULE_FIRMWARE("radeon/TURKS_me.bin");
187 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
188 MODULE_FIRMWARE("radeon/TURKS_smc.bin");
189 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
190 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
191 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
192 MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
193 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
194 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
195 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
196 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
197 MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
198 MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
199 MODULE_FIRMWARE("radeon/ARUBA_me.bin");
200 MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
203 static const u32 cayman_golden_registers2[] =
205 0x3e5c, 0xffffffff, 0x00000000,
206 0x3e48, 0xffffffff, 0x00000000,
207 0x3e4c, 0xffffffff, 0x00000000,
208 0x3e64, 0xffffffff, 0x00000000,
209 0x3e50, 0xffffffff, 0x00000000,
210 0x3e60, 0xffffffff, 0x00000000
213 static const u32 cayman_golden_registers[] =
215 0x5eb4, 0xffffffff, 0x00000002,
216 0x5e78, 0x8f311ff1, 0x001000f0,
217 0x3f90, 0xffff0000, 0xff000000,
218 0x9148, 0xffff0000, 0xff000000,
219 0x3f94, 0xffff0000, 0xff000000,
220 0x914c, 0xffff0000, 0xff000000,
221 0xc78, 0x00000080, 0x00000080,
222 0xbd4, 0x70073777, 0x00011003,
223 0xd02c, 0xbfffff1f, 0x08421000,
224 0xd0b8, 0x73773777, 0x02011003,
225 0x5bc0, 0x00200000, 0x50100000,
226 0x98f8, 0x33773777, 0x02011003,
227 0x98fc, 0xffffffff, 0x76541032,
228 0x7030, 0x31000311, 0x00000011,
229 0x2f48, 0x33773777, 0x42010001,
230 0x6b28, 0x00000010, 0x00000012,
231 0x7728, 0x00000010, 0x00000012,
232 0x10328, 0x00000010, 0x00000012,
233 0x10f28, 0x00000010, 0x00000012,
234 0x11b28, 0x00000010, 0x00000012,
235 0x12728, 0x00000010, 0x00000012,
236 0x240c, 0x000007ff, 0x00000000,
237 0x8a14, 0xf000001f, 0x00000007,
238 0x8b24, 0x3fff3fff, 0x00ff0fff,
239 0x8b10, 0x0000ff0f, 0x00000000,
240 0x28a4c, 0x07ffffff, 0x06000000,
241 0x10c, 0x00000001, 0x00010003,
242 0xa02c, 0xffffffff, 0x0000009b,
243 0x913c, 0x0000010f, 0x01000100,
244 0x8c04, 0xf8ff00ff, 0x40600060,
245 0x28350, 0x00000f01, 0x00000000,
246 0x9508, 0x3700001f, 0x00000002,
247 0x960c, 0xffffffff, 0x54763210,
248 0x88c4, 0x001f3ae3, 0x00000082,
249 0x88d0, 0xffffffff, 0x0f40df40,
250 0x88d4, 0x0000001f, 0x00000010,
251 0x8974, 0xffffffff, 0x00000000
254 static const u32 dvst_golden_registers2[] =
256 0x8f8, 0xffffffff, 0,
257 0x8fc, 0x00380000, 0,
258 0x8f8, 0xffffffff, 1,
262 static const u32 dvst_golden_registers[] =
264 0x690, 0x3fff3fff, 0x20c00033,
265 0x918c, 0x0fff0fff, 0x00010006,
266 0x91a8, 0x0fff0fff, 0x00010006,
267 0x9150, 0xffffdfff, 0x6e944040,
268 0x917c, 0x0fff0fff, 0x00030002,
269 0x9198, 0x0fff0fff, 0x00030002,
270 0x915c, 0x0fff0fff, 0x00010000,
271 0x3f90, 0xffff0001, 0xff000000,
272 0x9178, 0x0fff0fff, 0x00070000,
273 0x9194, 0x0fff0fff, 0x00070000,
274 0x9148, 0xffff0001, 0xff000000,
275 0x9190, 0x0fff0fff, 0x00090008,
276 0x91ac, 0x0fff0fff, 0x00090008,
277 0x3f94, 0xffff0000, 0xff000000,
278 0x914c, 0xffff0000, 0xff000000,
279 0x929c, 0x00000fff, 0x00000001,
280 0x55e4, 0xff607fff, 0xfc000100,
281 0x8a18, 0xff000fff, 0x00000100,
282 0x8b28, 0xff000fff, 0x00000100,
283 0x9144, 0xfffc0fff, 0x00000100,
284 0x6ed8, 0x00010101, 0x00010000,
285 0x9830, 0xffffffff, 0x00000000,
286 0x9834, 0xf00fffff, 0x00000400,
287 0x9838, 0xfffffffe, 0x00000000,
288 0xd0c0, 0xff000fff, 0x00000100,
289 0xd02c, 0xbfffff1f, 0x08421000,
290 0xd0b8, 0x73773777, 0x12010001,
291 0x5bb0, 0x000000f0, 0x00000070,
292 0x98f8, 0x73773777, 0x12010001,
293 0x98fc, 0xffffffff, 0x00000010,
294 0x9b7c, 0x00ff0000, 0x00fc0000,
295 0x8030, 0x00001f0f, 0x0000100a,
296 0x2f48, 0x73773777, 0x12010001,
297 0x2408, 0x00030000, 0x000c007f,
298 0x8a14, 0xf000003f, 0x00000007,
299 0x8b24, 0x3fff3fff, 0x00ff0fff,
300 0x8b10, 0x0000ff0f, 0x00000000,
301 0x28a4c, 0x07ffffff, 0x06000000,
302 0x4d8, 0x00000fff, 0x00000100,
303 0xa008, 0xffffffff, 0x00010000,
304 0x913c, 0xffff03ff, 0x01000100,
305 0x8c00, 0x000000ff, 0x00000003,
306 0x8c04, 0xf8ff00ff, 0x40600060,
307 0x8cf0, 0x1fff1fff, 0x08e00410,
308 0x28350, 0x00000f01, 0x00000000,
309 0x9508, 0xf700071f, 0x00000002,
310 0x960c, 0xffffffff, 0x54763210,
311 0x20ef8, 0x01ff01ff, 0x00000002,
312 0x20e98, 0xfffffbff, 0x00200000,
313 0x2015c, 0xffffffff, 0x00000f40,
314 0x88c4, 0x001f3ae3, 0x00000082,
315 0x8978, 0x3fffffff, 0x04050140,
316 0x88d4, 0x0000001f, 0x00000010,
317 0x8974, 0xffffffff, 0x00000000
320 static const u32 scrapper_golden_registers[] =
322 0x690, 0x3fff3fff, 0x20c00033,
323 0x918c, 0x0fff0fff, 0x00010006,
324 0x918c, 0x0fff0fff, 0x00010006,
325 0x91a8, 0x0fff0fff, 0x00010006,
326 0x91a8, 0x0fff0fff, 0x00010006,
327 0x9150, 0xffffdfff, 0x6e944040,
328 0x9150, 0xffffdfff, 0x6e944040,
329 0x917c, 0x0fff0fff, 0x00030002,
330 0x917c, 0x0fff0fff, 0x00030002,
331 0x9198, 0x0fff0fff, 0x00030002,
332 0x9198, 0x0fff0fff, 0x00030002,
333 0x915c, 0x0fff0fff, 0x00010000,
334 0x915c, 0x0fff0fff, 0x00010000,
335 0x3f90, 0xffff0001, 0xff000000,
336 0x3f90, 0xffff0001, 0xff000000,
337 0x9178, 0x0fff0fff, 0x00070000,
338 0x9178, 0x0fff0fff, 0x00070000,
339 0x9194, 0x0fff0fff, 0x00070000,
340 0x9194, 0x0fff0fff, 0x00070000,
341 0x9148, 0xffff0001, 0xff000000,
342 0x9148, 0xffff0001, 0xff000000,
343 0x9190, 0x0fff0fff, 0x00090008,
344 0x9190, 0x0fff0fff, 0x00090008,
345 0x91ac, 0x0fff0fff, 0x00090008,
346 0x91ac, 0x0fff0fff, 0x00090008,
347 0x3f94, 0xffff0000, 0xff000000,
348 0x3f94, 0xffff0000, 0xff000000,
349 0x914c, 0xffff0000, 0xff000000,
350 0x914c, 0xffff0000, 0xff000000,
351 0x929c, 0x00000fff, 0x00000001,
352 0x929c, 0x00000fff, 0x00000001,
353 0x55e4, 0xff607fff, 0xfc000100,
354 0x8a18, 0xff000fff, 0x00000100,
355 0x8a18, 0xff000fff, 0x00000100,
356 0x8b28, 0xff000fff, 0x00000100,
357 0x8b28, 0xff000fff, 0x00000100,
358 0x9144, 0xfffc0fff, 0x00000100,
359 0x9144, 0xfffc0fff, 0x00000100,
360 0x6ed8, 0x00010101, 0x00010000,
361 0x9830, 0xffffffff, 0x00000000,
362 0x9830, 0xffffffff, 0x00000000,
363 0x9834, 0xf00fffff, 0x00000400,
364 0x9834, 0xf00fffff, 0x00000400,
365 0x9838, 0xfffffffe, 0x00000000,
366 0x9838, 0xfffffffe, 0x00000000,
367 0xd0c0, 0xff000fff, 0x00000100,
368 0xd02c, 0xbfffff1f, 0x08421000,
369 0xd02c, 0xbfffff1f, 0x08421000,
370 0xd0b8, 0x73773777, 0x12010001,
371 0xd0b8, 0x73773777, 0x12010001,
372 0x5bb0, 0x000000f0, 0x00000070,
373 0x98f8, 0x73773777, 0x12010001,
374 0x98f8, 0x73773777, 0x12010001,
375 0x98fc, 0xffffffff, 0x00000010,
376 0x98fc, 0xffffffff, 0x00000010,
377 0x9b7c, 0x00ff0000, 0x00fc0000,
378 0x9b7c, 0x00ff0000, 0x00fc0000,
379 0x8030, 0x00001f0f, 0x0000100a,
380 0x8030, 0x00001f0f, 0x0000100a,
381 0x2f48, 0x73773777, 0x12010001,
382 0x2f48, 0x73773777, 0x12010001,
383 0x2408, 0x00030000, 0x000c007f,
384 0x8a14, 0xf000003f, 0x00000007,
385 0x8a14, 0xf000003f, 0x00000007,
386 0x8b24, 0x3fff3fff, 0x00ff0fff,
387 0x8b24, 0x3fff3fff, 0x00ff0fff,
388 0x8b10, 0x0000ff0f, 0x00000000,
389 0x8b10, 0x0000ff0f, 0x00000000,
390 0x28a4c, 0x07ffffff, 0x06000000,
391 0x28a4c, 0x07ffffff, 0x06000000,
392 0x4d8, 0x00000fff, 0x00000100,
393 0x4d8, 0x00000fff, 0x00000100,
394 0xa008, 0xffffffff, 0x00010000,
395 0xa008, 0xffffffff, 0x00010000,
396 0x913c, 0xffff03ff, 0x01000100,
397 0x913c, 0xffff03ff, 0x01000100,
398 0x90e8, 0x001fffff, 0x010400c0,
399 0x8c00, 0x000000ff, 0x00000003,
400 0x8c00, 0x000000ff, 0x00000003,
401 0x8c04, 0xf8ff00ff, 0x40600060,
402 0x8c04, 0xf8ff00ff, 0x40600060,
403 0x8c30, 0x0000000f, 0x00040005,
404 0x8cf0, 0x1fff1fff, 0x08e00410,
405 0x8cf0, 0x1fff1fff, 0x08e00410,
406 0x900c, 0x00ffffff, 0x0017071f,
407 0x28350, 0x00000f01, 0x00000000,
408 0x28350, 0x00000f01, 0x00000000,
409 0x9508, 0xf700071f, 0x00000002,
410 0x9508, 0xf700071f, 0x00000002,
411 0x9688, 0x00300000, 0x0017000f,
412 0x960c, 0xffffffff, 0x54763210,
413 0x960c, 0xffffffff, 0x54763210,
414 0x20ef8, 0x01ff01ff, 0x00000002,
415 0x20e98, 0xfffffbff, 0x00200000,
416 0x2015c, 0xffffffff, 0x00000f40,
417 0x88c4, 0x001f3ae3, 0x00000082,
418 0x88c4, 0x001f3ae3, 0x00000082,
419 0x8978, 0x3fffffff, 0x04050140,
420 0x8978, 0x3fffffff, 0x04050140,
421 0x88d4, 0x0000001f, 0x00000010,
422 0x88d4, 0x0000001f, 0x00000010,
423 0x8974, 0xffffffff, 0x00000000,
424 0x8974, 0xffffffff, 0x00000000
427 static void ni_init_golden_registers(struct radeon_device *rdev)
429 switch (rdev->family) {
431 radeon_program_register_sequence(rdev,
432 cayman_golden_registers,
433 (const u32)ARRAY_SIZE(cayman_golden_registers));
434 radeon_program_register_sequence(rdev,
435 cayman_golden_registers2,
436 (const u32)ARRAY_SIZE(cayman_golden_registers2));
439 if ((rdev->pdev->device == 0x9900) ||
440 (rdev->pdev->device == 0x9901) ||
441 (rdev->pdev->device == 0x9903) ||
442 (rdev->pdev->device == 0x9904) ||
443 (rdev->pdev->device == 0x9905) ||
444 (rdev->pdev->device == 0x9906) ||
445 (rdev->pdev->device == 0x9907) ||
446 (rdev->pdev->device == 0x9908) ||
447 (rdev->pdev->device == 0x9909) ||
448 (rdev->pdev->device == 0x990A) ||
449 (rdev->pdev->device == 0x990B) ||
450 (rdev->pdev->device == 0x990C) ||
451 (rdev->pdev->device == 0x990D) ||
452 (rdev->pdev->device == 0x990E) ||
453 (rdev->pdev->device == 0x990F) ||
454 (rdev->pdev->device == 0x9910) ||
455 (rdev->pdev->device == 0x9913) ||
456 (rdev->pdev->device == 0x9917) ||
457 (rdev->pdev->device == 0x9918)) {
458 radeon_program_register_sequence(rdev,
459 dvst_golden_registers,
460 (const u32)ARRAY_SIZE(dvst_golden_registers));
461 radeon_program_register_sequence(rdev,
462 dvst_golden_registers2,
463 (const u32)ARRAY_SIZE(dvst_golden_registers2));
465 radeon_program_register_sequence(rdev,
466 scrapper_golden_registers,
467 (const u32)ARRAY_SIZE(scrapper_golden_registers));
468 radeon_program_register_sequence(rdev,
469 dvst_golden_registers2,
470 (const u32)ARRAY_SIZE(dvst_golden_registers2));
478 #define BTC_IO_MC_REGS_SIZE 29
480 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
481 {0x00000077, 0xff010100},
482 {0x00000078, 0x00000000},
483 {0x00000079, 0x00001434},
484 {0x0000007a, 0xcc08ec08},
485 {0x0000007b, 0x00040000},
486 {0x0000007c, 0x000080c0},
487 {0x0000007d, 0x09000000},
488 {0x0000007e, 0x00210404},
489 {0x00000081, 0x08a8e800},
490 {0x00000082, 0x00030444},
491 {0x00000083, 0x00000000},
492 {0x00000085, 0x00000001},
493 {0x00000086, 0x00000002},
494 {0x00000087, 0x48490000},
495 {0x00000088, 0x20244647},
496 {0x00000089, 0x00000005},
497 {0x0000008b, 0x66030000},
498 {0x0000008c, 0x00006603},
499 {0x0000008d, 0x00000100},
500 {0x0000008f, 0x00001c0a},
501 {0x00000090, 0xff000001},
502 {0x00000094, 0x00101101},
503 {0x00000095, 0x00000fff},
504 {0x00000096, 0x00116fff},
505 {0x00000097, 0x60010000},
506 {0x00000098, 0x10010000},
507 {0x00000099, 0x00006000},
508 {0x0000009a, 0x00001000},
509 {0x0000009f, 0x00946a00}
512 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
513 {0x00000077, 0xff010100},
514 {0x00000078, 0x00000000},
515 {0x00000079, 0x00001434},
516 {0x0000007a, 0xcc08ec08},
517 {0x0000007b, 0x00040000},
518 {0x0000007c, 0x000080c0},
519 {0x0000007d, 0x09000000},
520 {0x0000007e, 0x00210404},
521 {0x00000081, 0x08a8e800},
522 {0x00000082, 0x00030444},
523 {0x00000083, 0x00000000},
524 {0x00000085, 0x00000001},
525 {0x00000086, 0x00000002},
526 {0x00000087, 0x48490000},
527 {0x00000088, 0x20244647},
528 {0x00000089, 0x00000005},
529 {0x0000008b, 0x66030000},
530 {0x0000008c, 0x00006603},
531 {0x0000008d, 0x00000100},
532 {0x0000008f, 0x00001c0a},
533 {0x00000090, 0xff000001},
534 {0x00000094, 0x00101101},
535 {0x00000095, 0x00000fff},
536 {0x00000096, 0x00116fff},
537 {0x00000097, 0x60010000},
538 {0x00000098, 0x10010000},
539 {0x00000099, 0x00006000},
540 {0x0000009a, 0x00001000},
541 {0x0000009f, 0x00936a00}
544 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
545 {0x00000077, 0xff010100},
546 {0x00000078, 0x00000000},
547 {0x00000079, 0x00001434},
548 {0x0000007a, 0xcc08ec08},
549 {0x0000007b, 0x00040000},
550 {0x0000007c, 0x000080c0},
551 {0x0000007d, 0x09000000},
552 {0x0000007e, 0x00210404},
553 {0x00000081, 0x08a8e800},
554 {0x00000082, 0x00030444},
555 {0x00000083, 0x00000000},
556 {0x00000085, 0x00000001},
557 {0x00000086, 0x00000002},
558 {0x00000087, 0x48490000},
559 {0x00000088, 0x20244647},
560 {0x00000089, 0x00000005},
561 {0x0000008b, 0x66030000},
562 {0x0000008c, 0x00006603},
563 {0x0000008d, 0x00000100},
564 {0x0000008f, 0x00001c0a},
565 {0x00000090, 0xff000001},
566 {0x00000094, 0x00101101},
567 {0x00000095, 0x00000fff},
568 {0x00000096, 0x00116fff},
569 {0x00000097, 0x60010000},
570 {0x00000098, 0x10010000},
571 {0x00000099, 0x00006000},
572 {0x0000009a, 0x00001000},
573 {0x0000009f, 0x00916a00}
576 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
577 {0x00000077, 0xff010100},
578 {0x00000078, 0x00000000},
579 {0x00000079, 0x00001434},
580 {0x0000007a, 0xcc08ec08},
581 {0x0000007b, 0x00040000},
582 {0x0000007c, 0x000080c0},
583 {0x0000007d, 0x09000000},
584 {0x0000007e, 0x00210404},
585 {0x00000081, 0x08a8e800},
586 {0x00000082, 0x00030444},
587 {0x00000083, 0x00000000},
588 {0x00000085, 0x00000001},
589 {0x00000086, 0x00000002},
590 {0x00000087, 0x48490000},
591 {0x00000088, 0x20244647},
592 {0x00000089, 0x00000005},
593 {0x0000008b, 0x66030000},
594 {0x0000008c, 0x00006603},
595 {0x0000008d, 0x00000100},
596 {0x0000008f, 0x00001c0a},
597 {0x00000090, 0xff000001},
598 {0x00000094, 0x00101101},
599 {0x00000095, 0x00000fff},
600 {0x00000096, 0x00116fff},
601 {0x00000097, 0x60010000},
602 {0x00000098, 0x10010000},
603 {0x00000099, 0x00006000},
604 {0x0000009a, 0x00001000},
605 {0x0000009f, 0x00976b00}
608 int ni_mc_load_microcode(struct radeon_device *rdev)
610 const __be32 *fw_data;
611 u32 mem_type, running, blackout = 0;
613 int i, ucode_size, regs_size;
618 switch (rdev->family) {
620 io_mc_regs = (u32 *)&barts_io_mc_regs;
621 ucode_size = BTC_MC_UCODE_SIZE;
622 regs_size = BTC_IO_MC_REGS_SIZE;
625 io_mc_regs = (u32 *)&turks_io_mc_regs;
626 ucode_size = BTC_MC_UCODE_SIZE;
627 regs_size = BTC_IO_MC_REGS_SIZE;
631 io_mc_regs = (u32 *)&caicos_io_mc_regs;
632 ucode_size = BTC_MC_UCODE_SIZE;
633 regs_size = BTC_IO_MC_REGS_SIZE;
636 io_mc_regs = (u32 *)&cayman_io_mc_regs;
637 ucode_size = CAYMAN_MC_UCODE_SIZE;
638 regs_size = BTC_IO_MC_REGS_SIZE;
642 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
643 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
645 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
647 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
648 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
651 /* reset the engine and set to writable */
652 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
653 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
655 /* load mc io regs */
656 for (i = 0; i < regs_size; i++) {
657 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
658 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
660 /* load the MC ucode */
661 fw_data = (const __be32 *)rdev->mc_fw->data;
662 for (i = 0; i < ucode_size; i++)
663 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
665 /* put the engine back into the active state */
666 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
667 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
668 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
670 /* wait for training to complete */
671 for (i = 0; i < rdev->usec_timeout; i++) {
672 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
678 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
684 int ni_init_microcode(struct radeon_device *rdev)
686 const char *chip_name;
687 const char *rlc_chip_name;
688 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
689 size_t smc_req_size = 0;
695 switch (rdev->family) {
698 rlc_chip_name = "BTC";
699 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
700 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
701 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
702 mc_req_size = BTC_MC_UCODE_SIZE * 4;
703 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
707 rlc_chip_name = "BTC";
708 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
709 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
710 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
711 mc_req_size = BTC_MC_UCODE_SIZE * 4;
712 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
715 chip_name = "CAICOS";
716 rlc_chip_name = "BTC";
717 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
718 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
719 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
720 mc_req_size = BTC_MC_UCODE_SIZE * 4;
721 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
724 chip_name = "CAYMAN";
725 rlc_chip_name = "CAYMAN";
726 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
727 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
728 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
729 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
730 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4);
734 rlc_chip_name = "ARUBA";
735 /* pfp/me same size as CAYMAN */
736 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
737 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
738 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
744 DRM_INFO("Loading %s Microcode\n", chip_name);
746 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
747 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
750 if (rdev->pfp_fw->size != pfp_req_size) {
752 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
753 rdev->pfp_fw->size, fw_name);
758 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
759 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
762 if (rdev->me_fw->size != me_req_size) {
764 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
765 rdev->me_fw->size, fw_name);
769 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
770 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
773 if (rdev->rlc_fw->size != rlc_req_size) {
775 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
776 rdev->rlc_fw->size, fw_name);
780 /* no MC ucode on TN */
781 if (!(rdev->flags & RADEON_IS_IGP)) {
782 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
783 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
786 if (rdev->mc_fw->size != mc_req_size) {
788 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
789 rdev->mc_fw->size, fw_name);
794 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
795 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
796 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
799 "smc: error loading firmware \"%s\"\n",
801 release_firmware(rdev->smc_fw);
804 } else if (rdev->smc_fw->size != smc_req_size) {
806 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
807 rdev->mc_fw->size, fw_name);
816 "ni_cp: Failed to load firmware \"%s\"\n",
818 release_firmware(rdev->pfp_fw);
820 release_firmware(rdev->me_fw);
822 release_firmware(rdev->rlc_fw);
824 release_firmware(rdev->mc_fw);
830 int tn_get_temp(struct radeon_device *rdev)
832 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
833 int actual_temp = (temp / 8) - 49;
835 return actual_temp * 1000;
841 static void cayman_gpu_init(struct radeon_device *rdev)
843 u32 gb_addr_config = 0;
844 u32 mc_shared_chmap, mc_arb_ramcfg;
845 u32 cgts_tcc_disable;
848 u32 cgts_sm_ctrl_reg;
849 u32 hdp_host_path_cntl;
851 u32 disabled_rb_mask;
854 switch (rdev->family) {
856 rdev->config.cayman.max_shader_engines = 2;
857 rdev->config.cayman.max_pipes_per_simd = 4;
858 rdev->config.cayman.max_tile_pipes = 8;
859 rdev->config.cayman.max_simds_per_se = 12;
860 rdev->config.cayman.max_backends_per_se = 4;
861 rdev->config.cayman.max_texture_channel_caches = 8;
862 rdev->config.cayman.max_gprs = 256;
863 rdev->config.cayman.max_threads = 256;
864 rdev->config.cayman.max_gs_threads = 32;
865 rdev->config.cayman.max_stack_entries = 512;
866 rdev->config.cayman.sx_num_of_sets = 8;
867 rdev->config.cayman.sx_max_export_size = 256;
868 rdev->config.cayman.sx_max_export_pos_size = 64;
869 rdev->config.cayman.sx_max_export_smx_size = 192;
870 rdev->config.cayman.max_hw_contexts = 8;
871 rdev->config.cayman.sq_num_cf_insts = 2;
873 rdev->config.cayman.sc_prim_fifo_size = 0x100;
874 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
875 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
876 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
880 rdev->config.cayman.max_shader_engines = 1;
881 rdev->config.cayman.max_pipes_per_simd = 4;
882 rdev->config.cayman.max_tile_pipes = 2;
883 if ((rdev->pdev->device == 0x9900) ||
884 (rdev->pdev->device == 0x9901) ||
885 (rdev->pdev->device == 0x9905) ||
886 (rdev->pdev->device == 0x9906) ||
887 (rdev->pdev->device == 0x9907) ||
888 (rdev->pdev->device == 0x9908) ||
889 (rdev->pdev->device == 0x9909) ||
890 (rdev->pdev->device == 0x990B) ||
891 (rdev->pdev->device == 0x990C) ||
892 (rdev->pdev->device == 0x990F) ||
893 (rdev->pdev->device == 0x9910) ||
894 (rdev->pdev->device == 0x9917) ||
895 (rdev->pdev->device == 0x9999) ||
896 (rdev->pdev->device == 0x999C)) {
897 rdev->config.cayman.max_simds_per_se = 6;
898 rdev->config.cayman.max_backends_per_se = 2;
899 rdev->config.cayman.max_hw_contexts = 8;
900 rdev->config.cayman.sx_max_export_size = 256;
901 rdev->config.cayman.sx_max_export_pos_size = 64;
902 rdev->config.cayman.sx_max_export_smx_size = 192;
903 } else if ((rdev->pdev->device == 0x9903) ||
904 (rdev->pdev->device == 0x9904) ||
905 (rdev->pdev->device == 0x990A) ||
906 (rdev->pdev->device == 0x990D) ||
907 (rdev->pdev->device == 0x990E) ||
908 (rdev->pdev->device == 0x9913) ||
909 (rdev->pdev->device == 0x9918) ||
910 (rdev->pdev->device == 0x999D)) {
911 rdev->config.cayman.max_simds_per_se = 4;
912 rdev->config.cayman.max_backends_per_se = 2;
913 rdev->config.cayman.max_hw_contexts = 8;
914 rdev->config.cayman.sx_max_export_size = 256;
915 rdev->config.cayman.sx_max_export_pos_size = 64;
916 rdev->config.cayman.sx_max_export_smx_size = 192;
917 } else if ((rdev->pdev->device == 0x9919) ||
918 (rdev->pdev->device == 0x9990) ||
919 (rdev->pdev->device == 0x9991) ||
920 (rdev->pdev->device == 0x9994) ||
921 (rdev->pdev->device == 0x9995) ||
922 (rdev->pdev->device == 0x9996) ||
923 (rdev->pdev->device == 0x999A) ||
924 (rdev->pdev->device == 0x99A0)) {
925 rdev->config.cayman.max_simds_per_se = 3;
926 rdev->config.cayman.max_backends_per_se = 1;
927 rdev->config.cayman.max_hw_contexts = 4;
928 rdev->config.cayman.sx_max_export_size = 128;
929 rdev->config.cayman.sx_max_export_pos_size = 32;
930 rdev->config.cayman.sx_max_export_smx_size = 96;
932 rdev->config.cayman.max_simds_per_se = 2;
933 rdev->config.cayman.max_backends_per_se = 1;
934 rdev->config.cayman.max_hw_contexts = 4;
935 rdev->config.cayman.sx_max_export_size = 128;
936 rdev->config.cayman.sx_max_export_pos_size = 32;
937 rdev->config.cayman.sx_max_export_smx_size = 96;
939 rdev->config.cayman.max_texture_channel_caches = 2;
940 rdev->config.cayman.max_gprs = 256;
941 rdev->config.cayman.max_threads = 256;
942 rdev->config.cayman.max_gs_threads = 32;
943 rdev->config.cayman.max_stack_entries = 512;
944 rdev->config.cayman.sx_num_of_sets = 8;
945 rdev->config.cayman.sq_num_cf_insts = 2;
947 rdev->config.cayman.sc_prim_fifo_size = 0x40;
948 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
949 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
950 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
955 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
956 WREG32((0x2c14 + j), 0x00000000);
957 WREG32((0x2c18 + j), 0x00000000);
958 WREG32((0x2c1c + j), 0x00000000);
959 WREG32((0x2c20 + j), 0x00000000);
960 WREG32((0x2c24 + j), 0x00000000);
963 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
965 evergreen_fix_pci_max_read_req_size(rdev);
967 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
968 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
970 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
971 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
972 if (rdev->config.cayman.mem_row_size_in_kb > 4)
973 rdev->config.cayman.mem_row_size_in_kb = 4;
974 /* XXX use MC settings? */
975 rdev->config.cayman.shader_engine_tile_size = 32;
976 rdev->config.cayman.num_gpus = 1;
977 rdev->config.cayman.multi_gpu_tile_size = 64;
979 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
980 rdev->config.cayman.num_tile_pipes = (1 << tmp);
981 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
982 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
983 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
984 rdev->config.cayman.num_shader_engines = tmp + 1;
985 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
986 rdev->config.cayman.num_gpus = tmp + 1;
987 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
988 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
989 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
990 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
993 /* setup tiling info dword. gb_addr_config is not adequate since it does
994 * not have bank info, so create a custom tiling dword.
997 * bits 11:8 group_size
998 * bits 15:12 row_size
1000 rdev->config.cayman.tile_config = 0;
1001 switch (rdev->config.cayman.num_tile_pipes) {
1004 rdev->config.cayman.tile_config |= (0 << 0);
1007 rdev->config.cayman.tile_config |= (1 << 0);
1010 rdev->config.cayman.tile_config |= (2 << 0);
1013 rdev->config.cayman.tile_config |= (3 << 0);
1017 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1018 if (rdev->flags & RADEON_IS_IGP)
1019 rdev->config.cayman.tile_config |= 1 << 4;
1021 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1022 case 0: /* four banks */
1023 rdev->config.cayman.tile_config |= 0 << 4;
1025 case 1: /* eight banks */
1026 rdev->config.cayman.tile_config |= 1 << 4;
1028 case 2: /* sixteen banks */
1030 rdev->config.cayman.tile_config |= 2 << 4;
1034 rdev->config.cayman.tile_config |=
1035 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1036 rdev->config.cayman.tile_config |=
1037 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1040 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
1041 u32 rb_disable_bitmap;
1043 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1044 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1045 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1047 tmp |= rb_disable_bitmap;
1049 /* enabled rb are just the one not disabled :) */
1050 disabled_rb_mask = tmp;
1052 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1054 /* if all the backends are disabled, fix it up here */
1055 if ((disabled_rb_mask & tmp) == tmp) {
1056 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1057 disabled_rb_mask &= ~(1 << i);
1060 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1061 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1063 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1064 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1065 if (ASIC_IS_DCE6(rdev))
1066 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1067 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1068 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1069 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1070 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1071 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1072 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1074 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1075 (rdev->flags & RADEON_IS_IGP)) {
1076 if ((disabled_rb_mask & 3) == 1) {
1077 /* RB0 disabled, RB1 enabled */
1080 /* RB1 disabled, RB0 enabled */
1084 tmp = gb_addr_config & NUM_PIPES_MASK;
1085 tmp = r6xx_remap_render_backend(rdev, tmp,
1086 rdev->config.cayman.max_backends_per_se *
1087 rdev->config.cayman.max_shader_engines,
1088 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
1090 WREG32(GB_BACKEND_MAP, tmp);
1092 cgts_tcc_disable = 0xffff0000;
1093 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
1094 cgts_tcc_disable &= ~(1 << (16 + i));
1095 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1096 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
1097 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
1098 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1100 /* reprogram the shader complex */
1101 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
1102 for (i = 0; i < 16; i++)
1103 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
1104 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
1106 /* set HW defaults for 3D engine */
1107 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1109 sx_debug_1 = RREG32(SX_DEBUG_1);
1110 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1111 WREG32(SX_DEBUG_1, sx_debug_1);
1113 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1114 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1115 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
1116 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1118 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
1120 /* need to be explicitly zero-ed */
1121 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
1122 WREG32(SQ_LSTMP_RING_BASE, 0);
1123 WREG32(SQ_HSTMP_RING_BASE, 0);
1124 WREG32(SQ_ESTMP_RING_BASE, 0);
1125 WREG32(SQ_GSTMP_RING_BASE, 0);
1126 WREG32(SQ_VSTMP_RING_BASE, 0);
1127 WREG32(SQ_PSTMP_RING_BASE, 0);
1129 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
1131 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
1132 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
1133 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
1135 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
1136 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
1137 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
1140 WREG32(VGT_NUM_INSTANCES, 1);
1142 WREG32(CP_PERFMON_CNTL, 0);
1144 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
1145 FETCH_FIFO_HIWATER(0x4) |
1146 DONE_FIFO_HIWATER(0xe0) |
1147 ALU_UPDATE_FIFO_HIWATER(0x8)));
1149 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
1150 WREG32(SQ_CONFIG, (VC_ENABLE |
1155 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1157 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1158 FORCE_EOV_MAX_REZ_CNT(255)));
1160 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1161 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1163 WREG32(VGT_GS_VERTEX_REUSE, 16);
1164 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1166 WREG32(CB_PERF_CTR0_SEL_0, 0);
1167 WREG32(CB_PERF_CTR0_SEL_1, 0);
1168 WREG32(CB_PERF_CTR1_SEL_0, 0);
1169 WREG32(CB_PERF_CTR1_SEL_1, 0);
1170 WREG32(CB_PERF_CTR2_SEL_0, 0);
1171 WREG32(CB_PERF_CTR2_SEL_1, 0);
1172 WREG32(CB_PERF_CTR3_SEL_0, 0);
1173 WREG32(CB_PERF_CTR3_SEL_1, 0);
1175 tmp = RREG32(HDP_MISC_CNTL);
1176 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1177 WREG32(HDP_MISC_CNTL, tmp);
1179 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1180 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1182 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1186 /* set clockgating golden values on TN */
1187 if (rdev->family == CHIP_ARUBA) {
1188 tmp = RREG32_CG(CG_CGTT_LOCAL_0);
1190 WREG32_CG(CG_CGTT_LOCAL_0, tmp);
1191 tmp = RREG32_CG(CG_CGTT_LOCAL_1);
1193 WREG32_CG(CG_CGTT_LOCAL_1, tmp);
1200 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1202 /* flush hdp cache */
1203 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1205 /* bits 0-7 are the VM contexts0-7 */
1206 WREG32(VM_INVALIDATE_REQUEST, 1);
1209 static int cayman_pcie_gart_enable(struct radeon_device *rdev)
1213 if (rdev->gart.robj == NULL) {
1214 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1217 r = radeon_gart_table_vram_pin(rdev);
1220 radeon_gart_restore(rdev);
1221 /* Setup TLB control */
1222 WREG32(MC_VM_MX_L1_TLB_CNTL,
1225 ENABLE_L1_FRAGMENT_PROCESSING |
1226 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1227 ENABLE_ADVANCED_DRIVER_MODEL |
1228 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1229 /* Setup L2 cache */
1230 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1231 ENABLE_L2_FRAGMENT_PROCESSING |
1232 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1233 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1234 EFFECTIVE_L2_QUEUE_SIZE(7) |
1235 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1236 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1237 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1239 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1240 /* setup context0 */
1241 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1242 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1243 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1244 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1245 (u32)(rdev->dummy_page.addr >> 12));
1246 WREG32(VM_CONTEXT0_CNTL2, 0);
1247 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1248 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1254 /* empty context1-7 */
1255 /* Assign the pt base to something valid for now; the pts used for
1256 * the VMs are determined by the application and setup and assigned
1257 * on the fly in the vm part of radeon_gart.c
1259 for (i = 1; i < 8; i++) {
1260 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1261 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), rdev->vm_manager.max_pfn);
1262 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1263 rdev->gart.table_addr >> 12);
1266 /* enable context1-7 */
1267 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1268 (u32)(rdev->dummy_page.addr >> 12));
1269 WREG32(VM_CONTEXT1_CNTL2, 4);
1270 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
1271 PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) |
1272 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1273 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1274 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1275 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1276 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
1277 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
1278 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
1279 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
1280 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
1281 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
1282 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1283 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
1285 cayman_pcie_gart_tlb_flush(rdev);
1286 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1287 (unsigned)(rdev->mc.gtt_size >> 20),
1288 (unsigned long long)rdev->gart.table_addr);
1289 rdev->gart.ready = true;
1293 static void cayman_pcie_gart_disable(struct radeon_device *rdev)
1295 /* Disable all tables */
1296 WREG32(VM_CONTEXT0_CNTL, 0);
1297 WREG32(VM_CONTEXT1_CNTL, 0);
1298 /* Setup TLB control */
1299 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1300 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1301 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1302 /* Setup L2 cache */
1303 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1304 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1305 EFFECTIVE_L2_QUEUE_SIZE(7) |
1306 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1307 WREG32(VM_L2_CNTL2, 0);
1308 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1309 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1310 radeon_gart_table_vram_unpin(rdev);
1313 static void cayman_pcie_gart_fini(struct radeon_device *rdev)
1315 cayman_pcie_gart_disable(rdev);
1316 radeon_gart_table_vram_free(rdev);
1317 radeon_gart_fini(rdev);
1320 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1321 int ring, u32 cp_int_cntl)
1323 u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1325 WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
1326 WREG32(CP_INT_CNTL, cp_int_cntl);
1332 void cayman_fence_ring_emit(struct radeon_device *rdev,
1333 struct radeon_fence *fence)
1335 struct radeon_ring *ring = &rdev->ring[fence->ring];
1336 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1337 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1338 PACKET3_SH_ACTION_ENA;
1340 /* flush read cache over gart for this vmid */
1341 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1342 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1343 radeon_ring_write(ring, 0xFFFFFFFF);
1344 radeon_ring_write(ring, 0);
1345 radeon_ring_write(ring, 10); /* poll interval */
1346 /* EVENT_WRITE_EOP - flush caches, send int */
1347 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1348 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1349 radeon_ring_write(ring, addr & 0xffffffff);
1350 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1351 radeon_ring_write(ring, fence->seq);
1352 radeon_ring_write(ring, 0);
1355 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1357 struct radeon_ring *ring = &rdev->ring[ib->ring];
1358 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1359 PACKET3_SH_ACTION_ENA;
1361 /* set to DX10/11 mode */
1362 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1363 radeon_ring_write(ring, 1);
1365 if (ring->rptr_save_reg) {
1366 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1367 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1368 radeon_ring_write(ring, ((ring->rptr_save_reg -
1369 PACKET3_SET_CONFIG_REG_START) >> 2));
1370 radeon_ring_write(ring, next_rptr);
1373 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1374 radeon_ring_write(ring,
1378 (ib->gpu_addr & 0xFFFFFFFC));
1379 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1380 radeon_ring_write(ring, ib->length_dw |
1381 (ib->vm ? (ib->vm->id << 24) : 0));
1383 /* flush read cache over gart for this vmid */
1384 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1385 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1386 radeon_ring_write(ring, 0xFFFFFFFF);
1387 radeon_ring_write(ring, 0);
1388 radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */
1391 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1394 WREG32(CP_ME_CNTL, 0);
1396 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1397 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1398 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1399 WREG32(SCRATCH_UMSK, 0);
1400 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1404 u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
1405 struct radeon_ring *ring)
1409 if (rdev->wb.enabled)
1410 rptr = rdev->wb.wb[ring->rptr_offs/4];
1412 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1413 rptr = RREG32(CP_RB0_RPTR);
1414 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1415 rptr = RREG32(CP_RB1_RPTR);
1417 rptr = RREG32(CP_RB2_RPTR);
1423 u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
1424 struct radeon_ring *ring)
1428 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1429 wptr = RREG32(CP_RB0_WPTR);
1430 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1431 wptr = RREG32(CP_RB1_WPTR);
1433 wptr = RREG32(CP_RB2_WPTR);
1438 void cayman_gfx_set_wptr(struct radeon_device *rdev,
1439 struct radeon_ring *ring)
1441 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
1442 WREG32(CP_RB0_WPTR, ring->wptr);
1443 (void)RREG32(CP_RB0_WPTR);
1444 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) {
1445 WREG32(CP_RB1_WPTR, ring->wptr);
1446 (void)RREG32(CP_RB1_WPTR);
1448 WREG32(CP_RB2_WPTR, ring->wptr);
1449 (void)RREG32(CP_RB2_WPTR);
1453 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1455 const __be32 *fw_data;
1458 if (!rdev->me_fw || !rdev->pfp_fw)
1461 cayman_cp_enable(rdev, false);
1463 fw_data = (const __be32 *)rdev->pfp_fw->data;
1464 WREG32(CP_PFP_UCODE_ADDR, 0);
1465 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1466 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1467 WREG32(CP_PFP_UCODE_ADDR, 0);
1469 fw_data = (const __be32 *)rdev->me_fw->data;
1470 WREG32(CP_ME_RAM_WADDR, 0);
1471 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1472 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1474 WREG32(CP_PFP_UCODE_ADDR, 0);
1475 WREG32(CP_ME_RAM_WADDR, 0);
1476 WREG32(CP_ME_RAM_RADDR, 0);
1480 static int cayman_cp_start(struct radeon_device *rdev)
1482 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1485 r = radeon_ring_lock(rdev, ring, 7);
1487 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1490 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1491 radeon_ring_write(ring, 0x1);
1492 radeon_ring_write(ring, 0x0);
1493 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1494 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1495 radeon_ring_write(ring, 0);
1496 radeon_ring_write(ring, 0);
1497 radeon_ring_unlock_commit(rdev, ring);
1499 cayman_cp_enable(rdev, true);
1501 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1503 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1507 /* setup clear context state */
1508 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1509 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1511 for (i = 0; i < cayman_default_size; i++)
1512 radeon_ring_write(ring, cayman_default_state[i]);
1514 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1515 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1517 /* set clear context state */
1518 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1519 radeon_ring_write(ring, 0);
1521 /* SQ_VTX_BASE_VTX_LOC */
1522 radeon_ring_write(ring, 0xc0026f00);
1523 radeon_ring_write(ring, 0x00000000);
1524 radeon_ring_write(ring, 0x00000000);
1525 radeon_ring_write(ring, 0x00000000);
1528 radeon_ring_write(ring, 0xc0036f00);
1529 radeon_ring_write(ring, 0x00000bc4);
1530 radeon_ring_write(ring, 0xffffffff);
1531 radeon_ring_write(ring, 0xffffffff);
1532 radeon_ring_write(ring, 0xffffffff);
1534 radeon_ring_write(ring, 0xc0026900);
1535 radeon_ring_write(ring, 0x00000316);
1536 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1537 radeon_ring_write(ring, 0x00000010); /* */
1539 radeon_ring_unlock_commit(rdev, ring);
1541 /* XXX init other rings */
1546 static void cayman_cp_fini(struct radeon_device *rdev)
1548 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1549 cayman_cp_enable(rdev, false);
1550 radeon_ring_fini(rdev, ring);
1551 radeon_scratch_free(rdev, ring->rptr_save_reg);
1554 static int cayman_cp_resume(struct radeon_device *rdev)
1556 static const int ridx[] = {
1557 RADEON_RING_TYPE_GFX_INDEX,
1558 CAYMAN_RING_TYPE_CP1_INDEX,
1559 CAYMAN_RING_TYPE_CP2_INDEX
1561 static const unsigned cp_rb_cntl[] = {
1566 static const unsigned cp_rb_rptr_addr[] = {
1571 static const unsigned cp_rb_rptr_addr_hi[] = {
1572 CP_RB0_RPTR_ADDR_HI,
1573 CP_RB1_RPTR_ADDR_HI,
1576 static const unsigned cp_rb_base[] = {
1581 static const unsigned cp_rb_rptr[] = {
1586 static const unsigned cp_rb_wptr[] = {
1591 struct radeon_ring *ring;
1594 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1595 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1601 RREG32(GRBM_SOFT_RESET);
1603 WREG32(GRBM_SOFT_RESET, 0);
1604 RREG32(GRBM_SOFT_RESET);
1606 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1607 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1609 /* Set the write pointer delay */
1610 WREG32(CP_RB_WPTR_DELAY, 0);
1612 WREG32(CP_DEBUG, (1 << 27));
1614 /* set the wb address whether it's enabled or not */
1615 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1616 WREG32(SCRATCH_UMSK, 0xff);
1618 for (i = 0; i < 3; ++i) {
1622 /* Set ring buffer size */
1623 ring = &rdev->ring[ridx[i]];
1624 rb_cntl = order_base_2(ring->ring_size / 8);
1625 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
1627 rb_cntl |= BUF_SWAP_32BIT;
1629 WREG32(cp_rb_cntl[i], rb_cntl);
1631 /* set the wb address whether it's enabled or not */
1632 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1633 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1634 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1637 /* set the rb base addr, this causes an internal reset of ALL rings */
1638 for (i = 0; i < 3; ++i) {
1639 ring = &rdev->ring[ridx[i]];
1640 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1643 for (i = 0; i < 3; ++i) {
1644 /* Initialize the ring buffer's read and write pointers */
1645 ring = &rdev->ring[ridx[i]];
1646 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1649 WREG32(cp_rb_rptr[i], 0);
1650 WREG32(cp_rb_wptr[i], ring->wptr);
1653 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1656 /* start the rings */
1657 cayman_cp_start(rdev);
1658 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1659 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1660 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1661 /* this only test cp0 */
1662 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1664 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1665 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1666 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1670 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1671 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1676 u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1682 tmp = RREG32(GRBM_STATUS);
1683 if (tmp & (PA_BUSY | SC_BUSY |
1685 TA_BUSY | VGT_BUSY |
1687 GDS_BUSY | SPI_BUSY |
1688 IA_BUSY | IA_BUSY_NO_DMA))
1689 reset_mask |= RADEON_RESET_GFX;
1691 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1692 CP_BUSY | CP_COHERENCY_BUSY))
1693 reset_mask |= RADEON_RESET_CP;
1695 if (tmp & GRBM_EE_BUSY)
1696 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1698 /* DMA_STATUS_REG 0 */
1699 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1700 if (!(tmp & DMA_IDLE))
1701 reset_mask |= RADEON_RESET_DMA;
1703 /* DMA_STATUS_REG 1 */
1704 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1705 if (!(tmp & DMA_IDLE))
1706 reset_mask |= RADEON_RESET_DMA1;
1709 tmp = RREG32(SRBM_STATUS2);
1711 reset_mask |= RADEON_RESET_DMA;
1713 if (tmp & DMA1_BUSY)
1714 reset_mask |= RADEON_RESET_DMA1;
1717 tmp = RREG32(SRBM_STATUS);
1718 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1719 reset_mask |= RADEON_RESET_RLC;
1722 reset_mask |= RADEON_RESET_IH;
1725 reset_mask |= RADEON_RESET_SEM;
1727 if (tmp & GRBM_RQ_PENDING)
1728 reset_mask |= RADEON_RESET_GRBM;
1731 reset_mask |= RADEON_RESET_VMC;
1733 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1734 MCC_BUSY | MCD_BUSY))
1735 reset_mask |= RADEON_RESET_MC;
1737 if (evergreen_is_display_hung(rdev))
1738 reset_mask |= RADEON_RESET_DISPLAY;
1741 tmp = RREG32(VM_L2_STATUS);
1743 reset_mask |= RADEON_RESET_VMC;
1745 /* Skip MC reset as it's mostly likely not hung, just busy */
1746 if (reset_mask & RADEON_RESET_MC) {
1747 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1748 reset_mask &= ~RADEON_RESET_MC;
1754 static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1756 struct evergreen_mc_save save;
1757 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1760 if (reset_mask == 0)
1763 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1765 evergreen_print_gpu_status_regs(rdev);
1766 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1768 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1770 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1772 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1775 /* Disable CP parsing/prefetching */
1776 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1778 if (reset_mask & RADEON_RESET_DMA) {
1780 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1781 tmp &= ~DMA_RB_ENABLE;
1782 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1785 if (reset_mask & RADEON_RESET_DMA1) {
1787 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1788 tmp &= ~DMA_RB_ENABLE;
1789 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1794 evergreen_mc_stop(rdev, &save);
1795 if (evergreen_mc_wait_for_idle(rdev)) {
1796 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1799 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1800 grbm_soft_reset = SOFT_RESET_CB |
1814 if (reset_mask & RADEON_RESET_CP) {
1815 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1817 srbm_soft_reset |= SOFT_RESET_GRBM;
1820 if (reset_mask & RADEON_RESET_DMA)
1821 srbm_soft_reset |= SOFT_RESET_DMA;
1823 if (reset_mask & RADEON_RESET_DMA1)
1824 srbm_soft_reset |= SOFT_RESET_DMA1;
1826 if (reset_mask & RADEON_RESET_DISPLAY)
1827 srbm_soft_reset |= SOFT_RESET_DC;
1829 if (reset_mask & RADEON_RESET_RLC)
1830 srbm_soft_reset |= SOFT_RESET_RLC;
1832 if (reset_mask & RADEON_RESET_SEM)
1833 srbm_soft_reset |= SOFT_RESET_SEM;
1835 if (reset_mask & RADEON_RESET_IH)
1836 srbm_soft_reset |= SOFT_RESET_IH;
1838 if (reset_mask & RADEON_RESET_GRBM)
1839 srbm_soft_reset |= SOFT_RESET_GRBM;
1841 if (reset_mask & RADEON_RESET_VMC)
1842 srbm_soft_reset |= SOFT_RESET_VMC;
1844 if (!(rdev->flags & RADEON_IS_IGP)) {
1845 if (reset_mask & RADEON_RESET_MC)
1846 srbm_soft_reset |= SOFT_RESET_MC;
1849 if (grbm_soft_reset) {
1850 tmp = RREG32(GRBM_SOFT_RESET);
1851 tmp |= grbm_soft_reset;
1852 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1853 WREG32(GRBM_SOFT_RESET, tmp);
1854 tmp = RREG32(GRBM_SOFT_RESET);
1858 tmp &= ~grbm_soft_reset;
1859 WREG32(GRBM_SOFT_RESET, tmp);
1860 tmp = RREG32(GRBM_SOFT_RESET);
1863 if (srbm_soft_reset) {
1864 tmp = RREG32(SRBM_SOFT_RESET);
1865 tmp |= srbm_soft_reset;
1866 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1867 WREG32(SRBM_SOFT_RESET, tmp);
1868 tmp = RREG32(SRBM_SOFT_RESET);
1872 tmp &= ~srbm_soft_reset;
1873 WREG32(SRBM_SOFT_RESET, tmp);
1874 tmp = RREG32(SRBM_SOFT_RESET);
1877 /* Wait a little for things to settle down */
1880 evergreen_mc_resume(rdev, &save);
1883 evergreen_print_gpu_status_regs(rdev);
1886 int cayman_asic_reset(struct radeon_device *rdev)
1890 reset_mask = cayman_gpu_check_soft_reset(rdev);
1893 r600_set_bios_scratch_engine_hung(rdev, true);
1895 cayman_gpu_soft_reset(rdev, reset_mask);
1897 reset_mask = cayman_gpu_check_soft_reset(rdev);
1900 evergreen_gpu_pci_config_reset(rdev);
1902 r600_set_bios_scratch_engine_hung(rdev, false);
1908 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1910 * @rdev: radeon_device pointer
1911 * @ring: radeon_ring structure holding ring information
1913 * Check if the GFX engine is locked up.
1914 * Returns true if the engine appears to be locked up, false if not.
1916 bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1918 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1920 if (!(reset_mask & (RADEON_RESET_GFX |
1921 RADEON_RESET_COMPUTE |
1922 RADEON_RESET_CP))) {
1923 radeon_ring_lockup_update(rdev, ring);
1926 return radeon_ring_test_lockup(rdev, ring);
1929 static int cayman_startup(struct radeon_device *rdev)
1931 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1934 /* enable pcie gen2 link */
1935 evergreen_pcie_gen2_enable(rdev);
1937 evergreen_program_aspm(rdev);
1939 /* scratch needs to be initialized before MC */
1940 r = r600_vram_scratch_init(rdev);
1944 evergreen_mc_program(rdev);
1946 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
1947 r = ni_mc_load_microcode(rdev);
1949 DRM_ERROR("Failed to load MC firmware!\n");
1954 r = cayman_pcie_gart_enable(rdev);
1957 cayman_gpu_init(rdev);
1959 /* allocate rlc buffers */
1960 if (rdev->flags & RADEON_IS_IGP) {
1961 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
1962 rdev->rlc.reg_list_size =
1963 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);
1964 rdev->rlc.cs_data = cayman_cs_data;
1965 r = sumo_rlc_init(rdev);
1967 DRM_ERROR("Failed to init rlc BOs!\n");
1972 /* allocate wb buffer */
1973 r = radeon_wb_init(rdev);
1977 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1979 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1983 r = uvd_v2_2_resume(rdev);
1985 r = radeon_fence_driver_start_ring(rdev,
1986 R600_RING_TYPE_UVD_INDEX);
1988 dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1991 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1993 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1995 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1999 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
2001 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2005 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2007 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2011 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
2013 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2018 if (!rdev->irq.installed) {
2019 r = radeon_irq_kms_init(rdev);
2024 r = r600_irq_init(rdev);
2026 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2027 radeon_irq_kms_fini(rdev);
2030 evergreen_irq_set(rdev);
2032 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2037 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2038 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2039 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2043 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2044 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
2045 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2049 r = cayman_cp_load_microcode(rdev);
2052 r = cayman_cp_resume(rdev);
2056 r = cayman_dma_resume(rdev);
2060 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2061 if (ring->ring_size) {
2062 r = radeon_ring_init(rdev, ring, ring->ring_size, 0,
2065 r = uvd_v1_0_init(rdev);
2067 DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
2070 r = radeon_ib_pool_init(rdev);
2072 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2076 r = radeon_vm_manager_init(rdev);
2078 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
2082 if (ASIC_IS_DCE6(rdev)) {
2083 r = dce6_audio_init(rdev);
2087 r = r600_audio_init(rdev);
2095 int cayman_resume(struct radeon_device *rdev)
2099 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2100 * posting will perform necessary task to bring back GPU into good
2104 atom_asic_init(rdev->mode_info.atom_context);
2106 /* init golden registers */
2107 ni_init_golden_registers(rdev);
2109 if (rdev->pm.pm_method == PM_METHOD_DPM)
2110 radeon_pm_resume(rdev);
2112 rdev->accel_working = true;
2113 r = cayman_startup(rdev);
2115 DRM_ERROR("cayman startup failed on resume\n");
2116 rdev->accel_working = false;
2122 int cayman_suspend(struct radeon_device *rdev)
2124 radeon_pm_suspend(rdev);
2125 if (ASIC_IS_DCE6(rdev))
2126 dce6_audio_fini(rdev);
2128 r600_audio_fini(rdev);
2129 radeon_vm_manager_fini(rdev);
2130 cayman_cp_enable(rdev, false);
2131 cayman_dma_stop(rdev);
2132 uvd_v1_0_fini(rdev);
2133 radeon_uvd_suspend(rdev);
2134 evergreen_irq_suspend(rdev);
2135 radeon_wb_disable(rdev);
2136 cayman_pcie_gart_disable(rdev);
2140 /* Plan is to move initialization in that function and use
2141 * helper function so that radeon_device_init pretty much
2142 * do nothing more than calling asic specific function. This
2143 * should also allow to remove a bunch of callback function
2146 int cayman_init(struct radeon_device *rdev)
2148 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2152 if (!radeon_get_bios(rdev)) {
2153 if (ASIC_IS_AVIVO(rdev))
2156 /* Must be an ATOMBIOS */
2157 if (!rdev->is_atom_bios) {
2158 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
2161 r = radeon_atombios_init(rdev);
2165 /* Post card if necessary */
2166 if (!radeon_card_posted(rdev)) {
2168 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2171 DRM_INFO("GPU not posted. posting now...\n");
2172 atom_asic_init(rdev->mode_info.atom_context);
2174 /* init golden registers */
2175 ni_init_golden_registers(rdev);
2176 /* Initialize scratch registers */
2177 r600_scratch_init(rdev);
2178 /* Initialize surface registers */
2179 radeon_surface_init(rdev);
2180 /* Initialize clocks */
2181 radeon_get_clock_info(rdev->ddev);
2183 r = radeon_fence_driver_init(rdev);
2186 /* initialize memory controller */
2187 r = evergreen_mc_init(rdev);
2190 /* Memory manager */
2191 r = radeon_bo_init(rdev);
2195 if (rdev->flags & RADEON_IS_IGP) {
2196 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2197 r = ni_init_microcode(rdev);
2199 DRM_ERROR("Failed to load firmware!\n");
2204 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2205 r = ni_init_microcode(rdev);
2207 DRM_ERROR("Failed to load firmware!\n");
2213 /* Initialize power management */
2214 radeon_pm_init(rdev);
2216 ring->ring_obj = NULL;
2217 r600_ring_init(rdev, ring, 1024 * 1024);
2219 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2220 ring->ring_obj = NULL;
2221 r600_ring_init(rdev, ring, 64 * 1024);
2223 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2224 ring->ring_obj = NULL;
2225 r600_ring_init(rdev, ring, 64 * 1024);
2227 r = radeon_uvd_init(rdev);
2229 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2230 ring->ring_obj = NULL;
2231 r600_ring_init(rdev, ring, 4096);
2234 rdev->ih.ring_obj = NULL;
2235 r600_ih_ring_init(rdev, 64 * 1024);
2237 r = r600_pcie_gart_init(rdev);
2241 rdev->accel_working = true;
2242 r = cayman_startup(rdev);
2244 dev_err(rdev->dev, "disabling GPU acceleration\n");
2245 cayman_cp_fini(rdev);
2246 cayman_dma_fini(rdev);
2247 r600_irq_fini(rdev);
2248 if (rdev->flags & RADEON_IS_IGP)
2249 sumo_rlc_fini(rdev);
2250 radeon_wb_fini(rdev);
2251 radeon_ib_pool_fini(rdev);
2252 radeon_vm_manager_fini(rdev);
2253 radeon_irq_kms_fini(rdev);
2254 cayman_pcie_gart_fini(rdev);
2255 rdev->accel_working = false;
2258 /* Don't start up if the MC ucode is missing.
2259 * The default clocks and voltages before the MC ucode
2260 * is loaded are not suffient for advanced operations.
2262 * We can skip this check for TN, because there is no MC
2265 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
2266 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2273 void cayman_fini(struct radeon_device *rdev)
2275 radeon_pm_fini(rdev);
2276 cayman_cp_fini(rdev);
2277 cayman_dma_fini(rdev);
2278 r600_irq_fini(rdev);
2279 if (rdev->flags & RADEON_IS_IGP)
2280 sumo_rlc_fini(rdev);
2281 radeon_wb_fini(rdev);
2282 radeon_vm_manager_fini(rdev);
2283 radeon_ib_pool_fini(rdev);
2284 radeon_irq_kms_fini(rdev);
2285 uvd_v1_0_fini(rdev);
2286 radeon_uvd_fini(rdev);
2287 cayman_pcie_gart_fini(rdev);
2288 r600_vram_scratch_fini(rdev);
2289 radeon_gem_fini(rdev);
2290 radeon_fence_driver_fini(rdev);
2291 radeon_bo_fini(rdev);
2292 radeon_atombios_fini(rdev);
2300 int cayman_vm_init(struct radeon_device *rdev)
2303 rdev->vm_manager.nvm = 8;
2304 /* base offset of vram pages */
2305 if (rdev->flags & RADEON_IS_IGP) {
2306 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2308 rdev->vm_manager.vram_base_offset = tmp;
2310 rdev->vm_manager.vram_base_offset = 0;
2314 void cayman_vm_fini(struct radeon_device *rdev)
2319 * cayman_vm_decode_fault - print human readable fault info
2321 * @rdev: radeon_device pointer
2322 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2323 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2325 * Print human readable fault information (cayman/TN).
2327 void cayman_vm_decode_fault(struct radeon_device *rdev,
2328 u32 status, u32 addr)
2330 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
2331 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
2332 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
2424 block = "TC_TFETCH";
2434 block = "TC_VFETCH";
2473 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2474 protections, vmid, addr,
2475 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
2480 * cayman_vm_flush - vm flush using the CP
2482 * @rdev: radeon_device pointer
2484 * Update the page table base and flush the VM TLB
2485 * using the CP (cayman-si).
2487 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
2489 struct radeon_ring *ring = &rdev->ring[ridx];
2494 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0));
2495 radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
2497 /* flush hdp cache */
2498 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2499 radeon_ring_write(ring, 0x1);
2501 /* bits 0-7 are the VM contexts0-7 */
2502 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
2503 radeon_ring_write(ring, 1 << vm->id);
2505 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2506 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2507 radeon_ring_write(ring, 0x0);