drivers/gpu/drm/radeon/ni.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "radeon_drm.h"
  32 #include "nid.h"
  33 #include "atom.h"
  34 #include "ni_reg.h"
  35 #include "cayman_blit_shaders.h"
  36
  37 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  38 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  39 extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
  40 extern void evergreen_mc_program(struct radeon_device *rdev);
  41 extern void evergreen_irq_suspend(struct radeon_device *rdev);
  42 extern int evergreen_mc_init(struct radeon_device *rdev);
  43 extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
  44 extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
  45
  46 #define EVERGREEN_PFP_UCODE_SIZE 1120
  47 #define EVERGREEN_PM4_UCODE_SIZE 1376
  48 #define EVERGREEN_RLC_UCODE_SIZE 768
  49 #define BTC_MC_UCODE_SIZE 6024
  50
  51 #define CAYMAN_PFP_UCODE_SIZE 2176
  52 #define CAYMAN_PM4_UCODE_SIZE 2176
  53 #define CAYMAN_RLC_UCODE_SIZE 1024
  54 #define CAYMAN_MC_UCODE_SIZE 6037
  55
  56 /* Firmware Names */
  57 MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
  58 MODULE_FIRMWARE("radeon/BARTS_me.bin");
  59 MODULE_FIRMWARE("radeon/BARTS_mc.bin");
  60 MODULE_FIRMWARE("radeon/BTC_rlc.bin");
  61 MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
  62 MODULE_FIRMWARE("radeon/TURKS_me.bin");
  63 MODULE_FIRMWARE("radeon/TURKS_mc.bin");
  64 MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
  65 MODULE_FIRMWARE("radeon/CAICOS_me.bin");
  66 MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
  67 MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
  68 MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
  69 MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
  70 MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
  71
  72 #define BTC_IO_MC_REGS_SIZE 29
  73
  74 static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
  75         {0x00000077, 0xff010100},
  76         {0x00000078, 0x00000000},
  77         {0x00000079, 0x00001434},
  78         {0x0000007a, 0xcc08ec08},
  79         {0x0000007b, 0x00040000},
  80         {0x0000007c, 0x000080c0},
  81         {0x0000007d, 0x09000000},
  82         {0x0000007e, 0x00210404},
  83         {0x00000081, 0x08a8e800},
  84         {0x00000082, 0x00030444},
  85         {0x00000083, 0x00000000},
  86         {0x00000085, 0x00000001},
  87         {0x00000086, 0x00000002},
  88         {0x00000087, 0x48490000},
  89         {0x00000088, 0x20244647},
  90         {0x00000089, 0x00000005},
  91         {0x0000008b, 0x66030000},
  92         {0x0000008c, 0x00006603},
  93         {0x0000008d, 0x00000100},
  94         {0x0000008f, 0x00001c0a},
  95         {0x00000090, 0xff000001},
  96         {0x00000094, 0x00101101},
  97         {0x00000095, 0x00000fff},
  98         {0x00000096, 0x00116fff},
  99         {0x00000097, 0x60010000},
 100         {0x00000098, 0x10010000},
 101         {0x00000099, 0x00006000},
 102         {0x0000009a, 0x00001000},
 103         {0x0000009f, 0x00946a00}
 104 };
 105
 106 static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 107         {0x00000077, 0xff010100},
 108         {0x00000078, 0x00000000},
 109         {0x00000079, 0x00001434},
 110         {0x0000007a, 0xcc08ec08},
 111         {0x0000007b, 0x00040000},
 112         {0x0000007c, 0x000080c0},
 113         {0x0000007d, 0x09000000},
 114         {0x0000007e, 0x00210404},
 115         {0x00000081, 0x08a8e800},
 116         {0x00000082, 0x00030444},
 117         {0x00000083, 0x00000000},
 118         {0x00000085, 0x00000001},
 119         {0x00000086, 0x00000002},
 120         {0x00000087, 0x48490000},
 121         {0x00000088, 0x20244647},
 122         {0x00000089, 0x00000005},
 123         {0x0000008b, 0x66030000},
 124         {0x0000008c, 0x00006603},
 125         {0x0000008d, 0x00000100},
 126         {0x0000008f, 0x00001c0a},
 127         {0x00000090, 0xff000001},
 128         {0x00000094, 0x00101101},
 129         {0x00000095, 0x00000fff},
 130         {0x00000096, 0x00116fff},
 131         {0x00000097, 0x60010000},
 132         {0x00000098, 0x10010000},
 133         {0x00000099, 0x00006000},
 134         {0x0000009a, 0x00001000},
 135         {0x0000009f, 0x00936a00}
 136 };
 137
 138 static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 139         {0x00000077, 0xff010100},
 140         {0x00000078, 0x00000000},
 141         {0x00000079, 0x00001434},
 142         {0x0000007a, 0xcc08ec08},
 143         {0x0000007b, 0x00040000},
 144         {0x0000007c, 0x000080c0},
 145         {0x0000007d, 0x09000000},
 146         {0x0000007e, 0x00210404},
 147         {0x00000081, 0x08a8e800},
 148         {0x00000082, 0x00030444},
 149         {0x00000083, 0x00000000},
 150         {0x00000085, 0x00000001},
 151         {0x00000086, 0x00000002},
 152         {0x00000087, 0x48490000},
 153         {0x00000088, 0x20244647},
 154         {0x00000089, 0x00000005},
 155         {0x0000008b, 0x66030000},
 156         {0x0000008c, 0x00006603},
 157         {0x0000008d, 0x00000100},
 158         {0x0000008f, 0x00001c0a},
 159         {0x00000090, 0xff000001},
 160         {0x00000094, 0x00101101},
 161         {0x00000095, 0x00000fff},
 162         {0x00000096, 0x00116fff},
 163         {0x00000097, 0x60010000},
 164         {0x00000098, 0x10010000},
 165         {0x00000099, 0x00006000},
 166         {0x0000009a, 0x00001000},
 167         {0x0000009f, 0x00916a00}
 168 };
 169
 170 static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
 171         {0x00000077, 0xff010100},
 172         {0x00000078, 0x00000000},
 173         {0x00000079, 0x00001434},
 174         {0x0000007a, 0xcc08ec08},
 175         {0x0000007b, 0x00040000},
 176         {0x0000007c, 0x000080c0},
 177         {0x0000007d, 0x09000000},
 178         {0x0000007e, 0x00210404},
 179         {0x00000081, 0x08a8e800},
 180         {0x00000082, 0x00030444},
 181         {0x00000083, 0x00000000},
 182         {0x00000085, 0x00000001},
 183         {0x00000086, 0x00000002},
 184         {0x00000087, 0x48490000},
 185         {0x00000088, 0x20244647},
 186         {0x00000089, 0x00000005},
 187         {0x0000008b, 0x66030000},
 188         {0x0000008c, 0x00006603},
 189         {0x0000008d, 0x00000100},
 190         {0x0000008f, 0x00001c0a},
 191         {0x00000090, 0xff000001},
 192         {0x00000094, 0x00101101},
 193         {0x00000095, 0x00000fff},
 194         {0x00000096, 0x00116fff},
 195         {0x00000097, 0x60010000},
 196         {0x00000098, 0x10010000},
 197         {0x00000099, 0x00006000},
 198         {0x0000009a, 0x00001000},
 199         {0x0000009f, 0x00976b00}
 200 };
 201
 202 int ni_mc_load_microcode(struct radeon_device *rdev)
 203 {
 204         const __be32 *fw_data;
 205         u32 mem_type, running, blackout = 0;
 206         u32 *io_mc_regs;
 207         int i, ucode_size, regs_size;
 208
 209         if (!rdev->mc_fw)
 210                 return -EINVAL;
 211
 212         switch (rdev->family) {
 213         case CHIP_BARTS:
 214                 io_mc_regs = (u32 *)&barts_io_mc_regs;
 215                 ucode_size = BTC_MC_UCODE_SIZE;
 216                 regs_size = BTC_IO_MC_REGS_SIZE;
 217                 break;
 218         case CHIP_TURKS:
 219                 io_mc_regs = (u32 *)&turks_io_mc_regs;
 220                 ucode_size = BTC_MC_UCODE_SIZE;
 221                 regs_size = BTC_IO_MC_REGS_SIZE;
 222                 break;
 223         case CHIP_CAICOS:
 224         default:
 225                 io_mc_regs = (u32 *)&caicos_io_mc_regs;
 226                 ucode_size = BTC_MC_UCODE_SIZE;
 227                 regs_size = BTC_IO_MC_REGS_SIZE;
 228                 break;
 229         case CHIP_CAYMAN:
 230                 io_mc_regs = (u32 *)&cayman_io_mc_regs;
 231                 ucode_size = CAYMAN_MC_UCODE_SIZE;
 232                 regs_size = BTC_IO_MC_REGS_SIZE;
 233                 break;
 234         }
 235
 236         mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
 237         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
 238
 239         if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
 240                 if (running) {
 241                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
 242                         WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
 243                 }
 244
 245                 /* reset the engine and set to writable */
 246                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 247                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
 248
 249                 /* load mc io regs */
 250                 for (i = 0; i < regs_size; i++) {
 251                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
 252                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
 253                 }
 254                 /* load the MC ucode */
 255                 fw_data = (const __be32 *)rdev->mc_fw->data;
 256                 for (i = 0; i < ucode_size; i++)
 257                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
 258
 259                 /* put the engine back into the active state */
 260                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 261                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
 262                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
 263
 264                 /* wait for training to complete */
 265                 for (i = 0; i < rdev->usec_timeout; i++) {
 266                         if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
 267                                 break;
 268                         udelay(1);
 269                 }
 270
 271                 if (running)
 272                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
 273         }
 274
 275         return 0;
 276 }
 277
 278 int ni_init_microcode(struct radeon_device *rdev)
 279 {
 280         struct platform_device *pdev;
 281         const char *chip_name;
 282         const char *rlc_chip_name;
 283         size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
 284         char fw_name[30];
 285         int err;
 286
 287         DRM_DEBUG("\n");
 288
 289         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 290         err = IS_ERR(pdev);
 291         if (err) {
 292                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 293                 return -EINVAL;
 294         }
 295
 296         switch (rdev->family) {
 297         case CHIP_BARTS:
 298                 chip_name = "BARTS";
 299                 rlc_chip_name = "BTC";
 300                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 301                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 302                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 303                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 304                 break;
 305         case CHIP_TURKS:
 306                 chip_name = "TURKS";
 307                 rlc_chip_name = "BTC";
 308                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 309                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 310                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 311                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 312                 break;
 313         case CHIP_CAICOS:
 314                 chip_name = "CAICOS";
 315                 rlc_chip_name = "BTC";
 316                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
 317                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
 318                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
 319                 mc_req_size = BTC_MC_UCODE_SIZE * 4;
 320                 break;
 321         case CHIP_CAYMAN:
 322                 chip_name = "CAYMAN";
 323                 rlc_chip_name = "CAYMAN";
 324                 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
 325                 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
 326                 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
 327                 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
 328                 break;
 329         default: BUG();
 330         }
 331
 332         DRM_INFO("Loading %s Microcode\n", chip_name);
 333
 334         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 335         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
 336         if (err)
 337                 goto out;
 338         if (rdev->pfp_fw->size != pfp_req_size) {
 339                 printk(KERN_ERR
 340                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 341                        rdev->pfp_fw->size, fw_name);
 342                 err = -EINVAL;
 343                 goto out;
 344         }
 345
 346         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 347         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 348         if (err)
 349                 goto out;
 350         if (rdev->me_fw->size != me_req_size) {
 351                 printk(KERN_ERR
 352                        "ni_cp: Bogus length %zu in firmware \"%s\"\n",
 353                        rdev->me_fw->size, fw_name);
 354                 err = -EINVAL;
 355         }
 356
 357         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
 358         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
 359         if (err)
 360                 goto out;
 361         if (rdev->rlc_fw->size != rlc_req_size) {
 362                 printk(KERN_ERR
 363                        "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
 364                        rdev->rlc_fw->size, fw_name);
 365                 err = -EINVAL;
 366         }
 367
 368         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 369         err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
 370         if (err)
 371                 goto out;
 372         if (rdev->mc_fw->size != mc_req_size) {
 373                 printk(KERN_ERR
 374                        "ni_mc: Bogus length %zu in firmware \"%s\"\n",
 375                        rdev->mc_fw->size, fw_name);
 376                 err = -EINVAL;
 377         }
 378 out:
 379         platform_device_unregister(pdev);
 380
 381         if (err) {
 382                 if (err != -EINVAL)
 383                         printk(KERN_ERR
 384                                "ni_cp: Failed to load firmware \"%s\"\n",
 385                                fw_name);
 386                 release_firmware(rdev->pfp_fw);
 387                 rdev->pfp_fw = NULL;
 388                 release_firmware(rdev->me_fw);
 389                 rdev->me_fw = NULL;
 390                 release_firmware(rdev->rlc_fw);
 391                 rdev->rlc_fw = NULL;
 392                 release_firmware(rdev->mc_fw);
 393                 rdev->mc_fw = NULL;
 394         }
 395         return err;
 396 }
 397
 398 /*
 399  * Core functions
 400  */
 401 static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 402                                                u32 num_tile_pipes,
 403                                                u32 num_backends_per_asic,
 404                                                u32 *backend_disable_mask_per_asic,
 405                                                u32 num_shader_engines)
 406 {
 407         u32 backend_map = 0;
 408         u32 enabled_backends_mask = 0;
 409         u32 enabled_backends_count = 0;
 410         u32 num_backends_per_se;
 411         u32 cur_pipe;
 412         u32 swizzle_pipe[CAYMAN_MAX_PIPES];
 413         u32 cur_backend = 0;
 414         u32 i;
 415         bool force_no_swizzle;
 416
 417         /* force legal values */
 418         if (num_tile_pipes < 1)
 419                 num_tile_pipes = 1;
 420         if (num_tile_pipes > rdev->config.cayman.max_tile_pipes)
 421                 num_tile_pipes = rdev->config.cayman.max_tile_pipes;
 422         if (num_shader_engines < 1)
 423                 num_shader_engines = 1;
 424         if (num_shader_engines > rdev->config.cayman.max_shader_engines)
 425                 num_shader_engines = rdev->config.cayman.max_shader_engines;
 426         if (num_backends_per_asic < num_shader_engines)
 427                 num_backends_per_asic = num_shader_engines;
 428         if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
 429                 num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
 430
 431         /* make sure we have the same number of backends per se */
 432         num_backends_per_asic = ALIGN(num_backends_per_asic, num_shader_engines);
 433         /* set up the number of backends per se */
 434         num_backends_per_se = num_backends_per_asic / num_shader_engines;
 435         if (num_backends_per_se > rdev->config.cayman.max_backends_per_se) {
 436                 num_backends_per_se = rdev->config.cayman.max_backends_per_se;
 437                 num_backends_per_asic = num_backends_per_se * num_shader_engines;
 438         }
 439
 440         /* create enable mask and count for enabled backends */
 441         for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 442                 if (((*backend_disable_mask_per_asic >> i) & 1) == 0) {
 443                         enabled_backends_mask |= (1 << i);
 444                         ++enabled_backends_count;
 445                 }
 446                 if (enabled_backends_count == num_backends_per_asic)
 447                         break;
 448         }
 449
 450         /* force the backends mask to match the current number of backends */
 451         if (enabled_backends_count != num_backends_per_asic) {
 452                 u32 this_backend_enabled;
 453                 u32 shader_engine;
 454                 u32 backend_per_se;
 455
 456                 enabled_backends_mask = 0;
 457                 enabled_backends_count = 0;
 458                 *backend_disable_mask_per_asic = CAYMAN_MAX_BACKENDS_MASK;
 459                 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 460                         /* calc the current se */
 461                         shader_engine = i / rdev->config.cayman.max_backends_per_se;
 462                         /* calc the backend per se */
 463                         backend_per_se = i % rdev->config.cayman.max_backends_per_se;
 464                         /* default to not enabled */
 465                         this_backend_enabled = 0;
 466                         if ((shader_engine < num_shader_engines) &&
 467                             (backend_per_se < num_backends_per_se))
 468                                 this_backend_enabled = 1;
 469                         if (this_backend_enabled) {
 470                                 enabled_backends_mask |= (1 << i);
 471                                 *backend_disable_mask_per_asic &= ~(1 << i);
 472                                 ++enabled_backends_count;
 473                         }
 474                 }
 475         }
 476
 477
 478         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * CAYMAN_MAX_PIPES);
 479         switch (rdev->family) {
 480         case CHIP_CAYMAN:
 481         case CHIP_ARUBA:
 482                 force_no_swizzle = true;
 483                 break;
 484         default:
 485                 force_no_swizzle = false;
 486                 break;
 487         }
 488         if (force_no_swizzle) {
 489                 bool last_backend_enabled = false;
 490
 491                 force_no_swizzle = false;
 492                 for (i = 0; i < CAYMAN_MAX_BACKENDS; ++i) {
 493                         if (((enabled_backends_mask >> i) & 1) == 1) {
 494                                 if (last_backend_enabled)
 495                                         force_no_swizzle = true;
 496                                 last_backend_enabled = true;
 497                         } else
 498                                 last_backend_enabled = false;
 499                 }
 500         }
 501
 502         switch (num_tile_pipes) {
 503         case 1:
 504         case 3:
 505         case 5:
 506         case 7:
 507                 DRM_ERROR("odd number of pipes!\n");
 508                 break;
 509         case 2:
 510                 swizzle_pipe[0] = 0;
 511                 swizzle_pipe[1] = 1;
 512                 break;
 513         case 4:
 514                 if (force_no_swizzle) {
 515                         swizzle_pipe[0] = 0;
 516                         swizzle_pipe[1] = 1;
 517                         swizzle_pipe[2] = 2;
 518                         swizzle_pipe[3] = 3;
 519                 } else {
 520                         swizzle_pipe[0] = 0;
 521                         swizzle_pipe[1] = 2;
 522                         swizzle_pipe[2] = 1;
 523                         swizzle_pipe[3] = 3;
 524                 }
 525                 break;
 526         case 6:
 527                 if (force_no_swizzle) {
 528                         swizzle_pipe[0] = 0;
 529                         swizzle_pipe[1] = 1;
 530                         swizzle_pipe[2] = 2;
 531                         swizzle_pipe[3] = 3;
 532                         swizzle_pipe[4] = 4;
 533                         swizzle_pipe[5] = 5;
 534                 } else {
 535                         swizzle_pipe[0] = 0;
 536                         swizzle_pipe[1] = 2;
 537                         swizzle_pipe[2] = 4;
 538                         swizzle_pipe[3] = 1;
 539                         swizzle_pipe[4] = 3;
 540                         swizzle_pipe[5] = 5;
 541                 }
 542                 break;
 543         case 8:
 544                 if (force_no_swizzle) {
 545                         swizzle_pipe[0] = 0;
 546                         swizzle_pipe[1] = 1;
 547                         swizzle_pipe[2] = 2;
 548                         swizzle_pipe[3] = 3;
 549                         swizzle_pipe[4] = 4;
 550                         swizzle_pipe[5] = 5;
 551                         swizzle_pipe[6] = 6;
 552                         swizzle_pipe[7] = 7;
 553                 } else {
 554                         swizzle_pipe[0] = 0;
 555                         swizzle_pipe[1] = 2;
 556                         swizzle_pipe[2] = 4;
 557                         swizzle_pipe[3] = 6;
 558                         swizzle_pipe[4] = 1;
 559                         swizzle_pipe[5] = 3;
 560                         swizzle_pipe[6] = 5;
 561                         swizzle_pipe[7] = 7;
 562                 }
 563                 break;
 564         }
 565
 566         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 567                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 568                         cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
 569
 570                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
 571
 572                 cur_backend = (cur_backend + 1) % CAYMAN_MAX_BACKENDS;
 573         }
 574
 575         return backend_map;
 576 }
 577
 578 static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev,
 579                                             u32 disable_mask_per_se,
 580                                             u32 max_disable_mask_per_se,
 581                                             u32 num_shader_engines)
 582 {
 583         u32 disable_field_width_per_se = r600_count_pipe_bits(disable_mask_per_se);
 584         u32 disable_mask_per_asic = disable_mask_per_se & max_disable_mask_per_se;
 585
 586         if (num_shader_engines == 1)
 587                 return disable_mask_per_asic;
 588         else if (num_shader_engines == 2)
 589                 return disable_mask_per_asic | (disable_mask_per_asic << disable_field_width_per_se);
 590         else
 591                 return 0xffffffff;
 592 }
 593
 594 static void cayman_gpu_init(struct radeon_device *rdev)
 595 {
 596         u32 cc_rb_backend_disable = 0;
 597         u32 cc_gc_shader_pipe_config;
 598         u32 gb_addr_config = 0;
 599         u32 mc_shared_chmap, mc_arb_ramcfg;
 600         u32 gb_backend_map;
 601         u32 cgts_tcc_disable;
 602         u32 sx_debug_1;
 603         u32 smx_dc_ctl0;
 604         u32 gc_user_shader_pipe_config;
 605         u32 gc_user_rb_backend_disable;
 606         u32 cgts_user_tcc_disable;
 607         u32 cgts_sm_ctrl_reg;
 608         u32 hdp_host_path_cntl;
 609         u32 tmp;
 610         int i, j;
 611
 612         switch (rdev->family) {
 613         case CHIP_CAYMAN:
 614                 rdev->config.cayman.max_shader_engines = 2;
 615                 rdev->config.cayman.max_pipes_per_simd = 4;
 616                 rdev->config.cayman.max_tile_pipes = 8;
 617                 rdev->config.cayman.max_simds_per_se = 12;
 618                 rdev->config.cayman.max_backends_per_se = 4;
 619                 rdev->config.cayman.max_texture_channel_caches = 8;
 620                 rdev->config.cayman.max_gprs = 256;
 621                 rdev->config.cayman.max_threads = 256;
 622                 rdev->config.cayman.max_gs_threads = 32;
 623                 rdev->config.cayman.max_stack_entries = 512;
 624                 rdev->config.cayman.sx_num_of_sets = 8;
 625                 rdev->config.cayman.sx_max_export_size = 256;
 626                 rdev->config.cayman.sx_max_export_pos_size = 64;
 627                 rdev->config.cayman.sx_max_export_smx_size = 192;
 628                 rdev->config.cayman.max_hw_contexts = 8;
 629                 rdev->config.cayman.sq_num_cf_insts = 2;
 630
 631                 rdev->config.cayman.sc_prim_fifo_size = 0x100;
 632                 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
 633                 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
 634                 break;
 635         case CHIP_ARUBA:
 636         default:
 637                 rdev->config.cayman.max_shader_engines = 1;
 638                 rdev->config.cayman.max_pipes_per_simd = 4;
 639                 rdev->config.cayman.max_tile_pipes = 2;
 640                 if ((rdev->pdev->device == 0x9900) ||
 641                     (rdev->pdev->device == 0x9901)) {
 642                         rdev->config.cayman.max_simds_per_se = 6;
 643                         rdev->config.cayman.max_backends_per_se = 2;
 644                 } else if ((rdev->pdev->device == 0x9903) ||
 645                            (rdev->pdev->device == 0x9904)) {
 646                         rdev->config.cayman.max_simds_per_se = 4;
 647                         rdev->config.cayman.max_backends_per_se = 2;
 648                 } else if ((rdev->pdev->device == 0x9990) ||
 649                            (rdev->pdev->device == 0x9991)) {
 650                         rdev->config.cayman.max_simds_per_se = 3;
 651                         rdev->config.cayman.max_backends_per_se = 1;
 652                 } else {
 653                         rdev->config.cayman.max_simds_per_se = 2;
 654                         rdev->config.cayman.max_backends_per_se = 1;
 655                 }
 656                 rdev->config.cayman.max_texture_channel_caches = 2;
 657                 rdev->config.cayman.max_gprs = 256;
 658                 rdev->config.cayman.max_threads = 256;
 659                 rdev->config.cayman.max_gs_threads = 32;
 660                 rdev->config.cayman.max_stack_entries = 512;
 661                 rdev->config.cayman.sx_num_of_sets = 8;
 662                 rdev->config.cayman.sx_max_export_size = 256;
 663                 rdev->config.cayman.sx_max_export_pos_size = 64;
 664                 rdev->config.cayman.sx_max_export_smx_size = 192;
 665                 rdev->config.cayman.max_hw_contexts = 8;
 666                 rdev->config.cayman.sq_num_cf_insts = 2;
 667
 668                 rdev->config.cayman.sc_prim_fifo_size = 0x40;
 669                 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
 670                 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
 671                 break;
 672         }
 673
 674         /* Initialize HDP */
 675         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 676                 WREG32((0x2c14 + j), 0x00000000);
 677                 WREG32((0x2c18 + j), 0x00000000);
 678                 WREG32((0x2c1c + j), 0x00000000);
 679                 WREG32((0x2c20 + j), 0x00000000);
 680                 WREG32((0x2c24 + j), 0x00000000);
 681         }
 682
 683         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 684
 685         evergreen_fix_pci_max_read_req_size(rdev);
 686
 687         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
 688         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 689
 690         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
 691         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
 692         cgts_tcc_disable = 0xffff0000;
 693         for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
 694                 cgts_tcc_disable &= ~(1 << (16 + i));
 695         gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
 696         gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
 697         cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
 698
 699         rdev->config.cayman.num_shader_engines = rdev->config.cayman.max_shader_engines;
 700         tmp = ((~gc_user_shader_pipe_config) & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
 701         rdev->config.cayman.num_shader_pipes_per_simd = r600_count_pipe_bits(tmp);
 702         rdev->config.cayman.num_tile_pipes = rdev->config.cayman.max_tile_pipes;
 703         tmp = ((~gc_user_shader_pipe_config) & INACTIVE_SIMDS_MASK) >> INACTIVE_SIMDS_SHIFT;
 704         rdev->config.cayman.num_simds_per_se = r600_count_pipe_bits(tmp);
 705         tmp = ((~gc_user_rb_backend_disable) & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
 706         rdev->config.cayman.num_backends_per_se = r600_count_pipe_bits(tmp);
 707         tmp = (gc_user_rb_backend_disable & BACKEND_DISABLE_MASK) >> BACKEND_DISABLE_SHIFT;
 708         rdev->config.cayman.backend_disable_mask_per_asic =
 709                 cayman_get_disable_mask_per_asic(rdev, tmp, CAYMAN_MAX_BACKENDS_PER_SE_MASK,
 710                                                  rdev->config.cayman.num_shader_engines);
 711         rdev->config.cayman.backend_map =
 712                 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
 713                                                     rdev->config.cayman.num_backends_per_se *
 714                                                     rdev->config.cayman.num_shader_engines,
 715                                                     &rdev->config.cayman.backend_disable_mask_per_asic,
 716                                                     rdev->config.cayman.num_shader_engines);
 717         tmp = ((~cgts_user_tcc_disable) & TCC_DISABLE_MASK) >> TCC_DISABLE_SHIFT;
 718         rdev->config.cayman.num_texture_channel_caches = r600_count_pipe_bits(tmp);
 719         tmp = (mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT;
 720         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 721         if (rdev->config.cayman.mem_max_burst_length_bytes > 512)
 722                 rdev->config.cayman.mem_max_burst_length_bytes = 512;
 723         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
 724         rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
 725         if (rdev->config.cayman.mem_row_size_in_kb > 4)
 726                 rdev->config.cayman.mem_row_size_in_kb = 4;
 727         /* XXX use MC settings? */
 728         rdev->config.cayman.shader_engine_tile_size = 32;
 729         rdev->config.cayman.num_gpus = 1;
 730         rdev->config.cayman.multi_gpu_tile_size = 64;
 731
 732         //gb_addr_config = 0x02011003
 733 #if 0
 734         gb_addr_config = RREG32(GB_ADDR_CONFIG);
 735 #else
 736         gb_addr_config = 0;
 737         switch (rdev->config.cayman.num_tile_pipes) {
 738         case 1:
 739         default:
 740                 gb_addr_config |= NUM_PIPES(0);
 741                 break;
 742         case 2:
 743                 gb_addr_config |= NUM_PIPES(1);
 744                 break;
 745         case 4:
 746                 gb_addr_config |= NUM_PIPES(2);
 747                 break;
 748         case 8:
 749                 gb_addr_config |= NUM_PIPES(3);
 750                 break;
 751         }
 752
 753         tmp = (rdev->config.cayman.mem_max_burst_length_bytes / 256) - 1;
 754         gb_addr_config |= PIPE_INTERLEAVE_SIZE(tmp);
 755         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.cayman.num_shader_engines - 1);
 756         tmp = (rdev->config.cayman.shader_engine_tile_size / 16) - 1;
 757         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(tmp);
 758         switch (rdev->config.cayman.num_gpus) {
 759         case 1:
 760         default:
 761                 gb_addr_config |= NUM_GPUS(0);
 762                 break;
 763         case 2:
 764                 gb_addr_config |= NUM_GPUS(1);
 765                 break;
 766         case 4:
 767                 gb_addr_config |= NUM_GPUS(2);
 768                 break;
 769         }
 770         switch (rdev->config.cayman.multi_gpu_tile_size) {
 771         case 16:
 772                 gb_addr_config |= MULTI_GPU_TILE_SIZE(0);
 773                 break;
 774         case 32:
 775         default:
 776                 gb_addr_config |= MULTI_GPU_TILE_SIZE(1);
 777                 break;
 778         case 64:
 779                 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
 780                 break;
 781         case 128:
 782                 gb_addr_config |= MULTI_GPU_TILE_SIZE(3);
 783                 break;
 784         }
 785         switch (rdev->config.cayman.mem_row_size_in_kb) {
 786         case 1:
 787         default:
 788                 gb_addr_config |= ROW_SIZE(0);
 789                 break;
 790         case 2:
 791                 gb_addr_config |= ROW_SIZE(1);
 792                 break;
 793         case 4:
 794                 gb_addr_config |= ROW_SIZE(2);
 795                 break;
 796         }
 797 #endif
 798
 799         tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
 800         rdev->config.cayman.num_tile_pipes = (1 << tmp);
 801         tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
 802         rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
 803         tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
 804         rdev->config.cayman.num_shader_engines = tmp + 1;
 805         tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
 806         rdev->config.cayman.num_gpus = tmp + 1;
 807         tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
 808         rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
 809         tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
 810         rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
 811
 812         //gb_backend_map = 0x76541032;
 813 #if 0
 814         gb_backend_map = RREG32(GB_BACKEND_MAP);
 815 #else
 816         gb_backend_map =
 817                 cayman_get_tile_pipe_to_backend_map(rdev, rdev->config.cayman.num_tile_pipes,
 818                                                     rdev->config.cayman.num_backends_per_se *
 819                                                     rdev->config.cayman.num_shader_engines,
 820                                                     &rdev->config.cayman.backend_disable_mask_per_asic,
 821                                                     rdev->config.cayman.num_shader_engines);
 822 #endif
 823         /* setup tiling info dword.  gb_addr_config is not adequate since it does
 824          * not have bank info, so create a custom tiling dword.
 825          * bits 3:0   num_pipes
 826          * bits 7:4   num_banks
 827          * bits 11:8  group_size
 828          * bits 15:12 row_size
 829          */
 830         rdev->config.cayman.tile_config = 0;
 831         switch (rdev->config.cayman.num_tile_pipes) {
 832         case 1:
 833         default:
 834                 rdev->config.cayman.tile_config |= (0 << 0);
 835                 break;
 836         case 2:
 837                 rdev->config.cayman.tile_config |= (1 << 0);
 838                 break;
 839         case 4:
 840                 rdev->config.cayman.tile_config |= (2 << 0);
 841                 break;
 842         case 8:
 843                 rdev->config.cayman.tile_config |= (3 << 0);
 844                 break;
 845         }
 846
 847         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
 848         if (rdev->flags & RADEON_IS_IGP)
 849                 rdev->config.evergreen.tile_config |= 1 << 4;
 850         else
 851                 rdev->config.cayman.tile_config |=
 852                         ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
 853         rdev->config.cayman.tile_config |=
 854                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
 855         rdev->config.cayman.tile_config |=
 856                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
 857
 858         rdev->config.cayman.backend_map = gb_backend_map;
 859         WREG32(GB_BACKEND_MAP, gb_backend_map);
 860         WREG32(GB_ADDR_CONFIG, gb_addr_config);
 861         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
 862         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
 863
 864         /* primary versions */
 865         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 866         WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 867         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 868
 869         WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
 870         WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
 871
 872         /* user versions */
 873         WREG32(GC_USER_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 874         WREG32(GC_USER_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 875         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 876
 877         WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
 878         WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
 879
 880         /* reprogram the shader complex */
 881         cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
 882         for (i = 0; i < 16; i++)
 883                 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
 884         WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
 885
 886         /* set HW defaults for 3D engine */
 887         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
 888
 889         sx_debug_1 = RREG32(SX_DEBUG_1);
 890         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 891         WREG32(SX_DEBUG_1, sx_debug_1);
 892
 893         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 894         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
 895         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
 896         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 897
 898         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
 899
 900         /* need to be explicitly zero-ed */
 901         WREG32(VGT_OFFCHIP_LDS_BASE, 0);
 902         WREG32(SQ_LSTMP_RING_BASE, 0);
 903         WREG32(SQ_HSTMP_RING_BASE, 0);
 904         WREG32(SQ_ESTMP_RING_BASE, 0);
 905         WREG32(SQ_GSTMP_RING_BASE, 0);
 906         WREG32(SQ_VSTMP_RING_BASE, 0);
 907         WREG32(SQ_PSTMP_RING_BASE, 0);
 908
 909         WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
 910
 911         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
 912                                         POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
 913                                         SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
 914
 915         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
 916                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
 917                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
 918
 919
 920         WREG32(VGT_NUM_INSTANCES, 1);
 921
 922         WREG32(CP_PERFMON_CNTL, 0);
 923
 924         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
 925                                   FETCH_FIFO_HIWATER(0x4) |
 926                                   DONE_FIFO_HIWATER(0xe0) |
 927                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
 928
 929         WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
 930         WREG32(SQ_CONFIG, (VC_ENABLE |
 931                            EXPORT_SRC_C |
 932                            GFX_PRIO(0) |
 933                            CS1_PRIO(0) |
 934                            CS2_PRIO(1)));
 935         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
 936
 937         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 938                                           FORCE_EOV_MAX_REZ_CNT(255)));
 939
 940         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
 941                AUTO_INVLD_EN(ES_AND_GS_AUTO));
 942
 943         WREG32(VGT_GS_VERTEX_REUSE, 16);
 944         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 945
 946         WREG32(CB_PERF_CTR0_SEL_0, 0);
 947         WREG32(CB_PERF_CTR0_SEL_1, 0);
 948         WREG32(CB_PERF_CTR1_SEL_0, 0);
 949         WREG32(CB_PERF_CTR1_SEL_1, 0);
 950         WREG32(CB_PERF_CTR2_SEL_0, 0);
 951         WREG32(CB_PERF_CTR2_SEL_1, 0);
 952         WREG32(CB_PERF_CTR3_SEL_0, 0);
 953         WREG32(CB_PERF_CTR3_SEL_1, 0);
 954
 955         tmp = RREG32(HDP_MISC_CNTL);
 956         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
 957         WREG32(HDP_MISC_CNTL, tmp);
 958
 959         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 960         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 961
 962         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
 963
 964         udelay(50);
 965 }
 966
 967 /*
 968  * GART
 969  */
 970 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
 971 {
 972         /* flush hdp cache */
 973         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 974
 975         /* bits 0-7 are the VM contexts0-7 */
 976         WREG32(VM_INVALIDATE_REQUEST, 1);
 977 }
 978
 979 int cayman_pcie_gart_enable(struct radeon_device *rdev)
 980 {
 981         int i, r;
 982
 983         if (rdev->gart.robj == NULL) {
 984                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 985                 return -EINVAL;
 986         }
 987         r = radeon_gart_table_vram_pin(rdev);
 988         if (r)
 989                 return r;
 990         radeon_gart_restore(rdev);
 991         /* Setup TLB control */
 992         WREG32(MC_VM_MX_L1_TLB_CNTL,
 993                (0xA << 7) |
 994                ENABLE_L1_TLB |
 995                ENABLE_L1_FRAGMENT_PROCESSING |
 996                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 997                ENABLE_ADVANCED_DRIVER_MODEL |
 998                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
 999         /* Setup L2 cache */
1000         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1001                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1002                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1003                EFFECTIVE_L2_QUEUE_SIZE(7) |
1004                CONTEXT1_IDENTITY_ACCESS_MODE(1));
1005         WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1006         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1007                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1008         /* setup context0 */
1009         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1010         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1011         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1012         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1013                         (u32)(rdev->dummy_page.addr >> 12));
1014         WREG32(VM_CONTEXT0_CNTL2, 0);
1015         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1016                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1017
1018         WREG32(0x15D4, 0);
1019         WREG32(0x15D8, 0);
1020         WREG32(0x15DC, 0);
1021
1022         /* empty context1-7 */
1023         for (i = 1; i < 8; i++) {
1024                 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1025                 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2), 0);
1026                 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1027                         rdev->gart.table_addr >> 12);
1028         }
1029
1030         /* enable context1-7 */
1031         WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1032                (u32)(rdev->dummy_page.addr >> 12));
1033         WREG32(VM_CONTEXT1_CNTL2, 0);
1034         WREG32(VM_CONTEXT1_CNTL, 0);
1035         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1036                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1037
1038         cayman_pcie_gart_tlb_flush(rdev);
1039         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1040                  (unsigned)(rdev->mc.gtt_size >> 20),
1041                  (unsigned long long)rdev->gart.table_addr);
1042         rdev->gart.ready = true;
1043         return 0;
1044 }
1045
1046 void cayman_pcie_gart_disable(struct radeon_device *rdev)
1047 {
1048         /* Disable all tables */
1049         WREG32(VM_CONTEXT0_CNTL, 0);
1050         WREG32(VM_CONTEXT1_CNTL, 0);
1051         /* Setup TLB control */
1052         WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1053                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1054                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1055         /* Setup L2 cache */
1056         WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1057                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1058                EFFECTIVE_L2_QUEUE_SIZE(7) |
1059                CONTEXT1_IDENTITY_ACCESS_MODE(1));
1060         WREG32(VM_L2_CNTL2, 0);
1061         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1062                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1063         radeon_gart_table_vram_unpin(rdev);
1064 }
1065
1066 void cayman_pcie_gart_fini(struct radeon_device *rdev)
1067 {
1068         cayman_pcie_gart_disable(rdev);
1069         radeon_gart_table_vram_free(rdev);
1070         radeon_gart_fini(rdev);
1071 }
1072
1073 void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1074                               int ring, u32 cp_int_cntl)
1075 {
1076         u32 srbm_gfx_cntl = RREG32(SRBM_GFX_CNTL) & ~3;
1077
1078         WREG32(SRBM_GFX_CNTL, srbm_gfx_cntl | (ring & 3));
1079         WREG32(CP_INT_CNTL, cp_int_cntl);
1080 }
1081
1082 /*
1083  * CP.
1084  */
1085 void cayman_fence_ring_emit(struct radeon_device *rdev,
1086                             struct radeon_fence *fence)
1087 {
1088         struct radeon_ring *ring = &rdev->ring[fence->ring];
1089         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1090
1091         /* flush read cache over gart for this vmid */
1092         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1093         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1094         radeon_ring_write(ring, 0);
1095         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1096         radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1097         radeon_ring_write(ring, 0xFFFFFFFF);
1098         radeon_ring_write(ring, 0);
1099         radeon_ring_write(ring, 10); /* poll interval */
1100         /* EVENT_WRITE_EOP - flush caches, send int */
1101         radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1102         radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1103         radeon_ring_write(ring, addr & 0xffffffff);
1104         radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1105         radeon_ring_write(ring, fence->seq);
1106         radeon_ring_write(ring, 0);
1107 }
1108
1109 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1110 {
1111         struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1112
1113         /* set to DX10/11 mode */
1114         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1115         radeon_ring_write(ring, 1);
1116         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1117         radeon_ring_write(ring,
1118 #ifdef __BIG_ENDIAN
1119                           (2 << 0) |
1120 #endif
1121                           (ib->gpu_addr & 0xFFFFFFFC));
1122         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1123         radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
1124
1125         /* flush read cache over gart for this vmid */
1126         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1127         radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
1128         radeon_ring_write(ring, ib->vm_id);
1129         radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1130         radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA);
1131         radeon_ring_write(ring, 0xFFFFFFFF);
1132         radeon_ring_write(ring, 0);
1133         radeon_ring_write(ring, 10); /* poll interval */
1134 }
1135
1136 static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1137 {
1138         if (enable)
1139                 WREG32(CP_ME_CNTL, 0);
1140         else {
1141                 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1142                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1143                 WREG32(SCRATCH_UMSK, 0);
1144         }
1145 }
1146
1147 static int cayman_cp_load_microcode(struct radeon_device *rdev)
1148 {
1149         const __be32 *fw_data;
1150         int i;
1151
1152         if (!rdev->me_fw || !rdev->pfp_fw)
1153                 return -EINVAL;
1154
1155         cayman_cp_enable(rdev, false);
1156
1157         fw_data = (const __be32 *)rdev->pfp_fw->data;
1158         WREG32(CP_PFP_UCODE_ADDR, 0);
1159         for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1160                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1161         WREG32(CP_PFP_UCODE_ADDR, 0);
1162
1163         fw_data = (const __be32 *)rdev->me_fw->data;
1164         WREG32(CP_ME_RAM_WADDR, 0);
1165         for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1166                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1167
1168         WREG32(CP_PFP_UCODE_ADDR, 0);
1169         WREG32(CP_ME_RAM_WADDR, 0);
1170         WREG32(CP_ME_RAM_RADDR, 0);
1171         return 0;
1172 }
1173
1174 static int cayman_cp_start(struct radeon_device *rdev)
1175 {
1176         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1177         int r, i;
1178
1179         r = radeon_ring_lock(rdev, ring, 7);
1180         if (r) {
1181                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1182                 return r;
1183         }
1184         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1185         radeon_ring_write(ring, 0x1);
1186         radeon_ring_write(ring, 0x0);
1187         radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1188         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1189         radeon_ring_write(ring, 0);
1190         radeon_ring_write(ring, 0);
1191         radeon_ring_unlock_commit(rdev, ring);
1192
1193         cayman_cp_enable(rdev, true);
1194
1195         r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1196         if (r) {
1197                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1198                 return r;
1199         }
1200
1201         /* setup clear context state */
1202         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1203         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1204
1205         for (i = 0; i < cayman_default_size; i++)
1206                 radeon_ring_write(ring, cayman_default_state[i]);
1207
1208         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1209         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1210
1211         /* set clear context state */
1212         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1213         radeon_ring_write(ring, 0);
1214
1215         /* SQ_VTX_BASE_VTX_LOC */
1216         radeon_ring_write(ring, 0xc0026f00);
1217         radeon_ring_write(ring, 0x00000000);
1218         radeon_ring_write(ring, 0x00000000);
1219         radeon_ring_write(ring, 0x00000000);
1220
1221         /* Clear consts */
1222         radeon_ring_write(ring, 0xc0036f00);
1223         radeon_ring_write(ring, 0x00000bc4);
1224         radeon_ring_write(ring, 0xffffffff);
1225         radeon_ring_write(ring, 0xffffffff);
1226         radeon_ring_write(ring, 0xffffffff);
1227
1228         radeon_ring_write(ring, 0xc0026900);
1229         radeon_ring_write(ring, 0x00000316);
1230         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1231         radeon_ring_write(ring, 0x00000010); /*  */
1232
1233         radeon_ring_unlock_commit(rdev, ring);
1234
1235         /* XXX init other rings */
1236
1237         return 0;
1238 }
1239
1240 static void cayman_cp_fini(struct radeon_device *rdev)
1241 {
1242         cayman_cp_enable(rdev, false);
1243         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1244 }
1245
1246 int cayman_cp_resume(struct radeon_device *rdev)
1247 {
1248         struct radeon_ring *ring;
1249         u32 tmp;
1250         u32 rb_bufsz;
1251         int r;
1252
1253         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1254         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1255                                  SOFT_RESET_PA |
1256                                  SOFT_RESET_SH |
1257                                  SOFT_RESET_VGT |
1258                                  SOFT_RESET_SPI |
1259                                  SOFT_RESET_SX));
1260         RREG32(GRBM_SOFT_RESET);
1261         mdelay(15);
1262         WREG32(GRBM_SOFT_RESET, 0);
1263         RREG32(GRBM_SOFT_RESET);
1264
1265         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1266         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1267
1268         /* Set the write pointer delay */
1269         WREG32(CP_RB_WPTR_DELAY, 0);
1270
1271         WREG32(CP_DEBUG, (1 << 27));
1272
1273         /* ring 0 - compute and gfx */
1274         /* Set ring buffer size */
1275         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1276         rb_bufsz = drm_order(ring->ring_size / 8);
1277         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1278 #ifdef __BIG_ENDIAN
1279         tmp |= BUF_SWAP_32BIT;
1280 #endif
1281         WREG32(CP_RB0_CNTL, tmp);
1282
1283         /* Initialize the ring buffer's read and write pointers */
1284         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1285         ring->wptr = 0;
1286         WREG32(CP_RB0_WPTR, ring->wptr);
1287
1288         /* set the wb address wether it's enabled or not */
1289         WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1290         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1291         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1292
1293         if (rdev->wb.enabled)
1294                 WREG32(SCRATCH_UMSK, 0xff);
1295         else {
1296                 tmp |= RB_NO_UPDATE;
1297                 WREG32(SCRATCH_UMSK, 0);
1298         }
1299
1300         mdelay(1);
1301         WREG32(CP_RB0_CNTL, tmp);
1302
1303         WREG32(CP_RB0_BASE, ring->gpu_addr >> 8);
1304
1305         ring->rptr = RREG32(CP_RB0_RPTR);
1306
1307         /* ring1  - compute only */
1308         /* Set ring buffer size */
1309         ring = &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX];
1310         rb_bufsz = drm_order(ring->ring_size / 8);
1311         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1312 #ifdef __BIG_ENDIAN
1313         tmp |= BUF_SWAP_32BIT;
1314 #endif
1315         WREG32(CP_RB1_CNTL, tmp);
1316
1317         /* Initialize the ring buffer's read and write pointers */
1318         WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1319         ring->wptr = 0;
1320         WREG32(CP_RB1_WPTR, ring->wptr);
1321
1322         /* set the wb address wether it's enabled or not */
1323         WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
1324         WREG32(CP_RB1_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFF);
1325
1326         mdelay(1);
1327         WREG32(CP_RB1_CNTL, tmp);
1328
1329         WREG32(CP_RB1_BASE, ring->gpu_addr >> 8);
1330
1331         ring->rptr = RREG32(CP_RB1_RPTR);
1332
1333         /* ring2 - compute only */
1334         /* Set ring buffer size */
1335         ring = &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX];
1336         rb_bufsz = drm_order(ring->ring_size / 8);
1337         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1338 #ifdef __BIG_ENDIAN
1339         tmp |= BUF_SWAP_32BIT;
1340 #endif
1341         WREG32(CP_RB2_CNTL, tmp);
1342
1343         /* Initialize the ring buffer's read and write pointers */
1344         WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1345         ring->wptr = 0;
1346         WREG32(CP_RB2_WPTR, ring->wptr);
1347
1348         /* set the wb address wether it's enabled or not */
1349         WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
1350         WREG32(CP_RB2_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFF);
1351
1352         mdelay(1);
1353         WREG32(CP_RB2_CNTL, tmp);
1354
1355         WREG32(CP_RB2_BASE, ring->gpu_addr >> 8);
1356
1357         ring->rptr = RREG32(CP_RB2_RPTR);
1358
1359         /* start the rings */
1360         cayman_cp_start(rdev);
1361         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1362         rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1363         rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1364         /* this only test cp0 */
1365         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1366         if (r) {
1367                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1368                 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1369                 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1370                 return r;
1371         }
1372
1373         return 0;
1374 }
1375
1376 bool cayman_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1377 {
1378         u32 srbm_status;
1379         u32 grbm_status;
1380         u32 grbm_status_se0, grbm_status_se1;
1381         struct r100_gpu_lockup *lockup = &rdev->config.cayman.lockup;
1382         int r;
1383
1384         srbm_status = RREG32(SRBM_STATUS);
1385         grbm_status = RREG32(GRBM_STATUS);
1386         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
1387         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
1388         if (!(grbm_status & GUI_ACTIVE)) {
1389                 r100_gpu_lockup_update(lockup, ring);
1390                 return false;
1391         }
1392         /* force CP activities */
1393         r = radeon_ring_lock(rdev, ring, 2);
1394         if (!r) {
1395                 /* PACKET2 NOP */
1396                 radeon_ring_write(ring, 0x80000000);
1397                 radeon_ring_write(ring, 0x80000000);
1398                 radeon_ring_unlock_commit(rdev, ring);
1399         }
1400         /* XXX deal with CP0,1,2 */
1401         ring->rptr = RREG32(ring->rptr_reg);
1402         return r100_gpu_cp_is_lockup(rdev, lockup, ring);
1403 }
1404
1405 static int cayman_gpu_soft_reset(struct radeon_device *rdev)
1406 {
1407         struct evergreen_mc_save save;
1408         u32 grbm_reset = 0;
1409
1410         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1411                 return 0;
1412
1413         dev_info(rdev->dev, "GPU softreset \n");
1414         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1415                 RREG32(GRBM_STATUS));
1416         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1417                 RREG32(GRBM_STATUS_SE0));
1418         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1419                 RREG32(GRBM_STATUS_SE1));
1420         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1421                 RREG32(SRBM_STATUS));
1422         dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_ADDR   0x%08X\n",
1423                  RREG32(0x14F8));
1424         dev_info(rdev->dev, "  VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1425                  RREG32(0x14D8));
1426         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
1427                  RREG32(0x14FC));
1428         dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1429                  RREG32(0x14DC));
1430
1431         evergreen_mc_stop(rdev, &save);
1432         if (evergreen_mc_wait_for_idle(rdev)) {
1433                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1434         }
1435         /* Disable CP parsing/prefetching */
1436         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1437
1438         /* reset all the gfx blocks */
1439         grbm_reset = (SOFT_RESET_CP |
1440                       SOFT_RESET_CB |
1441                       SOFT_RESET_DB |
1442                       SOFT_RESET_GDS |
1443                       SOFT_RESET_PA |
1444                       SOFT_RESET_SC |
1445                       SOFT_RESET_SPI |
1446                       SOFT_RESET_SH |
1447                       SOFT_RESET_SX |
1448                       SOFT_RESET_TC |
1449                       SOFT_RESET_TA |
1450                       SOFT_RESET_VGT |
1451                       SOFT_RESET_IA);
1452
1453         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1454         WREG32(GRBM_SOFT_RESET, grbm_reset);
1455         (void)RREG32(GRBM_SOFT_RESET);
1456         udelay(50);
1457         WREG32(GRBM_SOFT_RESET, 0);
1458         (void)RREG32(GRBM_SOFT_RESET);
1459         /* Wait a little for things to settle down */
1460         udelay(50);
1461
1462         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1463                 RREG32(GRBM_STATUS));
1464         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1465                 RREG32(GRBM_STATUS_SE0));
1466         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1467                 RREG32(GRBM_STATUS_SE1));
1468         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1469                 RREG32(SRBM_STATUS));
1470         evergreen_mc_resume(rdev, &save);
1471         return 0;
1472 }
1473
1474 int cayman_asic_reset(struct radeon_device *rdev)
1475 {
1476         return cayman_gpu_soft_reset(rdev);
1477 }
1478
1479 static int cayman_startup(struct radeon_device *rdev)
1480 {
1481         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1482         int r;
1483
1484         /* enable pcie gen2 link */
1485         evergreen_pcie_gen2_enable(rdev);
1486
1487         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
1488                 r = ni_init_microcode(rdev);
1489                 if (r) {
1490                         DRM_ERROR("Failed to load firmware!\n");
1491                         return r;
1492                 }
1493         }
1494         r = ni_mc_load_microcode(rdev);
1495         if (r) {
1496                 DRM_ERROR("Failed to load MC firmware!\n");
1497                 return r;
1498         }
1499
1500         r = r600_vram_scratch_init(rdev);
1501         if (r)
1502                 return r;
1503
1504         evergreen_mc_program(rdev);
1505         r = cayman_pcie_gart_enable(rdev);
1506         if (r)
1507                 return r;
1508         cayman_gpu_init(rdev);
1509
1510         r = evergreen_blit_init(rdev);
1511         if (r) {
1512                 r600_blit_fini(rdev);
1513                 rdev->asic->copy.copy = NULL;
1514                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1515         }
1516
1517         /* allocate wb buffer */
1518         r = radeon_wb_init(rdev);
1519         if (r)
1520                 return r;
1521
1522         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1523         if (r) {
1524                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1525                 return r;
1526         }
1527
1528         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
1529         if (r) {
1530                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1531                 return r;
1532         }
1533
1534         r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
1535         if (r) {
1536                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1537                 return r;
1538         }
1539
1540         /* Enable IRQ */
1541         r = r600_irq_init(rdev);
1542         if (r) {
1543                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1544                 radeon_irq_kms_fini(rdev);
1545                 return r;
1546         }
1547         evergreen_irq_set(rdev);
1548
1549         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1550                              CP_RB0_RPTR, CP_RB0_WPTR,
1551                              0, 0xfffff, RADEON_CP_PACKET2);
1552         if (r)
1553                 return r;
1554         r = cayman_cp_load_microcode(rdev);
1555         if (r)
1556                 return r;
1557         r = cayman_cp_resume(rdev);
1558         if (r)
1559                 return r;
1560
1561         r = radeon_ib_pool_start(rdev);
1562         if (r)
1563                 return r;
1564
1565         r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1566         if (r) {
1567                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1568                 rdev->accel_working = false;
1569                 return r;
1570         }
1571
1572         r = radeon_vm_manager_start(rdev);
1573         if (r)
1574                 return r;
1575
1576         return 0;
1577 }
1578
1579 int cayman_resume(struct radeon_device *rdev)
1580 {
1581         int r;
1582
1583         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1584          * posting will perform necessary task to bring back GPU into good
1585          * shape.
1586          */
1587         /* post card */
1588         atom_asic_init(rdev->mode_info.atom_context);
1589
1590         rdev->accel_working = true;
1591         r = cayman_startup(rdev);
1592         if (r) {
1593                 DRM_ERROR("cayman startup failed on resume\n");
1594                 rdev->accel_working = false;
1595                 return r;
1596         }
1597         return r;
1598 }
1599
1600 int cayman_suspend(struct radeon_device *rdev)
1601 {
1602         /* FIXME: we should wait for ring to be empty */
1603         radeon_ib_pool_suspend(rdev);
1604         radeon_vm_manager_suspend(rdev);
1605         r600_blit_suspend(rdev);
1606         cayman_cp_enable(rdev, false);
1607         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1608         evergreen_irq_suspend(rdev);
1609         radeon_wb_disable(rdev);
1610         cayman_pcie_gart_disable(rdev);
1611         return 0;
1612 }
1613
1614 /* Plan is to move initialization in that function and use
1615  * helper function so that radeon_device_init pretty much
1616  * do nothing more than calling asic specific function. This
1617  * should also allow to remove a bunch of callback function
1618  * like vram_info.
1619  */
1620 int cayman_init(struct radeon_device *rdev)
1621 {
1622         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1623         int r;
1624
1625         /* This don't do much */
1626         r = radeon_gem_init(rdev);
1627         if (r)
1628                 return r;
1629         /* Read BIOS */
1630         if (!radeon_get_bios(rdev)) {
1631                 if (ASIC_IS_AVIVO(rdev))
1632                         return -EINVAL;
1633         }
1634         /* Must be an ATOMBIOS */
1635         if (!rdev->is_atom_bios) {
1636                 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
1637                 return -EINVAL;
1638         }
1639         r = radeon_atombios_init(rdev);
1640         if (r)
1641                 return r;
1642
1643         /* Post card if necessary */
1644         if (!radeon_card_posted(rdev)) {
1645                 if (!rdev->bios) {
1646                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
1647                         return -EINVAL;
1648                 }
1649                 DRM_INFO("GPU not posted. posting now...\n");
1650                 atom_asic_init(rdev->mode_info.atom_context);
1651         }
1652         /* Initialize scratch registers */
1653         r600_scratch_init(rdev);
1654         /* Initialize surface registers */
1655         radeon_surface_init(rdev);
1656         /* Initialize clocks */
1657         radeon_get_clock_info(rdev->ddev);
1658         /* Fence driver */
1659         r = radeon_fence_driver_init(rdev);
1660         if (r)
1661                 return r;
1662         /* initialize memory controller */
1663         r = evergreen_mc_init(rdev);
1664         if (r)
1665                 return r;
1666         /* Memory manager */
1667         r = radeon_bo_init(rdev);
1668         if (r)
1669                 return r;
1670
1671         r = radeon_irq_kms_init(rdev);
1672         if (r)
1673                 return r;
1674
1675         ring->ring_obj = NULL;
1676         r600_ring_init(rdev, ring, 1024 * 1024);
1677
1678         rdev->ih.ring_obj = NULL;
1679         r600_ih_ring_init(rdev, 64 * 1024);
1680
1681         r = r600_pcie_gart_init(rdev);
1682         if (r)
1683                 return r;
1684
1685         r = radeon_ib_pool_init(rdev);
1686         rdev->accel_working = true;
1687         if (r) {
1688                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1689                 rdev->accel_working = false;
1690         }
1691         r = radeon_vm_manager_init(rdev);
1692         if (r) {
1693                 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
1694         }
1695
1696         r = cayman_startup(rdev);
1697         if (r) {
1698                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1699                 cayman_cp_fini(rdev);
1700                 r600_irq_fini(rdev);
1701                 radeon_wb_fini(rdev);
1702                 r100_ib_fini(rdev);
1703                 radeon_vm_manager_fini(rdev);
1704                 radeon_irq_kms_fini(rdev);
1705                 cayman_pcie_gart_fini(rdev);
1706                 rdev->accel_working = false;
1707         }
1708
1709         /* Don't start up if the MC ucode is missing.
1710          * The default clocks and voltages before the MC ucode
1711          * is loaded are not suffient for advanced operations.
1712          */
1713         if (!rdev->mc_fw) {
1714                 DRM_ERROR("radeon: MC ucode required for NI+.\n");
1715                 return -EINVAL;
1716         }
1717
1718         return 0;
1719 }
1720
1721 void cayman_fini(struct radeon_device *rdev)
1722 {
1723         r600_blit_fini(rdev);
1724         cayman_cp_fini(rdev);
1725         r600_irq_fini(rdev);
1726         radeon_wb_fini(rdev);
1727         radeon_vm_manager_fini(rdev);
1728         r100_ib_fini(rdev);
1729         radeon_irq_kms_fini(rdev);
1730         cayman_pcie_gart_fini(rdev);
1731         r600_vram_scratch_fini(rdev);
1732         radeon_gem_fini(rdev);
1733         radeon_semaphore_driver_fini(rdev);
1734         radeon_fence_driver_fini(rdev);
1735         radeon_bo_fini(rdev);
1736         radeon_atombios_fini(rdev);
1737         kfree(rdev->bios);
1738         rdev->bios = NULL;
1739 }
1740
1741 /*
1742  * vm
1743  */
1744 int cayman_vm_init(struct radeon_device *rdev)
1745 {
1746         /* number of VMs */
1747         rdev->vm_manager.nvm = 8;
1748         /* base offset of vram pages */
1749         if (rdev->flags & RADEON_IS_IGP) {
1750                 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
1751                 tmp <<= 22;
1752                 rdev->vm_manager.vram_base_offset = tmp;
1753         } else
1754                 rdev->vm_manager.vram_base_offset = 0;
1755         return 0;
1756 }
1757
1758 void cayman_vm_fini(struct radeon_device *rdev)
1759 {
1760 }
1761
1762 int cayman_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
1763 {
1764         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (id << 2), 0);
1765         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (id << 2), vm->last_pfn);
1766         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
1767         /* flush hdp cache */
1768         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1769         /* bits 0-7 are the VM contexts0-7 */
1770         WREG32(VM_INVALIDATE_REQUEST, 1 << id);
1771         return 0;
1772 }
1773
1774 void cayman_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
1775 {
1776         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (vm->id << 2), 0);
1777         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (vm->id << 2), 0);
1778         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
1779         /* flush hdp cache */
1780         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1781         /* bits 0-7 are the VM contexts0-7 */
1782         WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1783 }
1784
1785 void cayman_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
1786 {
1787         if (vm->id == -1)
1788                 return;
1789
1790         /* flush hdp cache */
1791         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1792         /* bits 0-7 are the VM contexts0-7 */
1793         WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
1794 }
1795
1796 #define R600_PTE_VALID     (1 << 0)
1797 #define R600_PTE_SYSTEM    (1 << 1)
1798 #define R600_PTE_SNOOPED   (1 << 2)
1799 #define R600_PTE_READABLE  (1 << 5)
1800 #define R600_PTE_WRITEABLE (1 << 6)
1801
1802 uint32_t cayman_vm_page_flags(struct radeon_device *rdev,
1803                               struct radeon_vm *vm,
1804                               uint32_t flags)
1805 {
1806         uint32_t r600_flags = 0;
1807
1808         r600_flags |= (flags & RADEON_VM_PAGE_VALID) ? R600_PTE_VALID : 0;
1809         r600_flags |= (flags & RADEON_VM_PAGE_READABLE) ? R600_PTE_READABLE : 0;
1810         r600_flags |= (flags & RADEON_VM_PAGE_WRITEABLE) ? R600_PTE_WRITEABLE : 0;
1811         if (flags & RADEON_VM_PAGE_SYSTEM) {
1812                 r600_flags |= R600_PTE_SYSTEM;
1813                 r600_flags |= (flags & RADEON_VM_PAGE_SNOOPED) ? R600_PTE_SNOOPED : 0;
1814         }
1815         return r600_flags;
1816 }
1817
1818 void cayman_vm_set_page(struct radeon_device *rdev, struct radeon_vm *vm,
1819                         unsigned pfn, uint64_t addr, uint32_t flags)
1820 {
1821         void __iomem *ptr = (void *)vm->pt;
1822
1823         addr = addr & 0xFFFFFFFFFFFFF000ULL;
1824         addr |= flags;
1825         writeq(addr, ptr + (pfn * 8));
1826 }