2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/math64.h>
31 #include <linux/seq_file.h>
33 #define MC_CG_ARB_FREQ_F0 0x0a
34 #define MC_CG_ARB_FREQ_F1 0x0b
35 #define MC_CG_ARB_FREQ_F2 0x0c
36 #define MC_CG_ARB_FREQ_F3 0x0d
38 #define SMC_RAM_END 0xC000
40 static const struct ni_cac_weights cac_weights_cayman_xt =
104 { 0, 0, 0, 0, 0, 0, 0, 0 },
109 static const struct ni_cac_weights cac_weights_cayman_pro =
173 { 0, 0, 0, 0, 0, 0, 0, 0 },
178 static const struct ni_cac_weights cac_weights_cayman_le =
242 { 0, 0, 0, 0, 0, 0, 0, 0 },
247 #define NISLANDS_MGCG_SEQUENCE 300
249 static const u32 cayman_cgcg_cgls_default[] =
251 0x000008f8, 0x00000010, 0xffffffff,
252 0x000008fc, 0x00000000, 0xffffffff,
253 0x000008f8, 0x00000011, 0xffffffff,
254 0x000008fc, 0x00000000, 0xffffffff,
255 0x000008f8, 0x00000012, 0xffffffff,
256 0x000008fc, 0x00000000, 0xffffffff,
257 0x000008f8, 0x00000013, 0xffffffff,
258 0x000008fc, 0x00000000, 0xffffffff,
259 0x000008f8, 0x00000014, 0xffffffff,
260 0x000008fc, 0x00000000, 0xffffffff,
261 0x000008f8, 0x00000015, 0xffffffff,
262 0x000008fc, 0x00000000, 0xffffffff,
263 0x000008f8, 0x00000016, 0xffffffff,
264 0x000008fc, 0x00000000, 0xffffffff,
265 0x000008f8, 0x00000017, 0xffffffff,
266 0x000008fc, 0x00000000, 0xffffffff,
267 0x000008f8, 0x00000018, 0xffffffff,
268 0x000008fc, 0x00000000, 0xffffffff,
269 0x000008f8, 0x00000019, 0xffffffff,
270 0x000008fc, 0x00000000, 0xffffffff,
271 0x000008f8, 0x0000001a, 0xffffffff,
272 0x000008fc, 0x00000000, 0xffffffff,
273 0x000008f8, 0x0000001b, 0xffffffff,
274 0x000008fc, 0x00000000, 0xffffffff,
275 0x000008f8, 0x00000020, 0xffffffff,
276 0x000008fc, 0x00000000, 0xffffffff,
277 0x000008f8, 0x00000021, 0xffffffff,
278 0x000008fc, 0x00000000, 0xffffffff,
279 0x000008f8, 0x00000022, 0xffffffff,
280 0x000008fc, 0x00000000, 0xffffffff,
281 0x000008f8, 0x00000023, 0xffffffff,
282 0x000008fc, 0x00000000, 0xffffffff,
283 0x000008f8, 0x00000024, 0xffffffff,
284 0x000008fc, 0x00000000, 0xffffffff,
285 0x000008f8, 0x00000025, 0xffffffff,
286 0x000008fc, 0x00000000, 0xffffffff,
287 0x000008f8, 0x00000026, 0xffffffff,
288 0x000008fc, 0x00000000, 0xffffffff,
289 0x000008f8, 0x00000027, 0xffffffff,
290 0x000008fc, 0x00000000, 0xffffffff,
291 0x000008f8, 0x00000028, 0xffffffff,
292 0x000008fc, 0x00000000, 0xffffffff,
293 0x000008f8, 0x00000029, 0xffffffff,
294 0x000008fc, 0x00000000, 0xffffffff,
295 0x000008f8, 0x0000002a, 0xffffffff,
296 0x000008fc, 0x00000000, 0xffffffff,
297 0x000008f8, 0x0000002b, 0xffffffff,
298 0x000008fc, 0x00000000, 0xffffffff
300 #define CAYMAN_CGCG_CGLS_DEFAULT_LENGTH sizeof(cayman_cgcg_cgls_default) / (3 * sizeof(u32))
302 static const u32 cayman_cgcg_cgls_disable[] =
304 0x000008f8, 0x00000010, 0xffffffff,
305 0x000008fc, 0xffffffff, 0xffffffff,
306 0x000008f8, 0x00000011, 0xffffffff,
307 0x000008fc, 0xffffffff, 0xffffffff,
308 0x000008f8, 0x00000012, 0xffffffff,
309 0x000008fc, 0xffffffff, 0xffffffff,
310 0x000008f8, 0x00000013, 0xffffffff,
311 0x000008fc, 0xffffffff, 0xffffffff,
312 0x000008f8, 0x00000014, 0xffffffff,
313 0x000008fc, 0xffffffff, 0xffffffff,
314 0x000008f8, 0x00000015, 0xffffffff,
315 0x000008fc, 0xffffffff, 0xffffffff,
316 0x000008f8, 0x00000016, 0xffffffff,
317 0x000008fc, 0xffffffff, 0xffffffff,
318 0x000008f8, 0x00000017, 0xffffffff,
319 0x000008fc, 0xffffffff, 0xffffffff,
320 0x000008f8, 0x00000018, 0xffffffff,
321 0x000008fc, 0xffffffff, 0xffffffff,
322 0x000008f8, 0x00000019, 0xffffffff,
323 0x000008fc, 0xffffffff, 0xffffffff,
324 0x000008f8, 0x0000001a, 0xffffffff,
325 0x000008fc, 0xffffffff, 0xffffffff,
326 0x000008f8, 0x0000001b, 0xffffffff,
327 0x000008fc, 0xffffffff, 0xffffffff,
328 0x000008f8, 0x00000020, 0xffffffff,
329 0x000008fc, 0x00000000, 0xffffffff,
330 0x000008f8, 0x00000021, 0xffffffff,
331 0x000008fc, 0x00000000, 0xffffffff,
332 0x000008f8, 0x00000022, 0xffffffff,
333 0x000008fc, 0x00000000, 0xffffffff,
334 0x000008f8, 0x00000023, 0xffffffff,
335 0x000008fc, 0x00000000, 0xffffffff,
336 0x000008f8, 0x00000024, 0xffffffff,
337 0x000008fc, 0x00000000, 0xffffffff,
338 0x000008f8, 0x00000025, 0xffffffff,
339 0x000008fc, 0x00000000, 0xffffffff,
340 0x000008f8, 0x00000026, 0xffffffff,
341 0x000008fc, 0x00000000, 0xffffffff,
342 0x000008f8, 0x00000027, 0xffffffff,
343 0x000008fc, 0x00000000, 0xffffffff,
344 0x000008f8, 0x00000028, 0xffffffff,
345 0x000008fc, 0x00000000, 0xffffffff,
346 0x000008f8, 0x00000029, 0xffffffff,
347 0x000008fc, 0x00000000, 0xffffffff,
348 0x000008f8, 0x0000002a, 0xffffffff,
349 0x000008fc, 0x00000000, 0xffffffff,
350 0x000008f8, 0x0000002b, 0xffffffff,
351 0x000008fc, 0x00000000, 0xffffffff,
352 0x00000644, 0x000f7902, 0x001f4180,
353 0x00000644, 0x000f3802, 0x001f4180
355 #define CAYMAN_CGCG_CGLS_DISABLE_LENGTH sizeof(cayman_cgcg_cgls_disable) / (3 * sizeof(u32))
357 static const u32 cayman_cgcg_cgls_enable[] =
359 0x00000644, 0x000f7882, 0x001f4080,
360 0x000008f8, 0x00000010, 0xffffffff,
361 0x000008fc, 0x00000000, 0xffffffff,
362 0x000008f8, 0x00000011, 0xffffffff,
363 0x000008fc, 0x00000000, 0xffffffff,
364 0x000008f8, 0x00000012, 0xffffffff,
365 0x000008fc, 0x00000000, 0xffffffff,
366 0x000008f8, 0x00000013, 0xffffffff,
367 0x000008fc, 0x00000000, 0xffffffff,
368 0x000008f8, 0x00000014, 0xffffffff,
369 0x000008fc, 0x00000000, 0xffffffff,
370 0x000008f8, 0x00000015, 0xffffffff,
371 0x000008fc, 0x00000000, 0xffffffff,
372 0x000008f8, 0x00000016, 0xffffffff,
373 0x000008fc, 0x00000000, 0xffffffff,
374 0x000008f8, 0x00000017, 0xffffffff,
375 0x000008fc, 0x00000000, 0xffffffff,
376 0x000008f8, 0x00000018, 0xffffffff,
377 0x000008fc, 0x00000000, 0xffffffff,
378 0x000008f8, 0x00000019, 0xffffffff,
379 0x000008fc, 0x00000000, 0xffffffff,
380 0x000008f8, 0x0000001a, 0xffffffff,
381 0x000008fc, 0x00000000, 0xffffffff,
382 0x000008f8, 0x0000001b, 0xffffffff,
383 0x000008fc, 0x00000000, 0xffffffff,
384 0x000008f8, 0x00000020, 0xffffffff,
385 0x000008fc, 0xffffffff, 0xffffffff,
386 0x000008f8, 0x00000021, 0xffffffff,
387 0x000008fc, 0xffffffff, 0xffffffff,
388 0x000008f8, 0x00000022, 0xffffffff,
389 0x000008fc, 0xffffffff, 0xffffffff,
390 0x000008f8, 0x00000023, 0xffffffff,
391 0x000008fc, 0xffffffff, 0xffffffff,
392 0x000008f8, 0x00000024, 0xffffffff,
393 0x000008fc, 0xffffffff, 0xffffffff,
394 0x000008f8, 0x00000025, 0xffffffff,
395 0x000008fc, 0xffffffff, 0xffffffff,
396 0x000008f8, 0x00000026, 0xffffffff,
397 0x000008fc, 0xffffffff, 0xffffffff,
398 0x000008f8, 0x00000027, 0xffffffff,
399 0x000008fc, 0xffffffff, 0xffffffff,
400 0x000008f8, 0x00000028, 0xffffffff,
401 0x000008fc, 0xffffffff, 0xffffffff,
402 0x000008f8, 0x00000029, 0xffffffff,
403 0x000008fc, 0xffffffff, 0xffffffff,
404 0x000008f8, 0x0000002a, 0xffffffff,
405 0x000008fc, 0xffffffff, 0xffffffff,
406 0x000008f8, 0x0000002b, 0xffffffff,
407 0x000008fc, 0xffffffff, 0xffffffff
409 #define CAYMAN_CGCG_CGLS_ENABLE_LENGTH sizeof(cayman_cgcg_cgls_enable) / (3 * sizeof(u32))
411 static const u32 cayman_mgcg_default[] =
413 0x0000802c, 0xc0000000, 0xffffffff,
414 0x00003fc4, 0xc0000000, 0xffffffff,
415 0x00005448, 0x00000100, 0xffffffff,
416 0x000055e4, 0x00000100, 0xffffffff,
417 0x0000160c, 0x00000100, 0xffffffff,
418 0x00008984, 0x06000100, 0xffffffff,
419 0x0000c164, 0x00000100, 0xffffffff,
420 0x00008a18, 0x00000100, 0xffffffff,
421 0x0000897c, 0x06000100, 0xffffffff,
422 0x00008b28, 0x00000100, 0xffffffff,
423 0x00009144, 0x00800200, 0xffffffff,
424 0x00009a60, 0x00000100, 0xffffffff,
425 0x00009868, 0x00000100, 0xffffffff,
426 0x00008d58, 0x00000100, 0xffffffff,
427 0x00009510, 0x00000100, 0xffffffff,
428 0x0000949c, 0x00000100, 0xffffffff,
429 0x00009654, 0x00000100, 0xffffffff,
430 0x00009030, 0x00000100, 0xffffffff,
431 0x00009034, 0x00000100, 0xffffffff,
432 0x00009038, 0x00000100, 0xffffffff,
433 0x0000903c, 0x00000100, 0xffffffff,
434 0x00009040, 0x00000100, 0xffffffff,
435 0x0000a200, 0x00000100, 0xffffffff,
436 0x0000a204, 0x00000100, 0xffffffff,
437 0x0000a208, 0x00000100, 0xffffffff,
438 0x0000a20c, 0x00000100, 0xffffffff,
439 0x00009744, 0x00000100, 0xffffffff,
440 0x00003f80, 0x00000100, 0xffffffff,
441 0x0000a210, 0x00000100, 0xffffffff,
442 0x0000a214, 0x00000100, 0xffffffff,
443 0x000004d8, 0x00000100, 0xffffffff,
444 0x00009664, 0x00000100, 0xffffffff,
445 0x00009698, 0x00000100, 0xffffffff,
446 0x000004d4, 0x00000200, 0xffffffff,
447 0x000004d0, 0x00000000, 0xffffffff,
448 0x000030cc, 0x00000104, 0xffffffff,
449 0x0000d0c0, 0x00000100, 0xffffffff,
450 0x0000d8c0, 0x00000100, 0xffffffff,
451 0x0000802c, 0x40000000, 0xffffffff,
452 0x00003fc4, 0x40000000, 0xffffffff,
453 0x0000915c, 0x00010000, 0xffffffff,
454 0x00009160, 0x00030002, 0xffffffff,
455 0x00009164, 0x00050004, 0xffffffff,
456 0x00009168, 0x00070006, 0xffffffff,
457 0x00009178, 0x00070000, 0xffffffff,
458 0x0000917c, 0x00030002, 0xffffffff,
459 0x00009180, 0x00050004, 0xffffffff,
460 0x0000918c, 0x00010006, 0xffffffff,
461 0x00009190, 0x00090008, 0xffffffff,
462 0x00009194, 0x00070000, 0xffffffff,
463 0x00009198, 0x00030002, 0xffffffff,
464 0x0000919c, 0x00050004, 0xffffffff,
465 0x000091a8, 0x00010006, 0xffffffff,
466 0x000091ac, 0x00090008, 0xffffffff,
467 0x000091b0, 0x00070000, 0xffffffff,
468 0x000091b4, 0x00030002, 0xffffffff,
469 0x000091b8, 0x00050004, 0xffffffff,
470 0x000091c4, 0x00010006, 0xffffffff,
471 0x000091c8, 0x00090008, 0xffffffff,
472 0x000091cc, 0x00070000, 0xffffffff,
473 0x000091d0, 0x00030002, 0xffffffff,
474 0x000091d4, 0x00050004, 0xffffffff,
475 0x000091e0, 0x00010006, 0xffffffff,
476 0x000091e4, 0x00090008, 0xffffffff,
477 0x000091e8, 0x00000000, 0xffffffff,
478 0x000091ec, 0x00070000, 0xffffffff,
479 0x000091f0, 0x00030002, 0xffffffff,
480 0x000091f4, 0x00050004, 0xffffffff,
481 0x00009200, 0x00010006, 0xffffffff,
482 0x00009204, 0x00090008, 0xffffffff,
483 0x00009208, 0x00070000, 0xffffffff,
484 0x0000920c, 0x00030002, 0xffffffff,
485 0x00009210, 0x00050004, 0xffffffff,
486 0x0000921c, 0x00010006, 0xffffffff,
487 0x00009220, 0x00090008, 0xffffffff,
488 0x00009224, 0x00070000, 0xffffffff,
489 0x00009228, 0x00030002, 0xffffffff,
490 0x0000922c, 0x00050004, 0xffffffff,
491 0x00009238, 0x00010006, 0xffffffff,
492 0x0000923c, 0x00090008, 0xffffffff,
493 0x00009240, 0x00070000, 0xffffffff,
494 0x00009244, 0x00030002, 0xffffffff,
495 0x00009248, 0x00050004, 0xffffffff,
496 0x00009254, 0x00010006, 0xffffffff,
497 0x00009258, 0x00090008, 0xffffffff,
498 0x0000925c, 0x00070000, 0xffffffff,
499 0x00009260, 0x00030002, 0xffffffff,
500 0x00009264, 0x00050004, 0xffffffff,
501 0x00009270, 0x00010006, 0xffffffff,
502 0x00009274, 0x00090008, 0xffffffff,
503 0x00009278, 0x00070000, 0xffffffff,
504 0x0000927c, 0x00030002, 0xffffffff,
505 0x00009280, 0x00050004, 0xffffffff,
506 0x0000928c, 0x00010006, 0xffffffff,
507 0x00009290, 0x00090008, 0xffffffff,
508 0x000092a8, 0x00070000, 0xffffffff,
509 0x000092ac, 0x00030002, 0xffffffff,
510 0x000092b0, 0x00050004, 0xffffffff,
511 0x000092bc, 0x00010006, 0xffffffff,
512 0x000092c0, 0x00090008, 0xffffffff,
513 0x000092c4, 0x00070000, 0xffffffff,
514 0x000092c8, 0x00030002, 0xffffffff,
515 0x000092cc, 0x00050004, 0xffffffff,
516 0x000092d8, 0x00010006, 0xffffffff,
517 0x000092dc, 0x00090008, 0xffffffff,
518 0x00009294, 0x00000000, 0xffffffff,
519 0x0000802c, 0x40010000, 0xffffffff,
520 0x00003fc4, 0x40010000, 0xffffffff,
521 0x0000915c, 0x00010000, 0xffffffff,
522 0x00009160, 0x00030002, 0xffffffff,
523 0x00009164, 0x00050004, 0xffffffff,
524 0x00009168, 0x00070006, 0xffffffff,
525 0x00009178, 0x00070000, 0xffffffff,
526 0x0000917c, 0x00030002, 0xffffffff,
527 0x00009180, 0x00050004, 0xffffffff,
528 0x0000918c, 0x00010006, 0xffffffff,
529 0x00009190, 0x00090008, 0xffffffff,
530 0x00009194, 0x00070000, 0xffffffff,
531 0x00009198, 0x00030002, 0xffffffff,
532 0x0000919c, 0x00050004, 0xffffffff,
533 0x000091a8, 0x00010006, 0xffffffff,
534 0x000091ac, 0x00090008, 0xffffffff,
535 0x000091b0, 0x00070000, 0xffffffff,
536 0x000091b4, 0x00030002, 0xffffffff,
537 0x000091b8, 0x00050004, 0xffffffff,
538 0x000091c4, 0x00010006, 0xffffffff,
539 0x000091c8, 0x00090008, 0xffffffff,
540 0x000091cc, 0x00070000, 0xffffffff,
541 0x000091d0, 0x00030002, 0xffffffff,
542 0x000091d4, 0x00050004, 0xffffffff,
543 0x000091e0, 0x00010006, 0xffffffff,
544 0x000091e4, 0x00090008, 0xffffffff,
545 0x000091e8, 0x00000000, 0xffffffff,
546 0x000091ec, 0x00070000, 0xffffffff,
547 0x000091f0, 0x00030002, 0xffffffff,
548 0x000091f4, 0x00050004, 0xffffffff,
549 0x00009200, 0x00010006, 0xffffffff,
550 0x00009204, 0x00090008, 0xffffffff,
551 0x00009208, 0x00070000, 0xffffffff,
552 0x0000920c, 0x00030002, 0xffffffff,
553 0x00009210, 0x00050004, 0xffffffff,
554 0x0000921c, 0x00010006, 0xffffffff,
555 0x00009220, 0x00090008, 0xffffffff,
556 0x00009224, 0x00070000, 0xffffffff,
557 0x00009228, 0x00030002, 0xffffffff,
558 0x0000922c, 0x00050004, 0xffffffff,
559 0x00009238, 0x00010006, 0xffffffff,
560 0x0000923c, 0x00090008, 0xffffffff,
561 0x00009240, 0x00070000, 0xffffffff,
562 0x00009244, 0x00030002, 0xffffffff,
563 0x00009248, 0x00050004, 0xffffffff,
564 0x00009254, 0x00010006, 0xffffffff,
565 0x00009258, 0x00090008, 0xffffffff,
566 0x0000925c, 0x00070000, 0xffffffff,
567 0x00009260, 0x00030002, 0xffffffff,
568 0x00009264, 0x00050004, 0xffffffff,
569 0x00009270, 0x00010006, 0xffffffff,
570 0x00009274, 0x00090008, 0xffffffff,
571 0x00009278, 0x00070000, 0xffffffff,
572 0x0000927c, 0x00030002, 0xffffffff,
573 0x00009280, 0x00050004, 0xffffffff,
574 0x0000928c, 0x00010006, 0xffffffff,
575 0x00009290, 0x00090008, 0xffffffff,
576 0x000092a8, 0x00070000, 0xffffffff,
577 0x000092ac, 0x00030002, 0xffffffff,
578 0x000092b0, 0x00050004, 0xffffffff,
579 0x000092bc, 0x00010006, 0xffffffff,
580 0x000092c0, 0x00090008, 0xffffffff,
581 0x000092c4, 0x00070000, 0xffffffff,
582 0x000092c8, 0x00030002, 0xffffffff,
583 0x000092cc, 0x00050004, 0xffffffff,
584 0x000092d8, 0x00010006, 0xffffffff,
585 0x000092dc, 0x00090008, 0xffffffff,
586 0x00009294, 0x00000000, 0xffffffff,
587 0x0000802c, 0xc0000000, 0xffffffff,
588 0x00003fc4, 0xc0000000, 0xffffffff,
589 0x000008f8, 0x00000010, 0xffffffff,
590 0x000008fc, 0x00000000, 0xffffffff,
591 0x000008f8, 0x00000011, 0xffffffff,
592 0x000008fc, 0x00000000, 0xffffffff,
593 0x000008f8, 0x00000012, 0xffffffff,
594 0x000008fc, 0x00000000, 0xffffffff,
595 0x000008f8, 0x00000013, 0xffffffff,
596 0x000008fc, 0x00000000, 0xffffffff,
597 0x000008f8, 0x00000014, 0xffffffff,
598 0x000008fc, 0x00000000, 0xffffffff,
599 0x000008f8, 0x00000015, 0xffffffff,
600 0x000008fc, 0x00000000, 0xffffffff,
601 0x000008f8, 0x00000016, 0xffffffff,
602 0x000008fc, 0x00000000, 0xffffffff,
603 0x000008f8, 0x00000017, 0xffffffff,
604 0x000008fc, 0x00000000, 0xffffffff,
605 0x000008f8, 0x00000018, 0xffffffff,
606 0x000008fc, 0x00000000, 0xffffffff,
607 0x000008f8, 0x00000019, 0xffffffff,
608 0x000008fc, 0x00000000, 0xffffffff,
609 0x000008f8, 0x0000001a, 0xffffffff,
610 0x000008fc, 0x00000000, 0xffffffff,
611 0x000008f8, 0x0000001b, 0xffffffff,
612 0x000008fc, 0x00000000, 0xffffffff
614 #define CAYMAN_MGCG_DEFAULT_LENGTH sizeof(cayman_mgcg_default) / (3 * sizeof(u32))
616 static const u32 cayman_mgcg_disable[] =
618 0x0000802c, 0xc0000000, 0xffffffff,
619 0x000008f8, 0x00000000, 0xffffffff,
620 0x000008fc, 0xffffffff, 0xffffffff,
621 0x000008f8, 0x00000001, 0xffffffff,
622 0x000008fc, 0xffffffff, 0xffffffff,
623 0x000008f8, 0x00000002, 0xffffffff,
624 0x000008fc, 0xffffffff, 0xffffffff,
625 0x000008f8, 0x00000003, 0xffffffff,
626 0x000008fc, 0xffffffff, 0xffffffff,
627 0x00009150, 0x00600000, 0xffffffff
629 #define CAYMAN_MGCG_DISABLE_LENGTH sizeof(cayman_mgcg_disable) / (3 * sizeof(u32))
631 static const u32 cayman_mgcg_enable[] =
633 0x0000802c, 0xc0000000, 0xffffffff,
634 0x000008f8, 0x00000000, 0xffffffff,
635 0x000008fc, 0x00000000, 0xffffffff,
636 0x000008f8, 0x00000001, 0xffffffff,
637 0x000008fc, 0x00000000, 0xffffffff,
638 0x000008f8, 0x00000002, 0xffffffff,
639 0x000008fc, 0x00600000, 0xffffffff,
640 0x000008f8, 0x00000003, 0xffffffff,
641 0x000008fc, 0x00000000, 0xffffffff,
642 0x00009150, 0x96944200, 0xffffffff
645 #define CAYMAN_MGCG_ENABLE_LENGTH sizeof(cayman_mgcg_enable) / (3 * sizeof(u32))
647 #define NISLANDS_SYSLS_SEQUENCE 100
649 static const u32 cayman_sysls_default[] =
651 /* Register, Value, Mask bits */
652 0x000055e8, 0x00000000, 0xffffffff,
653 0x0000d0bc, 0x00000000, 0xffffffff,
654 0x0000d8bc, 0x00000000, 0xffffffff,
655 0x000015c0, 0x000c1401, 0xffffffff,
656 0x0000264c, 0x000c0400, 0xffffffff,
657 0x00002648, 0x000c0400, 0xffffffff,
658 0x00002650, 0x000c0400, 0xffffffff,
659 0x000020b8, 0x000c0400, 0xffffffff,
660 0x000020bc, 0x000c0400, 0xffffffff,
661 0x000020c0, 0x000c0c80, 0xffffffff,
662 0x0000f4a0, 0x000000c0, 0xffffffff,
663 0x0000f4a4, 0x00680fff, 0xffffffff,
664 0x00002f50, 0x00000404, 0xffffffff,
665 0x000004c8, 0x00000001, 0xffffffff,
666 0x000064ec, 0x00000000, 0xffffffff,
667 0x00000c7c, 0x00000000, 0xffffffff,
668 0x00008dfc, 0x00000000, 0xffffffff
670 #define CAYMAN_SYSLS_DEFAULT_LENGTH sizeof(cayman_sysls_default) / (3 * sizeof(u32))
672 static const u32 cayman_sysls_disable[] =
674 /* Register, Value, Mask bits */
675 0x0000d0c0, 0x00000000, 0xffffffff,
676 0x0000d8c0, 0x00000000, 0xffffffff,
677 0x000055e8, 0x00000000, 0xffffffff,
678 0x0000d0bc, 0x00000000, 0xffffffff,
679 0x0000d8bc, 0x00000000, 0xffffffff,
680 0x000015c0, 0x00041401, 0xffffffff,
681 0x0000264c, 0x00040400, 0xffffffff,
682 0x00002648, 0x00040400, 0xffffffff,
683 0x00002650, 0x00040400, 0xffffffff,
684 0x000020b8, 0x00040400, 0xffffffff,
685 0x000020bc, 0x00040400, 0xffffffff,
686 0x000020c0, 0x00040c80, 0xffffffff,
687 0x0000f4a0, 0x000000c0, 0xffffffff,
688 0x0000f4a4, 0x00680000, 0xffffffff,
689 0x00002f50, 0x00000404, 0xffffffff,
690 0x000004c8, 0x00000001, 0xffffffff,
691 0x000064ec, 0x00007ffd, 0xffffffff,
692 0x00000c7c, 0x0000ff00, 0xffffffff,
693 0x00008dfc, 0x0000007f, 0xffffffff
695 #define CAYMAN_SYSLS_DISABLE_LENGTH sizeof(cayman_sysls_disable) / (3 * sizeof(u32))
697 static const u32 cayman_sysls_enable[] =
699 /* Register, Value, Mask bits */
700 0x000055e8, 0x00000001, 0xffffffff,
701 0x0000d0bc, 0x00000100, 0xffffffff,
702 0x0000d8bc, 0x00000100, 0xffffffff,
703 0x000015c0, 0x000c1401, 0xffffffff,
704 0x0000264c, 0x000c0400, 0xffffffff,
705 0x00002648, 0x000c0400, 0xffffffff,
706 0x00002650, 0x000c0400, 0xffffffff,
707 0x000020b8, 0x000c0400, 0xffffffff,
708 0x000020bc, 0x000c0400, 0xffffffff,
709 0x000020c0, 0x000c0c80, 0xffffffff,
710 0x0000f4a0, 0x000000c0, 0xffffffff,
711 0x0000f4a4, 0x00680fff, 0xffffffff,
712 0x00002f50, 0x00000903, 0xffffffff,
713 0x000004c8, 0x00000000, 0xffffffff,
714 0x000064ec, 0x00000000, 0xffffffff,
715 0x00000c7c, 0x00000000, 0xffffffff,
716 0x00008dfc, 0x00000000, 0xffffffff
718 #define CAYMAN_SYSLS_ENABLE_LENGTH sizeof(cayman_sysls_enable) / (3 * sizeof(u32))
720 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
721 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
723 struct ni_power_info *ni_get_pi(struct radeon_device *rdev)
725 struct ni_power_info *pi = rdev->pm.dpm.priv;
730 struct ni_ps *ni_get_ps(struct radeon_ps *rps)
732 struct ni_ps *ps = rps->ps_priv;
737 static void ni_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
742 s64 kt, kv, leakage_w, i_leakage, vddc, temperature;
744 i_leakage = div64_s64(drm_int2fixp(ileakage), 1000);
745 vddc = div64_s64(drm_int2fixp(v), 1000);
746 temperature = div64_s64(drm_int2fixp(t), 1000);
748 kt = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->at), 1000),
749 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bt), 1000), temperature)));
750 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 1000),
751 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 1000), vddc)));
753 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
755 *leakage = drm_fixp2int(leakage_w * 1000);
758 static void ni_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
759 const struct ni_leakage_coeffients *coeff,
765 ni_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
768 bool ni_dpm_vblank_too_short(struct radeon_device *rdev)
770 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
771 u32 vblank_time = r600_dpm_get_vblank_time(rdev);
772 /* we never hit the non-gddr5 limit so disable it */
773 u32 switch_limit = pi->mem_gddr5 ? 450 : 0;
775 if (vblank_time < switch_limit)
782 static void ni_apply_state_adjust_rules(struct radeon_device *rdev,
783 struct radeon_ps *rps)
785 struct ni_ps *ps = ni_get_ps(rps);
786 struct radeon_clock_and_voltage_limits *max_limits;
787 bool disable_mclk_switching;
792 if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
793 ni_dpm_vblank_too_short(rdev))
794 disable_mclk_switching = true;
796 disable_mclk_switching = false;
798 if (rdev->pm.dpm.ac_power)
799 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
801 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
803 if (rdev->pm.dpm.ac_power == false) {
804 for (i = 0; i < ps->performance_level_count; i++) {
805 if (ps->performance_levels[i].mclk > max_limits->mclk)
806 ps->performance_levels[i].mclk = max_limits->mclk;
807 if (ps->performance_levels[i].sclk > max_limits->sclk)
808 ps->performance_levels[i].sclk = max_limits->sclk;
809 if (ps->performance_levels[i].vddc > max_limits->vddc)
810 ps->performance_levels[i].vddc = max_limits->vddc;
811 if (ps->performance_levels[i].vddci > max_limits->vddci)
812 ps->performance_levels[i].vddci = max_limits->vddci;
816 /* XXX validate the min clocks required for display */
818 if (disable_mclk_switching) {
819 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
820 sclk = ps->performance_levels[0].sclk;
821 vddc = ps->performance_levels[0].vddc;
822 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
824 sclk = ps->performance_levels[0].sclk;
825 mclk = ps->performance_levels[0].mclk;
826 vddc = ps->performance_levels[0].vddc;
827 vddci = ps->performance_levels[0].vddci;
830 /* adjusted low state */
831 ps->performance_levels[0].sclk = sclk;
832 ps->performance_levels[0].mclk = mclk;
833 ps->performance_levels[0].vddc = vddc;
834 ps->performance_levels[0].vddci = vddci;
836 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
837 &ps->performance_levels[0].sclk,
838 &ps->performance_levels[0].mclk);
840 for (i = 1; i < ps->performance_level_count; i++) {
841 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
842 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
843 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
844 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
847 if (disable_mclk_switching) {
848 mclk = ps->performance_levels[0].mclk;
849 for (i = 1; i < ps->performance_level_count; i++) {
850 if (mclk < ps->performance_levels[i].mclk)
851 mclk = ps->performance_levels[i].mclk;
853 for (i = 0; i < ps->performance_level_count; i++) {
854 ps->performance_levels[i].mclk = mclk;
855 ps->performance_levels[i].vddci = vddci;
858 for (i = 1; i < ps->performance_level_count; i++) {
859 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
860 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
861 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
862 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
866 for (i = 1; i < ps->performance_level_count; i++)
867 btc_skip_blacklist_clocks(rdev, max_limits->sclk, max_limits->mclk,
868 &ps->performance_levels[i].sclk,
869 &ps->performance_levels[i].mclk);
871 for (i = 0; i < ps->performance_level_count; i++)
872 btc_adjust_clock_combinations(rdev, max_limits,
873 &ps->performance_levels[i]);
875 for (i = 0; i < ps->performance_level_count; i++) {
876 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
877 ps->performance_levels[i].sclk,
878 max_limits->vddc, &ps->performance_levels[i].vddc);
879 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
880 ps->performance_levels[i].mclk,
881 max_limits->vddci, &ps->performance_levels[i].vddci);
882 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
883 ps->performance_levels[i].mclk,
884 max_limits->vddc, &ps->performance_levels[i].vddc);
885 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
886 rdev->clock.current_dispclk,
887 max_limits->vddc, &ps->performance_levels[i].vddc);
890 for (i = 0; i < ps->performance_level_count; i++) {
891 btc_apply_voltage_delta_rules(rdev,
892 max_limits->vddc, max_limits->vddci,
893 &ps->performance_levels[i].vddc,
894 &ps->performance_levels[i].vddci);
897 ps->dc_compatible = true;
898 for (i = 0; i < ps->performance_level_count; i++) {
899 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
900 ps->dc_compatible = false;
902 if (ps->performance_levels[i].vddc < rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2)
903 ps->performance_levels[i].flags &= ~ATOM_PPLIB_R600_FLAGS_PCIEGEN2;
907 static void ni_cg_clockgating_default(struct radeon_device *rdev)
910 const u32 *ps = NULL;
912 ps = (const u32 *)&cayman_cgcg_cgls_default;
913 count = CAYMAN_CGCG_CGLS_DEFAULT_LENGTH;
915 btc_program_mgcg_hw_sequence(rdev, ps, count);
918 static void ni_gfx_clockgating_enable(struct radeon_device *rdev,
922 const u32 *ps = NULL;
925 ps = (const u32 *)&cayman_cgcg_cgls_enable;
926 count = CAYMAN_CGCG_CGLS_ENABLE_LENGTH;
928 ps = (const u32 *)&cayman_cgcg_cgls_disable;
929 count = CAYMAN_CGCG_CGLS_DISABLE_LENGTH;
932 btc_program_mgcg_hw_sequence(rdev, ps, count);
935 static void ni_mg_clockgating_default(struct radeon_device *rdev)
938 const u32 *ps = NULL;
940 ps = (const u32 *)&cayman_mgcg_default;
941 count = CAYMAN_MGCG_DEFAULT_LENGTH;
943 btc_program_mgcg_hw_sequence(rdev, ps, count);
946 static void ni_mg_clockgating_enable(struct radeon_device *rdev,
950 const u32 *ps = NULL;
953 ps = (const u32 *)&cayman_mgcg_enable;
954 count = CAYMAN_MGCG_ENABLE_LENGTH;
956 ps = (const u32 *)&cayman_mgcg_disable;
957 count = CAYMAN_MGCG_DISABLE_LENGTH;
960 btc_program_mgcg_hw_sequence(rdev, ps, count);
963 static void ni_ls_clockgating_default(struct radeon_device *rdev)
966 const u32 *ps = NULL;
968 ps = (const u32 *)&cayman_sysls_default;
969 count = CAYMAN_SYSLS_DEFAULT_LENGTH;
971 btc_program_mgcg_hw_sequence(rdev, ps, count);
974 static void ni_ls_clockgating_enable(struct radeon_device *rdev,
978 const u32 *ps = NULL;
981 ps = (const u32 *)&cayman_sysls_enable;
982 count = CAYMAN_SYSLS_ENABLE_LENGTH;
984 ps = (const u32 *)&cayman_sysls_disable;
985 count = CAYMAN_SYSLS_DISABLE_LENGTH;
988 btc_program_mgcg_hw_sequence(rdev, ps, count);
992 static int ni_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
993 struct radeon_clock_voltage_dependency_table *table)
995 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
999 for (i = 0; i < table->count; i++) {
1000 if (0xff01 == table->entries[i].v) {
1001 if (pi->max_vddc == 0)
1003 table->entries[i].v = pi->max_vddc;
1010 static int ni_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
1014 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1015 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
1017 ret = ni_patch_single_dependency_table_based_on_leakage(rdev,
1018 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
1022 static void ni_stop_dpm(struct radeon_device *rdev)
1024 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
1028 static int ni_notify_hw_of_power_source(struct radeon_device *rdev,
1032 return (rv770_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
1039 static PPSMC_Result ni_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
1040 PPSMC_Msg msg, u32 parameter)
1042 WREG32(SMC_SCRATCH0, parameter);
1043 return rv770_send_msg_to_smc(rdev, msg);
1046 static int ni_restrict_performance_levels_before_switch(struct radeon_device *rdev)
1048 if (rv770_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
1051 return (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
1055 int ni_dpm_force_performance_level(struct radeon_device *rdev,
1056 enum radeon_dpm_forced_level level)
1058 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
1059 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
1062 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
1064 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
1065 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
1068 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
1070 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
1071 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
1074 if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
1078 rdev->pm.dpm.forced_level = level;
1083 static void ni_stop_smc(struct radeon_device *rdev)
1088 for (i = 0; i < rdev->usec_timeout; i++) {
1089 tmp = RREG32(LB_SYNC_RESET_SEL) & LB_SYNC_RESET_SEL_MASK;
1097 r7xx_stop_smc(rdev);
1100 static int ni_process_firmware_header(struct radeon_device *rdev)
1102 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1103 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1104 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1108 ret = rv770_read_smc_sram_dword(rdev,
1109 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1110 NISLANDS_SMC_FIRMWARE_HEADER_stateTable,
1111 &tmp, pi->sram_end);
1116 pi->state_table_start = (u16)tmp;
1118 ret = rv770_read_smc_sram_dword(rdev,
1119 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1120 NISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
1121 &tmp, pi->sram_end);
1126 pi->soft_regs_start = (u16)tmp;
1128 ret = rv770_read_smc_sram_dword(rdev,
1129 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1130 NISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
1131 &tmp, pi->sram_end);
1136 eg_pi->mc_reg_table_start = (u16)tmp;
1138 ret = rv770_read_smc_sram_dword(rdev,
1139 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1140 NISLANDS_SMC_FIRMWARE_HEADER_fanTable,
1141 &tmp, pi->sram_end);
1146 ni_pi->fan_table_start = (u16)tmp;
1148 ret = rv770_read_smc_sram_dword(rdev,
1149 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1150 NISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
1151 &tmp, pi->sram_end);
1156 ni_pi->arb_table_start = (u16)tmp;
1158 ret = rv770_read_smc_sram_dword(rdev,
1159 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1160 NISLANDS_SMC_FIRMWARE_HEADER_cacTable,
1161 &tmp, pi->sram_end);
1166 ni_pi->cac_table_start = (u16)tmp;
1168 ret = rv770_read_smc_sram_dword(rdev,
1169 NISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
1170 NISLANDS_SMC_FIRMWARE_HEADER_spllTable,
1171 &tmp, pi->sram_end);
1176 ni_pi->spll_table_start = (u16)tmp;
1182 static void ni_read_clock_registers(struct radeon_device *rdev)
1184 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1186 ni_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
1187 ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
1188 ni_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
1189 ni_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
1190 ni_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
1191 ni_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
1192 ni_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
1193 ni_pi->clock_registers.mpll_ad_func_cntl_2 = RREG32(MPLL_AD_FUNC_CNTL_2);
1194 ni_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
1195 ni_pi->clock_registers.mpll_dq_func_cntl_2 = RREG32(MPLL_DQ_FUNC_CNTL_2);
1196 ni_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
1197 ni_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
1198 ni_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
1199 ni_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
1203 static int ni_enter_ulp_state(struct radeon_device *rdev)
1205 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1207 if (pi->gfx_clock_gating) {
1208 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
1209 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
1210 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
1211 RREG32(GB_ADDR_CONFIG);
1214 WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
1215 ~HOST_SMC_MSG_MASK);
1223 static void ni_program_response_times(struct radeon_device *rdev)
1225 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
1226 u32 vddc_dly, bb_dly, acpi_dly, vbi_dly, mclk_switch_limit;
1227 u32 reference_clock;
1229 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
1231 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
1232 backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
1234 if (voltage_response_time == 0)
1235 voltage_response_time = 1000;
1237 if (backbias_response_time == 0)
1238 backbias_response_time = 1000;
1240 acpi_delay_time = 15000;
1241 vbi_time_out = 100000;
1243 reference_clock = radeon_get_xclk(rdev);
1245 vddc_dly = (voltage_response_time * reference_clock) / 1600;
1246 bb_dly = (backbias_response_time * reference_clock) / 1600;
1247 acpi_dly = (acpi_delay_time * reference_clock) / 1600;
1248 vbi_dly = (vbi_time_out * reference_clock) / 1600;
1250 mclk_switch_limit = (460 * reference_clock) / 100;
1252 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
1253 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_bbias, bb_dly);
1254 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
1255 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
1256 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
1257 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_mclk_switch_lim, mclk_switch_limit);
1260 static void ni_populate_smc_voltage_table(struct radeon_device *rdev,
1261 struct atom_voltage_table *voltage_table,
1262 NISLANDS_SMC_STATETABLE *table)
1266 for (i = 0; i < voltage_table->count; i++) {
1267 table->highSMIO[i] = 0;
1268 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
1272 static void ni_populate_smc_voltage_tables(struct radeon_device *rdev,
1273 NISLANDS_SMC_STATETABLE *table)
1275 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1276 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1279 if (eg_pi->vddc_voltage_table.count) {
1280 ni_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
1281 table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] = 0;
1282 table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDC] =
1283 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1285 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
1286 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
1287 table->maxVDDCIndexInPPTable = i;
1293 if (eg_pi->vddci_voltage_table.count) {
1294 ni_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
1296 table->voltageMaskTable.highMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] = 0;
1297 table->voltageMaskTable.lowMask[NISLANDS_SMC_VOLTAGEMASK_VDDCI] =
1298 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
1302 static int ni_populate_voltage_value(struct radeon_device *rdev,
1303 struct atom_voltage_table *table,
1305 NISLANDS_SMC_VOLTAGE_VALUE *voltage)
1309 for (i = 0; i < table->count; i++) {
1310 if (value <= table->entries[i].value) {
1311 voltage->index = (u8)i;
1312 voltage->value = cpu_to_be16(table->entries[i].value);
1317 if (i >= table->count)
1323 static void ni_populate_mvdd_value(struct radeon_device *rdev,
1325 NISLANDS_SMC_VOLTAGE_VALUE *voltage)
1327 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1328 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1330 if (!pi->mvdd_control) {
1331 voltage->index = eg_pi->mvdd_high_index;
1332 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1336 if (mclk <= pi->mvdd_split_frequency) {
1337 voltage->index = eg_pi->mvdd_low_index;
1338 voltage->value = cpu_to_be16(MVDD_LOW_VALUE);
1340 voltage->index = eg_pi->mvdd_high_index;
1341 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1345 static int ni_get_std_voltage_value(struct radeon_device *rdev,
1346 NISLANDS_SMC_VOLTAGE_VALUE *voltage,
1349 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries &&
1350 ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count))
1351 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
1353 *std_voltage = be16_to_cpu(voltage->value);
1358 static void ni_populate_std_voltage_value(struct radeon_device *rdev,
1359 u16 value, u8 index,
1360 NISLANDS_SMC_VOLTAGE_VALUE *voltage)
1362 voltage->index = index;
1363 voltage->value = cpu_to_be16(value);
1366 static u32 ni_get_smc_power_scaling_factor(struct radeon_device *rdev)
1369 u32 xclk = radeon_get_xclk(rdev);
1370 u32 tmp = RREG32(CG_CAC_CTRL) & TID_CNT_MASK;
1372 xclk_period = (1000000000UL / xclk);
1373 xclk_period /= 10000UL;
1375 return tmp * xclk_period;
1378 static u32 ni_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
1380 return (power_in_watts * scaling_factor) << 2;
1383 static u32 ni_calculate_power_boost_limit(struct radeon_device *rdev,
1384 struct radeon_ps *radeon_state,
1387 struct ni_ps *state = ni_get_ps(radeon_state);
1388 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1389 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1390 u32 power_boost_limit = 0;
1393 if (ni_pi->enable_power_containment &&
1394 ni_pi->use_power_boost_limit) {
1395 NISLANDS_SMC_VOLTAGE_VALUE vddc;
1400 if (state->performance_level_count < 3)
1403 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1404 state->performance_levels[state->performance_level_count - 2].vddc,
1409 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_med);
1413 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1414 state->performance_levels[state->performance_level_count - 1].vddc,
1419 ret = ni_get_std_voltage_value(rdev, &vddc, &std_vddc_high);
1423 n = ((u64)near_tdp_limit * ((u64)std_vddc_med * (u64)std_vddc_med) * 90);
1424 d = ((u64)std_vddc_high * (u64)std_vddc_high * 100);
1425 tmp = div64_u64(n, d);
1429 power_boost_limit = (u32)tmp;
1432 return power_boost_limit;
1435 static int ni_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
1436 bool adjust_polarity,
1439 u32 *near_tdp_limit)
1441 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
1444 if (adjust_polarity) {
1445 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
1446 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit + (*tdp_limit - rdev->pm.dpm.tdp_limit);
1448 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
1449 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit - (rdev->pm.dpm.tdp_limit - *tdp_limit);
1455 static int ni_populate_smc_tdp_limits(struct radeon_device *rdev,
1456 struct radeon_ps *radeon_state)
1458 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1459 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1461 if (ni_pi->enable_power_containment) {
1462 NISLANDS_SMC_STATETABLE *smc_table = &ni_pi->smc_statetable;
1463 u32 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
1466 u32 power_boost_limit;
1469 if (scaling_factor == 0)
1472 memset(smc_table, 0, sizeof(NISLANDS_SMC_STATETABLE));
1474 ret = ni_calculate_adjusted_tdp_limits(rdev,
1476 rdev->pm.dpm.tdp_adjustment,
1482 power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state,
1485 smc_table->dpm2Params.TDPLimit =
1486 cpu_to_be32(ni_scale_power_for_smc(tdp_limit, scaling_factor));
1487 smc_table->dpm2Params.NearTDPLimit =
1488 cpu_to_be32(ni_scale_power_for_smc(near_tdp_limit, scaling_factor));
1489 smc_table->dpm2Params.SafePowerLimit =
1490 cpu_to_be32(ni_scale_power_for_smc((near_tdp_limit * NISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100,
1492 smc_table->dpm2Params.PowerBoostLimit =
1493 cpu_to_be32(ni_scale_power_for_smc(power_boost_limit, scaling_factor));
1495 ret = rv770_copy_bytes_to_smc(rdev,
1496 (u16)(pi->state_table_start + offsetof(NISLANDS_SMC_STATETABLE, dpm2Params) +
1497 offsetof(PP_NIslands_DPM2Parameters, TDPLimit)),
1498 (u8 *)(&smc_table->dpm2Params.TDPLimit),
1499 sizeof(u32) * 4, pi->sram_end);
1507 int ni_copy_and_switch_arb_sets(struct radeon_device *rdev,
1508 u32 arb_freq_src, u32 arb_freq_dest)
1510 u32 mc_arb_dram_timing;
1511 u32 mc_arb_dram_timing2;
1515 switch (arb_freq_src) {
1516 case MC_CG_ARB_FREQ_F0:
1517 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
1518 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
1519 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
1521 case MC_CG_ARB_FREQ_F1:
1522 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
1523 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
1524 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
1526 case MC_CG_ARB_FREQ_F2:
1527 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
1528 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
1529 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
1531 case MC_CG_ARB_FREQ_F3:
1532 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
1533 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
1534 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
1540 switch (arb_freq_dest) {
1541 case MC_CG_ARB_FREQ_F0:
1542 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
1543 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
1544 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
1546 case MC_CG_ARB_FREQ_F1:
1547 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
1548 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
1549 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
1551 case MC_CG_ARB_FREQ_F2:
1552 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
1553 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
1554 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
1556 case MC_CG_ARB_FREQ_F3:
1557 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
1558 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
1559 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
1565 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
1566 WREG32(MC_CG_CONFIG, mc_cg_config);
1567 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
1572 static int ni_init_arb_table_index(struct radeon_device *rdev)
1574 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1575 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1579 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1580 &tmp, pi->sram_end);
1585 tmp |= ((u32)MC_CG_ARB_FREQ_F1) << 24;
1587 return rv770_write_smc_sram_dword(rdev, ni_pi->arb_table_start,
1591 static int ni_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
1593 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
1596 static int ni_force_switch_to_arb_f0(struct radeon_device *rdev)
1598 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1599 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1603 ret = rv770_read_smc_sram_dword(rdev, ni_pi->arb_table_start,
1604 &tmp, pi->sram_end);
1608 tmp = (tmp >> 24) & 0xff;
1610 if (tmp == MC_CG_ARB_FREQ_F0)
1613 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
1616 static int ni_populate_memory_timing_parameters(struct radeon_device *rdev,
1617 struct rv7xx_pl *pl,
1618 SMC_NIslands_MCArbDramTimingRegisterSet *arb_regs)
1623 arb_regs->mc_arb_rfsh_rate =
1624 (u8)rv770_calculate_memory_refresh_rate(rdev, pl->sclk);
1627 radeon_atom_set_engine_dram_timings(rdev,
1631 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
1632 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
1634 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
1635 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
1640 static int ni_do_program_memory_timing_parameters(struct radeon_device *rdev,
1641 struct radeon_ps *radeon_state,
1642 unsigned int first_arb_set)
1644 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1645 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1646 struct ni_ps *state = ni_get_ps(radeon_state);
1647 SMC_NIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
1650 for (i = 0; i < state->performance_level_count; i++) {
1651 ret = ni_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
1655 ret = rv770_copy_bytes_to_smc(rdev,
1656 (u16)(ni_pi->arb_table_start +
1657 offsetof(SMC_NIslands_MCArbDramTimingRegisters, data) +
1658 sizeof(SMC_NIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i)),
1660 (u16)sizeof(SMC_NIslands_MCArbDramTimingRegisterSet),
1668 static int ni_program_memory_timing_parameters(struct radeon_device *rdev,
1669 struct radeon_ps *radeon_new_state)
1671 return ni_do_program_memory_timing_parameters(rdev, radeon_new_state,
1672 NISLANDS_DRIVER_STATE_ARB_INDEX);
1675 static void ni_populate_initial_mvdd_value(struct radeon_device *rdev,
1676 struct NISLANDS_SMC_VOLTAGE_VALUE *voltage)
1678 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1680 voltage->index = eg_pi->mvdd_high_index;
1681 voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
1684 static int ni_populate_smc_initial_state(struct radeon_device *rdev,
1685 struct radeon_ps *radeon_initial_state,
1686 NISLANDS_SMC_STATETABLE *table)
1688 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
1689 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1690 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1691 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1695 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
1696 cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl);
1697 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 =
1698 cpu_to_be32(ni_pi->clock_registers.mpll_ad_func_cntl_2);
1699 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
1700 cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl);
1701 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 =
1702 cpu_to_be32(ni_pi->clock_registers.mpll_dq_func_cntl_2);
1703 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
1704 cpu_to_be32(ni_pi->clock_registers.mclk_pwrmgt_cntl);
1705 table->initialState.levels[0].mclk.vDLL_CNTL =
1706 cpu_to_be32(ni_pi->clock_registers.dll_cntl);
1707 table->initialState.levels[0].mclk.vMPLL_SS =
1708 cpu_to_be32(ni_pi->clock_registers.mpll_ss1);
1709 table->initialState.levels[0].mclk.vMPLL_SS2 =
1710 cpu_to_be32(ni_pi->clock_registers.mpll_ss2);
1711 table->initialState.levels[0].mclk.mclk_value =
1712 cpu_to_be32(initial_state->performance_levels[0].mclk);
1714 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
1715 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl);
1716 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
1717 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_2);
1718 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
1719 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_3);
1720 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
1721 cpu_to_be32(ni_pi->clock_registers.cg_spll_func_cntl_4);
1722 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
1723 cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum);
1724 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
1725 cpu_to_be32(ni_pi->clock_registers.cg_spll_spread_spectrum_2);
1726 table->initialState.levels[0].sclk.sclk_value =
1727 cpu_to_be32(initial_state->performance_levels[0].sclk);
1728 table->initialState.levels[0].arbRefreshState =
1729 NISLANDS_INITIAL_STATE_ARB_INDEX;
1731 table->initialState.levels[0].ACIndex = 0;
1733 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
1734 initial_state->performance_levels[0].vddc,
1735 &table->initialState.levels[0].vddc);
1739 ret = ni_get_std_voltage_value(rdev,
1740 &table->initialState.levels[0].vddc,
1743 ni_populate_std_voltage_value(rdev, std_vddc,
1744 table->initialState.levels[0].vddc.index,
1745 &table->initialState.levels[0].std_vddc);
1748 if (eg_pi->vddci_control)
1749 ni_populate_voltage_value(rdev,
1750 &eg_pi->vddci_voltage_table,
1751 initial_state->performance_levels[0].vddci,
1752 &table->initialState.levels[0].vddci);
1754 ni_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
1756 reg = CG_R(0xffff) | CG_L(0);
1757 table->initialState.levels[0].aT = cpu_to_be32(reg);
1759 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
1761 if (pi->boot_in_gen2)
1762 table->initialState.levels[0].gen2PCIE = 1;
1764 table->initialState.levels[0].gen2PCIE = 0;
1766 if (pi->mem_gddr5) {
1767 table->initialState.levels[0].strobeMode =
1768 cypress_get_strobe_mode_settings(rdev,
1769 initial_state->performance_levels[0].mclk);
1771 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
1772 table->initialState.levels[0].mcFlags = NISLANDS_SMC_MC_EDC_RD_FLAG | NISLANDS_SMC_MC_EDC_WR_FLAG;
1774 table->initialState.levels[0].mcFlags = 0;
1777 table->initialState.levelCount = 1;
1779 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
1781 table->initialState.levels[0].dpm2.MaxPS = 0;
1782 table->initialState.levels[0].dpm2.NearTDPDec = 0;
1783 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
1784 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
1786 reg = MIN_POWER_MASK | MAX_POWER_MASK;
1787 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
1789 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
1790 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
1795 static int ni_populate_smc_acpi_state(struct radeon_device *rdev,
1796 NISLANDS_SMC_STATETABLE *table)
1798 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1799 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
1800 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1801 u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl;
1802 u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;
1803 u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl;
1804 u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;
1805 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;
1806 u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;
1807 u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;
1808 u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4;
1809 u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl;
1810 u32 dll_cntl = ni_pi->clock_registers.dll_cntl;
1814 table->ACPIState = table->initialState;
1816 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
1818 if (pi->acpi_vddc) {
1819 ret = ni_populate_voltage_value(rdev,
1820 &eg_pi->vddc_voltage_table,
1821 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
1825 ret = ni_get_std_voltage_value(rdev,
1826 &table->ACPIState.levels[0].vddc, &std_vddc);
1828 ni_populate_std_voltage_value(rdev, std_vddc,
1829 table->ACPIState.levels[0].vddc.index,
1830 &table->ACPIState.levels[0].std_vddc);
1833 if (pi->pcie_gen2) {
1834 if (pi->acpi_pcie_gen2)
1835 table->ACPIState.levels[0].gen2PCIE = 1;
1837 table->ACPIState.levels[0].gen2PCIE = 0;
1839 table->ACPIState.levels[0].gen2PCIE = 0;
1842 ret = ni_populate_voltage_value(rdev,
1843 &eg_pi->vddc_voltage_table,
1844 pi->min_vddc_in_table,
1845 &table->ACPIState.levels[0].vddc);
1849 ret = ni_get_std_voltage_value(rdev,
1850 &table->ACPIState.levels[0].vddc,
1853 ni_populate_std_voltage_value(rdev, std_vddc,
1854 table->ACPIState.levels[0].vddc.index,
1855 &table->ACPIState.levels[0].std_vddc);
1857 table->ACPIState.levels[0].gen2PCIE = 0;
1860 if (eg_pi->acpi_vddci) {
1861 if (eg_pi->vddci_control)
1862 ni_populate_voltage_value(rdev,
1863 &eg_pi->vddci_voltage_table,
1865 &table->ACPIState.levels[0].vddci);
1869 mpll_ad_func_cntl &= ~PDNB;
1871 mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN;
1874 mpll_dq_func_cntl &= ~PDNB;
1875 mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS;
1878 mclk_pwrmgt_cntl |= (MRDCKA0_RESET |
1887 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
1896 dll_cntl |= (MRDCKA0_BYPASS |
1905 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
1906 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
1908 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
1909 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
1910 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
1911 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
1912 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
1913 table->ACPIState.levels[0].mclk.vDLL_CNTL = cpu_to_be32(dll_cntl);
1915 table->ACPIState.levels[0].mclk.mclk_value = 0;
1917 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl);
1918 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2);
1919 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3);
1920 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(spll_func_cntl_4);
1922 table->ACPIState.levels[0].sclk.sclk_value = 0;
1924 ni_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
1926 if (eg_pi->dynamic_ac_timing)
1927 table->ACPIState.levels[0].ACIndex = 1;
1929 table->ACPIState.levels[0].dpm2.MaxPS = 0;
1930 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
1931 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
1932 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
1934 reg = MIN_POWER_MASK | MAX_POWER_MASK;
1935 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
1937 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
1938 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
1943 static int ni_init_smc_table(struct radeon_device *rdev)
1945 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
1946 struct ni_power_info *ni_pi = ni_get_pi(rdev);
1948 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
1949 NISLANDS_SMC_STATETABLE *table = &ni_pi->smc_statetable;
1951 memset(table, 0, sizeof(NISLANDS_SMC_STATETABLE));
1953 ni_populate_smc_voltage_tables(rdev, table);
1955 switch (rdev->pm.int_thermal_type) {
1956 case THERMAL_TYPE_NI:
1957 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
1958 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
1960 case THERMAL_TYPE_NONE:
1961 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
1964 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
1968 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
1969 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1971 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
1972 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
1974 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
1975 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1978 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1980 ret = ni_populate_smc_initial_state(rdev, radeon_boot_state, table);
1984 ret = ni_populate_smc_acpi_state(rdev, table);
1988 table->driverState = table->initialState;
1990 table->ULVState = table->initialState;
1992 ret = ni_do_program_memory_timing_parameters(rdev, radeon_boot_state,
1993 NISLANDS_INITIAL_STATE_ARB_INDEX);
1997 return rv770_copy_bytes_to_smc(rdev, pi->state_table_start, (u8 *)table,
1998 sizeof(NISLANDS_SMC_STATETABLE), pi->sram_end);
2001 static int ni_calculate_sclk_params(struct radeon_device *rdev,
2003 NISLANDS_SMC_SCLK_VALUE *sclk)
2005 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2006 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2007 struct atom_clock_dividers dividers;
2008 u32 spll_func_cntl = ni_pi->clock_registers.cg_spll_func_cntl;
2009 u32 spll_func_cntl_2 = ni_pi->clock_registers.cg_spll_func_cntl_2;
2010 u32 spll_func_cntl_3 = ni_pi->clock_registers.cg_spll_func_cntl_3;
2011 u32 spll_func_cntl_4 = ni_pi->clock_registers.cg_spll_func_cntl_4;
2012 u32 cg_spll_spread_spectrum = ni_pi->clock_registers.cg_spll_spread_spectrum;
2013 u32 cg_spll_spread_spectrum_2 = ni_pi->clock_registers.cg_spll_spread_spectrum_2;
2015 u32 reference_clock = rdev->clock.spll.reference_freq;
2016 u32 reference_divider;
2020 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2021 engine_clock, false, ÷rs);
2025 reference_divider = 1 + dividers.ref_div;
2028 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834;
2029 do_div(tmp, reference_clock);
2032 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
2033 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
2034 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
2036 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
2037 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
2039 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
2040 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
2041 spll_func_cntl_3 |= SPLL_DITHEN;
2044 struct radeon_atom_ss ss;
2045 u32 vco_freq = engine_clock * dividers.post_div;
2047 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2048 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
2049 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
2050 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
2052 cg_spll_spread_spectrum &= ~CLK_S_MASK;
2053 cg_spll_spread_spectrum |= CLK_S(clk_s);
2054 cg_spll_spread_spectrum |= SSEN;
2056 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
2057 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
2061 sclk->sclk_value = engine_clock;
2062 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
2063 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
2064 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
2065 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
2066 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
2067 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
2072 static int ni_populate_sclk_value(struct radeon_device *rdev,
2074 NISLANDS_SMC_SCLK_VALUE *sclk)
2076 NISLANDS_SMC_SCLK_VALUE sclk_tmp;
2079 ret = ni_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
2081 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
2082 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
2083 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
2084 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
2085 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
2086 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
2087 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
2093 static int ni_init_smc_spll_table(struct radeon_device *rdev)
2095 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2096 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2097 SMC_NISLANDS_SPLL_DIV_TABLE *spll_table;
2098 NISLANDS_SMC_SCLK_VALUE sclk_params;
2107 if (ni_pi->spll_table_start == 0)
2110 spll_table = kzalloc(sizeof(SMC_NISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2111 if (spll_table == NULL)
2114 for (i = 0; i < 256; i++) {
2115 ret = ni_calculate_sclk_params(rdev, sclk, &sclk_params);
2119 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2120 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2121 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2122 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2124 fb_div &= ~0x00001FFF;
2128 if (p_div & ~(SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2131 if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2134 if (clk_s & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2137 if (clk_v & ~(SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2143 tmp = ((fb_div << SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2144 ((p_div << SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2145 spll_table->freq[i] = cpu_to_be32(tmp);
2147 tmp = ((clk_v << SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2148 ((clk_s << SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_NISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2149 spll_table->ss[i] = cpu_to_be32(tmp);
2155 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->spll_table_start, (u8 *)spll_table,
2156 sizeof(SMC_NISLANDS_SPLL_DIV_TABLE), pi->sram_end);
2163 static int ni_populate_mclk_value(struct radeon_device *rdev,
2166 NISLANDS_SMC_MCLK_VALUE *mclk,
2170 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2171 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2172 u32 mpll_ad_func_cntl = ni_pi->clock_registers.mpll_ad_func_cntl;
2173 u32 mpll_ad_func_cntl_2 = ni_pi->clock_registers.mpll_ad_func_cntl_2;
2174 u32 mpll_dq_func_cntl = ni_pi->clock_registers.mpll_dq_func_cntl;
2175 u32 mpll_dq_func_cntl_2 = ni_pi->clock_registers.mpll_dq_func_cntl_2;
2176 u32 mclk_pwrmgt_cntl = ni_pi->clock_registers.mclk_pwrmgt_cntl;
2177 u32 dll_cntl = ni_pi->clock_registers.dll_cntl;
2178 u32 mpll_ss1 = ni_pi->clock_registers.mpll_ss1;
2179 u32 mpll_ss2 = ni_pi->clock_registers.mpll_ss2;
2180 struct atom_clock_dividers dividers;
2186 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
2187 memory_clock, strobe_mode, ÷rs);
2192 mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
2194 if (mc_seq_misc7 & 0x8000000)
2195 dividers.post_div = 1;
2198 ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
2200 mpll_ad_func_cntl &= ~(CLKR_MASK |
2201 YCLK_POST_DIV_MASK |
2205 mpll_ad_func_cntl |= CLKR(dividers.ref_div);
2206 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
2207 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
2208 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
2209 mpll_ad_func_cntl |= IBIAS(ibias);
2211 if (dividers.vco_mode)
2212 mpll_ad_func_cntl_2 |= VCO_MODE;
2214 mpll_ad_func_cntl_2 &= ~VCO_MODE;
2216 if (pi->mem_gddr5) {
2217 mpll_dq_func_cntl &= ~(CLKR_MASK |
2218 YCLK_POST_DIV_MASK |
2222 mpll_dq_func_cntl |= CLKR(dividers.ref_div);
2223 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
2224 mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
2225 mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
2226 mpll_dq_func_cntl |= IBIAS(ibias);
2229 mpll_dq_func_cntl &= ~PDNB;
2231 mpll_dq_func_cntl |= PDNB;
2233 if (dividers.vco_mode)
2234 mpll_dq_func_cntl_2 |= VCO_MODE;
2236 mpll_dq_func_cntl_2 &= ~VCO_MODE;
2240 struct radeon_atom_ss ss;
2241 u32 vco_freq = memory_clock * dividers.post_div;
2243 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
2244 ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
2245 u32 reference_clock = rdev->clock.mpll.reference_freq;
2246 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
2247 u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
2248 u32 clk_v = ss.percentage *
2249 (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
2251 mpll_ss1 &= ~CLKV_MASK;
2252 mpll_ss1 |= CLKV(clk_v);
2254 mpll_ss2 &= ~CLKS_MASK;
2255 mpll_ss2 |= CLKS(clk_s);
2259 dll_speed = rv740_get_dll_speed(pi->mem_gddr5,
2262 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
2263 mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed);
2265 mclk_pwrmgt_cntl |= (MRDCKA0_PDNB |
2274 mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
2284 mclk->mclk_value = cpu_to_be32(memory_clock);
2285 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
2286 mclk->vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
2287 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
2288 mclk->vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
2289 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
2290 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
2291 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
2292 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
2297 static void ni_populate_smc_sp(struct radeon_device *rdev,
2298 struct radeon_ps *radeon_state,
2299 NISLANDS_SMC_SWSTATE *smc_state)
2301 struct ni_ps *ps = ni_get_ps(radeon_state);
2302 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2305 for (i = 0; i < ps->performance_level_count - 1; i++)
2306 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
2308 smc_state->levels[ps->performance_level_count - 1].bSP =
2309 cpu_to_be32(pi->psp);
2312 static int ni_convert_power_level_to_smc(struct radeon_device *rdev,
2313 struct rv7xx_pl *pl,
2314 NISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
2316 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2317 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2318 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2322 u32 tmp = RREG32(DC_STUTTER_CNTL);
2324 level->gen2PCIE = pi->pcie_gen2 ?
2325 ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
2327 ret = ni_populate_sclk_value(rdev, pl->sclk, &level->sclk);
2332 if (pi->mclk_stutter_mode_threshold &&
2333 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
2334 !eg_pi->uvd_enabled &&
2335 (tmp & DC_STUTTER_ENABLE_A) &&
2336 (tmp & DC_STUTTER_ENABLE_B))
2337 level->mcFlags |= NISLANDS_SMC_MC_STUTTER_EN;
2339 if (pi->mem_gddr5) {
2340 if (pl->mclk > pi->mclk_edc_enable_threshold)
2341 level->mcFlags |= NISLANDS_SMC_MC_EDC_RD_FLAG;
2342 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
2343 level->mcFlags |= NISLANDS_SMC_MC_EDC_WR_FLAG;
2345 level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
2347 if (level->strobeMode & NISLANDS_SMC_STROBE_ENABLE) {
2348 if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
2349 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
2350 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
2352 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
2354 dll_state_on = false;
2355 if (pl->mclk > ni_pi->mclk_rtt_mode_threshold)
2356 level->mcFlags |= NISLANDS_SMC_MC_RTT_ENABLE;
2359 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk,
2361 (level->strobeMode & NISLANDS_SMC_STROBE_ENABLE) != 0,
2364 ret = ni_populate_mclk_value(rdev, pl->sclk, pl->mclk, &level->mclk, 1, 1);
2369 ret = ni_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2370 pl->vddc, &level->vddc);
2374 ret = ni_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
2378 ni_populate_std_voltage_value(rdev, std_vddc,
2379 level->vddc.index, &level->std_vddc);
2381 if (eg_pi->vddci_control) {
2382 ret = ni_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
2383 pl->vddci, &level->vddci);
2388 ni_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
2393 static int ni_populate_smc_t(struct radeon_device *rdev,
2394 struct radeon_ps *radeon_state,
2395 NISLANDS_SMC_SWSTATE *smc_state)
2397 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2398 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2399 struct ni_ps *state = ni_get_ps(radeon_state);
2405 if (state->performance_level_count >= 9)
2408 if (state->performance_level_count < 2) {
2409 a_t = CG_R(0xffff) | CG_L(0);
2410 smc_state->levels[0].aT = cpu_to_be32(a_t);
2414 smc_state->levels[0].aT = cpu_to_be32(0);
2416 for (i = 0; i <= state->performance_level_count - 2; i++) {
2417 if (eg_pi->uvd_enabled)
2418 ret = r600_calculate_at(
2419 1000 * (i * (eg_pi->smu_uvd_hs ? 2 : 8) + 2),
2421 state->performance_levels[i + 1].sclk,
2422 state->performance_levels[i].sclk,
2426 ret = r600_calculate_at(
2429 state->performance_levels[i + 1].sclk,
2430 state->performance_levels[i].sclk,
2435 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
2436 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
2439 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
2440 a_t |= CG_R(t_l * pi->bsp / 20000);
2441 smc_state->levels[i].aT = cpu_to_be32(a_t);
2443 high_bsp = (i == state->performance_level_count - 2) ?
2446 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
2447 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
2453 static int ni_populate_power_containment_values(struct radeon_device *rdev,
2454 struct radeon_ps *radeon_state,
2455 NISLANDS_SMC_SWSTATE *smc_state)
2457 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2458 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2459 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2460 struct ni_ps *state = ni_get_ps(radeon_state);
2467 u32 power_boost_limit;
2470 if (ni_pi->enable_power_containment == false)
2473 if (state->performance_level_count == 0)
2476 if (smc_state->levelCount != state->performance_level_count)
2479 ret = ni_calculate_adjusted_tdp_limits(rdev,
2481 rdev->pm.dpm.tdp_adjustment,
2487 power_boost_limit = ni_calculate_power_boost_limit(rdev, radeon_state, near_tdp_limit);
2489 ret = rv770_write_smc_sram_dword(rdev,
2490 pi->state_table_start +
2491 offsetof(NISLANDS_SMC_STATETABLE, dpm2Params) +
2492 offsetof(PP_NIslands_DPM2Parameters, PowerBoostLimit),
2493 ni_scale_power_for_smc(power_boost_limit, ni_get_smc_power_scaling_factor(rdev)),
2496 power_boost_limit = 0;
2498 smc_state->levels[0].dpm2.MaxPS = 0;
2499 smc_state->levels[0].dpm2.NearTDPDec = 0;
2500 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2501 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2502 smc_state->levels[0].stateFlags |= power_boost_limit ? PPSMC_STATEFLAG_POWERBOOST : 0;
2504 for (i = 1; i < state->performance_level_count; i++) {
2505 prev_sclk = state->performance_levels[i-1].sclk;
2506 max_sclk = state->performance_levels[i].sclk;
2507 max_ps_percent = (i != (state->performance_level_count - 1)) ?
2508 NISLANDS_DPM2_MAXPS_PERCENT_M : NISLANDS_DPM2_MAXPS_PERCENT_H;
2510 if (max_sclk < prev_sclk)
2513 if ((max_ps_percent == 0) || (prev_sclk == max_sclk) || eg_pi->uvd_enabled)
2514 min_sclk = max_sclk;
2516 min_sclk = prev_sclk;
2518 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2520 if (min_sclk < state->performance_levels[0].sclk)
2521 min_sclk = state->performance_levels[0].sclk;
2526 smc_state->levels[i].dpm2.MaxPS =
2527 (u8)((NISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2528 smc_state->levels[i].dpm2.NearTDPDec = NISLANDS_DPM2_NEAR_TDP_DEC;
2529 smc_state->levels[i].dpm2.AboveSafeInc = NISLANDS_DPM2_ABOVE_SAFE_INC;
2530 smc_state->levels[i].dpm2.BelowSafeInc = NISLANDS_DPM2_BELOW_SAFE_INC;
2531 smc_state->levels[i].stateFlags |=
2532 ((i != (state->performance_level_count - 1)) && power_boost_limit) ?
2533 PPSMC_STATEFLAG_POWERBOOST : 0;
2539 static int ni_populate_sq_ramping_values(struct radeon_device *rdev,
2540 struct radeon_ps *radeon_state,
2541 NISLANDS_SMC_SWSTATE *smc_state)
2543 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2544 struct ni_ps *state = ni_get_ps(radeon_state);
2545 u32 sq_power_throttle;
2546 u32 sq_power_throttle2;
2547 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2550 if (state->performance_level_count == 0)
2553 if (smc_state->levelCount != state->performance_level_count)
2556 if (rdev->pm.dpm.sq_ramping_threshold == 0)
2559 if (NISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2560 enable_sq_ramping = false;
2562 if (NISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2563 enable_sq_ramping = false;
2565 if (NISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2566 enable_sq_ramping = false;
2568 if (NISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2569 enable_sq_ramping = false;
2571 if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2572 enable_sq_ramping = false;
2574 for (i = 0; i < state->performance_level_count; i++) {
2575 sq_power_throttle = 0;
2576 sq_power_throttle2 = 0;
2578 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2579 enable_sq_ramping) {
2580 sq_power_throttle |= MAX_POWER(NISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2581 sq_power_throttle |= MIN_POWER(NISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2582 sq_power_throttle2 |= MAX_POWER_DELTA(NISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2583 sq_power_throttle2 |= STI_SIZE(NISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2584 sq_power_throttle2 |= LTI_RATIO(NISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2586 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2587 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2590 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2591 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2597 static int ni_enable_power_containment(struct radeon_device *rdev,
2598 struct radeon_ps *radeon_new_state,
2601 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2602 PPSMC_Result smc_result;
2605 if (ni_pi->enable_power_containment) {
2607 if (!r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) {
2608 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2609 if (smc_result != PPSMC_Result_OK) {
2611 ni_pi->pc_enabled = false;
2613 ni_pi->pc_enabled = true;
2617 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2618 if (smc_result != PPSMC_Result_OK)
2620 ni_pi->pc_enabled = false;
2627 static int ni_convert_power_state_to_smc(struct radeon_device *rdev,
2628 struct radeon_ps *radeon_state,
2629 NISLANDS_SMC_SWSTATE *smc_state)
2631 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2632 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2633 struct ni_ps *state = ni_get_ps(radeon_state);
2635 u32 threshold = state->performance_levels[state->performance_level_count - 1].sclk * 100 / 100;
2637 if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC))
2638 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
2640 smc_state->levelCount = 0;
2642 if (state->performance_level_count > NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE)
2645 for (i = 0; i < state->performance_level_count; i++) {
2646 ret = ni_convert_power_level_to_smc(rdev, &state->performance_levels[i],
2647 &smc_state->levels[i]);
2648 smc_state->levels[i].arbRefreshState =
2649 (u8)(NISLANDS_DRIVER_STATE_ARB_INDEX + i);
2654 if (ni_pi->enable_power_containment)
2655 smc_state->levels[i].displayWatermark =
2656 (state->performance_levels[i].sclk < threshold) ?
2657 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
2659 smc_state->levels[i].displayWatermark = (i < 2) ?
2660 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
2662 if (eg_pi->dynamic_ac_timing)
2663 smc_state->levels[i].ACIndex = NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
2665 smc_state->levels[i].ACIndex = 0;
2667 smc_state->levelCount++;
2670 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_watermark_threshold,
2671 cpu_to_be32(threshold / 512));
2673 ni_populate_smc_sp(rdev, radeon_state, smc_state);
2675 ret = ni_populate_power_containment_values(rdev, radeon_state, smc_state);
2677 ni_pi->enable_power_containment = false;
2679 ret = ni_populate_sq_ramping_values(rdev, radeon_state, smc_state);
2681 ni_pi->enable_sq_ramping = false;
2683 return ni_populate_smc_t(rdev, radeon_state, smc_state);
2686 static int ni_upload_sw_state(struct radeon_device *rdev,
2687 struct radeon_ps *radeon_new_state)
2689 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2690 u16 address = pi->state_table_start +
2691 offsetof(NISLANDS_SMC_STATETABLE, driverState);
2692 u16 state_size = sizeof(NISLANDS_SMC_SWSTATE) +
2693 ((NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1) * sizeof(NISLANDS_SMC_HW_PERFORMANCE_LEVEL));
2695 NISLANDS_SMC_SWSTATE *smc_state = kzalloc(state_size, GFP_KERNEL);
2697 if (smc_state == NULL)
2700 ret = ni_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
2704 ret = rv770_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, state_size, pi->sram_end);
2712 static int ni_set_mc_special_registers(struct radeon_device *rdev,
2713 struct ni_mc_reg_table *table)
2715 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2719 for (i = 0, j = table->last; i < table->last; i++) {
2720 switch (table->mc_reg_address[i].s1) {
2721 case MC_SEQ_MISC1 >> 2:
2722 if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2724 temp_reg = RREG32(MC_PMG_CMD_EMRS);
2725 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
2726 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
2727 for (k = 0; k < table->num_entries; k++)
2728 table->mc_reg_table_entry[k].mc_data[j] =
2729 ((temp_reg & 0xffff0000)) |
2730 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
2732 if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2735 temp_reg = RREG32(MC_PMG_CMD_MRS);
2736 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
2737 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
2738 for(k = 0; k < table->num_entries; k++) {
2739 table->mc_reg_table_entry[k].mc_data[j] =
2740 (temp_reg & 0xffff0000) |
2741 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2743 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
2746 if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2749 case MC_SEQ_RESERVE_M >> 2:
2750 temp_reg = RREG32(MC_PMG_CMD_MRS1);
2751 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
2752 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
2753 for (k = 0; k < table->num_entries; k++)
2754 table->mc_reg_table_entry[k].mc_data[j] =
2755 (temp_reg & 0xffff0000) |
2756 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2758 if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2771 static bool ni_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
2776 case MC_SEQ_RAS_TIMING >> 2:
2777 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
2779 case MC_SEQ_CAS_TIMING >> 2:
2780 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
2782 case MC_SEQ_MISC_TIMING >> 2:
2783 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
2785 case MC_SEQ_MISC_TIMING2 >> 2:
2786 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
2788 case MC_SEQ_RD_CTL_D0 >> 2:
2789 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
2791 case MC_SEQ_RD_CTL_D1 >> 2:
2792 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
2794 case MC_SEQ_WR_CTL_D0 >> 2:
2795 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
2797 case MC_SEQ_WR_CTL_D1 >> 2:
2798 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
2800 case MC_PMG_CMD_EMRS >> 2:
2801 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
2803 case MC_PMG_CMD_MRS >> 2:
2804 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
2806 case MC_PMG_CMD_MRS1 >> 2:
2807 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
2809 case MC_SEQ_PMG_TIMING >> 2:
2810 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
2812 case MC_PMG_CMD_MRS2 >> 2:
2813 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
2823 static void ni_set_valid_flag(struct ni_mc_reg_table *table)
2827 for (i = 0; i < table->last; i++) {
2828 for (j = 1; j < table->num_entries; j++) {
2829 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
2830 table->valid_flag |= 1 << i;
2837 static void ni_set_s0_mc_reg_index(struct ni_mc_reg_table *table)
2842 for (i = 0; i < table->last; i++)
2843 table->mc_reg_address[i].s0 =
2844 ni_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
2845 address : table->mc_reg_address[i].s1;
2848 static int ni_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
2849 struct ni_mc_reg_table *ni_table)
2853 if (table->last > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2855 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
2858 for (i = 0; i < table->last; i++)
2859 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2860 ni_table->last = table->last;
2862 for (i = 0; i < table->num_entries; i++) {
2863 ni_table->mc_reg_table_entry[i].mclk_max =
2864 table->mc_reg_table_entry[i].mclk_max;
2865 for (j = 0; j < table->last; j++)
2866 ni_table->mc_reg_table_entry[i].mc_data[j] =
2867 table->mc_reg_table_entry[i].mc_data[j];
2869 ni_table->num_entries = table->num_entries;
2874 static int ni_initialize_mc_reg_table(struct radeon_device *rdev)
2876 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2878 struct atom_mc_reg_table *table;
2879 struct ni_mc_reg_table *ni_table = &ni_pi->mc_reg_table;
2880 u8 module_index = rv770_get_memory_module_index(rdev);
2882 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
2886 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
2887 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
2888 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
2889 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
2890 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
2891 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
2892 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
2893 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
2894 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
2895 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
2896 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
2897 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
2898 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
2900 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
2905 ret = ni_copy_vbios_mc_reg_table(table, ni_table);
2910 ni_set_s0_mc_reg_index(ni_table);
2912 ret = ni_set_mc_special_registers(rdev, ni_table);
2917 ni_set_valid_flag(ni_table);
2925 static void ni_populate_mc_reg_addresses(struct radeon_device *rdev,
2926 SMC_NIslands_MCRegisters *mc_reg_table)
2928 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2931 for (i = 0, j = 0; j < ni_pi->mc_reg_table.last; j++) {
2932 if (ni_pi->mc_reg_table.valid_flag & (1 << j)) {
2933 if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2935 mc_reg_table->address[i].s0 =
2936 cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s0);
2937 mc_reg_table->address[i].s1 =
2938 cpu_to_be16(ni_pi->mc_reg_table.mc_reg_address[j].s1);
2942 mc_reg_table->last = (u8)i;
2946 static void ni_convert_mc_registers(struct ni_mc_reg_entry *entry,
2947 SMC_NIslands_MCRegisterSet *data,
2948 u32 num_entries, u32 valid_flag)
2952 for (i = 0, j = 0; j < num_entries; j++) {
2953 if (valid_flag & (1 << j)) {
2954 data->value[i] = cpu_to_be32(entry->mc_data[j]);
2960 static void ni_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
2961 struct rv7xx_pl *pl,
2962 SMC_NIslands_MCRegisterSet *mc_reg_table_data)
2964 struct ni_power_info *ni_pi = ni_get_pi(rdev);
2967 for (i = 0; i < ni_pi->mc_reg_table.num_entries; i++) {
2968 if (pl->mclk <= ni_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
2972 if ((i == ni_pi->mc_reg_table.num_entries) && (i > 0))
2975 ni_convert_mc_registers(&ni_pi->mc_reg_table.mc_reg_table_entry[i],
2977 ni_pi->mc_reg_table.last,
2978 ni_pi->mc_reg_table.valid_flag);
2981 static void ni_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
2982 struct radeon_ps *radeon_state,
2983 SMC_NIslands_MCRegisters *mc_reg_table)
2985 struct ni_ps *state = ni_get_ps(radeon_state);
2988 for (i = 0; i < state->performance_level_count; i++) {
2989 ni_convert_mc_reg_table_entry_to_smc(rdev,
2990 &state->performance_levels[i],
2991 &mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
2995 static int ni_populate_mc_reg_table(struct radeon_device *rdev,
2996 struct radeon_ps *radeon_boot_state)
2998 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2999 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3000 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3001 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
3002 SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table;
3004 memset(mc_reg_table, 0, sizeof(SMC_NIslands_MCRegisters));
3006 rv770_write_smc_soft_register(rdev, NI_SMC_SOFT_REGISTER_seq_index, 1);
3008 ni_populate_mc_reg_addresses(rdev, mc_reg_table);
3010 ni_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
3011 &mc_reg_table->data[0]);
3013 ni_convert_mc_registers(&ni_pi->mc_reg_table.mc_reg_table_entry[0],
3014 &mc_reg_table->data[1],
3015 ni_pi->mc_reg_table.last,
3016 ni_pi->mc_reg_table.valid_flag);
3018 ni_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, mc_reg_table);
3020 return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,
3022 sizeof(SMC_NIslands_MCRegisters),
3026 static int ni_upload_mc_reg_table(struct radeon_device *rdev,
3027 struct radeon_ps *radeon_new_state)
3029 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3030 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3031 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3032 struct ni_ps *ni_new_state = ni_get_ps(radeon_new_state);
3033 SMC_NIslands_MCRegisters *mc_reg_table = &ni_pi->smc_mc_reg_table;
3036 memset(mc_reg_table, 0, sizeof(SMC_NIslands_MCRegisters));
3038 ni_convert_mc_reg_table_to_smc(rdev, radeon_new_state, mc_reg_table);
3040 address = eg_pi->mc_reg_table_start +
3041 (u16)offsetof(SMC_NIslands_MCRegisters, data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
3043 return rv770_copy_bytes_to_smc(rdev, address,
3044 (u8 *)&mc_reg_table->data[NISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
3045 sizeof(SMC_NIslands_MCRegisterSet) * ni_new_state->performance_level_count,
3049 static int ni_init_driver_calculated_leakage_table(struct radeon_device *rdev,
3050 PP_NIslands_CACTABLES *cac_tables)
3052 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3053 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3055 unsigned int i, j, table_size;
3057 u32 smc_leakage, max_leakage = 0;
3060 table_size = eg_pi->vddc_voltage_table.count;
3062 if (SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES < table_size)
3063 table_size = SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
3065 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
3067 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++) {
3068 for (j = 0; j < table_size; j++) {
3069 t = (1000 * ((i + 1) * 8));
3071 if (t < ni_pi->cac_data.leakage_minimum_temperature)
3072 t = ni_pi->cac_data.leakage_minimum_temperature;
3074 ni_calculate_leakage_for_v_and_t(rdev,
3075 &ni_pi->cac_data.leakage_coefficients,
3076 eg_pi->vddc_voltage_table.entries[j].value,
3078 ni_pi->cac_data.i_leakage,
3081 smc_leakage = ni_scale_power_for_smc(leakage, scaling_factor) / 1000;
3082 if (smc_leakage > max_leakage)
3083 max_leakage = smc_leakage;
3085 cac_tables->cac_lkge_lut[i][j] = cpu_to_be32(smc_leakage);
3089 for (j = table_size; j < SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
3090 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++)
3091 cac_tables->cac_lkge_lut[i][j] = cpu_to_be32(max_leakage);
3096 static int ni_init_simplified_leakage_table(struct radeon_device *rdev,
3097 PP_NIslands_CACTABLES *cac_tables)
3099 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3100 struct radeon_cac_leakage_table *leakage_table =
3101 &rdev->pm.dpm.dyn_state.cac_leakage_table;
3102 u32 i, j, table_size;
3103 u32 smc_leakage, max_leakage = 0;
3109 table_size = leakage_table->count;
3111 if (eg_pi->vddc_voltage_table.count != table_size)
3112 table_size = (eg_pi->vddc_voltage_table.count < leakage_table->count) ?
3113 eg_pi->vddc_voltage_table.count : leakage_table->count;
3115 if (SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES < table_size)
3116 table_size = SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
3118 if (table_size == 0)
3121 scaling_factor = ni_get_smc_power_scaling_factor(rdev);
3123 for (j = 0; j < table_size; j++) {
3124 smc_leakage = leakage_table->entries[j].leakage;
3126 if (smc_leakage > max_leakage)
3127 max_leakage = smc_leakage;
3129 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++)
3130 cac_tables->cac_lkge_lut[i][j] =
3131 cpu_to_be32(ni_scale_power_for_smc(smc_leakage, scaling_factor));
3134 for (j = table_size; j < SMC_NISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
3135 for (i = 0; i < SMC_NISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES; i++)
3136 cac_tables->cac_lkge_lut[i][j] =
3137 cpu_to_be32(ni_scale_power_for_smc(max_leakage, scaling_factor));
3142 static int ni_initialize_smc_cac_tables(struct radeon_device *rdev)
3144 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3145 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3146 PP_NIslands_CACTABLES *cac_tables = NULL;
3150 if (ni_pi->enable_cac == false)
3153 cac_tables = kzalloc(sizeof(PP_NIslands_CACTABLES), GFP_KERNEL);
3157 reg = RREG32(CG_CAC_CTRL) & ~(TID_CNT_MASK | TID_UNIT_MASK);
3158 reg |= (TID_CNT(ni_pi->cac_weights->tid_cnt) |
3159 TID_UNIT(ni_pi->cac_weights->tid_unit));
3160 WREG32(CG_CAC_CTRL, reg);
3162 for (i = 0; i < NISLANDS_DCCAC_MAX_LEVELS; i++)
3163 ni_pi->dc_cac_table[i] = ni_pi->cac_weights->dc_cac[i];
3165 for (i = 0; i < SMC_NISLANDS_BIF_LUT_NUM_OF_ENTRIES; i++)
3166 cac_tables->cac_bif_lut[i] = ni_pi->cac_weights->pcie_cac[i];
3168 ni_pi->cac_data.i_leakage = rdev->pm.dpm.cac_leakage;
3169 ni_pi->cac_data.pwr_const = 0;
3170 ni_pi->cac_data.dc_cac_value = ni_pi->dc_cac_table[NISLANDS_DCCAC_LEVEL_0];
3171 ni_pi->cac_data.bif_cac_value = 0;
3172 ni_pi->cac_data.mc_wr_weight = ni_pi->cac_weights->mc_write_weight;
3173 ni_pi->cac_data.mc_rd_weight = ni_pi->cac_weights->mc_read_weight;
3174 ni_pi->cac_data.allow_ovrflw = 0;
3175 ni_pi->cac_data.l2num_win_tdp = ni_pi->lta_window_size;
3176 ni_pi->cac_data.num_win_tdp = 0;
3177 ni_pi->cac_data.lts_truncate_n = ni_pi->lts_truncate;
3179 if (ni_pi->driver_calculate_cac_leakage)
3180 ret = ni_init_driver_calculated_leakage_table(rdev, cac_tables);
3182 ret = ni_init_simplified_leakage_table(rdev, cac_tables);
3187 cac_tables->pwr_const = cpu_to_be32(ni_pi->cac_data.pwr_const);
3188 cac_tables->dc_cacValue = cpu_to_be32(ni_pi->cac_data.dc_cac_value);
3189 cac_tables->bif_cacValue = cpu_to_be32(ni_pi->cac_data.bif_cac_value);
3190 cac_tables->AllowOvrflw = ni_pi->cac_data.allow_ovrflw;
3191 cac_tables->MCWrWeight = ni_pi->cac_data.mc_wr_weight;
3192 cac_tables->MCRdWeight = ni_pi->cac_data.mc_rd_weight;
3193 cac_tables->numWin_TDP = ni_pi->cac_data.num_win_tdp;
3194 cac_tables->l2numWin_TDP = ni_pi->cac_data.l2num_win_tdp;
3195 cac_tables->lts_truncate_n = ni_pi->cac_data.lts_truncate_n;
3197 ret = rv770_copy_bytes_to_smc(rdev, ni_pi->cac_table_start, (u8 *)cac_tables,
3198 sizeof(PP_NIslands_CACTABLES), pi->sram_end);
3202 ni_pi->enable_cac = false;
3203 ni_pi->enable_power_containment = false;
3211 static int ni_initialize_hardware_cac_manager(struct radeon_device *rdev)
3213 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3216 if (!ni_pi->enable_cac ||
3217 !ni_pi->cac_configuration_required)
3220 if (ni_pi->cac_weights == NULL)
3223 reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_0) & ~(WEIGHT_TCP_SIG0_MASK |
3224 WEIGHT_TCP_SIG1_MASK |
3225 WEIGHT_TA_SIG_MASK);
3226 reg |= (WEIGHT_TCP_SIG0(ni_pi->cac_weights->weight_tcp_sig0) |
3227 WEIGHT_TCP_SIG1(ni_pi->cac_weights->weight_tcp_sig1) |
3228 WEIGHT_TA_SIG(ni_pi->cac_weights->weight_ta_sig));
3229 WREG32_CG(CG_CAC_REGION_1_WEIGHT_0, reg);
3231 reg = RREG32_CG(CG_CAC_REGION_1_WEIGHT_1) & ~(WEIGHT_TCC_EN0_MASK |
3232 WEIGHT_TCC_EN1_MASK |
3233 WEIGHT_TCC_EN2_MASK);
3234 reg |= (WEIGHT_TCC_EN0(ni_pi->cac_weights->weight_tcc_en0) |
3235 WEIGHT_TCC_EN1(ni_pi->cac_weights->weight_tcc_en1) |
3236 WEIGHT_TCC_EN2(ni_pi->cac_weights->weight_tcc_en2));
3237 WREG32_CG(CG_CAC_REGION_1_WEIGHT_1, reg);
3239 reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_0) & ~(WEIGHT_CB_EN0_MASK |
3240 WEIGHT_CB_EN1_MASK |
3241 WEIGHT_CB_EN2_MASK |
3242 WEIGHT_CB_EN3_MASK);
3243 reg |= (WEIGHT_CB_EN0(ni_pi->cac_weights->weight_cb_en0) |
3244 WEIGHT_CB_EN1(ni_pi->cac_weights->weight_cb_en1) |
3245 WEIGHT_CB_EN2(ni_pi->cac_weights->weight_cb_en2) |
3246 WEIGHT_CB_EN3(ni_pi->cac_weights->weight_cb_en3));
3247 WREG32_CG(CG_CAC_REGION_2_WEIGHT_0, reg);
3249 reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_1) & ~(WEIGHT_DB_SIG0_MASK |
3250 WEIGHT_DB_SIG1_MASK |
3251 WEIGHT_DB_SIG2_MASK |
3252 WEIGHT_DB_SIG3_MASK);
3253 reg |= (WEIGHT_DB_SIG0(ni_pi->cac_weights->weight_db_sig0) |
3254 WEIGHT_DB_SIG1(ni_pi->cac_weights->weight_db_sig1) |
3255 WEIGHT_DB_SIG2(ni_pi->cac_weights->weight_db_sig2) |
3256 WEIGHT_DB_SIG3(ni_pi->cac_weights->weight_db_sig3));
3257 WREG32_CG(CG_CAC_REGION_2_WEIGHT_1, reg);
3259 reg = RREG32_CG(CG_CAC_REGION_2_WEIGHT_2) & ~(WEIGHT_SXM_SIG0_MASK |
3260 WEIGHT_SXM_SIG1_MASK |
3261 WEIGHT_SXM_SIG2_MASK |
3262 WEIGHT_SXS_SIG0_MASK |
3263 WEIGHT_SXS_SIG1_MASK);
3264 reg |= (WEIGHT_SXM_SIG0(ni_pi->cac_weights->weight_sxm_sig0) |
3265 WEIGHT_SXM_SIG1(ni_pi->cac_weights->weight_sxm_sig1) |
3266 WEIGHT_SXM_SIG2(ni_pi->cac_weights->weight_sxm_sig2) |
3267 WEIGHT_SXS_SIG0(ni_pi->cac_weights->weight_sxs_sig0) |
3268 WEIGHT_SXS_SIG1(ni_pi->cac_weights->weight_sxs_sig1));
3269 WREG32_CG(CG_CAC_REGION_2_WEIGHT_2, reg);
3271 reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_0) & ~(WEIGHT_XBR_0_MASK |
3274 WEIGHT_SPI_SIG0_MASK);
3275 reg |= (WEIGHT_XBR_0(ni_pi->cac_weights->weight_xbr_0) |
3276 WEIGHT_XBR_1(ni_pi->cac_weights->weight_xbr_1) |
3277 WEIGHT_XBR_2(ni_pi->cac_weights->weight_xbr_2) |
3278 WEIGHT_SPI_SIG0(ni_pi->cac_weights->weight_spi_sig0));
3279 WREG32_CG(CG_CAC_REGION_3_WEIGHT_0, reg);
3281 reg = RREG32_CG(CG_CAC_REGION_3_WEIGHT_1) & ~(WEIGHT_SPI_SIG1_MASK |
3282 WEIGHT_SPI_SIG2_MASK |
3283 WEIGHT_SPI_SIG3_MASK |
3284 WEIGHT_SPI_SIG4_MASK |
3285 WEIGHT_SPI_SIG5_MASK);
3286 reg |= (WEIGHT_SPI_SIG1(ni_pi->cac_weights->weight_spi_sig1) |
3287 WEIGHT_SPI_SIG2(ni_pi->cac_weights->weight_spi_sig2) |
3288 WEIGHT_SPI_SIG3(ni_pi->cac_weights->weight_spi_sig3) |
3289 WEIGHT_SPI_SIG4(ni_pi->cac_weights->weight_spi_sig4) |
3290 WEIGHT_SPI_SIG5(ni_pi->cac_weights->weight_spi_sig5));
3291 WREG32_CG(CG_CAC_REGION_3_WEIGHT_1, reg);
3293 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_0) & ~(WEIGHT_LDS_SIG0_MASK |
3294 WEIGHT_LDS_SIG1_MASK |
3296 reg |= (WEIGHT_LDS_SIG0(ni_pi->cac_weights->weight_lds_sig0) |
3297 WEIGHT_LDS_SIG1(ni_pi->cac_weights->weight_lds_sig1) |
3298 WEIGHT_SC(ni_pi->cac_weights->weight_sc));
3299 WREG32_CG(CG_CAC_REGION_4_WEIGHT_0, reg);
3301 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_1) & ~(WEIGHT_BIF_MASK |
3303 WEIGHT_PA_SIG0_MASK |
3304 WEIGHT_PA_SIG1_MASK |
3305 WEIGHT_VGT_SIG0_MASK);
3306 reg |= (WEIGHT_BIF(ni_pi->cac_weights->weight_bif) |
3307 WEIGHT_CP(ni_pi->cac_weights->weight_cp) |
3308 WEIGHT_PA_SIG0(ni_pi->cac_weights->weight_pa_sig0) |
3309 WEIGHT_PA_SIG1(ni_pi->cac_weights->weight_pa_sig1) |
3310 WEIGHT_VGT_SIG0(ni_pi->cac_weights->weight_vgt_sig0));
3311 WREG32_CG(CG_CAC_REGION_4_WEIGHT_1, reg);
3313 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_2) & ~(WEIGHT_VGT_SIG1_MASK |
3314 WEIGHT_VGT_SIG2_MASK |
3315 WEIGHT_DC_SIG0_MASK |
3316 WEIGHT_DC_SIG1_MASK |
3317 WEIGHT_DC_SIG2_MASK);
3318 reg |= (WEIGHT_VGT_SIG1(ni_pi->cac_weights->weight_vgt_sig1) |
3319 WEIGHT_VGT_SIG2(ni_pi->cac_weights->weight_vgt_sig2) |
3320 WEIGHT_DC_SIG0(ni_pi->cac_weights->weight_dc_sig0) |
3321 WEIGHT_DC_SIG1(ni_pi->cac_weights->weight_dc_sig1) |
3322 WEIGHT_DC_SIG2(ni_pi->cac_weights->weight_dc_sig2));
3323 WREG32_CG(CG_CAC_REGION_4_WEIGHT_2, reg);
3325 reg = RREG32_CG(CG_CAC_REGION_4_WEIGHT_3) & ~(WEIGHT_DC_SIG3_MASK |
3326 WEIGHT_UVD_SIG0_MASK |
3327 WEIGHT_UVD_SIG1_MASK |
3328 WEIGHT_SPARE0_MASK |
3329 WEIGHT_SPARE1_MASK);
3330 reg |= (WEIGHT_DC_SIG3(ni_pi->cac_weights->weight_dc_sig3) |
3331 WEIGHT_UVD_SIG0(ni_pi->cac_weights->weight_uvd_sig0) |
3332 WEIGHT_UVD_SIG1(ni_pi->cac_weights->weight_uvd_sig1) |
3333 WEIGHT_SPARE0(ni_pi->cac_weights->weight_spare0) |
3334 WEIGHT_SPARE1(ni_pi->cac_weights->weight_spare1));
3335 WREG32_CG(CG_CAC_REGION_4_WEIGHT_3, reg);
3337 reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_0) & ~(WEIGHT_SQ_VSP_MASK |
3338 WEIGHT_SQ_VSP0_MASK);
3339 reg |= (WEIGHT_SQ_VSP(ni_pi->cac_weights->weight_sq_vsp) |
3340 WEIGHT_SQ_VSP0(ni_pi->cac_weights->weight_sq_vsp0));
3341 WREG32_CG(CG_CAC_REGION_5_WEIGHT_0, reg);
3343 reg = RREG32_CG(CG_CAC_REGION_5_WEIGHT_1) & ~(WEIGHT_SQ_GPR_MASK);
3344 reg |= WEIGHT_SQ_GPR(ni_pi->cac_weights->weight_sq_gpr);
3345 WREG32_CG(CG_CAC_REGION_5_WEIGHT_1, reg);
3347 reg = RREG32_CG(CG_CAC_REGION_4_OVERRIDE_4) & ~(OVR_MODE_SPARE_0_MASK |
3348 OVR_VAL_SPARE_0_MASK |
3349 OVR_MODE_SPARE_1_MASK |
3350 OVR_VAL_SPARE_1_MASK);
3351 reg |= (OVR_MODE_SPARE_0(ni_pi->cac_weights->ovr_mode_spare_0) |
3352 OVR_VAL_SPARE_0(ni_pi->cac_weights->ovr_val_spare_0) |
3353 OVR_MODE_SPARE_1(ni_pi->cac_weights->ovr_mode_spare_1) |
3354 OVR_VAL_SPARE_1(ni_pi->cac_weights->ovr_val_spare_1));
3355 WREG32_CG(CG_CAC_REGION_4_OVERRIDE_4, reg);
3357 reg = RREG32(SQ_CAC_THRESHOLD) & ~(VSP_MASK |
3360 reg |= (VSP(ni_pi->cac_weights->vsp) |
3361 VSP0(ni_pi->cac_weights->vsp0) |
3362 GPR(ni_pi->cac_weights->gpr));
3363 WREG32(SQ_CAC_THRESHOLD, reg);
3365 reg = (MCDW_WR_ENABLE |
3370 WREG32(MC_CG_CONFIG, reg);
3372 reg = (READ_WEIGHT(ni_pi->cac_weights->mc_read_weight) |
3373 WRITE_WEIGHT(ni_pi->cac_weights->mc_write_weight) |
3375 WREG32(MC_CG_DATAPORT, reg);
3380 static int ni_enable_smc_cac(struct radeon_device *rdev,
3381 struct radeon_ps *radeon_new_state,
3384 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3386 PPSMC_Result smc_result;
3388 if (ni_pi->enable_cac) {
3390 if (!r600_is_uvd_state(radeon_new_state->class, radeon_new_state->class2)) {
3391 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_CollectCAC_PowerCorreln);
3393 if (ni_pi->support_cac_long_term_average) {
3394 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
3395 if (PPSMC_Result_OK != smc_result)
3396 ni_pi->support_cac_long_term_average = false;
3399 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
3400 if (PPSMC_Result_OK != smc_result)
3403 ni_pi->cac_enabled = (PPSMC_Result_OK == smc_result) ? true : false;
3405 } else if (ni_pi->cac_enabled) {
3406 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
3408 ni_pi->cac_enabled = false;
3410 if (ni_pi->support_cac_long_term_average) {
3411 smc_result = rv770_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
3412 if (PPSMC_Result_OK != smc_result)
3413 ni_pi->support_cac_long_term_average = false;
3421 static int ni_pcie_performance_request(struct radeon_device *rdev,
3422 u8 perf_req, bool advertise)
3424 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3426 #if defined(CONFIG_ACPI)
3427 if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) ||
3428 (perf_req == PCIE_PERF_REQ_PECI_GEN2)) {
3429 if (eg_pi->pcie_performance_request_registered == false)
3430 radeon_acpi_pcie_notify_device_ready(rdev);
3431 eg_pi->pcie_performance_request_registered = true;
3432 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
3433 } else if ((perf_req == PCIE_PERF_REQ_REMOVE_REGISTRY) &&
3434 eg_pi->pcie_performance_request_registered) {
3435 eg_pi->pcie_performance_request_registered = false;
3436 return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
3442 static int ni_advertise_gen2_capability(struct radeon_device *rdev)
3444 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3447 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3449 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3450 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
3451 pi->pcie_gen2 = true;
3453 pi->pcie_gen2 = false;
3456 ni_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);
3461 static void ni_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
3464 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3467 tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
3469 if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3470 (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3472 if (!pi->boot_in_gen2) {
3473 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
3474 bif |= CG_CLIENT_REQ(0xd);
3475 WREG32(CG_BIF_REQ_AND_RSP, bif);
3477 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
3478 tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
3479 tmp |= LC_GEN2_EN_STRAP;
3481 tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3482 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
3484 tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3485 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
3487 if (!pi->boot_in_gen2) {
3488 bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
3489 bif |= CG_CLIENT_REQ(0xd);
3490 WREG32(CG_BIF_REQ_AND_RSP, bif);
3492 tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
3493 tmp &= ~LC_GEN2_EN_STRAP;
3495 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
3500 static void ni_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
3503 ni_enable_bif_dynamic_pcie_gen2(rdev, enable);
3506 WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
3508 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
3511 void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
3512 struct radeon_ps *new_ps,
3513 struct radeon_ps *old_ps)
3515 struct ni_ps *new_state = ni_get_ps(new_ps);
3516 struct ni_ps *current_state = ni_get_ps(old_ps);
3518 if ((new_ps->vclk == old_ps->vclk) &&
3519 (new_ps->dclk == old_ps->dclk))
3522 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3523 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3526 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3529 void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
3530 struct radeon_ps *new_ps,
3531 struct radeon_ps *old_ps)
3533 struct ni_ps *new_state = ni_get_ps(new_ps);
3534 struct ni_ps *current_state = ni_get_ps(old_ps);
3536 if ((new_ps->vclk == old_ps->vclk) &&
3537 (new_ps->dclk == old_ps->dclk))
3540 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3541 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3544 radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
3547 void ni_dpm_setup_asic(struct radeon_device *rdev)
3549 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3551 ni_read_clock_registers(rdev);
3552 btc_read_arb_registers(rdev);
3553 rv770_get_memory_type(rdev);
3554 if (eg_pi->pcie_performance_request)
3555 ni_advertise_gen2_capability(rdev);
3556 rv770_get_pcie_gen2_status(rdev);
3557 rv770_enable_acpi_pm(rdev);
3560 void ni_update_current_ps(struct radeon_device *rdev,
3561 struct radeon_ps *rps)
3563 struct ni_ps *new_ps = ni_get_ps(rps);
3564 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3565 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3567 eg_pi->current_rps = *rps;
3568 ni_pi->current_ps = *new_ps;
3569 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3572 void ni_update_requested_ps(struct radeon_device *rdev,
3573 struct radeon_ps *rps)
3575 struct ni_ps *new_ps = ni_get_ps(rps);
3576 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3577 struct ni_power_info *ni_pi = ni_get_pi(rdev);
3579 eg_pi->requested_rps = *rps;
3580 ni_pi->requested_ps = *new_ps;
3581 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3584 int ni_dpm_enable(struct radeon_device *rdev)
3586 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3587 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3588 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
3591 if (pi->gfx_clock_gating)
3592 ni_cg_clockgating_default(rdev);
3593 if (btc_dpm_enabled(rdev))
3595 if (pi->mg_clock_gating)
3596 ni_mg_clockgating_default(rdev);
3597 if (eg_pi->ls_clock_gating)
3598 ni_ls_clockgating_default(rdev);
3599 if (pi->voltage_control) {
3600 rv770_enable_voltage_control(rdev, true);
3601 ret = cypress_construct_voltage_tables(rdev);
3603 DRM_ERROR("cypress_construct_voltage_tables failed\n");
3607 if (eg_pi->dynamic_ac_timing) {
3608 ret = ni_initialize_mc_reg_table(rdev);
3610 eg_pi->dynamic_ac_timing = false;
3613 cypress_enable_spread_spectrum(rdev, true);
3614 if (pi->thermal_protection)
3615 rv770_enable_thermal_protection(rdev, true);
3616 rv770_setup_bsp(rdev);
3617 rv770_program_git(rdev);
3618 rv770_program_tp(rdev);
3619 rv770_program_tpp(rdev);
3620 rv770_program_sstp(rdev);
3621 cypress_enable_display_gap(rdev);
3622 rv770_program_vc(rdev);
3623 if (pi->dynamic_pcie_gen2)
3624 ni_enable_dynamic_pcie_gen2(rdev, true);
3625 ret = rv770_upload_firmware(rdev);
3627 DRM_ERROR("rv770_upload_firmware failed\n");
3630 ret = ni_process_firmware_header(rdev);
3632 DRM_ERROR("ni_process_firmware_header failed\n");
3635 ret = ni_initial_switch_from_arb_f0_to_f1(rdev);
3637 DRM_ERROR("ni_initial_switch_from_arb_f0_to_f1 failed\n");
3640 ret = ni_init_smc_table(rdev);
3642 DRM_ERROR("ni_init_smc_table failed\n");
3645 ret = ni_init_smc_spll_table(rdev);
3647 DRM_ERROR("ni_init_smc_spll_table failed\n");
3650 ret = ni_init_arb_table_index(rdev);
3652 DRM_ERROR("ni_init_arb_table_index failed\n");
3655 if (eg_pi->dynamic_ac_timing) {
3656 ret = ni_populate_mc_reg_table(rdev, boot_ps);
3658 DRM_ERROR("ni_populate_mc_reg_table failed\n");
3662 ret = ni_initialize_smc_cac_tables(rdev);
3664 DRM_ERROR("ni_initialize_smc_cac_tables failed\n");
3667 ret = ni_initialize_hardware_cac_manager(rdev);
3669 DRM_ERROR("ni_initialize_hardware_cac_manager failed\n");
3672 ret = ni_populate_smc_tdp_limits(rdev, boot_ps);
3674 DRM_ERROR("ni_populate_smc_tdp_limits failed\n");
3677 ni_program_response_times(rdev);
3678 r7xx_start_smc(rdev);
3679 ret = cypress_notify_smc_display_change(rdev, false);
3681 DRM_ERROR("cypress_notify_smc_display_change failed\n");
3684 cypress_enable_sclk_control(rdev, true);
3685 if (eg_pi->memory_transition)
3686 cypress_enable_mclk_control(rdev, true);
3687 cypress_start_dpm(rdev);
3688 if (pi->gfx_clock_gating)
3689 ni_gfx_clockgating_enable(rdev, true);
3690 if (pi->mg_clock_gating)
3691 ni_mg_clockgating_enable(rdev, true);
3692 if (eg_pi->ls_clock_gating)
3693 ni_ls_clockgating_enable(rdev, true);
3695 if (rdev->irq.installed &&
3696 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
3697 PPSMC_Result result;
3699 ret = rv770_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, 0xff * 1000);
3702 rdev->irq.dpm_thermal = true;
3703 radeon_irq_set(rdev);
3704 result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3706 if (result != PPSMC_Result_OK)
3707 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
3710 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
3712 ni_update_current_ps(rdev, boot_ps);
3717 void ni_dpm_disable(struct radeon_device *rdev)
3719 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3720 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3721 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
3723 if (!btc_dpm_enabled(rdev))
3725 rv770_clear_vc(rdev);
3726 if (pi->thermal_protection)
3727 rv770_enable_thermal_protection(rdev, false);
3728 ni_enable_power_containment(rdev, boot_ps, false);
3729 ni_enable_smc_cac(rdev, boot_ps, false);
3730 cypress_enable_spread_spectrum(rdev, false);
3731 rv770_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
3732 if (pi->dynamic_pcie_gen2)
3733 ni_enable_dynamic_pcie_gen2(rdev, false);
3735 if (rdev->irq.installed &&
3736 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
3737 rdev->irq.dpm_thermal = false;
3738 radeon_irq_set(rdev);
3741 if (pi->gfx_clock_gating)
3742 ni_gfx_clockgating_enable(rdev, false);
3743 if (pi->mg_clock_gating)
3744 ni_mg_clockgating_enable(rdev, false);
3745 if (eg_pi->ls_clock_gating)
3746 ni_ls_clockgating_enable(rdev, false);
3748 btc_reset_to_default(rdev);
3750 ni_force_switch_to_arb_f0(rdev);
3752 ni_update_current_ps(rdev, boot_ps);
3755 static int ni_power_control_set_level(struct radeon_device *rdev)
3757 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
3760 ret = ni_restrict_performance_levels_before_switch(rdev);
3763 ret = rv770_halt_smc(rdev);
3766 ret = ni_populate_smc_tdp_limits(rdev, new_ps);
3769 ret = rv770_resume_smc(rdev);
3772 ret = rv770_set_sw_state(rdev);
3779 int ni_dpm_pre_set_power_state(struct radeon_device *rdev)
3781 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3782 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
3783 struct radeon_ps *new_ps = &requested_ps;
3785 ni_update_requested_ps(rdev, new_ps);
3787 ni_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
3792 int ni_dpm_set_power_state(struct radeon_device *rdev)
3794 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3795 struct radeon_ps *new_ps = &eg_pi->requested_rps;
3796 struct radeon_ps *old_ps = &eg_pi->current_rps;
3799 ret = ni_restrict_performance_levels_before_switch(rdev);
3801 DRM_ERROR("ni_restrict_performance_levels_before_switch failed\n");
3804 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
3805 ret = ni_enable_power_containment(rdev, new_ps, false);
3807 DRM_ERROR("ni_enable_power_containment failed\n");
3810 ret = ni_enable_smc_cac(rdev, new_ps, false);
3812 DRM_ERROR("ni_enable_smc_cac failed\n");
3815 ret = rv770_halt_smc(rdev);
3817 DRM_ERROR("rv770_halt_smc failed\n");
3820 if (eg_pi->smu_uvd_hs)
3821 btc_notify_uvd_to_smc(rdev, new_ps);
3822 ret = ni_upload_sw_state(rdev, new_ps);
3824 DRM_ERROR("ni_upload_sw_state failed\n");
3827 if (eg_pi->dynamic_ac_timing) {
3828 ret = ni_upload_mc_reg_table(rdev, new_ps);
3830 DRM_ERROR("ni_upload_mc_reg_table failed\n");
3834 ret = ni_program_memory_timing_parameters(rdev, new_ps);
3836 DRM_ERROR("ni_program_memory_timing_parameters failed\n");
3839 ret = rv770_resume_smc(rdev);
3841 DRM_ERROR("rv770_resume_smc failed\n");
3844 ret = rv770_set_sw_state(rdev);
3846 DRM_ERROR("rv770_set_sw_state failed\n");
3849 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
3850 ret = ni_enable_smc_cac(rdev, new_ps, true);
3852 DRM_ERROR("ni_enable_smc_cac failed\n");
3855 ret = ni_enable_power_containment(rdev, new_ps, true);
3857 DRM_ERROR("ni_enable_power_containment failed\n");
3862 ret = ni_power_control_set_level(rdev);
3864 DRM_ERROR("ni_power_control_set_level failed\n");
3868 ret = ni_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
3870 DRM_ERROR("ni_dpm_force_performance_level failed\n");
3877 void ni_dpm_post_set_power_state(struct radeon_device *rdev)
3879 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3880 struct radeon_ps *new_ps = &eg_pi->requested_rps;
3882 ni_update_current_ps(rdev, new_ps);
3885 void ni_dpm_reset_asic(struct radeon_device *rdev)
3887 ni_restrict_performance_levels_before_switch(rdev);
3888 rv770_set_boot_state(rdev);
3892 struct _ATOM_POWERPLAY_INFO info;
3893 struct _ATOM_POWERPLAY_INFO_V2 info_2;
3894 struct _ATOM_POWERPLAY_INFO_V3 info_3;
3895 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
3896 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
3897 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
3900 union pplib_clock_info {
3901 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
3902 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
3903 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
3904 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
3907 union pplib_power_state {
3908 struct _ATOM_PPLIB_STATE v1;
3909 struct _ATOM_PPLIB_STATE_V2 v2;
3912 static void ni_parse_pplib_non_clock_info(struct radeon_device *rdev,
3913 struct radeon_ps *rps,
3914 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
3917 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
3918 rps->class = le16_to_cpu(non_clock_info->usClassification);
3919 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
3921 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
3922 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
3923 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
3924 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
3925 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
3926 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
3932 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
3933 rdev->pm.dpm.boot_ps = rps;
3934 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3935 rdev->pm.dpm.uvd_ps = rps;
3938 static void ni_parse_pplib_clock_info(struct radeon_device *rdev,
3939 struct radeon_ps *rps, int index,
3940 union pplib_clock_info *clock_info)
3942 struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3943 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3944 struct ni_ps *ps = ni_get_ps(rps);
3946 struct rv7xx_pl *pl = &ps->performance_levels[index];
3948 ps->performance_level_count = index + 1;
3950 pl->sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
3951 pl->sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
3952 pl->mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
3953 pl->mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
3955 pl->vddc = le16_to_cpu(clock_info->evergreen.usVDDC);
3956 pl->vddci = le16_to_cpu(clock_info->evergreen.usVDDCI);
3957 pl->flags = le32_to_cpu(clock_info->evergreen.ulFlags);
3959 /* patch up vddc if necessary */
3960 if (pl->vddc == 0xff01) {
3961 if (radeon_atom_get_max_vddc(rdev, 0, 0, &vddc) == 0)
3965 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
3966 pi->acpi_vddc = pl->vddc;
3967 eg_pi->acpi_vddci = pl->vddci;
3968 if (ps->performance_levels[0].flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
3969 pi->acpi_pcie_gen2 = true;
3971 pi->acpi_pcie_gen2 = false;
3974 if (rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) {
3975 eg_pi->ulv.supported = true;
3979 if (pi->min_vddc_in_table > pl->vddc)
3980 pi->min_vddc_in_table = pl->vddc;
3982 if (pi->max_vddc_in_table < pl->vddc)
3983 pi->max_vddc_in_table = pl->vddc;
3985 /* patch up boot state */
3986 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
3987 u16 vddc, vddci, mvdd;
3988 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
3989 pl->mclk = rdev->clock.default_mclk;
3990 pl->sclk = rdev->clock.default_sclk;
3995 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
3996 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
3997 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
3998 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
3999 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
4000 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
4004 static int ni_parse_power_table(struct radeon_device *rdev)
4006 struct radeon_mode_info *mode_info = &rdev->mode_info;
4007 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
4008 union pplib_power_state *power_state;
4010 union pplib_clock_info *clock_info;
4011 union power_info *power_info;
4012 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
4017 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
4018 &frev, &crev, &data_offset))
4020 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
4022 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
4023 power_info->pplib.ucNumStates, GFP_KERNEL);
4024 if (!rdev->pm.dpm.ps)
4026 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
4027 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
4028 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
4030 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
4031 power_state = (union pplib_power_state *)
4032 (mode_info->atom_context->bios + data_offset +
4033 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
4034 i * power_info->pplib.ucStateEntrySize);
4035 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
4036 (mode_info->atom_context->bios + data_offset +
4037 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
4038 (power_state->v1.ucNonClockStateIndex *
4039 power_info->pplib.ucNonClockSize));
4040 if (power_info->pplib.ucStateEntrySize - 1) {
4042 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
4044 kfree(rdev->pm.dpm.ps);
4047 rdev->pm.dpm.ps[i].ps_priv = ps;
4048 ni_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
4050 power_info->pplib.ucNonClockSize);
4051 idx = (u8 *)&power_state->v1.ucClockStateIndices[0];
4052 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
4053 clock_info = (union pplib_clock_info *)
4054 (mode_info->atom_context->bios + data_offset +
4055 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
4056 (idx[j] * power_info->pplib.ucClockInfoSize));
4057 ni_parse_pplib_clock_info(rdev,
4058 &rdev->pm.dpm.ps[i], j,
4063 rdev->pm.dpm.num_ps = power_info->pplib.ucNumStates;
4067 int ni_dpm_init(struct radeon_device *rdev)
4069 struct rv7xx_power_info *pi;
4070 struct evergreen_power_info *eg_pi;
4071 struct ni_power_info *ni_pi;
4072 struct atom_clock_dividers dividers;
4075 ni_pi = kzalloc(sizeof(struct ni_power_info), GFP_KERNEL);
4078 rdev->pm.dpm.priv = ni_pi;
4082 rv770_get_max_vddc(rdev);
4084 eg_pi->ulv.supported = false;
4086 eg_pi->acpi_vddci = 0;
4087 pi->min_vddc_in_table = 0;
4088 pi->max_vddc_in_table = 0;
4090 ret = ni_parse_power_table(rdev);
4093 ret = r600_parse_extended_power_table(rdev);
4097 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
4098 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
4099 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
4100 r600_free_extended_power_table(rdev);
4103 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
4104 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
4105 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
4106 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
4107 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
4108 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
4109 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
4110 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
4111 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
4113 ni_patch_dependency_tables_based_on_leakage(rdev);
4115 if (rdev->pm.dpm.voltage_response_time == 0)
4116 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
4117 if (rdev->pm.dpm.backbias_response_time == 0)
4118 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
4120 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4121 0, false, ÷rs);
4123 pi->ref_div = dividers.ref_div + 1;
4125 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
4127 pi->rlp = RV770_RLP_DFLT;
4128 pi->rmp = RV770_RMP_DFLT;
4129 pi->lhp = RV770_LHP_DFLT;
4130 pi->lmp = RV770_LMP_DFLT;
4132 eg_pi->ats[0].rlp = RV770_RLP_DFLT;
4133 eg_pi->ats[0].rmp = RV770_RMP_DFLT;
4134 eg_pi->ats[0].lhp = RV770_LHP_DFLT;
4135 eg_pi->ats[0].lmp = RV770_LMP_DFLT;
4137 eg_pi->ats[1].rlp = BTC_RLP_UVD_DFLT;
4138 eg_pi->ats[1].rmp = BTC_RMP_UVD_DFLT;
4139 eg_pi->ats[1].lhp = BTC_LHP_UVD_DFLT;
4140 eg_pi->ats[1].lmp = BTC_LMP_UVD_DFLT;
4142 eg_pi->smu_uvd_hs = true;
4144 if (rdev->pdev->device == 0x6707) {
4145 pi->mclk_strobe_mode_threshold = 55000;
4146 pi->mclk_edc_enable_threshold = 55000;
4147 eg_pi->mclk_edc_wr_enable_threshold = 55000;
4149 pi->mclk_strobe_mode_threshold = 40000;
4150 pi->mclk_edc_enable_threshold = 40000;
4151 eg_pi->mclk_edc_wr_enable_threshold = 40000;
4153 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
4155 pi->voltage_control =
4156 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0);
4159 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 0);
4161 eg_pi->vddci_control =
4162 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0);
4164 rv770_get_engine_memory_ss(rdev);
4166 pi->asi = RV770_ASI_DFLT;
4167 pi->pasi = CYPRESS_HASI_DFLT;
4168 pi->vrc = CYPRESS_VRC_DFLT;
4170 pi->power_gating = false;
4172 pi->gfx_clock_gating = true;
4174 pi->mg_clock_gating = true;
4175 pi->mgcgtssm = true;
4176 eg_pi->ls_clock_gating = false;
4177 eg_pi->sclk_deep_sleep = false;
4179 pi->dynamic_pcie_gen2 = true;
4181 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE)
4182 pi->thermal_protection = true;
4184 pi->thermal_protection = false;
4186 pi->display_gap = true;
4192 eg_pi->dynamic_ac_timing = true;
4195 eg_pi->light_sleep = true;
4196 eg_pi->memory_transition = true;
4197 #if defined(CONFIG_ACPI)
4198 eg_pi->pcie_performance_request =
4199 radeon_acpi_is_pcie_performance_request_supported(rdev);
4201 eg_pi->pcie_performance_request = false;
4204 eg_pi->dll_default_on = false;
4206 eg_pi->sclk_deep_sleep = false;
4208 pi->mclk_stutter_mode_threshold = 0;
4210 pi->sram_end = SMC_RAM_END;
4212 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 3;
4213 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
4214 rdev->pm.dpm.dyn_state.min_vddc_for_pcie_gen2 = 900;
4215 rdev->pm.dpm.dyn_state.valid_sclk_values.count = ARRAY_SIZE(btc_valid_sclk);
4216 rdev->pm.dpm.dyn_state.valid_sclk_values.values = btc_valid_sclk;
4217 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
4218 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
4219 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 12500;
4221 ni_pi->cac_data.leakage_coefficients.at = 516;
4222 ni_pi->cac_data.leakage_coefficients.bt = 18;
4223 ni_pi->cac_data.leakage_coefficients.av = 51;
4224 ni_pi->cac_data.leakage_coefficients.bv = 2957;
4226 switch (rdev->pdev->device) {
4232 ni_pi->cac_weights = &cac_weights_cayman_xt;
4239 ni_pi->cac_weights = &cac_weights_cayman_pro;
4246 ni_pi->cac_weights = &cac_weights_cayman_le;
4250 if (ni_pi->cac_weights->enable_power_containment_by_default) {
4251 ni_pi->enable_power_containment = true;
4252 ni_pi->enable_cac = true;
4253 ni_pi->enable_sq_ramping = true;
4255 ni_pi->enable_power_containment = false;
4256 ni_pi->enable_cac = false;
4257 ni_pi->enable_sq_ramping = false;
4260 ni_pi->driver_calculate_cac_leakage = false;
4261 ni_pi->cac_configuration_required = true;
4263 if (ni_pi->cac_configuration_required) {
4264 ni_pi->support_cac_long_term_average = true;
4265 ni_pi->lta_window_size = ni_pi->cac_weights->l2_lta_window_size;
4266 ni_pi->lts_truncate = ni_pi->cac_weights->lts_truncate;
4268 ni_pi->support_cac_long_term_average = false;
4269 ni_pi->lta_window_size = 0;
4270 ni_pi->lts_truncate = 0;
4273 ni_pi->use_power_boost_limit = true;
4275 /* make sure dc limits are valid */
4276 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
4277 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
4278 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
4279 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
4284 void ni_dpm_fini(struct radeon_device *rdev)
4288 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
4289 kfree(rdev->pm.dpm.ps[i].ps_priv);
4291 kfree(rdev->pm.dpm.ps);
4292 kfree(rdev->pm.dpm.priv);
4293 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
4294 r600_free_extended_power_table(rdev);
4297 void ni_dpm_print_power_state(struct radeon_device *rdev,
4298 struct radeon_ps *rps)
4300 struct ni_ps *ps = ni_get_ps(rps);
4301 struct rv7xx_pl *pl;
4304 r600_dpm_print_class_info(rps->class, rps->class2);
4305 r600_dpm_print_cap_info(rps->caps);
4306 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
4307 for (i = 0; i < ps->performance_level_count; i++) {
4308 pl = &ps->performance_levels[i];
4309 if (rdev->family >= CHIP_TAHITI)
4310 printk("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
4311 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
4313 printk("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
4314 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
4316 r600_dpm_print_ps_status(rdev, rps);
4319 void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
4322 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
4323 struct ni_ps *ps = ni_get_ps(rps);
4324 struct rv7xx_pl *pl;
4326 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
4327 CURRENT_STATE_INDEX_SHIFT;
4329 if (current_index >= ps->performance_level_count) {
4330 seq_printf(m, "invalid dpm profile %d\n", current_index);
4332 pl = &ps->performance_levels[current_index];
4333 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
4334 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
4335 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
4339 u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low)
4341 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4342 struct ni_ps *requested_state = ni_get_ps(&eg_pi->requested_rps);
4345 return requested_state->performance_levels[0].sclk;
4347 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
4350 u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low)
4352 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4353 struct ni_ps *requested_state = ni_get_ps(&eg_pi->requested_rps);
4356 return requested_state->performance_levels[0].mclk;
4358 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;