drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/module.h>
  45
  46 #include "r100_reg_safe.h"
  47 #include "rn50_reg_safe.h"
  48
  49 /* Firmware Names */
  50 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  51 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  52 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  53 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  54 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  55 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  56 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  57
  58 MODULE_FIRMWARE(FIRMWARE_R100);
  59 MODULE_FIRMWARE(FIRMWARE_R200);
  60 MODULE_FIRMWARE(FIRMWARE_R300);
  61 MODULE_FIRMWARE(FIRMWARE_R420);
  62 MODULE_FIRMWARE(FIRMWARE_RS690);
  63 MODULE_FIRMWARE(FIRMWARE_RS600);
  64 MODULE_FIRMWARE(FIRMWARE_R520);
  65
  66 #include "r100_track.h"
  67
  68 /* This files gather functions specifics to:
  69  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  70  * and others in some cases.
  71  */
  72
  73 /**
  74  * r100_wait_for_vblank - vblank wait asic callback.
  75  *
  76  * @rdev: radeon_device pointer
  77  * @crtc: crtc to wait for vblank on
  78  *
  79  * Wait for vblank on the requested crtc (r1xx-r4xx).
  80  */
  81 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
  82 {
  83         int i;
  84
  85         if (crtc >= rdev->num_crtc)
  86                 return;
  87
  88         if (crtc == 0) {
  89                 if (RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN) {
  90                         for (i = 0; i < rdev->usec_timeout; i++) {
  91                                 if (!(RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR))
  92                                         break;
  93                                 udelay(1);
  94                         }
  95                         for (i = 0; i < rdev->usec_timeout; i++) {
  96                                 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
  97                                         break;
  98                                 udelay(1);
  99                         }
 100                 }
 101         } else {
 102                 if (RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN) {
 103                         for (i = 0; i < rdev->usec_timeout; i++) {
 104                                 if (!(RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR))
 105                                         break;
 106                                 udelay(1);
 107                         }
 108                         for (i = 0; i < rdev->usec_timeout; i++) {
 109                                 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
 110                                         break;
 111                                 udelay(1);
 112                         }
 113                 }
 114         }
 115 }
 116
 117 /**
 118  * r100_pre_page_flip - pre-pageflip callback.
 119  *
 120  * @rdev: radeon_device pointer
 121  * @crtc: crtc to prepare for pageflip on
 122  *
 123  * Pre-pageflip callback (r1xx-r4xx).
 124  * Enables the pageflip irq (vblank irq).
 125  */
 126 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
 127 {
 128         /* enable the pflip int */
 129         radeon_irq_kms_pflip_irq_get(rdev, crtc);
 130 }
 131
 132 /**
 133  * r100_post_page_flip - pos-pageflip callback.
 134  *
 135  * @rdev: radeon_device pointer
 136  * @crtc: crtc to cleanup pageflip on
 137  *
 138  * Post-pageflip callback (r1xx-r4xx).
 139  * Disables the pageflip irq (vblank irq).
 140  */
 141 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
 142 {
 143         /* disable the pflip int */
 144         radeon_irq_kms_pflip_irq_put(rdev, crtc);
 145 }
 146
 147 /**
 148  * r100_page_flip - pageflip callback.
 149  *
 150  * @rdev: radeon_device pointer
 151  * @crtc_id: crtc to cleanup pageflip on
 152  * @crtc_base: new address of the crtc (GPU MC address)
 153  *
 154  * Does the actual pageflip (r1xx-r4xx).
 155  * During vblank we take the crtc lock and wait for the update_pending
 156  * bit to go high, when it does, we release the lock, and allow the
 157  * double buffered update to take place.
 158  * Returns the current update pending status.
 159  */
 160 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 161 {
 162         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 163         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 164         int i;
 165
 166         /* Lock the graphics update lock */
 167         /* update the scanout addresses */
 168         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 169
 170         /* Wait for update_pending to go high. */
 171         for (i = 0; i < rdev->usec_timeout; i++) {
 172                 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
 173                         break;
 174                 udelay(1);
 175         }
 176         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 177
 178         /* Unlock the lock, so double-buffering can take place inside vblank */
 179         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 180         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 181
 182         /* Return current update_pending status: */
 183         return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
 184 }
 185
 186 /**
 187  * r100_pm_get_dynpm_state - look up dynpm power state callback.
 188  *
 189  * @rdev: radeon_device pointer
 190  *
 191  * Look up the optimal power state based on the
 192  * current state of the GPU (r1xx-r5xx).
 193  * Used for dynpm only.
 194  */
 195 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 196 {
 197         int i;
 198         rdev->pm.dynpm_can_upclock = true;
 199         rdev->pm.dynpm_can_downclock = true;
 200
 201         switch (rdev->pm.dynpm_planned_action) {
 202         case DYNPM_ACTION_MINIMUM:
 203                 rdev->pm.requested_power_state_index = 0;
 204                 rdev->pm.dynpm_can_downclock = false;
 205                 break;
 206         case DYNPM_ACTION_DOWNCLOCK:
 207                 if (rdev->pm.current_power_state_index == 0) {
 208                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 209                         rdev->pm.dynpm_can_downclock = false;
 210                 } else {
 211                         if (rdev->pm.active_crtc_count > 1) {
 212                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 213                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 214                                                 continue;
 215                                         else if (i >= rdev->pm.current_power_state_index) {
 216                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 217                                                 break;
 218                                         } else {
 219                                                 rdev->pm.requested_power_state_index = i;
 220                                                 break;
 221                                         }
 222                                 }
 223                         } else
 224                                 rdev->pm.requested_power_state_index =
 225                                         rdev->pm.current_power_state_index - 1;
 226                 }
 227                 /* don't use the power state if crtcs are active and no display flag is set */
 228                 if ((rdev->pm.active_crtc_count > 0) &&
 229                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 230                      RADEON_PM_MODE_NO_DISPLAY)) {
 231                         rdev->pm.requested_power_state_index++;
 232                 }
 233                 break;
 234         case DYNPM_ACTION_UPCLOCK:
 235                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 236                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 237                         rdev->pm.dynpm_can_upclock = false;
 238                 } else {
 239                         if (rdev->pm.active_crtc_count > 1) {
 240                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 241                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 242                                                 continue;
 243                                         else if (i <= rdev->pm.current_power_state_index) {
 244                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 245                                                 break;
 246                                         } else {
 247                                                 rdev->pm.requested_power_state_index = i;
 248                                                 break;
 249                                         }
 250                                 }
 251                         } else
 252                                 rdev->pm.requested_power_state_index =
 253                                         rdev->pm.current_power_state_index + 1;
 254                 }
 255                 break;
 256         case DYNPM_ACTION_DEFAULT:
 257                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 258                 rdev->pm.dynpm_can_upclock = false;
 259                 break;
 260         case DYNPM_ACTION_NONE:
 261         default:
 262                 DRM_ERROR("Requested mode for not defined action\n");
 263                 return;
 264         }
 265         /* only one clock mode per power state */
 266         rdev->pm.requested_clock_mode_index = 0;
 267
 268         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 269                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 270                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 271                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 272                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 273                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 274                   pcie_lanes);
 275 }
 276
 277 /**
 278  * r100_pm_init_profile - Initialize power profiles callback.
 279  *
 280  * @rdev: radeon_device pointer
 281  *
 282  * Initialize the power states used in profile mode
 283  * (r1xx-r3xx).
 284  * Used for profile mode only.
 285  */
 286 void r100_pm_init_profile(struct radeon_device *rdev)
 287 {
 288         /* default */
 289         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 290         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 291         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 292         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 293         /* low sh */
 294         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 295         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 296         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 297         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 298         /* mid sh */
 299         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 300         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 301         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 302         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 303         /* high sh */
 304         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 305         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 306         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 307         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 308         /* low mh */
 309         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 310         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 311         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 312         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 313         /* mid mh */
 314         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 315         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 316         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 317         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 318         /* high mh */
 319         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 320         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 321         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 322         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 323 }
 324
 325 /**
 326  * r100_pm_misc - set additional pm hw parameters callback.
 327  *
 328  * @rdev: radeon_device pointer
 329  *
 330  * Set non-clock parameters associated with a power state
 331  * (voltage, pcie lanes, etc.) (r1xx-r4xx).
 332  */
 333 void r100_pm_misc(struct radeon_device *rdev)
 334 {
 335         int requested_index = rdev->pm.requested_power_state_index;
 336         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 337         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 338         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 339
 340         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 341                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 342                         tmp = RREG32(voltage->gpio.reg);
 343                         if (voltage->active_high)
 344                                 tmp |= voltage->gpio.mask;
 345                         else
 346                                 tmp &= ~(voltage->gpio.mask);
 347                         WREG32(voltage->gpio.reg, tmp);
 348                         if (voltage->delay)
 349                                 udelay(voltage->delay);
 350                 } else {
 351                         tmp = RREG32(voltage->gpio.reg);
 352                         if (voltage->active_high)
 353                                 tmp &= ~voltage->gpio.mask;
 354                         else
 355                                 tmp |= voltage->gpio.mask;
 356                         WREG32(voltage->gpio.reg, tmp);
 357                         if (voltage->delay)
 358                                 udelay(voltage->delay);
 359                 }
 360         }
 361
 362         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 363         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 364         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 365         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 366         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 367         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 368                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 369                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 370                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 371                 else
 372                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 373                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 374                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 375                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 376                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 377         } else
 378                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 379
 380         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 381                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 382                 if (voltage->delay) {
 383                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 384                         switch (voltage->delay) {
 385                         case 33:
 386                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 387                                 break;
 388                         case 66:
 389                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 390                                 break;
 391                         case 99:
 392                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 393                                 break;
 394                         case 132:
 395                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 396                                 break;
 397                         }
 398                 } else
 399                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 400         } else
 401                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 402
 403         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 404                 sclk_cntl &= ~FORCE_HDP;
 405         else
 406                 sclk_cntl |= FORCE_HDP;
 407
 408         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 409         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 410         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 411
 412         /* set pcie lanes */
 413         if ((rdev->flags & RADEON_IS_PCIE) &&
 414             !(rdev->flags & RADEON_IS_IGP) &&
 415             rdev->asic->pm.set_pcie_lanes &&
 416             (ps->pcie_lanes !=
 417              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 418                 radeon_set_pcie_lanes(rdev,
 419                                       ps->pcie_lanes);
 420                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 421         }
 422 }
 423
 424 /**
 425  * r100_pm_prepare - pre-power state change callback.
 426  *
 427  * @rdev: radeon_device pointer
 428  *
 429  * Prepare for a power state change (r1xx-r4xx).
 430  */
 431 void r100_pm_prepare(struct radeon_device *rdev)
 432 {
 433         struct drm_device *ddev = rdev->ddev;
 434         struct drm_crtc *crtc;
 435         struct radeon_crtc *radeon_crtc;
 436         u32 tmp;
 437
 438         /* disable any active CRTCs */
 439         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 440                 radeon_crtc = to_radeon_crtc(crtc);
 441                 if (radeon_crtc->enabled) {
 442                         if (radeon_crtc->crtc_id) {
 443                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 444                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 445                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 446                         } else {
 447                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 448                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 449                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 450                         }
 451                 }
 452         }
 453 }
 454
 455 /**
 456  * r100_pm_finish - post-power state change callback.
 457  *
 458  * @rdev: radeon_device pointer
 459  *
 460  * Clean up after a power state change (r1xx-r4xx).
 461  */
 462 void r100_pm_finish(struct radeon_device *rdev)
 463 {
 464         struct drm_device *ddev = rdev->ddev;
 465         struct drm_crtc *crtc;
 466         struct radeon_crtc *radeon_crtc;
 467         u32 tmp;
 468
 469         /* enable any active CRTCs */
 470         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 471                 radeon_crtc = to_radeon_crtc(crtc);
 472                 if (radeon_crtc->enabled) {
 473                         if (radeon_crtc->crtc_id) {
 474                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 475                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 476                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 477                         } else {
 478                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 479                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 480                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 481                         }
 482                 }
 483         }
 484 }
 485
 486 /**
 487  * r100_gui_idle - gui idle callback.
 488  *
 489  * @rdev: radeon_device pointer
 490  *
 491  * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
 492  * Returns true if idle, false if not.
 493  */
 494 bool r100_gui_idle(struct radeon_device *rdev)
 495 {
 496         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 497                 return false;
 498         else
 499                 return true;
 500 }
 501
 502 /* hpd for digital panel detect/disconnect */
 503 /**
 504  * r100_hpd_sense - hpd sense callback.
 505  *
 506  * @rdev: radeon_device pointer
 507  * @hpd: hpd (hotplug detect) pin
 508  *
 509  * Checks if a digital monitor is connected (r1xx-r4xx).
 510  * Returns true if connected, false if not connected.
 511  */
 512 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 513 {
 514         bool connected = false;
 515
 516         switch (hpd) {
 517         case RADEON_HPD_1:
 518                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 519                         connected = true;
 520                 break;
 521         case RADEON_HPD_2:
 522                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 523                         connected = true;
 524                 break;
 525         default:
 526                 break;
 527         }
 528         return connected;
 529 }
 530
 531 /**
 532  * r100_hpd_set_polarity - hpd set polarity callback.
 533  *
 534  * @rdev: radeon_device pointer
 535  * @hpd: hpd (hotplug detect) pin
 536  *
 537  * Set the polarity of the hpd pin (r1xx-r4xx).
 538  */
 539 void r100_hpd_set_polarity(struct radeon_device *rdev,
 540                            enum radeon_hpd_id hpd)
 541 {
 542         u32 tmp;
 543         bool connected = r100_hpd_sense(rdev, hpd);
 544
 545         switch (hpd) {
 546         case RADEON_HPD_1:
 547                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 548                 if (connected)
 549                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 550                 else
 551                         tmp |= RADEON_FP_DETECT_INT_POL;
 552                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 553                 break;
 554         case RADEON_HPD_2:
 555                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 556                 if (connected)
 557                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 558                 else
 559                         tmp |= RADEON_FP2_DETECT_INT_POL;
 560                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 561                 break;
 562         default:
 563                 break;
 564         }
 565 }
 566
 567 /**
 568  * r100_hpd_init - hpd setup callback.
 569  *
 570  * @rdev: radeon_device pointer
 571  *
 572  * Setup the hpd pins used by the card (r1xx-r4xx).
 573  * Set the polarity, and enable the hpd interrupts.
 574  */
 575 void r100_hpd_init(struct radeon_device *rdev)
 576 {
 577         struct drm_device *dev = rdev->ddev;
 578         struct drm_connector *connector;
 579         unsigned enable = 0;
 580
 581         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 582                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 583                 enable |= 1 << radeon_connector->hpd.hpd;
 584                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 585         }
 586         radeon_irq_kms_enable_hpd(rdev, enable);
 587 }
 588
 589 /**
 590  * r100_hpd_fini - hpd tear down callback.
 591  *
 592  * @rdev: radeon_device pointer
 593  *
 594  * Tear down the hpd pins used by the card (r1xx-r4xx).
 595  * Disable the hpd interrupts.
 596  */
 597 void r100_hpd_fini(struct radeon_device *rdev)
 598 {
 599         struct drm_device *dev = rdev->ddev;
 600         struct drm_connector *connector;
 601         unsigned disable = 0;
 602
 603         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 604                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 605                 disable |= 1 << radeon_connector->hpd.hpd;
 606         }
 607         radeon_irq_kms_disable_hpd(rdev, disable);
 608 }
 609
 610 /*
 611  * PCI GART
 612  */
 613 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 614 {
 615         /* TODO: can we do somethings here ? */
 616         /* It seems hw only cache one entry so we should discard this
 617          * entry otherwise if first GPU GART read hit this entry it
 618          * could end up in wrong address. */
 619 }
 620
 621 int r100_pci_gart_init(struct radeon_device *rdev)
 622 {
 623         int r;
 624
 625         if (rdev->gart.ptr) {
 626                 WARN(1, "R100 PCI GART already initialized\n");
 627                 return 0;
 628         }
 629         /* Initialize common gart structure */
 630         r = radeon_gart_init(rdev);
 631         if (r)
 632                 return r;
 633         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 634         rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 635         rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 636         return radeon_gart_table_ram_alloc(rdev);
 637 }
 638
 639 int r100_pci_gart_enable(struct radeon_device *rdev)
 640 {
 641         uint32_t tmp;
 642
 643         radeon_gart_restore(rdev);
 644         /* discard memory request outside of configured range */
 645         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 646         WREG32(RADEON_AIC_CNTL, tmp);
 647         /* set address range for PCI address translate */
 648         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 649         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 650         /* set PCI GART page-table base address */
 651         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 652         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 653         WREG32(RADEON_AIC_CNTL, tmp);
 654         r100_pci_gart_tlb_flush(rdev);
 655         DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
 656                  (unsigned)(rdev->mc.gtt_size >> 20),
 657                  (unsigned long long)rdev->gart.table_addr);
 658         rdev->gart.ready = true;
 659         return 0;
 660 }
 661
 662 void r100_pci_gart_disable(struct radeon_device *rdev)
 663 {
 664         uint32_t tmp;
 665
 666         /* discard memory request outside of configured range */
 667         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 668         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 669         WREG32(RADEON_AIC_LO_ADDR, 0);
 670         WREG32(RADEON_AIC_HI_ADDR, 0);
 671 }
 672
 673 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 674 {
 675         u32 *gtt = rdev->gart.ptr;
 676
 677         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 678                 return -EINVAL;
 679         }
 680         gtt[i] = cpu_to_le32(lower_32_bits(addr));
 681         return 0;
 682 }
 683
 684 void r100_pci_gart_fini(struct radeon_device *rdev)
 685 {
 686         radeon_gart_fini(rdev);
 687         r100_pci_gart_disable(rdev);
 688         radeon_gart_table_ram_free(rdev);
 689 }
 690
 691 int r100_irq_set(struct radeon_device *rdev)
 692 {
 693         uint32_t tmp = 0;
 694
 695         if (!rdev->irq.installed) {
 696                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 697                 WREG32(R_000040_GEN_INT_CNTL, 0);
 698                 return -EINVAL;
 699         }
 700         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 701                 tmp |= RADEON_SW_INT_ENABLE;
 702         }
 703         if (rdev->irq.gui_idle) {
 704                 tmp |= RADEON_GUI_IDLE_MASK;
 705         }
 706         if (rdev->irq.crtc_vblank_int[0] ||
 707             atomic_read(&rdev->irq.pflip[0])) {
 708                 tmp |= RADEON_CRTC_VBLANK_MASK;
 709         }
 710         if (rdev->irq.crtc_vblank_int[1] ||
 711             atomic_read(&rdev->irq.pflip[1])) {
 712                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 713         }
 714         if (rdev->irq.hpd[0]) {
 715                 tmp |= RADEON_FP_DETECT_MASK;
 716         }
 717         if (rdev->irq.hpd[1]) {
 718                 tmp |= RADEON_FP2_DETECT_MASK;
 719         }
 720         WREG32(RADEON_GEN_INT_CNTL, tmp);
 721         return 0;
 722 }
 723
 724 void r100_irq_disable(struct radeon_device *rdev)
 725 {
 726         u32 tmp;
 727
 728         WREG32(R_000040_GEN_INT_CNTL, 0);
 729         /* Wait and acknowledge irq */
 730         mdelay(1);
 731         tmp = RREG32(R_000044_GEN_INT_STATUS);
 732         WREG32(R_000044_GEN_INT_STATUS, tmp);
 733 }
 734
 735 static uint32_t r100_irq_ack(struct radeon_device *rdev)
 736 {
 737         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 738         uint32_t irq_mask = RADEON_SW_INT_TEST |
 739                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 740                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 741
 742         /* the interrupt works, but the status bit is permanently asserted */
 743         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 744                 if (!rdev->irq.gui_idle_acked)
 745                         irq_mask |= RADEON_GUI_IDLE_STAT;
 746         }
 747
 748         if (irqs) {
 749                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 750         }
 751         return irqs & irq_mask;
 752 }
 753
 754 int r100_irq_process(struct radeon_device *rdev)
 755 {
 756         uint32_t status, msi_rearm;
 757         bool queue_hotplug = false;
 758
 759         /* reset gui idle ack.  the status bit is broken */
 760         rdev->irq.gui_idle_acked = false;
 761
 762         status = r100_irq_ack(rdev);
 763         if (!status) {
 764                 return IRQ_NONE;
 765         }
 766         if (rdev->shutdown) {
 767                 return IRQ_NONE;
 768         }
 769         while (status) {
 770                 /* SW interrupt */
 771                 if (status & RADEON_SW_INT_TEST) {
 772                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 773                 }
 774                 /* gui idle interrupt */
 775                 if (status & RADEON_GUI_IDLE_STAT) {
 776                         rdev->irq.gui_idle_acked = true;
 777                         wake_up(&rdev->irq.idle_queue);
 778                 }
 779                 /* Vertical blank interrupts */
 780                 if (status & RADEON_CRTC_VBLANK_STAT) {
 781                         if (rdev->irq.crtc_vblank_int[0]) {
 782                                 drm_handle_vblank(rdev->ddev, 0);
 783                                 rdev->pm.vblank_sync = true;
 784                                 wake_up(&rdev->irq.vblank_queue);
 785                         }
 786                         if (atomic_read(&rdev->irq.pflip[0]))
 787                                 radeon_crtc_handle_flip(rdev, 0);
 788                 }
 789                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 790                         if (rdev->irq.crtc_vblank_int[1]) {
 791                                 drm_handle_vblank(rdev->ddev, 1);
 792                                 rdev->pm.vblank_sync = true;
 793                                 wake_up(&rdev->irq.vblank_queue);
 794                         }
 795                         if (atomic_read(&rdev->irq.pflip[1]))
 796                                 radeon_crtc_handle_flip(rdev, 1);
 797                 }
 798                 if (status & RADEON_FP_DETECT_STAT) {
 799                         queue_hotplug = true;
 800                         DRM_DEBUG("HPD1\n");
 801                 }
 802                 if (status & RADEON_FP2_DETECT_STAT) {
 803                         queue_hotplug = true;
 804                         DRM_DEBUG("HPD2\n");
 805                 }
 806                 status = r100_irq_ack(rdev);
 807         }
 808         /* reset gui idle ack.  the status bit is broken */
 809         rdev->irq.gui_idle_acked = false;
 810         if (queue_hotplug)
 811                 schedule_work(&rdev->hotplug_work);
 812         if (rdev->msi_enabled) {
 813                 switch (rdev->family) {
 814                 case CHIP_RS400:
 815                 case CHIP_RS480:
 816                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 817                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 818                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 819                         break;
 820                 default:
 821                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 822                         break;
 823                 }
 824         }
 825         return IRQ_HANDLED;
 826 }
 827
 828 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 829 {
 830         if (crtc == 0)
 831                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 832         else
 833                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 834 }
 835
 836 /* Who ever call radeon_fence_emit should call ring_lock and ask
 837  * for enough space (today caller are ib schedule and buffer move) */
 838 void r100_fence_ring_emit(struct radeon_device *rdev,
 839                           struct radeon_fence *fence)
 840 {
 841         struct radeon_ring *ring = &rdev->ring[fence->ring];
 842
 843         /* We have to make sure that caches are flushed before
 844          * CPU might read something from VRAM. */
 845         radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 846         radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
 847         radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 848         radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
 849         /* Wait until IDLE & CLEAN */
 850         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 851         radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 852         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 853         radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
 854                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 855         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 856         radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
 857         /* Emit fence sequence & fire IRQ */
 858         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 859         radeon_ring_write(ring, fence->seq);
 860         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 861         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 862 }
 863
 864 void r100_semaphore_ring_emit(struct radeon_device *rdev,
 865                               struct radeon_ring *ring,
 866                               struct radeon_semaphore *semaphore,
 867                               bool emit_wait)
 868 {
 869         /* Unused on older asics, since we don't have semaphores or multiple rings */
 870         BUG();
 871 }
 872
 873 int r100_copy_blit(struct radeon_device *rdev,
 874                    uint64_t src_offset,
 875                    uint64_t dst_offset,
 876                    unsigned num_gpu_pages,
 877                    struct radeon_fence **fence)
 878 {
 879         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 880         uint32_t cur_pages;
 881         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
 882         uint32_t pitch;
 883         uint32_t stride_pixels;
 884         unsigned ndw;
 885         int num_loops;
 886         int r = 0;
 887
 888         /* radeon limited to 16k stride */
 889         stride_bytes &= 0x3fff;
 890         /* radeon pitch is /64 */
 891         pitch = stride_bytes / 64;
 892         stride_pixels = stride_bytes / 4;
 893         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
 894
 895         /* Ask for enough room for blit + flush + fence */
 896         ndw = 64 + (10 * num_loops);
 897         r = radeon_ring_lock(rdev, ring, ndw);
 898         if (r) {
 899                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 900                 return -EINVAL;
 901         }
 902         while (num_gpu_pages > 0) {
 903                 cur_pages = num_gpu_pages;
 904                 if (cur_pages > 8191) {
 905                         cur_pages = 8191;
 906                 }
 907                 num_gpu_pages -= cur_pages;
 908
 909                 /* pages are in Y direction - height
 910                    page width in X direction - width */
 911                 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
 912                 radeon_ring_write(ring,
 913                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 914                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 915                                   RADEON_GMC_SRC_CLIPPING |
 916                                   RADEON_GMC_DST_CLIPPING |
 917                                   RADEON_GMC_BRUSH_NONE |
 918                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 919                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 920                                   RADEON_ROP3_S |
 921                                   RADEON_DP_SRC_SOURCE_MEMORY |
 922                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 923                                   RADEON_GMC_WR_MSK_DIS);
 924                 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
 925                 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
 926                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 927                 radeon_ring_write(ring, 0);
 928                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 929                 radeon_ring_write(ring, num_gpu_pages);
 930                 radeon_ring_write(ring, num_gpu_pages);
 931                 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
 932         }
 933         radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 934         radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
 935         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 936         radeon_ring_write(ring,
 937                           RADEON_WAIT_2D_IDLECLEAN |
 938                           RADEON_WAIT_HOST_IDLECLEAN |
 939                           RADEON_WAIT_DMA_GUI_IDLE);
 940         if (fence) {
 941                 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
 942         }
 943         radeon_ring_unlock_commit(rdev, ring);
 944         return r;
 945 }
 946
 947 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 948 {
 949         unsigned i;
 950         u32 tmp;
 951
 952         for (i = 0; i < rdev->usec_timeout; i++) {
 953                 tmp = RREG32(R_000E40_RBBM_STATUS);
 954                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 955                         return 0;
 956                 }
 957                 udelay(1);
 958         }
 959         return -1;
 960 }
 961
 962 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 963 {
 964         int r;
 965
 966         r = radeon_ring_lock(rdev, ring, 2);
 967         if (r) {
 968                 return;
 969         }
 970         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
 971         radeon_ring_write(ring,
 972                           RADEON_ISYNC_ANY2D_IDLE3D |
 973                           RADEON_ISYNC_ANY3D_IDLE2D |
 974                           RADEON_ISYNC_WAIT_IDLEGUI |
 975                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 976         radeon_ring_unlock_commit(rdev, ring);
 977 }
 978
 979
 980 /* Load the microcode for the CP */
 981 static int r100_cp_init_microcode(struct radeon_device *rdev)
 982 {
 983         struct platform_device *pdev;
 984         const char *fw_name = NULL;
 985         int err;
 986
 987         DRM_DEBUG_KMS("\n");
 988
 989         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 990         err = IS_ERR(pdev);
 991         if (err) {
 992                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 993                 return -EINVAL;
 994         }
 995         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 996             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 997             (rdev->family == CHIP_RS200)) {
 998                 DRM_INFO("Loading R100 Microcode\n");
 999                 fw_name = FIRMWARE_R100;
1000         } else if ((rdev->family == CHIP_R200) ||
1001                    (rdev->family == CHIP_RV250) ||
1002                    (rdev->family == CHIP_RV280) ||
1003                    (rdev->family == CHIP_RS300)) {
1004                 DRM_INFO("Loading R200 Microcode\n");
1005                 fw_name = FIRMWARE_R200;
1006         } else if ((rdev->family == CHIP_R300) ||
1007                    (rdev->family == CHIP_R350) ||
1008                    (rdev->family == CHIP_RV350) ||
1009                    (rdev->family == CHIP_RV380) ||
1010                    (rdev->family == CHIP_RS400) ||
1011                    (rdev->family == CHIP_RS480)) {
1012                 DRM_INFO("Loading R300 Microcode\n");
1013                 fw_name = FIRMWARE_R300;
1014         } else if ((rdev->family == CHIP_R420) ||
1015                    (rdev->family == CHIP_R423) ||
1016                    (rdev->family == CHIP_RV410)) {
1017                 DRM_INFO("Loading R400 Microcode\n");
1018                 fw_name = FIRMWARE_R420;
1019         } else if ((rdev->family == CHIP_RS690) ||
1020                    (rdev->family == CHIP_RS740)) {
1021                 DRM_INFO("Loading RS690/RS740 Microcode\n");
1022                 fw_name = FIRMWARE_RS690;
1023         } else if (rdev->family == CHIP_RS600) {
1024                 DRM_INFO("Loading RS600 Microcode\n");
1025                 fw_name = FIRMWARE_RS600;
1026         } else if ((rdev->family == CHIP_RV515) ||
1027                    (rdev->family == CHIP_R520) ||
1028                    (rdev->family == CHIP_RV530) ||
1029                    (rdev->family == CHIP_R580) ||
1030                    (rdev->family == CHIP_RV560) ||
1031                    (rdev->family == CHIP_RV570)) {
1032                 DRM_INFO("Loading R500 Microcode\n");
1033                 fw_name = FIRMWARE_R520;
1034         }
1035
1036         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1037         platform_device_unregister(pdev);
1038         if (err) {
1039                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1040                        fw_name);
1041         } else if (rdev->me_fw->size % 8) {
1042                 printk(KERN_ERR
1043                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1044                        rdev->me_fw->size, fw_name);
1045                 err = -EINVAL;
1046                 release_firmware(rdev->me_fw);
1047                 rdev->me_fw = NULL;
1048         }
1049         return err;
1050 }
1051
1052 static void r100_cp_load_microcode(struct radeon_device *rdev)
1053 {
1054         const __be32 *fw_data;
1055         int i, size;
1056
1057         if (r100_gui_wait_for_idle(rdev)) {
1058                 printk(KERN_WARNING "Failed to wait GUI idle while "
1059                        "programming pipes. Bad things might happen.\n");
1060         }
1061
1062         if (rdev->me_fw) {
1063                 size = rdev->me_fw->size / 4;
1064                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1065                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1066                 for (i = 0; i < size; i += 2) {
1067                         WREG32(RADEON_CP_ME_RAM_DATAH,
1068                                be32_to_cpup(&fw_data[i]));
1069                         WREG32(RADEON_CP_ME_RAM_DATAL,
1070                                be32_to_cpup(&fw_data[i + 1]));
1071                 }
1072         }
1073 }
1074
1075 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1076 {
1077         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1078         unsigned rb_bufsz;
1079         unsigned rb_blksz;
1080         unsigned max_fetch;
1081         unsigned pre_write_timer;
1082         unsigned pre_write_limit;
1083         unsigned indirect2_start;
1084         unsigned indirect1_start;
1085         uint32_t tmp;
1086         int r;
1087
1088         if (r100_debugfs_cp_init(rdev)) {
1089                 DRM_ERROR("Failed to register debugfs file for CP !\n");
1090         }
1091         if (!rdev->me_fw) {
1092                 r = r100_cp_init_microcode(rdev);
1093                 if (r) {
1094                         DRM_ERROR("Failed to load firmware!\n");
1095                         return r;
1096                 }
1097         }
1098
1099         /* Align ring size */
1100         rb_bufsz = drm_order(ring_size / 8);
1101         ring_size = (1 << (rb_bufsz + 1)) * 4;
1102         r100_cp_load_microcode(rdev);
1103         r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1104                              RADEON_CP_RB_RPTR, RADEON_CP_RB_WPTR,
1105                              0, 0x7fffff, RADEON_CP_PACKET2);
1106         if (r) {
1107                 return r;
1108         }
1109         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1110          * the rptr copy in system ram */
1111         rb_blksz = 9;
1112         /* cp will read 128bytes at a time (4 dwords) */
1113         max_fetch = 1;
1114         ring->align_mask = 16 - 1;
1115         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1116         pre_write_timer = 64;
1117         /* Force CP_RB_WPTR write if written more than one time before the
1118          * delay expire
1119          */
1120         pre_write_limit = 0;
1121         /* Setup the cp cache like this (cache size is 96 dwords) :
1122          *      RING            0  to 15
1123          *      INDIRECT1       16 to 79
1124          *      INDIRECT2       80 to 95
1125          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1126          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1127          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1128          * Idea being that most of the gpu cmd will be through indirect1 buffer
1129          * so it gets the bigger cache.
1130          */
1131         indirect2_start = 80;
1132         indirect1_start = 16;
1133         /* cp setup */
1134         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1135         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1136                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1137                REG_SET(RADEON_MAX_FETCH, max_fetch));
1138 #ifdef __BIG_ENDIAN
1139         tmp |= RADEON_BUF_SWAP_32BIT;
1140 #endif
1141         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1142
1143         /* Set ring address */
1144         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1145         WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1146         /* Force read & write ptr to 0 */
1147         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1148         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1149         ring->wptr = 0;
1150         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1151
1152         /* set the wb address whether it's enabled or not */
1153         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1154                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1155         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1156
1157         if (rdev->wb.enabled)
1158                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1159         else {
1160                 tmp |= RADEON_RB_NO_UPDATE;
1161                 WREG32(R_000770_SCRATCH_UMSK, 0);
1162         }
1163
1164         WREG32(RADEON_CP_RB_CNTL, tmp);
1165         udelay(10);
1166         ring->rptr = RREG32(RADEON_CP_RB_RPTR);
1167         /* Set cp mode to bus mastering & enable cp*/
1168         WREG32(RADEON_CP_CSQ_MODE,
1169                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1170                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1171         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1172         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1173         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1174
1175         /* at this point everything should be setup correctly to enable master */
1176         pci_set_master(rdev->pdev);
1177
1178         radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1179         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1180         if (r) {
1181                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1182                 return r;
1183         }
1184         ring->ready = true;
1185         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1186
1187         if (!ring->rptr_save_reg /* not resuming from suspend */
1188             && radeon_ring_supports_scratch_reg(rdev, ring)) {
1189                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1190                 if (r) {
1191                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1192                         ring->rptr_save_reg = 0;
1193                 }
1194         }
1195         return 0;
1196 }
1197
1198 void r100_cp_fini(struct radeon_device *rdev)
1199 {
1200         if (r100_cp_wait_for_idle(rdev)) {
1201                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1202         }
1203         /* Disable ring */
1204         r100_cp_disable(rdev);
1205         radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1206         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1207         DRM_INFO("radeon: cp finalized\n");
1208 }
1209
1210 void r100_cp_disable(struct radeon_device *rdev)
1211 {
1212         /* Disable ring */
1213         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1214         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1215         WREG32(RADEON_CP_CSQ_MODE, 0);
1216         WREG32(RADEON_CP_CSQ_CNTL, 0);
1217         WREG32(R_000770_SCRATCH_UMSK, 0);
1218         if (r100_gui_wait_for_idle(rdev)) {
1219                 printk(KERN_WARNING "Failed to wait GUI idle while "
1220                        "programming pipes. Bad things might happen.\n");
1221         }
1222 }
1223
1224 /*
1225  * CS functions
1226  */
1227 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1228                             struct radeon_cs_packet *pkt,
1229                             unsigned idx,
1230                             unsigned reg)
1231 {
1232         int r;
1233         u32 tile_flags = 0;
1234         u32 tmp;
1235         struct radeon_cs_reloc *reloc;
1236         u32 value;
1237
1238         r = r100_cs_packet_next_reloc(p, &reloc);
1239         if (r) {
1240                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1241                           idx, reg);
1242                 r100_cs_dump_packet(p, pkt);
1243                 return r;
1244         }
1245
1246         value = radeon_get_ib_value(p, idx);
1247         tmp = value & 0x003fffff;
1248         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1249
1250         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1251                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1252                         tile_flags |= RADEON_DST_TILE_MACRO;
1253                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1254                         if (reg == RADEON_SRC_PITCH_OFFSET) {
1255                                 DRM_ERROR("Cannot src blit from microtiled surface\n");
1256                                 r100_cs_dump_packet(p, pkt);
1257                                 return -EINVAL;
1258                         }
1259                         tile_flags |= RADEON_DST_TILE_MICRO;
1260                 }
1261
1262                 tmp |= tile_flags;
1263                 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1264         } else
1265                 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1266         return 0;
1267 }
1268
1269 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1270                              struct radeon_cs_packet *pkt,
1271                              int idx)
1272 {
1273         unsigned c, i;
1274         struct radeon_cs_reloc *reloc;
1275         struct r100_cs_track *track;
1276         int r = 0;
1277         volatile uint32_t *ib;
1278         u32 idx_value;
1279
1280         ib = p->ib.ptr;
1281         track = (struct r100_cs_track *)p->track;
1282         c = radeon_get_ib_value(p, idx++) & 0x1F;
1283         if (c > 16) {
1284             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1285                       pkt->opcode);
1286             r100_cs_dump_packet(p, pkt);
1287             return -EINVAL;
1288         }
1289         track->num_arrays = c;
1290         for (i = 0; i < (c - 1); i+=2, idx+=3) {
1291                 r = r100_cs_packet_next_reloc(p, &reloc);
1292                 if (r) {
1293                         DRM_ERROR("No reloc for packet3 %d\n",
1294                                   pkt->opcode);
1295                         r100_cs_dump_packet(p, pkt);
1296                         return r;
1297                 }
1298                 idx_value = radeon_get_ib_value(p, idx);
1299                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1300
1301                 track->arrays[i + 0].esize = idx_value >> 8;
1302                 track->arrays[i + 0].robj = reloc->robj;
1303                 track->arrays[i + 0].esize &= 0x7F;
1304                 r = r100_cs_packet_next_reloc(p, &reloc);
1305                 if (r) {
1306                         DRM_ERROR("No reloc for packet3 %d\n",
1307                                   pkt->opcode);
1308                         r100_cs_dump_packet(p, pkt);
1309                         return r;
1310                 }
1311                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset);
1312                 track->arrays[i + 1].robj = reloc->robj;
1313                 track->arrays[i + 1].esize = idx_value >> 24;
1314                 track->arrays[i + 1].esize &= 0x7F;
1315         }
1316         if (c & 1) {
1317                 r = r100_cs_packet_next_reloc(p, &reloc);
1318                 if (r) {
1319                         DRM_ERROR("No reloc for packet3 %d\n",
1320                                           pkt->opcode);
1321                         r100_cs_dump_packet(p, pkt);
1322                         return r;
1323                 }
1324                 idx_value = radeon_get_ib_value(p, idx);
1325                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1326                 track->arrays[i + 0].robj = reloc->robj;
1327                 track->arrays[i + 0].esize = idx_value >> 8;
1328                 track->arrays[i + 0].esize &= 0x7F;
1329         }
1330         return r;
1331 }
1332
1333 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1334                           struct radeon_cs_packet *pkt,
1335                           const unsigned *auth, unsigned n,
1336                           radeon_packet0_check_t check)
1337 {
1338         unsigned reg;
1339         unsigned i, j, m;
1340         unsigned idx;
1341         int r;
1342
1343         idx = pkt->idx + 1;
1344         reg = pkt->reg;
1345         /* Check that register fall into register range
1346          * determined by the number of entry (n) in the
1347          * safe register bitmap.
1348          */
1349         if (pkt->one_reg_wr) {
1350                 if ((reg >> 7) > n) {
1351                         return -EINVAL;
1352                 }
1353         } else {
1354                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1355                         return -EINVAL;
1356                 }
1357         }
1358         for (i = 0; i <= pkt->count; i++, idx++) {
1359                 j = (reg >> 7);
1360                 m = 1 << ((reg >> 2) & 31);
1361                 if (auth[j] & m) {
1362                         r = check(p, pkt, idx, reg);
1363                         if (r) {
1364                                 return r;
1365                         }
1366                 }
1367                 if (pkt->one_reg_wr) {
1368                         if (!(auth[j] & m)) {
1369                                 break;
1370                         }
1371                 } else {
1372                         reg += 4;
1373                 }
1374         }
1375         return 0;
1376 }
1377
1378 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1379                          struct radeon_cs_packet *pkt)
1380 {
1381         volatile uint32_t *ib;
1382         unsigned i;
1383         unsigned idx;
1384
1385         ib = p->ib.ptr;
1386         idx = pkt->idx;
1387         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1388                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1389         }
1390 }
1391
1392 /**
1393  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1394  * @parser:     parser structure holding parsing context.
1395  * @pkt:        where to store packet informations
1396  *
1397  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1398  * if packet is bigger than remaining ib size. or if packets is unknown.
1399  **/
1400 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1401                          struct radeon_cs_packet *pkt,
1402                          unsigned idx)
1403 {
1404         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1405         uint32_t header;
1406
1407         if (idx >= ib_chunk->length_dw) {
1408                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1409                           idx, ib_chunk->length_dw);
1410                 return -EINVAL;
1411         }
1412         header = radeon_get_ib_value(p, idx);
1413         pkt->idx = idx;
1414         pkt->type = CP_PACKET_GET_TYPE(header);
1415         pkt->count = CP_PACKET_GET_COUNT(header);
1416         switch (pkt->type) {
1417         case PACKET_TYPE0:
1418                 pkt->reg = CP_PACKET0_GET_REG(header);
1419                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1420                 break;
1421         case PACKET_TYPE3:
1422                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1423                 break;
1424         case PACKET_TYPE2:
1425                 pkt->count = -1;
1426                 break;
1427         default:
1428                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1429                 return -EINVAL;
1430         }
1431         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1432                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1433                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1434                 return -EINVAL;
1435         }
1436         return 0;
1437 }
1438
1439 /**
1440  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1441  * @parser:             parser structure holding parsing context.
1442  *
1443  * Userspace sends a special sequence for VLINE waits.
1444  * PACKET0 - VLINE_START_END + value
1445  * PACKET0 - WAIT_UNTIL +_value
1446  * RELOC (P3) - crtc_id in reloc.
1447  *
1448  * This function parses this and relocates the VLINE START END
1449  * and WAIT UNTIL packets to the correct crtc.
1450  * It also detects a switched off crtc and nulls out the
1451  * wait in that case.
1452  */
1453 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1454 {
1455         struct drm_mode_object *obj;
1456         struct drm_crtc *crtc;
1457         struct radeon_crtc *radeon_crtc;
1458         struct radeon_cs_packet p3reloc, waitreloc;
1459         int crtc_id;
1460         int r;
1461         uint32_t header, h_idx, reg;
1462         volatile uint32_t *ib;
1463
1464         ib = p->ib.ptr;
1465
1466         /* parse the wait until */
1467         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1468         if (r)
1469                 return r;
1470
1471         /* check its a wait until and only 1 count */
1472         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1473             waitreloc.count != 0) {
1474                 DRM_ERROR("vline wait had illegal wait until segment\n");
1475                 return -EINVAL;
1476         }
1477
1478         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1479                 DRM_ERROR("vline wait had illegal wait until\n");
1480                 return -EINVAL;
1481         }
1482
1483         /* jump over the NOP */
1484         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1485         if (r)
1486                 return r;
1487
1488         h_idx = p->idx - 2;
1489         p->idx += waitreloc.count + 2;
1490         p->idx += p3reloc.count + 2;
1491
1492         header = radeon_get_ib_value(p, h_idx);
1493         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1494         reg = CP_PACKET0_GET_REG(header);
1495         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1496         if (!obj) {
1497                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1498                 return -EINVAL;
1499         }
1500         crtc = obj_to_crtc(obj);
1501         radeon_crtc = to_radeon_crtc(crtc);
1502         crtc_id = radeon_crtc->crtc_id;
1503
1504         if (!crtc->enabled) {
1505                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1506                 ib[h_idx + 2] = PACKET2(0);
1507                 ib[h_idx + 3] = PACKET2(0);
1508         } else if (crtc_id == 1) {
1509                 switch (reg) {
1510                 case AVIVO_D1MODE_VLINE_START_END:
1511                         header &= ~R300_CP_PACKET0_REG_MASK;
1512                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1513                         break;
1514                 case RADEON_CRTC_GUI_TRIG_VLINE:
1515                         header &= ~R300_CP_PACKET0_REG_MASK;
1516                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1517                         break;
1518                 default:
1519                         DRM_ERROR("unknown crtc reloc\n");
1520                         return -EINVAL;
1521                 }
1522                 ib[h_idx] = header;
1523                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1524         }
1525
1526         return 0;
1527 }
1528
1529 /**
1530  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1531  * @parser:             parser structure holding parsing context.
1532  * @data:               pointer to relocation data
1533  * @offset_start:       starting offset
1534  * @offset_mask:        offset mask (to align start offset on)
1535  * @reloc:              reloc informations
1536  *
1537  * Check next packet is relocation packet3, do bo validation and compute
1538  * GPU offset using the provided start.
1539  **/
1540 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1541                               struct radeon_cs_reloc **cs_reloc)
1542 {
1543         struct radeon_cs_chunk *relocs_chunk;
1544         struct radeon_cs_packet p3reloc;
1545         unsigned idx;
1546         int r;
1547
1548         if (p->chunk_relocs_idx == -1) {
1549                 DRM_ERROR("No relocation chunk !\n");
1550                 return -EINVAL;
1551         }
1552         *cs_reloc = NULL;
1553         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1554         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1555         if (r) {
1556                 return r;
1557         }
1558         p->idx += p3reloc.count + 2;
1559         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1560                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1561                           p3reloc.idx);
1562                 r100_cs_dump_packet(p, &p3reloc);
1563                 return -EINVAL;
1564         }
1565         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1566         if (idx >= relocs_chunk->length_dw) {
1567                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1568                           idx, relocs_chunk->length_dw);
1569                 r100_cs_dump_packet(p, &p3reloc);
1570                 return -EINVAL;
1571         }
1572         /* FIXME: we assume reloc size is 4 dwords */
1573         *cs_reloc = p->relocs_ptr[(idx / 4)];
1574         return 0;
1575 }
1576
1577 static int r100_get_vtx_size(uint32_t vtx_fmt)
1578 {
1579         int vtx_size;
1580         vtx_size = 2;
1581         /* ordered according to bits in spec */
1582         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1583                 vtx_size++;
1584         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1585                 vtx_size += 3;
1586         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1587                 vtx_size++;
1588         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1589                 vtx_size++;
1590         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1591                 vtx_size += 3;
1592         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1593                 vtx_size++;
1594         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1595                 vtx_size++;
1596         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1597                 vtx_size += 2;
1598         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1599                 vtx_size += 2;
1600         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1601                 vtx_size++;
1602         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1603                 vtx_size += 2;
1604         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1605                 vtx_size++;
1606         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1607                 vtx_size += 2;
1608         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1609                 vtx_size++;
1610         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1611                 vtx_size++;
1612         /* blend weight */
1613         if (vtx_fmt & (0x7 << 15))
1614                 vtx_size += (vtx_fmt >> 15) & 0x7;
1615         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1616                 vtx_size += 3;
1617         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1618                 vtx_size += 2;
1619         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1620                 vtx_size++;
1621         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1622                 vtx_size++;
1623         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1624                 vtx_size++;
1625         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1626                 vtx_size++;
1627         return vtx_size;
1628 }
1629
1630 static int r100_packet0_check(struct radeon_cs_parser *p,
1631                               struct radeon_cs_packet *pkt,
1632                               unsigned idx, unsigned reg)
1633 {
1634         struct radeon_cs_reloc *reloc;
1635         struct r100_cs_track *track;
1636         volatile uint32_t *ib;
1637         uint32_t tmp;
1638         int r;
1639         int i, face;
1640         u32 tile_flags = 0;
1641         u32 idx_value;
1642
1643         ib = p->ib.ptr;
1644         track = (struct r100_cs_track *)p->track;
1645
1646         idx_value = radeon_get_ib_value(p, idx);
1647
1648         switch (reg) {
1649         case RADEON_CRTC_GUI_TRIG_VLINE:
1650                 r = r100_cs_packet_parse_vline(p);
1651                 if (r) {
1652                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1653                                   idx, reg);
1654                         r100_cs_dump_packet(p, pkt);
1655                         return r;
1656                 }
1657                 break;
1658                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1659                  * range access */
1660         case RADEON_DST_PITCH_OFFSET:
1661         case RADEON_SRC_PITCH_OFFSET:
1662                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1663                 if (r)
1664                         return r;
1665                 break;
1666         case RADEON_RB3D_DEPTHOFFSET:
1667                 r = r100_cs_packet_next_reloc(p, &reloc);
1668                 if (r) {
1669                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1670                                   idx, reg);
1671                         r100_cs_dump_packet(p, pkt);
1672                         return r;
1673                 }
1674                 track->zb.robj = reloc->robj;
1675                 track->zb.offset = idx_value;
1676                 track->zb_dirty = true;
1677                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1678                 break;
1679         case RADEON_RB3D_COLOROFFSET:
1680                 r = r100_cs_packet_next_reloc(p, &reloc);
1681                 if (r) {
1682                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1683                                   idx, reg);
1684                         r100_cs_dump_packet(p, pkt);
1685                         return r;
1686                 }
1687                 track->cb[0].robj = reloc->robj;
1688                 track->cb[0].offset = idx_value;
1689                 track->cb_dirty = true;
1690                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1691                 break;
1692         case RADEON_PP_TXOFFSET_0:
1693         case RADEON_PP_TXOFFSET_1:
1694         case RADEON_PP_TXOFFSET_2:
1695                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1696                 r = r100_cs_packet_next_reloc(p, &reloc);
1697                 if (r) {
1698                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1699                                   idx, reg);
1700                         r100_cs_dump_packet(p, pkt);
1701                         return r;
1702                 }
1703                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1704                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1705                                 tile_flags |= RADEON_TXO_MACRO_TILE;
1706                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1707                                 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1708
1709                         tmp = idx_value & ~(0x7 << 2);
1710                         tmp |= tile_flags;
1711                         ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
1712                 } else
1713                         ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1714                 track->textures[i].robj = reloc->robj;
1715                 track->tex_dirty = true;
1716                 break;
1717         case RADEON_PP_CUBIC_OFFSET_T0_0:
1718         case RADEON_PP_CUBIC_OFFSET_T0_1:
1719         case RADEON_PP_CUBIC_OFFSET_T0_2:
1720         case RADEON_PP_CUBIC_OFFSET_T0_3:
1721         case RADEON_PP_CUBIC_OFFSET_T0_4:
1722                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1723                 r = r100_cs_packet_next_reloc(p, &reloc);
1724                 if (r) {
1725                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1726                                   idx, reg);
1727                         r100_cs_dump_packet(p, pkt);
1728                         return r;
1729                 }
1730                 track->textures[0].cube_info[i].offset = idx_value;
1731                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1732                 track->textures[0].cube_info[i].robj = reloc->robj;
1733                 track->tex_dirty = true;
1734                 break;
1735         case RADEON_PP_CUBIC_OFFSET_T1_0:
1736         case RADEON_PP_CUBIC_OFFSET_T1_1:
1737         case RADEON_PP_CUBIC_OFFSET_T1_2:
1738         case RADEON_PP_CUBIC_OFFSET_T1_3:
1739         case RADEON_PP_CUBIC_OFFSET_T1_4:
1740                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1741                 r = r100_cs_packet_next_reloc(p, &reloc);
1742                 if (r) {
1743                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1744                                   idx, reg);
1745                         r100_cs_dump_packet(p, pkt);
1746                         return r;
1747                 }
1748                 track->textures[1].cube_info[i].offset = idx_value;
1749                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1750                 track->textures[1].cube_info[i].robj = reloc->robj;
1751                 track->tex_dirty = true;
1752                 break;
1753         case RADEON_PP_CUBIC_OFFSET_T2_0:
1754         case RADEON_PP_CUBIC_OFFSET_T2_1:
1755         case RADEON_PP_CUBIC_OFFSET_T2_2:
1756         case RADEON_PP_CUBIC_OFFSET_T2_3:
1757         case RADEON_PP_CUBIC_OFFSET_T2_4:
1758                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1759                 r = r100_cs_packet_next_reloc(p, &reloc);
1760                 if (r) {
1761                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1762                                   idx, reg);
1763                         r100_cs_dump_packet(p, pkt);
1764                         return r;
1765                 }
1766                 track->textures[2].cube_info[i].offset = idx_value;
1767                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1768                 track->textures[2].cube_info[i].robj = reloc->robj;
1769                 track->tex_dirty = true;
1770                 break;
1771         case RADEON_RE_WIDTH_HEIGHT:
1772                 track->maxy = ((idx_value >> 16) & 0x7FF);
1773                 track->cb_dirty = true;
1774                 track->zb_dirty = true;
1775                 break;
1776         case RADEON_RB3D_COLORPITCH:
1777                 r = r100_cs_packet_next_reloc(p, &reloc);
1778                 if (r) {
1779                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1780                                   idx, reg);
1781                         r100_cs_dump_packet(p, pkt);
1782                         return r;
1783                 }
1784                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1785                         if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1786                                 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1787                         if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1788                                 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1789
1790                         tmp = idx_value & ~(0x7 << 16);
1791                         tmp |= tile_flags;
1792                         ib[idx] = tmp;
1793                 } else
1794                         ib[idx] = idx_value;
1795
1796                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1797                 track->cb_dirty = true;
1798                 break;
1799         case RADEON_RB3D_DEPTHPITCH:
1800                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1801                 track->zb_dirty = true;
1802                 break;
1803         case RADEON_RB3D_CNTL:
1804                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1805                 case 7:
1806                 case 8:
1807                 case 9:
1808                 case 11:
1809                 case 12:
1810                         track->cb[0].cpp = 1;
1811                         break;
1812                 case 3:
1813                 case 4:
1814                 case 15:
1815                         track->cb[0].cpp = 2;
1816                         break;
1817                 case 6:
1818                         track->cb[0].cpp = 4;
1819                         break;
1820                 default:
1821                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1822                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1823                         return -EINVAL;
1824                 }
1825                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1826                 track->cb_dirty = true;
1827                 track->zb_dirty = true;
1828                 break;
1829         case RADEON_RB3D_ZSTENCILCNTL:
1830                 switch (idx_value & 0xf) {
1831                 case 0:
1832                         track->zb.cpp = 2;
1833                         break;
1834                 case 2:
1835                 case 3:
1836                 case 4:
1837                 case 5:
1838                 case 9:
1839                 case 11:
1840                         track->zb.cpp = 4;
1841                         break;
1842                 default:
1843                         break;
1844                 }
1845                 track->zb_dirty = true;
1846                 break;
1847         case RADEON_RB3D_ZPASS_ADDR:
1848                 r = r100_cs_packet_next_reloc(p, &reloc);
1849                 if (r) {
1850                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1851                                   idx, reg);
1852                         r100_cs_dump_packet(p, pkt);
1853                         return r;
1854                 }
1855                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1856                 break;
1857         case RADEON_PP_CNTL:
1858                 {
1859                         uint32_t temp = idx_value >> 4;
1860                         for (i = 0; i < track->num_texture; i++)
1861                                 track->textures[i].enabled = !!(temp & (1 << i));
1862                         track->tex_dirty = true;
1863                 }
1864                 break;
1865         case RADEON_SE_VF_CNTL:
1866                 track->vap_vf_cntl = idx_value;
1867                 break;
1868         case RADEON_SE_VTX_FMT:
1869                 track->vtx_size = r100_get_vtx_size(idx_value);
1870                 break;
1871         case RADEON_PP_TEX_SIZE_0:
1872         case RADEON_PP_TEX_SIZE_1:
1873         case RADEON_PP_TEX_SIZE_2:
1874                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1875                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1876                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1877                 track->tex_dirty = true;
1878                 break;
1879         case RADEON_PP_TEX_PITCH_0:
1880         case RADEON_PP_TEX_PITCH_1:
1881         case RADEON_PP_TEX_PITCH_2:
1882                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1883                 track->textures[i].pitch = idx_value + 32;
1884                 track->tex_dirty = true;
1885                 break;
1886         case RADEON_PP_TXFILTER_0:
1887         case RADEON_PP_TXFILTER_1:
1888         case RADEON_PP_TXFILTER_2:
1889                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1890                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1891                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1892                 tmp = (idx_value >> 23) & 0x7;
1893                 if (tmp == 2 || tmp == 6)
1894                         track->textures[i].roundup_w = false;
1895                 tmp = (idx_value >> 27) & 0x7;
1896                 if (tmp == 2 || tmp == 6)
1897                         track->textures[i].roundup_h = false;
1898                 track->tex_dirty = true;
1899                 break;
1900         case RADEON_PP_TXFORMAT_0:
1901         case RADEON_PP_TXFORMAT_1:
1902         case RADEON_PP_TXFORMAT_2:
1903                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1904                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1905                         track->textures[i].use_pitch = 1;
1906                 } else {
1907                         track->textures[i].use_pitch = 0;
1908                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1909                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1910                 }
1911                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1912                         track->textures[i].tex_coord_type = 2;
1913                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1914                 case RADEON_TXFORMAT_I8:
1915                 case RADEON_TXFORMAT_RGB332:
1916                 case RADEON_TXFORMAT_Y8:
1917                         track->textures[i].cpp = 1;
1918                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1919                         break;
1920                 case RADEON_TXFORMAT_AI88:
1921                 case RADEON_TXFORMAT_ARGB1555:
1922                 case RADEON_TXFORMAT_RGB565:
1923                 case RADEON_TXFORMAT_ARGB4444:
1924                 case RADEON_TXFORMAT_VYUY422:
1925                 case RADEON_TXFORMAT_YVYU422:
1926                 case RADEON_TXFORMAT_SHADOW16:
1927                 case RADEON_TXFORMAT_LDUDV655:
1928                 case RADEON_TXFORMAT_DUDV88:
1929                         track->textures[i].cpp = 2;
1930                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1931                         break;
1932                 case RADEON_TXFORMAT_ARGB8888:
1933                 case RADEON_TXFORMAT_RGBA8888:
1934                 case RADEON_TXFORMAT_SHADOW32:
1935                 case RADEON_TXFORMAT_LDUDUV8888:
1936                         track->textures[i].cpp = 4;
1937                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1938                         break;
1939                 case RADEON_TXFORMAT_DXT1:
1940                         track->textures[i].cpp = 1;
1941                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1942                         break;
1943                 case RADEON_TXFORMAT_DXT23:
1944                 case RADEON_TXFORMAT_DXT45:
1945                         track->textures[i].cpp = 1;
1946                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1947                         break;
1948                 }
1949                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1950                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1951                 track->tex_dirty = true;
1952                 break;
1953         case RADEON_PP_CUBIC_FACES_0:
1954         case RADEON_PP_CUBIC_FACES_1:
1955         case RADEON_PP_CUBIC_FACES_2:
1956                 tmp = idx_value;
1957                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1958                 for (face = 0; face < 4; face++) {
1959                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1960                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1961                 }
1962                 track->tex_dirty = true;
1963                 break;
1964         default:
1965                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1966                        reg, idx);
1967                 return -EINVAL;
1968         }
1969         return 0;
1970 }
1971
1972 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1973                                          struct radeon_cs_packet *pkt,
1974                                          struct radeon_bo *robj)
1975 {
1976         unsigned idx;
1977         u32 value;
1978         idx = pkt->idx + 1;
1979         value = radeon_get_ib_value(p, idx + 2);
1980         if ((value + 1) > radeon_bo_size(robj)) {
1981                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1982                           "(need %u have %lu) !\n",
1983                           value + 1,
1984                           radeon_bo_size(robj));
1985                 return -EINVAL;
1986         }
1987         return 0;
1988 }
1989
1990 static int r100_packet3_check(struct radeon_cs_parser *p,
1991                               struct radeon_cs_packet *pkt)
1992 {
1993         struct radeon_cs_reloc *reloc;
1994         struct r100_cs_track *track;
1995         unsigned idx;
1996         volatile uint32_t *ib;
1997         int r;
1998
1999         ib = p->ib.ptr;
2000         idx = pkt->idx + 1;
2001         track = (struct r100_cs_track *)p->track;
2002         switch (pkt->opcode) {
2003         case PACKET3_3D_LOAD_VBPNTR:
2004                 r = r100_packet3_load_vbpntr(p, pkt, idx);
2005                 if (r)
2006                         return r;
2007                 break;
2008         case PACKET3_INDX_BUFFER:
2009                 r = r100_cs_packet_next_reloc(p, &reloc);
2010                 if (r) {
2011                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
2012                         r100_cs_dump_packet(p, pkt);
2013                         return r;
2014                 }
2015                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
2016                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
2017                 if (r) {
2018                         return r;
2019                 }
2020                 break;
2021         case 0x23:
2022                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
2023                 r = r100_cs_packet_next_reloc(p, &reloc);
2024                 if (r) {
2025                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
2026                         r100_cs_dump_packet(p, pkt);
2027                         return r;
2028                 }
2029                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
2030                 track->num_arrays = 1;
2031                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
2032
2033                 track->arrays[0].robj = reloc->robj;
2034                 track->arrays[0].esize = track->vtx_size;
2035
2036                 track->max_indx = radeon_get_ib_value(p, idx+1);
2037
2038                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
2039                 track->immd_dwords = pkt->count - 1;
2040                 r = r100_cs_track_check(p->rdev, track);
2041                 if (r)
2042                         return r;
2043                 break;
2044         case PACKET3_3D_DRAW_IMMD:
2045                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
2046                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
2047                         return -EINVAL;
2048                 }
2049                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
2050                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2051                 track->immd_dwords = pkt->count - 1;
2052                 r = r100_cs_track_check(p->rdev, track);
2053                 if (r)
2054                         return r;
2055                 break;
2056                 /* triggers drawing using in-packet vertex data */
2057         case PACKET3_3D_DRAW_IMMD_2:
2058                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
2059                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
2060                         return -EINVAL;
2061                 }
2062                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2063                 track->immd_dwords = pkt->count;
2064                 r = r100_cs_track_check(p->rdev, track);
2065                 if (r)
2066                         return r;
2067                 break;
2068                 /* triggers drawing using in-packet vertex data */
2069         case PACKET3_3D_DRAW_VBUF_2:
2070                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2071                 r = r100_cs_track_check(p->rdev, track);
2072                 if (r)
2073                         return r;
2074                 break;
2075                 /* triggers drawing of vertex buffers setup elsewhere */
2076         case PACKET3_3D_DRAW_INDX_2:
2077                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
2078                 r = r100_cs_track_check(p->rdev, track);
2079                 if (r)
2080                         return r;
2081                 break;
2082                 /* triggers drawing using indices to vertex buffer */
2083         case PACKET3_3D_DRAW_VBUF:
2084                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2085                 r = r100_cs_track_check(p->rdev, track);
2086                 if (r)
2087                         return r;
2088                 break;
2089                 /* triggers drawing of vertex buffers setup elsewhere */
2090         case PACKET3_3D_DRAW_INDX:
2091                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
2092                 r = r100_cs_track_check(p->rdev, track);
2093                 if (r)
2094                         return r;
2095                 break;
2096                 /* triggers drawing using indices to vertex buffer */
2097         case PACKET3_3D_CLEAR_HIZ:
2098         case PACKET3_3D_CLEAR_ZMASK:
2099                 if (p->rdev->hyperz_filp != p->filp)
2100                         return -EINVAL;
2101                 break;
2102         case PACKET3_NOP:
2103                 break;
2104         default:
2105                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
2106                 return -EINVAL;
2107         }
2108         return 0;
2109 }
2110
2111 int r100_cs_parse(struct radeon_cs_parser *p)
2112 {
2113         struct radeon_cs_packet pkt;
2114         struct r100_cs_track *track;
2115         int r;
2116
2117         track = kzalloc(sizeof(*track), GFP_KERNEL);
2118         if (!track)
2119                 return -ENOMEM;
2120         r100_cs_track_clear(p->rdev, track);
2121         p->track = track;
2122         do {
2123                 r = r100_cs_packet_parse(p, &pkt, p->idx);
2124                 if (r) {
2125                         return r;
2126                 }
2127                 p->idx += pkt.count + 2;
2128                 switch (pkt.type) {
2129                         case PACKET_TYPE0:
2130                                 if (p->rdev->family >= CHIP_R200)
2131                                         r = r100_cs_parse_packet0(p, &pkt,
2132                                                                   p->rdev->config.r100.reg_safe_bm,
2133                                                                   p->rdev->config.r100.reg_safe_bm_size,
2134                                                                   &r200_packet0_check);
2135                                 else
2136                                         r = r100_cs_parse_packet0(p, &pkt,
2137                                                                   p->rdev->config.r100.reg_safe_bm,
2138                                                                   p->rdev->config.r100.reg_safe_bm_size,
2139                                                                   &r100_packet0_check);
2140                                 break;
2141                         case PACKET_TYPE2:
2142                                 break;
2143                         case PACKET_TYPE3:
2144                                 r = r100_packet3_check(p, &pkt);
2145                                 break;
2146                         default:
2147                                 DRM_ERROR("Unknown packet type %d !\n",
2148                                           pkt.type);
2149                                 return -EINVAL;
2150                 }
2151                 if (r) {
2152                         return r;
2153                 }
2154         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2155         return 0;
2156 }
2157
2158 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2159 {
2160         DRM_ERROR("pitch                      %d\n", t->pitch);
2161         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2162         DRM_ERROR("width                      %d\n", t->width);
2163         DRM_ERROR("width_11                   %d\n", t->width_11);
2164         DRM_ERROR("height                     %d\n", t->height);
2165         DRM_ERROR("height_11                  %d\n", t->height_11);
2166         DRM_ERROR("num levels                 %d\n", t->num_levels);
2167         DRM_ERROR("depth                      %d\n", t->txdepth);
2168         DRM_ERROR("bpp                        %d\n", t->cpp);
2169         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2170         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2171         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2172         DRM_ERROR("compress format            %d\n", t->compress_format);
2173 }
2174
2175 static int r100_track_compress_size(int compress_format, int w, int h)
2176 {
2177         int block_width, block_height, block_bytes;
2178         int wblocks, hblocks;
2179         int min_wblocks;
2180         int sz;
2181
2182         block_width = 4;
2183         block_height = 4;
2184
2185         switch (compress_format) {
2186         case R100_TRACK_COMP_DXT1:
2187                 block_bytes = 8;
2188                 min_wblocks = 4;
2189                 break;
2190         default:
2191         case R100_TRACK_COMP_DXT35:
2192                 block_bytes = 16;
2193                 min_wblocks = 2;
2194                 break;
2195         }
2196
2197         hblocks = (h + block_height - 1) / block_height;
2198         wblocks = (w + block_width - 1) / block_width;
2199         if (wblocks < min_wblocks)
2200                 wblocks = min_wblocks;
2201         sz = wblocks * hblocks * block_bytes;
2202         return sz;
2203 }
2204
2205 static int r100_cs_track_cube(struct radeon_device *rdev,
2206                               struct r100_cs_track *track, unsigned idx)
2207 {
2208         unsigned face, w, h;
2209         struct radeon_bo *cube_robj;
2210         unsigned long size;
2211         unsigned compress_format = track->textures[idx].compress_format;
2212
2213         for (face = 0; face < 5; face++) {
2214                 cube_robj = track->textures[idx].cube_info[face].robj;
2215                 w = track->textures[idx].cube_info[face].width;
2216                 h = track->textures[idx].cube_info[face].height;
2217
2218                 if (compress_format) {
2219                         size = r100_track_compress_size(compress_format, w, h);
2220                 } else
2221                         size = w * h;
2222                 size *= track->textures[idx].cpp;
2223
2224                 size += track->textures[idx].cube_info[face].offset;
2225
2226                 if (size > radeon_bo_size(cube_robj)) {
2227                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2228                                   size, radeon_bo_size(cube_robj));
2229                         r100_cs_track_texture_print(&track->textures[idx]);
2230                         return -1;
2231                 }
2232         }
2233         return 0;
2234 }
2235
2236 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2237                                        struct r100_cs_track *track)
2238 {
2239         struct radeon_bo *robj;
2240         unsigned long size;
2241         unsigned u, i, w, h, d;
2242         int ret;
2243
2244         for (u = 0; u < track->num_texture; u++) {
2245                 if (!track->textures[u].enabled)
2246                         continue;
2247                 if (track->textures[u].lookup_disable)
2248                         continue;
2249                 robj = track->textures[u].robj;
2250                 if (robj == NULL) {
2251                         DRM_ERROR("No texture bound to unit %u\n", u);
2252                         return -EINVAL;
2253                 }
2254                 size = 0;
2255                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2256                         if (track->textures[u].use_pitch) {
2257                                 if (rdev->family < CHIP_R300)
2258                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2259                                 else
2260                                         w = track->textures[u].pitch / (1 << i);
2261                         } else {
2262                                 w = track->textures[u].width;
2263                                 if (rdev->family >= CHIP_RV515)
2264                                         w |= track->textures[u].width_11;
2265                                 w = w / (1 << i);
2266                                 if (track->textures[u].roundup_w)
2267                                         w = roundup_pow_of_two(w);
2268                         }
2269                         h = track->textures[u].height;
2270                         if (rdev->family >= CHIP_RV515)
2271                                 h |= track->textures[u].height_11;
2272                         h = h / (1 << i);
2273                         if (track->textures[u].roundup_h)
2274                                 h = roundup_pow_of_two(h);
2275                         if (track->textures[u].tex_coord_type == 1) {
2276                                 d = (1 << track->textures[u].txdepth) / (1 << i);
2277                                 if (!d)
2278                                         d = 1;
2279                         } else {
2280                                 d = 1;
2281                         }
2282                         if (track->textures[u].compress_format) {
2283
2284                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2285                                 /* compressed textures are block based */
2286                         } else
2287                                 size += w * h * d;
2288                 }
2289                 size *= track->textures[u].cpp;
2290
2291                 switch (track->textures[u].tex_coord_type) {
2292                 case 0:
2293                 case 1:
2294                         break;
2295                 case 2:
2296                         if (track->separate_cube) {
2297                                 ret = r100_cs_track_cube(rdev, track, u);
2298                                 if (ret)
2299                                         return ret;
2300                         } else
2301                                 size *= 6;
2302                         break;
2303                 default:
2304                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2305                                   "%u\n", track->textures[u].tex_coord_type, u);
2306                         return -EINVAL;
2307                 }
2308                 if (size > radeon_bo_size(robj)) {
2309                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2310                                   "%lu\n", u, size, radeon_bo_size(robj));
2311                         r100_cs_track_texture_print(&track->textures[u]);
2312                         return -EINVAL;
2313                 }
2314         }
2315         return 0;
2316 }
2317
2318 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2319 {
2320         unsigned i;
2321         unsigned long size;
2322         unsigned prim_walk;
2323         unsigned nverts;
2324         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2325
2326         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2327             !track->blend_read_enable)
2328                 num_cb = 0;
2329
2330         for (i = 0; i < num_cb; i++) {
2331                 if (track->cb[i].robj == NULL) {
2332                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2333                         return -EINVAL;
2334                 }
2335                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2336                 size += track->cb[i].offset;
2337                 if (size > radeon_bo_size(track->cb[i].robj)) {
2338                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2339                                   "(need %lu have %lu) !\n", i, size,
2340                                   radeon_bo_size(track->cb[i].robj));
2341                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2342                                   i, track->cb[i].pitch, track->cb[i].cpp,
2343                                   track->cb[i].offset, track->maxy);
2344                         return -EINVAL;
2345                 }
2346         }
2347         track->cb_dirty = false;
2348
2349         if (track->zb_dirty && track->z_enabled) {
2350                 if (track->zb.robj == NULL) {
2351                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2352                         return -EINVAL;
2353                 }
2354                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2355                 size += track->zb.offset;
2356                 if (size > radeon_bo_size(track->zb.robj)) {
2357                         DRM_ERROR("[drm] Buffer too small for z buffer "
2358                                   "(need %lu have %lu) !\n", size,
2359                                   radeon_bo_size(track->zb.robj));
2360                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2361                                   track->zb.pitch, track->zb.cpp,
2362                                   track->zb.offset, track->maxy);
2363                         return -EINVAL;
2364                 }
2365         }
2366         track->zb_dirty = false;
2367
2368         if (track->aa_dirty && track->aaresolve) {
2369                 if (track->aa.robj == NULL) {
2370                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2371                         return -EINVAL;
2372                 }
2373                 /* I believe the format comes from colorbuffer0. */
2374                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2375                 size += track->aa.offset;
2376                 if (size > radeon_bo_size(track->aa.robj)) {
2377                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2378                                   "(need %lu have %lu) !\n", i, size,
2379                                   radeon_bo_size(track->aa.robj));
2380                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2381                                   i, track->aa.pitch, track->cb[0].cpp,
2382                                   track->aa.offset, track->maxy);
2383                         return -EINVAL;
2384                 }
2385         }
2386         track->aa_dirty = false;
2387
2388         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2389         if (track->vap_vf_cntl & (1 << 14)) {
2390                 nverts = track->vap_alt_nverts;
2391         } else {
2392                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2393         }
2394         switch (prim_walk) {
2395         case 1:
2396                 for (i = 0; i < track->num_arrays; i++) {
2397                         size = track->arrays[i].esize * track->max_indx * 4;
2398                         if (track->arrays[i].robj == NULL) {
2399                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2400                                           "bound\n", prim_walk, i);
2401                                 return -EINVAL;
2402                         }
2403                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2404                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2405                                         "need %lu dwords have %lu dwords\n",
2406                                         prim_walk, i, size >> 2,
2407                                         radeon_bo_size(track->arrays[i].robj)
2408                                         >> 2);
2409                                 DRM_ERROR("Max indices %u\n", track->max_indx);
2410                                 return -EINVAL;
2411                         }
2412                 }
2413                 break;
2414         case 2:
2415                 for (i = 0; i < track->num_arrays; i++) {
2416                         size = track->arrays[i].esize * (nverts - 1) * 4;
2417                         if (track->arrays[i].robj == NULL) {
2418                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2419                                           "bound\n", prim_walk, i);
2420                                 return -EINVAL;
2421                         }
2422                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2423                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2424                                         "need %lu dwords have %lu dwords\n",
2425                                         prim_walk, i, size >> 2,
2426                                         radeon_bo_size(track->arrays[i].robj)
2427                                         >> 2);
2428                                 return -EINVAL;
2429                         }
2430                 }
2431                 break;
2432         case 3:
2433                 size = track->vtx_size * nverts;
2434                 if (size != track->immd_dwords) {
2435                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2436                                   track->immd_dwords, size);
2437                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2438                                   nverts, track->vtx_size);
2439                         return -EINVAL;
2440                 }
2441                 break;
2442         default:
2443                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2444                           prim_walk);
2445                 return -EINVAL;
2446         }
2447
2448         if (track->tex_dirty) {
2449                 track->tex_dirty = false;
2450                 return r100_cs_track_texture_check(rdev, track);
2451         }
2452         return 0;
2453 }
2454
2455 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2456 {
2457         unsigned i, face;
2458
2459         track->cb_dirty = true;
2460         track->zb_dirty = true;
2461         track->tex_dirty = true;
2462         track->aa_dirty = true;
2463
2464         if (rdev->family < CHIP_R300) {
2465                 track->num_cb = 1;
2466                 if (rdev->family <= CHIP_RS200)
2467                         track->num_texture = 3;
2468                 else
2469                         track->num_texture = 6;
2470                 track->maxy = 2048;
2471                 track->separate_cube = 1;
2472         } else {
2473                 track->num_cb = 4;
2474                 track->num_texture = 16;
2475                 track->maxy = 4096;
2476                 track->separate_cube = 0;
2477                 track->aaresolve = false;
2478                 track->aa.robj = NULL;
2479         }
2480
2481         for (i = 0; i < track->num_cb; i++) {
2482                 track->cb[i].robj = NULL;
2483                 track->cb[i].pitch = 8192;
2484                 track->cb[i].cpp = 16;
2485                 track->cb[i].offset = 0;
2486         }
2487         track->z_enabled = true;
2488         track->zb.robj = NULL;
2489         track->zb.pitch = 8192;
2490         track->zb.cpp = 4;
2491         track->zb.offset = 0;
2492         track->vtx_size = 0x7F;
2493         track->immd_dwords = 0xFFFFFFFFUL;
2494         track->num_arrays = 11;
2495         track->max_indx = 0x00FFFFFFUL;
2496         for (i = 0; i < track->num_arrays; i++) {
2497                 track->arrays[i].robj = NULL;
2498                 track->arrays[i].esize = 0x7F;
2499         }
2500         for (i = 0; i < track->num_texture; i++) {
2501                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2502                 track->textures[i].pitch = 16536;
2503                 track->textures[i].width = 16536;
2504                 track->textures[i].height = 16536;
2505                 track->textures[i].width_11 = 1 << 11;
2506                 track->textures[i].height_11 = 1 << 11;
2507                 track->textures[i].num_levels = 12;
2508                 if (rdev->family <= CHIP_RS200) {
2509                         track->textures[i].tex_coord_type = 0;
2510                         track->textures[i].txdepth = 0;
2511                 } else {
2512                         track->textures[i].txdepth = 16;
2513                         track->textures[i].tex_coord_type = 1;
2514                 }
2515                 track->textures[i].cpp = 64;
2516                 track->textures[i].robj = NULL;
2517                 /* CS IB emission code makes sure texture unit are disabled */
2518                 track->textures[i].enabled = false;
2519                 track->textures[i].lookup_disable = false;
2520                 track->textures[i].roundup_w = true;
2521                 track->textures[i].roundup_h = true;
2522                 if (track->separate_cube)
2523                         for (face = 0; face < 5; face++) {
2524                                 track->textures[i].cube_info[face].robj = NULL;
2525                                 track->textures[i].cube_info[face].width = 16536;
2526                                 track->textures[i].cube_info[face].height = 16536;
2527                                 track->textures[i].cube_info[face].offset = 0;
2528                         }
2529         }
2530 }
2531
2532 /*
2533  * Global GPU functions
2534  */
2535 void r100_errata(struct radeon_device *rdev)
2536 {
2537         rdev->pll_errata = 0;
2538
2539         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2540                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2541         }
2542
2543         if (rdev->family == CHIP_RV100 ||
2544             rdev->family == CHIP_RS100 ||
2545             rdev->family == CHIP_RS200) {
2546                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2547         }
2548 }
2549
2550 /* Wait for vertical sync on primary CRTC */
2551 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
2552 {
2553         uint32_t crtc_gen_cntl, tmp;
2554         int i;
2555
2556         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
2557         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
2558             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
2559                 return;
2560         }
2561         /* Clear the CRTC_VBLANK_SAVE bit */
2562         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
2563         for (i = 0; i < rdev->usec_timeout; i++) {
2564                 tmp = RREG32(RADEON_CRTC_STATUS);
2565                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
2566                         return;
2567                 }
2568                 DRM_UDELAY(1);
2569         }
2570 }
2571
2572 /* Wait for vertical sync on secondary CRTC */
2573 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
2574 {
2575         uint32_t crtc2_gen_cntl, tmp;
2576         int i;
2577
2578         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
2579         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
2580             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
2581                 return;
2582
2583         /* Clear the CRTC_VBLANK_SAVE bit */
2584         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
2585         for (i = 0; i < rdev->usec_timeout; i++) {
2586                 tmp = RREG32(RADEON_CRTC2_STATUS);
2587                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
2588                         return;
2589                 }
2590                 DRM_UDELAY(1);
2591         }
2592 }
2593
2594 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2595 {
2596         unsigned i;
2597         uint32_t tmp;
2598
2599         for (i = 0; i < rdev->usec_timeout; i++) {
2600                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2601                 if (tmp >= n) {
2602                         return 0;
2603                 }
2604                 DRM_UDELAY(1);
2605         }
2606         return -1;
2607 }
2608
2609 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2610 {
2611         unsigned i;
2612         uint32_t tmp;
2613
2614         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2615                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2616                        " Bad things might happen.\n");
2617         }
2618         for (i = 0; i < rdev->usec_timeout; i++) {
2619                 tmp = RREG32(RADEON_RBBM_STATUS);
2620                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2621                         return 0;
2622                 }
2623                 DRM_UDELAY(1);
2624         }
2625         return -1;
2626 }
2627
2628 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2629 {
2630         unsigned i;
2631         uint32_t tmp;
2632
2633         for (i = 0; i < rdev->usec_timeout; i++) {
2634                 /* read MC_STATUS */
2635                 tmp = RREG32(RADEON_MC_STATUS);
2636                 if (tmp & RADEON_MC_IDLE) {
2637                         return 0;
2638                 }
2639                 DRM_UDELAY(1);
2640         }
2641         return -1;
2642 }
2643
2644 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2645 {
2646         u32 rbbm_status;
2647
2648         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2649         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2650                 radeon_ring_lockup_update(ring);
2651                 return false;
2652         }
2653         /* force CP activities */
2654         radeon_ring_force_activity(rdev, ring);
2655         return radeon_ring_test_lockup(rdev, ring);
2656 }
2657
2658 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2659 void r100_enable_bm(struct radeon_device *rdev)
2660 {
2661         uint32_t tmp;
2662         /* Enable bus mastering */
2663         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2664         WREG32(RADEON_BUS_CNTL, tmp);
2665 }
2666
2667 void r100_bm_disable(struct radeon_device *rdev)
2668 {
2669         u32 tmp;
2670
2671         /* disable bus mastering */
2672         tmp = RREG32(R_000030_BUS_CNTL);
2673         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2674         mdelay(1);
2675         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2676         mdelay(1);
2677         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2678         tmp = RREG32(RADEON_BUS_CNTL);
2679         mdelay(1);
2680         pci_clear_master(rdev->pdev);
2681         mdelay(1);
2682 }
2683
2684 int r100_asic_reset(struct radeon_device *rdev)
2685 {
2686         struct r100_mc_save save;
2687         u32 status, tmp;
2688         int ret = 0;
2689
2690         status = RREG32(R_000E40_RBBM_STATUS);
2691         if (!G_000E40_GUI_ACTIVE(status)) {
2692                 return 0;
2693         }
2694         r100_mc_stop(rdev, &save);
2695         status = RREG32(R_000E40_RBBM_STATUS);
2696         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2697         /* stop CP */
2698         WREG32(RADEON_CP_CSQ_CNTL, 0);
2699         tmp = RREG32(RADEON_CP_RB_CNTL);
2700         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2701         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2702         WREG32(RADEON_CP_RB_WPTR, 0);
2703         WREG32(RADEON_CP_RB_CNTL, tmp);
2704         /* save PCI state */
2705         pci_save_state(rdev->pdev);
2706         /* disable bus mastering */
2707         r100_bm_disable(rdev);
2708         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2709                                         S_0000F0_SOFT_RESET_RE(1) |
2710                                         S_0000F0_SOFT_RESET_PP(1) |
2711                                         S_0000F0_SOFT_RESET_RB(1));
2712         RREG32(R_0000F0_RBBM_SOFT_RESET);
2713         mdelay(500);
2714         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2715         mdelay(1);
2716         status = RREG32(R_000E40_RBBM_STATUS);
2717         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2718         /* reset CP */
2719         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2720         RREG32(R_0000F0_RBBM_SOFT_RESET);
2721         mdelay(500);
2722         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2723         mdelay(1);
2724         status = RREG32(R_000E40_RBBM_STATUS);
2725         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2726         /* restore PCI & busmastering */
2727         pci_restore_state(rdev->pdev);
2728         r100_enable_bm(rdev);
2729         /* Check if GPU is idle */
2730         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2731                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2732                 dev_err(rdev->dev, "failed to reset GPU\n");
2733                 ret = -1;
2734         } else
2735                 dev_info(rdev->dev, "GPU reset succeed\n");
2736         r100_mc_resume(rdev, &save);
2737         return ret;
2738 }
2739
2740 void r100_set_common_regs(struct radeon_device *rdev)
2741 {
2742         struct drm_device *dev = rdev->ddev;
2743         bool force_dac2 = false;
2744         u32 tmp;
2745
2746         /* set these so they don't interfere with anything */
2747         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2748         WREG32(RADEON_SUBPIC_CNTL, 0);
2749         WREG32(RADEON_VIPH_CONTROL, 0);
2750         WREG32(RADEON_I2C_CNTL_1, 0);
2751         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2752         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2753         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2754
2755         /* always set up dac2 on rn50 and some rv100 as lots
2756          * of servers seem to wire it up to a VGA port but
2757          * don't report it in the bios connector
2758          * table.
2759          */
2760         switch (dev->pdev->device) {
2761                 /* RN50 */
2762         case 0x515e:
2763         case 0x5969:
2764                 force_dac2 = true;
2765                 break;
2766                 /* RV100*/
2767         case 0x5159:
2768         case 0x515a:
2769                 /* DELL triple head servers */
2770                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2771                     ((dev->pdev->subsystem_device == 0x016c) ||
2772                      (dev->pdev->subsystem_device == 0x016d) ||
2773                      (dev->pdev->subsystem_device == 0x016e) ||
2774                      (dev->pdev->subsystem_device == 0x016f) ||
2775                      (dev->pdev->subsystem_device == 0x0170) ||
2776                      (dev->pdev->subsystem_device == 0x017d) ||
2777                      (dev->pdev->subsystem_device == 0x017e) ||
2778                      (dev->pdev->subsystem_device == 0x0183) ||
2779                      (dev->pdev->subsystem_device == 0x018a) ||
2780                      (dev->pdev->subsystem_device == 0x019a)))
2781                         force_dac2 = true;
2782                 break;
2783         }
2784
2785         if (force_dac2) {
2786                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2787                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2788                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2789
2790                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2791                    enable it, even it's detected.
2792                 */
2793
2794                 /* force it to crtc0 */
2795                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2796                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2797                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2798
2799                 /* set up the TV DAC */
2800                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2801                                  RADEON_TV_DAC_STD_MASK |
2802                                  RADEON_TV_DAC_RDACPD |
2803                                  RADEON_TV_DAC_GDACPD |
2804                                  RADEON_TV_DAC_BDACPD |
2805                                  RADEON_TV_DAC_BGADJ_MASK |
2806                                  RADEON_TV_DAC_DACADJ_MASK);
2807                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2808                                 RADEON_TV_DAC_NHOLD |
2809                                 RADEON_TV_DAC_STD_PS2 |
2810                                 (0x58 << 16));
2811
2812                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2813                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2814                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2815         }
2816
2817         /* switch PM block to ACPI mode */
2818         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2819         tmp &= ~RADEON_PM_MODE_SEL;
2820         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2821
2822 }
2823
2824 /*
2825  * VRAM info
2826  */
2827 static void r100_vram_get_type(struct radeon_device *rdev)
2828 {
2829         uint32_t tmp;
2830
2831         rdev->mc.vram_is_ddr = false;
2832         if (rdev->flags & RADEON_IS_IGP)
2833                 rdev->mc.vram_is_ddr = true;
2834         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2835                 rdev->mc.vram_is_ddr = true;
2836         if ((rdev->family == CHIP_RV100) ||
2837             (rdev->family == CHIP_RS100) ||
2838             (rdev->family == CHIP_RS200)) {
2839                 tmp = RREG32(RADEON_MEM_CNTL);
2840                 if (tmp & RV100_HALF_MODE) {
2841                         rdev->mc.vram_width = 32;
2842                 } else {
2843                         rdev->mc.vram_width = 64;
2844                 }
2845                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2846                         rdev->mc.vram_width /= 4;
2847                         rdev->mc.vram_is_ddr = true;
2848                 }
2849         } else if (rdev->family <= CHIP_RV280) {
2850                 tmp = RREG32(RADEON_MEM_CNTL);
2851                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2852                         rdev->mc.vram_width = 128;
2853                 } else {
2854                         rdev->mc.vram_width = 64;
2855                 }
2856         } else {
2857                 /* newer IGPs */
2858                 rdev->mc.vram_width = 128;
2859         }
2860 }
2861
2862 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2863 {
2864         u32 aper_size;
2865         u8 byte;
2866
2867         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2868
2869         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2870          * that is has the 2nd generation multifunction PCI interface
2871          */
2872         if (rdev->family == CHIP_RV280 ||
2873             rdev->family >= CHIP_RV350) {
2874                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2875                        ~RADEON_HDP_APER_CNTL);
2876                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2877                 return aper_size * 2;
2878         }
2879
2880         /* Older cards have all sorts of funny issues to deal with. First
2881          * check if it's a multifunction card by reading the PCI config
2882          * header type... Limit those to one aperture size
2883          */
2884         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2885         if (byte & 0x80) {
2886                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2887                 DRM_INFO("Limiting VRAM to one aperture\n");
2888                 return aper_size;
2889         }
2890
2891         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2892          * have set it up. We don't write this as it's broken on some ASICs but
2893          * we expect the BIOS to have done the right thing (might be too optimistic...)
2894          */
2895         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2896                 return aper_size * 2;
2897         return aper_size;
2898 }
2899
2900 void r100_vram_init_sizes(struct radeon_device *rdev)
2901 {
2902         u64 config_aper_size;
2903
2904         /* work out accessible VRAM */
2905         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2906         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2907         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2908         /* FIXME we don't use the second aperture yet when we could use it */
2909         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2910                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2911         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2912         if (rdev->flags & RADEON_IS_IGP) {
2913                 uint32_t tom;
2914                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2915                 tom = RREG32(RADEON_NB_TOM);
2916                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2917                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2918                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2919         } else {
2920                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2921                 /* Some production boards of m6 will report 0
2922                  * if it's 8 MB
2923                  */
2924                 if (rdev->mc.real_vram_size == 0) {
2925                         rdev->mc.real_vram_size = 8192 * 1024;
2926                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2927                 }
2928                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2929                  * Novell bug 204882 + along with lots of ubuntu ones
2930                  */
2931                 if (rdev->mc.aper_size > config_aper_size)
2932                         config_aper_size = rdev->mc.aper_size;
2933
2934                 if (config_aper_size > rdev->mc.real_vram_size)
2935                         rdev->mc.mc_vram_size = config_aper_size;
2936                 else
2937                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2938         }
2939 }
2940
2941 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2942 {
2943         uint32_t temp;
2944
2945         temp = RREG32(RADEON_CONFIG_CNTL);
2946         if (state == false) {
2947                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2948                 temp |= RADEON_CFG_VGA_IO_DIS;
2949         } else {
2950                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2951         }
2952         WREG32(RADEON_CONFIG_CNTL, temp);
2953 }
2954
2955 void r100_mc_init(struct radeon_device *rdev)
2956 {
2957         u64 base;
2958
2959         r100_vram_get_type(rdev);
2960         r100_vram_init_sizes(rdev);
2961         base = rdev->mc.aper_base;
2962         if (rdev->flags & RADEON_IS_IGP)
2963                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2964         radeon_vram_location(rdev, &rdev->mc, base);
2965         rdev->mc.gtt_base_align = 0;
2966         if (!(rdev->flags & RADEON_IS_AGP))
2967                 radeon_gtt_location(rdev, &rdev->mc);
2968         radeon_update_bandwidth_info(rdev);
2969 }
2970
2971
2972 /*
2973  * Indirect registers accessor
2974  */
2975 void r100_pll_errata_after_index(struct radeon_device *rdev)
2976 {
2977         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2978                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2979                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2980         }
2981 }
2982
2983 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2984 {
2985         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2986          * or the chip could hang on a subsequent access
2987          */
2988         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2989                 mdelay(5);
2990         }
2991
2992         /* This function is required to workaround a hardware bug in some (all?)
2993          * revisions of the R300.  This workaround should be called after every
2994          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2995          * may not be correct.
2996          */
2997         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2998                 uint32_t save, tmp;
2999
3000                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
3001                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
3002                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
3003                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
3004                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
3005         }
3006 }
3007
3008 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
3009 {
3010         uint32_t data;
3011
3012         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
3013         r100_pll_errata_after_index(rdev);
3014         data = RREG32(RADEON_CLOCK_CNTL_DATA);
3015         r100_pll_errata_after_data(rdev);
3016         return data;
3017 }
3018
3019 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
3020 {
3021         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
3022         r100_pll_errata_after_index(rdev);
3023         WREG32(RADEON_CLOCK_CNTL_DATA, v);
3024         r100_pll_errata_after_data(rdev);
3025 }
3026
3027 void r100_set_safe_registers(struct radeon_device *rdev)
3028 {
3029         if (ASIC_IS_RN50(rdev)) {
3030                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
3031                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
3032         } else if (rdev->family < CHIP_R200) {
3033                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
3034                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
3035         } else {
3036                 r200_set_safe_registers(rdev);
3037         }
3038 }
3039
3040 /*
3041  * Debugfs info
3042  */
3043 #if defined(CONFIG_DEBUG_FS)
3044 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
3045 {
3046         struct drm_info_node *node = (struct drm_info_node *) m->private;
3047         struct drm_device *dev = node->minor->dev;
3048         struct radeon_device *rdev = dev->dev_private;
3049         uint32_t reg, value;
3050         unsigned i;
3051
3052         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
3053         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
3054         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3055         for (i = 0; i < 64; i++) {
3056                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
3057                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
3058                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
3059                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
3060                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
3061         }
3062         return 0;
3063 }
3064
3065 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
3066 {
3067         struct drm_info_node *node = (struct drm_info_node *) m->private;
3068         struct drm_device *dev = node->minor->dev;
3069         struct radeon_device *rdev = dev->dev_private;
3070         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3071         uint32_t rdp, wdp;
3072         unsigned count, i, j;
3073
3074         radeon_ring_free_size(rdev, ring);
3075         rdp = RREG32(RADEON_CP_RB_RPTR);
3076         wdp = RREG32(RADEON_CP_RB_WPTR);
3077         count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
3078         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3079         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
3080         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
3081         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
3082         seq_printf(m, "%u dwords in ring\n", count);
3083         for (j = 0; j <= count; j++) {
3084                 i = (rdp + j) & ring->ptr_mask;
3085                 seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
3086         }
3087         return 0;
3088 }
3089
3090
3091 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
3092 {
3093         struct drm_info_node *node = (struct drm_info_node *) m->private;
3094         struct drm_device *dev = node->minor->dev;
3095         struct radeon_device *rdev = dev->dev_private;
3096         uint32_t csq_stat, csq2_stat, tmp;
3097         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
3098         unsigned i;
3099
3100         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
3101         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
3102         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
3103         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
3104         r_rptr = (csq_stat >> 0) & 0x3ff;
3105         r_wptr = (csq_stat >> 10) & 0x3ff;
3106         ib1_rptr = (csq_stat >> 20) & 0x3ff;
3107         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
3108         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
3109         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
3110         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
3111         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
3112         seq_printf(m, "Ring rptr %u\n", r_rptr);
3113         seq_printf(m, "Ring wptr %u\n", r_wptr);
3114         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
3115         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
3116         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
3117         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
3118         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
3119          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
3120         seq_printf(m, "Ring fifo:\n");
3121         for (i = 0; i < 256; i++) {
3122                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3123                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3124                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
3125         }
3126         seq_printf(m, "Indirect1 fifo:\n");
3127         for (i = 256; i <= 512; i++) {
3128                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3129                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3130                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
3131         }
3132         seq_printf(m, "Indirect2 fifo:\n");
3133         for (i = 640; i < ib1_wptr; i++) {
3134                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
3135                 tmp = RREG32(RADEON_CP_CSQ_DATA);
3136                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
3137         }
3138         return 0;
3139 }
3140
3141 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
3142 {
3143         struct drm_info_node *node = (struct drm_info_node *) m->private;
3144         struct drm_device *dev = node->minor->dev;
3145         struct radeon_device *rdev = dev->dev_private;
3146         uint32_t tmp;
3147
3148         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3149         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3150         tmp = RREG32(RADEON_MC_FB_LOCATION);
3151         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3152         tmp = RREG32(RADEON_BUS_CNTL);
3153         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3154         tmp = RREG32(RADEON_MC_AGP_LOCATION);
3155         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3156         tmp = RREG32(RADEON_AGP_BASE);
3157         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3158         tmp = RREG32(RADEON_HOST_PATH_CNTL);
3159         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3160         tmp = RREG32(0x01D0);
3161         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3162         tmp = RREG32(RADEON_AIC_LO_ADDR);
3163         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3164         tmp = RREG32(RADEON_AIC_HI_ADDR);
3165         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3166         tmp = RREG32(0x01E4);
3167         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3168         return 0;
3169 }
3170
3171 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3172         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3173 };
3174
3175 static struct drm_info_list r100_debugfs_cp_list[] = {
3176         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3177         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3178 };
3179
3180 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3181         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3182 };
3183 #endif
3184
3185 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3186 {
3187 #if defined(CONFIG_DEBUG_FS)
3188         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3189 #else
3190         return 0;
3191 #endif
3192 }
3193
3194 int r100_debugfs_cp_init(struct radeon_device *rdev)
3195 {
3196 #if defined(CONFIG_DEBUG_FS)
3197         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3198 #else
3199         return 0;
3200 #endif
3201 }
3202
3203 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3204 {
3205 #if defined(CONFIG_DEBUG_FS)
3206         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3207 #else
3208         return 0;
3209 #endif
3210 }
3211
3212 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3213                          uint32_t tiling_flags, uint32_t pitch,
3214                          uint32_t offset, uint32_t obj_size)
3215 {
3216         int surf_index = reg * 16;
3217         int flags = 0;
3218
3219         if (rdev->family <= CHIP_RS200) {
3220                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3221                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3222                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
3223                 if (tiling_flags & RADEON_TILING_MACRO)
3224                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
3225         } else if (rdev->family <= CHIP_RV280) {
3226                 if (tiling_flags & (RADEON_TILING_MACRO))
3227                         flags |= R200_SURF_TILE_COLOR_MACRO;
3228                 if (tiling_flags & RADEON_TILING_MICRO)
3229                         flags |= R200_SURF_TILE_COLOR_MICRO;
3230         } else {
3231                 if (tiling_flags & RADEON_TILING_MACRO)
3232                         flags |= R300_SURF_TILE_MACRO;
3233                 if (tiling_flags & RADEON_TILING_MICRO)
3234                         flags |= R300_SURF_TILE_MICRO;
3235         }
3236
3237         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3238                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3239         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3240                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3241
3242         /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
3243         if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
3244                 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
3245                         if (ASIC_IS_RN50(rdev))
3246                                 pitch /= 16;
3247         }
3248
3249         /* r100/r200 divide by 16 */
3250         if (rdev->family < CHIP_R300)
3251                 flags |= pitch / 16;
3252         else
3253                 flags |= pitch / 8;
3254
3255
3256         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3257         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3258         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3259         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3260         return 0;
3261 }
3262
3263 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3264 {
3265         int surf_index = reg * 16;
3266         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3267 }
3268
3269 void r100_bandwidth_update(struct radeon_device *rdev)
3270 {
3271         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3272         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3273         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3274         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3275         fixed20_12 memtcas_ff[8] = {
3276                 dfixed_init(1),
3277                 dfixed_init(2),
3278                 dfixed_init(3),
3279                 dfixed_init(0),
3280                 dfixed_init_half(1),
3281                 dfixed_init_half(2),
3282                 dfixed_init(0),
3283         };
3284         fixed20_12 memtcas_rs480_ff[8] = {
3285                 dfixed_init(0),
3286                 dfixed_init(1),
3287                 dfixed_init(2),
3288                 dfixed_init(3),
3289                 dfixed_init(0),
3290                 dfixed_init_half(1),
3291                 dfixed_init_half(2),
3292                 dfixed_init_half(3),
3293         };
3294         fixed20_12 memtcas2_ff[8] = {
3295                 dfixed_init(0),
3296                 dfixed_init(1),
3297                 dfixed_init(2),
3298                 dfixed_init(3),
3299                 dfixed_init(4),
3300                 dfixed_init(5),
3301                 dfixed_init(6),
3302                 dfixed_init(7),
3303         };
3304         fixed20_12 memtrbs[8] = {
3305                 dfixed_init(1),
3306                 dfixed_init_half(1),
3307                 dfixed_init(2),
3308                 dfixed_init_half(2),
3309                 dfixed_init(3),
3310                 dfixed_init_half(3),
3311                 dfixed_init(4),
3312                 dfixed_init_half(4)
3313         };
3314         fixed20_12 memtrbs_r4xx[8] = {
3315                 dfixed_init(4),
3316                 dfixed_init(5),
3317                 dfixed_init(6),
3318                 dfixed_init(7),
3319                 dfixed_init(8),
3320                 dfixed_init(9),
3321                 dfixed_init(10),
3322                 dfixed_init(11)
3323         };
3324         fixed20_12 min_mem_eff;
3325         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3326         fixed20_12 cur_latency_mclk, cur_latency_sclk;
3327         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3328                 disp_drain_rate2, read_return_rate;
3329         fixed20_12 time_disp1_drop_priority;
3330         int c;
3331         int cur_size = 16;       /* in octawords */
3332         int critical_point = 0, critical_point2;
3333 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
3334         int stop_req, max_stop_req;
3335         struct drm_display_mode *mode1 = NULL;
3336         struct drm_display_mode *mode2 = NULL;
3337         uint32_t pixel_bytes1 = 0;
3338         uint32_t pixel_bytes2 = 0;
3339
3340         radeon_update_display_priority(rdev);
3341
3342         if (rdev->mode_info.crtcs[0]->base.enabled) {
3343                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3344                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
3345         }
3346         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3347                 if (rdev->mode_info.crtcs[1]->base.enabled) {
3348                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3349                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
3350                 }
3351         }
3352
3353         min_mem_eff.full = dfixed_const_8(0);
3354         /* get modes */
3355         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3356                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3357                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3358                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3359                 /* check crtc enables */
3360                 if (mode2)
3361                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3362                 if (mode1)
3363                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3364                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3365         }
3366
3367         /*
3368          * determine is there is enough bw for current mode
3369          */
3370         sclk_ff = rdev->pm.sclk;
3371         mclk_ff = rdev->pm.mclk;
3372
3373         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3374         temp_ff.full = dfixed_const(temp);
3375         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3376
3377         pix_clk.full = 0;
3378         pix_clk2.full = 0;
3379         peak_disp_bw.full = 0;
3380         if (mode1) {
3381                 temp_ff.full = dfixed_const(1000);
3382                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3383                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3384                 temp_ff.full = dfixed_const(pixel_bytes1);
3385                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3386         }
3387         if (mode2) {
3388                 temp_ff.full = dfixed_const(1000);
3389                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3390                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3391                 temp_ff.full = dfixed_const(pixel_bytes2);
3392                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3393         }
3394
3395         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3396         if (peak_disp_bw.full >= mem_bw.full) {
3397                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3398                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3399         }
3400
3401         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
3402         temp = RREG32(RADEON_MEM_TIMING_CNTL);
3403         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3404                 mem_trcd = ((temp >> 2) & 0x3) + 1;
3405                 mem_trp  = ((temp & 0x3)) + 1;
3406                 mem_tras = ((temp & 0x70) >> 4) + 1;
3407         } else if (rdev->family == CHIP_R300 ||
3408                    rdev->family == CHIP_R350) { /* r300, r350 */
3409                 mem_trcd = (temp & 0x7) + 1;
3410                 mem_trp = ((temp >> 8) & 0x7) + 1;
3411                 mem_tras = ((temp >> 11) & 0xf) + 4;
3412         } else if (rdev->family == CHIP_RV350 ||
3413                    rdev->family <= CHIP_RV380) {
3414                 /* rv3x0 */
3415                 mem_trcd = (temp & 0x7) + 3;
3416                 mem_trp = ((temp >> 8) & 0x7) + 3;
3417                 mem_tras = ((temp >> 11) & 0xf) + 6;
3418         } else if (rdev->family == CHIP_R420 ||
3419                    rdev->family == CHIP_R423 ||
3420                    rdev->family == CHIP_RV410) {
3421                 /* r4xx */
3422                 mem_trcd = (temp & 0xf) + 3;
3423                 if (mem_trcd > 15)
3424                         mem_trcd = 15;
3425                 mem_trp = ((temp >> 8) & 0xf) + 3;
3426                 if (mem_trp > 15)
3427                         mem_trp = 15;
3428                 mem_tras = ((temp >> 12) & 0x1f) + 6;
3429                 if (mem_tras > 31)
3430                         mem_tras = 31;
3431         } else { /* RV200, R200 */
3432                 mem_trcd = (temp & 0x7) + 1;
3433                 mem_trp = ((temp >> 8) & 0x7) + 1;
3434                 mem_tras = ((temp >> 12) & 0xf) + 4;
3435         }
3436         /* convert to FF */
3437         trcd_ff.full = dfixed_const(mem_trcd);
3438         trp_ff.full = dfixed_const(mem_trp);
3439         tras_ff.full = dfixed_const(mem_tras);
3440
3441         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3442         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3443         data = (temp & (7 << 20)) >> 20;
3444         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3445                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3446                         tcas_ff = memtcas_rs480_ff[data];
3447                 else
3448                         tcas_ff = memtcas_ff[data];
3449         } else
3450                 tcas_ff = memtcas2_ff[data];
3451
3452         if (rdev->family == CHIP_RS400 ||
3453             rdev->family == CHIP_RS480) {
3454                 /* extra cas latency stored in bits 23-25 0-4 clocks */
3455                 data = (temp >> 23) & 0x7;
3456                 if (data < 5)
3457                         tcas_ff.full += dfixed_const(data);
3458         }
3459
3460         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3461                 /* on the R300, Tcas is included in Trbs.
3462                  */
3463                 temp = RREG32(RADEON_MEM_CNTL);
3464                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3465                 if (data == 1) {
3466                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
3467                                 temp = RREG32(R300_MC_IND_INDEX);
3468                                 temp &= ~R300_MC_IND_ADDR_MASK;
3469                                 temp |= R300_MC_READ_CNTL_CD_mcind;
3470                                 WREG32(R300_MC_IND_INDEX, temp);
3471                                 temp = RREG32(R300_MC_IND_DATA);
3472                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3473                         } else {
3474                                 temp = RREG32(R300_MC_READ_CNTL_AB);
3475                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3476                         }
3477                 } else {
3478                         temp = RREG32(R300_MC_READ_CNTL_AB);
3479                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3480                 }
3481                 if (rdev->family == CHIP_RV410 ||
3482                     rdev->family == CHIP_R420 ||
3483                     rdev->family == CHIP_R423)
3484                         trbs_ff = memtrbs_r4xx[data];
3485                 else
3486                         trbs_ff = memtrbs[data];
3487                 tcas_ff.full += trbs_ff.full;
3488         }
3489
3490         sclk_eff_ff.full = sclk_ff.full;
3491
3492         if (rdev->flags & RADEON_IS_AGP) {
3493                 fixed20_12 agpmode_ff;
3494                 agpmode_ff.full = dfixed_const(radeon_agpmode);
3495                 temp_ff.full = dfixed_const_666(16);
3496                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3497         }
3498         /* TODO PCIE lanes may affect this - agpmode == 16?? */
3499
3500         if (ASIC_IS_R300(rdev)) {
3501                 sclk_delay_ff.full = dfixed_const(250);
3502         } else {
3503                 if ((rdev->family == CHIP_RV100) ||
3504                     rdev->flags & RADEON_IS_IGP) {
3505                         if (rdev->mc.vram_is_ddr)
3506                                 sclk_delay_ff.full = dfixed_const(41);
3507                         else
3508                                 sclk_delay_ff.full = dfixed_const(33);
3509                 } else {
3510                         if (rdev->mc.vram_width == 128)
3511                                 sclk_delay_ff.full = dfixed_const(57);
3512                         else
3513                                 sclk_delay_ff.full = dfixed_const(41);
3514                 }
3515         }
3516
3517         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3518
3519         if (rdev->mc.vram_is_ddr) {
3520                 if (rdev->mc.vram_width == 32) {
3521                         k1.full = dfixed_const(40);
3522                         c  = 3;
3523                 } else {
3524                         k1.full = dfixed_const(20);
3525                         c  = 1;
3526                 }
3527         } else {
3528                 k1.full = dfixed_const(40);
3529                 c  = 3;
3530         }
3531
3532         temp_ff.full = dfixed_const(2);
3533         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3534         temp_ff.full = dfixed_const(c);
3535         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3536         temp_ff.full = dfixed_const(4);
3537         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3538         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3539         mc_latency_mclk.full += k1.full;
3540
3541         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3542         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3543
3544         /*
3545           HW cursor time assuming worst case of full size colour cursor.
3546         */
3547         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3548         temp_ff.full += trcd_ff.full;
3549         if (temp_ff.full < tras_ff.full)
3550                 temp_ff.full = tras_ff.full;
3551         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3552
3553         temp_ff.full = dfixed_const(cur_size);
3554         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3555         /*
3556           Find the total latency for the display data.
3557         */
3558         disp_latency_overhead.full = dfixed_const(8);
3559         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3560         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3561         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3562
3563         if (mc_latency_mclk.full > mc_latency_sclk.full)
3564                 disp_latency.full = mc_latency_mclk.full;
3565         else
3566                 disp_latency.full = mc_latency_sclk.full;
3567
3568         /* setup Max GRPH_STOP_REQ default value */
3569         if (ASIC_IS_RV100(rdev))
3570                 max_stop_req = 0x5c;
3571         else
3572                 max_stop_req = 0x7c;
3573
3574         if (mode1) {
3575                 /*  CRTC1
3576                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3577                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3578                 */
3579                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3580
3581                 if (stop_req > max_stop_req)
3582                         stop_req = max_stop_req;
3583
3584                 /*
3585                   Find the drain rate of the display buffer.
3586                 */
3587                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3588                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3589
3590                 /*
3591                   Find the critical point of the display buffer.
3592                 */
3593                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3594                 crit_point_ff.full += dfixed_const_half(0);
3595
3596                 critical_point = dfixed_trunc(crit_point_ff);
3597
3598                 if (rdev->disp_priority == 2) {
3599                         critical_point = 0;
3600                 }
3601
3602                 /*
3603                   The critical point should never be above max_stop_req-4.  Setting
3604                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3605                 */
3606                 if (max_stop_req - critical_point < 4)
3607                         critical_point = 0;
3608
3609                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3610                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3611                         critical_point = 0x10;
3612                 }
3613
3614                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3615                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3616                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3617                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3618                 if ((rdev->family == CHIP_R350) &&
3619                     (stop_req > 0x15)) {
3620                         stop_req -= 0x10;
3621                 }
3622                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3623                 temp |= RADEON_GRPH_BUFFER_SIZE;
3624                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3625                           RADEON_GRPH_CRITICAL_AT_SOF |
3626                           RADEON_GRPH_STOP_CNTL);
3627                 /*
3628                   Write the result into the register.
3629                 */
3630                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3631                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3632
3633 #if 0
3634                 if ((rdev->family == CHIP_RS400) ||
3635                     (rdev->family == CHIP_RS480)) {
3636                         /* attempt to program RS400 disp regs correctly ??? */
3637                         temp = RREG32(RS400_DISP1_REG_CNTL);
3638                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3639                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3640                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3641                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3642                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3643                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3644                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3645                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3646                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3647                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3648                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3649                 }
3650 #endif
3651
3652                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3653                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3654                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3655         }
3656
3657         if (mode2) {
3658                 u32 grph2_cntl;
3659                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3660
3661                 if (stop_req > max_stop_req)
3662                         stop_req = max_stop_req;
3663
3664                 /*
3665                   Find the drain rate of the display buffer.
3666                 */
3667                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3668                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3669
3670                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3671                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3672                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3673                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3674                 if ((rdev->family == CHIP_R350) &&
3675                     (stop_req > 0x15)) {
3676                         stop_req -= 0x10;
3677                 }
3678                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3679                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3680                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3681                           RADEON_GRPH_CRITICAL_AT_SOF |
3682                           RADEON_GRPH_STOP_CNTL);
3683
3684                 if ((rdev->family == CHIP_RS100) ||
3685                     (rdev->family == CHIP_RS200))
3686                         critical_point2 = 0;
3687                 else {
3688                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3689                         temp_ff.full = dfixed_const(temp);
3690                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3691                         if (sclk_ff.full < temp_ff.full)
3692                                 temp_ff.full = sclk_ff.full;
3693
3694                         read_return_rate.full = temp_ff.full;
3695
3696                         if (mode1) {
3697                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3698                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3699                         } else {
3700                                 time_disp1_drop_priority.full = 0;
3701                         }
3702                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3703                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3704                         crit_point_ff.full += dfixed_const_half(0);
3705
3706                         critical_point2 = dfixed_trunc(crit_point_ff);
3707
3708                         if (rdev->disp_priority == 2) {
3709                                 critical_point2 = 0;
3710                         }
3711
3712                         if (max_stop_req - critical_point2 < 4)
3713                                 critical_point2 = 0;
3714
3715                 }
3716
3717                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3718                         /* some R300 cards have problem with this set to 0 */
3719                         critical_point2 = 0x10;
3720                 }
3721
3722                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3723                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3724
3725                 if ((rdev->family == CHIP_RS400) ||
3726                     (rdev->family == CHIP_RS480)) {
3727 #if 0
3728                         /* attempt to program RS400 disp2 regs correctly ??? */
3729                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3730                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3731                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3732                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3733                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3734                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3735                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3736                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3737                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3738                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3739                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3740                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3741 #endif
3742                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3743                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3744                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3745                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3746                 }
3747
3748                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3749                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3750         }
3751 }
3752
3753 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3754 {
3755         uint32_t scratch;
3756         uint32_t tmp = 0;
3757         unsigned i;
3758         int r;
3759
3760         r = radeon_scratch_get(rdev, &scratch);
3761         if (r) {
3762                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3763                 return r;
3764         }
3765         WREG32(scratch, 0xCAFEDEAD);
3766         r = radeon_ring_lock(rdev, ring, 2);
3767         if (r) {
3768                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3769                 radeon_scratch_free(rdev, scratch);
3770                 return r;
3771         }
3772         radeon_ring_write(ring, PACKET0(scratch, 0));
3773         radeon_ring_write(ring, 0xDEADBEEF);
3774         radeon_ring_unlock_commit(rdev, ring);
3775         for (i = 0; i < rdev->usec_timeout; i++) {
3776                 tmp = RREG32(scratch);
3777                 if (tmp == 0xDEADBEEF) {
3778                         break;
3779                 }
3780                 DRM_UDELAY(1);
3781         }
3782         if (i < rdev->usec_timeout) {
3783                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3784         } else {
3785                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3786                           scratch, tmp);
3787                 r = -EINVAL;
3788         }
3789         radeon_scratch_free(rdev, scratch);
3790         return r;
3791 }
3792
3793 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3794 {
3795         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3796
3797         if (ring->rptr_save_reg) {
3798                 u32 next_rptr = ring->wptr + 2 + 3;
3799                 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3800                 radeon_ring_write(ring, next_rptr);
3801         }
3802
3803         radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3804         radeon_ring_write(ring, ib->gpu_addr);
3805         radeon_ring_write(ring, ib->length_dw);
3806 }
3807
3808 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3809 {
3810         struct radeon_ib ib;
3811         uint32_t scratch;
3812         uint32_t tmp = 0;
3813         unsigned i;
3814         int r;
3815
3816         r = radeon_scratch_get(rdev, &scratch);
3817         if (r) {
3818                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3819                 return r;
3820         }
3821         WREG32(scratch, 0xCAFEDEAD);
3822         r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, 256);
3823         if (r) {
3824                 return r;
3825         }
3826         ib.ptr[0] = PACKET0(scratch, 0);
3827         ib.ptr[1] = 0xDEADBEEF;
3828         ib.ptr[2] = PACKET2(0);
3829         ib.ptr[3] = PACKET2(0);
3830         ib.ptr[4] = PACKET2(0);
3831         ib.ptr[5] = PACKET2(0);
3832         ib.ptr[6] = PACKET2(0);
3833         ib.ptr[7] = PACKET2(0);
3834         ib.length_dw = 8;
3835         r = radeon_ib_schedule(rdev, &ib, NULL);
3836         if (r) {
3837                 radeon_scratch_free(rdev, scratch);
3838                 radeon_ib_free(rdev, &ib);
3839                 return r;
3840         }
3841         r = radeon_fence_wait(ib.fence, false);
3842         if (r) {
3843                 return r;
3844         }
3845         for (i = 0; i < rdev->usec_timeout; i++) {
3846                 tmp = RREG32(scratch);
3847                 if (tmp == 0xDEADBEEF) {
3848                         break;
3849                 }
3850                 DRM_UDELAY(1);
3851         }
3852         if (i < rdev->usec_timeout) {
3853                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3854         } else {
3855                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3856                           scratch, tmp);
3857                 r = -EINVAL;
3858         }
3859         radeon_scratch_free(rdev, scratch);
3860         radeon_ib_free(rdev, &ib);
3861         return r;
3862 }
3863
3864 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3865 {
3866         /* Shutdown CP we shouldn't need to do that but better be safe than
3867          * sorry
3868          */
3869         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3870         WREG32(R_000740_CP_CSQ_CNTL, 0);
3871
3872         /* Save few CRTC registers */
3873         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3874         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3875         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3876         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3877         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3878                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3879                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3880         }
3881
3882         /* Disable VGA aperture access */
3883         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3884         /* Disable cursor, overlay, crtc */
3885         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3886         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3887                                         S_000054_CRTC_DISPLAY_DIS(1));
3888         WREG32(R_000050_CRTC_GEN_CNTL,
3889                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3890                         S_000050_CRTC_DISP_REQ_EN_B(1));
3891         WREG32(R_000420_OV0_SCALE_CNTL,
3892                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3893         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3894         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3895                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3896                                                 S_000360_CUR2_LOCK(1));
3897                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3898                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3899                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3900                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3901                 WREG32(R_000360_CUR2_OFFSET,
3902                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3903         }
3904 }
3905
3906 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3907 {
3908         /* Update base address for crtc */
3909         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3910         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3911                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3912         }
3913         /* Restore CRTC registers */
3914         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3915         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3916         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3917         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3918                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3919         }
3920 }
3921
3922 void r100_vga_render_disable(struct radeon_device *rdev)
3923 {
3924         u32 tmp;
3925
3926         tmp = RREG8(R_0003C2_GENMO_WT);
3927         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3928 }
3929
3930 static void r100_debugfs(struct radeon_device *rdev)
3931 {
3932         int r;
3933
3934         r = r100_debugfs_mc_info_init(rdev);
3935         if (r)
3936                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3937 }
3938
3939 static void r100_mc_program(struct radeon_device *rdev)
3940 {
3941         struct r100_mc_save save;
3942
3943         /* Stops all mc clients */
3944         r100_mc_stop(rdev, &save);
3945         if (rdev->flags & RADEON_IS_AGP) {
3946                 WREG32(R_00014C_MC_AGP_LOCATION,
3947                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3948                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3949                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3950                 if (rdev->family > CHIP_RV200)
3951                         WREG32(R_00015C_AGP_BASE_2,
3952                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3953         } else {
3954                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3955                 WREG32(R_000170_AGP_BASE, 0);
3956                 if (rdev->family > CHIP_RV200)
3957                         WREG32(R_00015C_AGP_BASE_2, 0);
3958         }
3959         /* Wait for mc idle */
3960         if (r100_mc_wait_for_idle(rdev))
3961                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3962         /* Program MC, should be a 32bits limited address space */
3963         WREG32(R_000148_MC_FB_LOCATION,
3964                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3965                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3966         r100_mc_resume(rdev, &save);
3967 }
3968
3969 void r100_clock_startup(struct radeon_device *rdev)
3970 {
3971         u32 tmp;
3972
3973         if (radeon_dynclks != -1 && radeon_dynclks)
3974                 radeon_legacy_set_clock_gating(rdev, 1);
3975         /* We need to force on some of the block */
3976         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3977         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3978         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3979                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3980         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3981 }
3982
3983 static int r100_startup(struct radeon_device *rdev)
3984 {
3985         int r;
3986
3987         /* set common regs */
3988         r100_set_common_regs(rdev);
3989         /* program mc */
3990         r100_mc_program(rdev);
3991         /* Resume clock */
3992         r100_clock_startup(rdev);
3993         /* Initialize GART (initialize after TTM so we can allocate
3994          * memory through TTM but finalize after TTM) */
3995         r100_enable_bm(rdev);
3996         if (rdev->flags & RADEON_IS_PCI) {
3997                 r = r100_pci_gart_enable(rdev);
3998                 if (r)
3999                         return r;
4000         }
4001
4002         /* allocate wb buffer */
4003         r = radeon_wb_init(rdev);
4004         if (r)
4005                 return r;
4006
4007         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
4008         if (r) {
4009                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
4010                 return r;
4011         }
4012
4013         /* Enable IRQ */
4014         r100_irq_set(rdev);
4015         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
4016         /* 1M ring buffer */
4017         r = r100_cp_init(rdev, 1024 * 1024);
4018         if (r) {
4019                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
4020                 return r;
4021         }
4022
4023         r = radeon_ib_pool_init(rdev);
4024         if (r) {
4025                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
4026                 return r;
4027         }
4028
4029         return 0;
4030 }
4031
4032 int r100_resume(struct radeon_device *rdev)
4033 {
4034         int r;
4035
4036         /* Make sur GART are not working */
4037         if (rdev->flags & RADEON_IS_PCI)
4038                 r100_pci_gart_disable(rdev);
4039         /* Resume clock before doing reset */
4040         r100_clock_startup(rdev);
4041         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4042         if (radeon_asic_reset(rdev)) {
4043                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4044                         RREG32(R_000E40_RBBM_STATUS),
4045                         RREG32(R_0007C0_CP_STAT));
4046         }
4047         /* post */
4048         radeon_combios_asic_init(rdev->ddev);
4049         /* Resume clock after posting */
4050         r100_clock_startup(rdev);
4051         /* Initialize surface registers */
4052         radeon_surface_init(rdev);
4053
4054         rdev->accel_working = true;
4055         r = r100_startup(rdev);
4056         if (r) {
4057                 rdev->accel_working = false;
4058         }
4059         return r;
4060 }
4061
4062 int r100_suspend(struct radeon_device *rdev)
4063 {
4064         r100_cp_disable(rdev);
4065         radeon_wb_disable(rdev);
4066         r100_irq_disable(rdev);
4067         if (rdev->flags & RADEON_IS_PCI)
4068                 r100_pci_gart_disable(rdev);
4069         return 0;
4070 }
4071
4072 void r100_fini(struct radeon_device *rdev)
4073 {
4074         r100_cp_fini(rdev);
4075         radeon_wb_fini(rdev);
4076         radeon_ib_pool_fini(rdev);
4077         radeon_gem_fini(rdev);
4078         if (rdev->flags & RADEON_IS_PCI)
4079                 r100_pci_gart_fini(rdev);
4080         radeon_agp_fini(rdev);
4081         radeon_irq_kms_fini(rdev);
4082         radeon_fence_driver_fini(rdev);
4083         radeon_bo_fini(rdev);
4084         radeon_atombios_fini(rdev);
4085         kfree(rdev->bios);
4086         rdev->bios = NULL;
4087 }
4088
4089 /*
4090  * Due to how kexec works, it can leave the hw fully initialised when it
4091  * boots the new kernel. However doing our init sequence with the CP and
4092  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
4093  * do some quick sanity checks and restore sane values to avoid this
4094  * problem.
4095  */
4096 void r100_restore_sanity(struct radeon_device *rdev)
4097 {
4098         u32 tmp;
4099
4100         tmp = RREG32(RADEON_CP_CSQ_CNTL);
4101         if (tmp) {
4102                 WREG32(RADEON_CP_CSQ_CNTL, 0);
4103         }
4104         tmp = RREG32(RADEON_CP_RB_CNTL);
4105         if (tmp) {
4106                 WREG32(RADEON_CP_RB_CNTL, 0);
4107         }
4108         tmp = RREG32(RADEON_SCRATCH_UMSK);
4109         if (tmp) {
4110                 WREG32(RADEON_SCRATCH_UMSK, 0);
4111         }
4112 }
4113
4114 int r100_init(struct radeon_device *rdev)
4115 {
4116         int r;
4117
4118         /* Register debugfs file specific to this group of asics */
4119         r100_debugfs(rdev);
4120         /* Disable VGA */
4121         r100_vga_render_disable(rdev);
4122         /* Initialize scratch registers */
4123         radeon_scratch_init(rdev);
4124         /* Initialize surface registers */
4125         radeon_surface_init(rdev);
4126         /* sanity check some register to avoid hangs like after kexec */
4127         r100_restore_sanity(rdev);
4128         /* TODO: disable VGA need to use VGA request */
4129         /* BIOS*/
4130         if (!radeon_get_bios(rdev)) {
4131                 if (ASIC_IS_AVIVO(rdev))
4132                         return -EINVAL;
4133         }
4134         if (rdev->is_atom_bios) {
4135                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
4136                 return -EINVAL;
4137         } else {
4138                 r = radeon_combios_init(rdev);
4139                 if (r)
4140                         return r;
4141         }
4142         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4143         if (radeon_asic_reset(rdev)) {
4144                 dev_warn(rdev->dev,
4145                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4146                         RREG32(R_000E40_RBBM_STATUS),
4147                         RREG32(R_0007C0_CP_STAT));
4148         }
4149         /* check if cards are posted or not */
4150         if (radeon_boot_test_post_card(rdev) == false)
4151                 return -EINVAL;
4152         /* Set asic errata */
4153         r100_errata(rdev);
4154         /* Initialize clocks */
4155         radeon_get_clock_info(rdev->ddev);
4156         /* initialize AGP */
4157         if (rdev->flags & RADEON_IS_AGP) {
4158                 r = radeon_agp_init(rdev);
4159                 if (r) {
4160                         radeon_agp_disable(rdev);
4161                 }
4162         }
4163         /* initialize VRAM */
4164         r100_mc_init(rdev);
4165         /* Fence driver */
4166         r = radeon_fence_driver_init(rdev);
4167         if (r)
4168                 return r;
4169         r = radeon_irq_kms_init(rdev);
4170         if (r)
4171                 return r;
4172         /* Memory manager */
4173         r = radeon_bo_init(rdev);
4174         if (r)
4175                 return r;
4176         if (rdev->flags & RADEON_IS_PCI) {
4177                 r = r100_pci_gart_init(rdev);
4178                 if (r)
4179                         return r;
4180         }
4181         r100_set_safe_registers(rdev);
4182
4183         rdev->accel_working = true;
4184         r = r100_startup(rdev);
4185         if (r) {
4186                 /* Somethings want wront with the accel init stop accel */
4187                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4188                 r100_cp_fini(rdev);
4189                 radeon_wb_fini(rdev);
4190                 radeon_ib_pool_fini(rdev);
4191                 radeon_irq_kms_fini(rdev);
4192                 if (rdev->flags & RADEON_IS_PCI)
4193                         r100_pci_gart_fini(rdev);
4194                 rdev->accel_working = false;
4195         }
4196         return 0;
4197 }
4198
4199 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
4200 {
4201         if (reg < rdev->rmmio_size)
4202                 return readl(((void __iomem *)rdev->rmmio) + reg);
4203         else {
4204                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4205                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4206         }
4207 }
4208
4209 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
4210 {
4211         if (reg < rdev->rmmio_size)
4212                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4213         else {
4214                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4215                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4216         }
4217 }
4218
4219 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4220 {
4221         if (reg < rdev->rio_mem_size)
4222                 return ioread32(rdev->rio_mem + reg);
4223         else {
4224                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4225                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4226         }
4227 }
4228
4229 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4230 {
4231         if (reg < rdev->rio_mem_size)
4232                 iowrite32(v, rdev->rio_mem + reg);
4233         else {
4234                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4235                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4236         }
4237 }