drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include "drmP.h"
  31 #include "drm.h"
  32 #include "radeon_drm.h"
  33 #include "radeon_reg.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "r100d.h"
  37 #include "rs100d.h"
  38 #include "rv200d.h"
  39 #include "rv250d.h"
  40 #include "atom.h"
  41
  42 #include <linux/firmware.h>
  43 #include <linux/platform_device.h>
  44
  45 #include "r100_reg_safe.h"
  46 #include "rn50_reg_safe.h"
  47
  48 /* Firmware Names */
  49 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  50 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  51 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  52 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  53 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  54 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  55 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  56
  57 MODULE_FIRMWARE(FIRMWARE_R100);
  58 MODULE_FIRMWARE(FIRMWARE_R200);
  59 MODULE_FIRMWARE(FIRMWARE_R300);
  60 MODULE_FIRMWARE(FIRMWARE_R420);
  61 MODULE_FIRMWARE(FIRMWARE_RS690);
  62 MODULE_FIRMWARE(FIRMWARE_RS600);
  63 MODULE_FIRMWARE(FIRMWARE_R520);
  64
  65 #include "r100_track.h"
  66
  67 /* This files gather functions specifics to:
  68  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  69  */
  70
  71 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
  72 {
  73         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
  74         u32 tmp;
  75
  76         /* make sure flip is at vb rather than hb */
  77         tmp = RREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset);
  78         tmp &= ~RADEON_CRTC_OFFSET_FLIP_CNTL;
  79         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, tmp);
  80
  81         /* set pageflip to happen as late as possible in the vblank interval.
  82          * same field for crtc1/2
  83          */
  84         tmp = RREG32(RADEON_CRTC_GEN_CNTL);
  85         tmp &= ~RADEON_CRTC_VSTAT_MODE_MASK;
  86         WREG32(RADEON_CRTC_GEN_CNTL, tmp);
  87
  88         /* enable the pflip int */
  89         radeon_irq_kms_pflip_irq_get(rdev, crtc);
  90 }
  91
  92 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
  93 {
  94         /* disable the pflip int */
  95         radeon_irq_kms_pflip_irq_put(rdev, crtc);
  96 }
  97
  98 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
  99 {
 100         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 101         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 102
 103         /* Lock the graphics update lock */
 104         /* update the scanout addresses */
 105         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 106
 107         /* Note: We don't wait for update_pending to assert, as this never
 108          * happens for some reason on R1xx - R4xx. Adds a bit of imprecision.
 109          */
 110
 111         /* Unlock the lock, so double-buffering can take place inside vblank */
 112         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 113         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 114
 115         /* Return current update_pending status: */
 116         return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
 117 }
 118
 119 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 120 {
 121         int i;
 122         rdev->pm.dynpm_can_upclock = true;
 123         rdev->pm.dynpm_can_downclock = true;
 124
 125         switch (rdev->pm.dynpm_planned_action) {
 126         case DYNPM_ACTION_MINIMUM:
 127                 rdev->pm.requested_power_state_index = 0;
 128                 rdev->pm.dynpm_can_downclock = false;
 129                 break;
 130         case DYNPM_ACTION_DOWNCLOCK:
 131                 if (rdev->pm.current_power_state_index == 0) {
 132                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 133                         rdev->pm.dynpm_can_downclock = false;
 134                 } else {
 135                         if (rdev->pm.active_crtc_count > 1) {
 136                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 137                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 138                                                 continue;
 139                                         else if (i >= rdev->pm.current_power_state_index) {
 140                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 141                                                 break;
 142                                         } else {
 143                                                 rdev->pm.requested_power_state_index = i;
 144                                                 break;
 145                                         }
 146                                 }
 147                         } else
 148                                 rdev->pm.requested_power_state_index =
 149                                         rdev->pm.current_power_state_index - 1;
 150                 }
 151                 /* don't use the power state if crtcs are active and no display flag is set */
 152                 if ((rdev->pm.active_crtc_count > 0) &&
 153                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 154                      RADEON_PM_MODE_NO_DISPLAY)) {
 155                         rdev->pm.requested_power_state_index++;
 156                 }
 157                 break;
 158         case DYNPM_ACTION_UPCLOCK:
 159                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 160                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 161                         rdev->pm.dynpm_can_upclock = false;
 162                 } else {
 163                         if (rdev->pm.active_crtc_count > 1) {
 164                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 165                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 166                                                 continue;
 167                                         else if (i <= rdev->pm.current_power_state_index) {
 168                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 169                                                 break;
 170                                         } else {
 171                                                 rdev->pm.requested_power_state_index = i;
 172                                                 break;
 173                                         }
 174                                 }
 175                         } else
 176                                 rdev->pm.requested_power_state_index =
 177                                         rdev->pm.current_power_state_index + 1;
 178                 }
 179                 break;
 180         case DYNPM_ACTION_DEFAULT:
 181                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 182                 rdev->pm.dynpm_can_upclock = false;
 183                 break;
 184         case DYNPM_ACTION_NONE:
 185         default:
 186                 DRM_ERROR("Requested mode for not defined action\n");
 187                 return;
 188         }
 189         /* only one clock mode per power state */
 190         rdev->pm.requested_clock_mode_index = 0;
 191
 192         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 193                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 194                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 195                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 196                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 197                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 198                   pcie_lanes);
 199 }
 200
 201 void r100_pm_init_profile(struct radeon_device *rdev)
 202 {
 203         /* default */
 204         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 205         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 206         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 207         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 208         /* low sh */
 209         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 210         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 211         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 212         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 213         /* mid sh */
 214         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 215         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 216         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 217         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 218         /* high sh */
 219         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 220         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 221         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 222         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 223         /* low mh */
 224         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 225         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 226         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 227         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 228         /* mid mh */
 229         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 230         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 231         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 232         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 233         /* high mh */
 234         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 235         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 236         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 237         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 238 }
 239
 240 void r100_pm_misc(struct radeon_device *rdev)
 241 {
 242         int requested_index = rdev->pm.requested_power_state_index;
 243         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 244         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 245         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 246
 247         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 248                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 249                         tmp = RREG32(voltage->gpio.reg);
 250                         if (voltage->active_high)
 251                                 tmp |= voltage->gpio.mask;
 252                         else
 253                                 tmp &= ~(voltage->gpio.mask);
 254                         WREG32(voltage->gpio.reg, tmp);
 255                         if (voltage->delay)
 256                                 udelay(voltage->delay);
 257                 } else {
 258                         tmp = RREG32(voltage->gpio.reg);
 259                         if (voltage->active_high)
 260                                 tmp &= ~voltage->gpio.mask;
 261                         else
 262                                 tmp |= voltage->gpio.mask;
 263                         WREG32(voltage->gpio.reg, tmp);
 264                         if (voltage->delay)
 265                                 udelay(voltage->delay);
 266                 }
 267         }
 268
 269         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 270         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 271         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 272         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 273         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 274         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 275                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 276                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 277                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 278                 else
 279                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 280                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 281                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 282                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 283                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 284         } else
 285                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 286
 287         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 288                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 289                 if (voltage->delay) {
 290                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 291                         switch (voltage->delay) {
 292                         case 33:
 293                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 294                                 break;
 295                         case 66:
 296                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 297                                 break;
 298                         case 99:
 299                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 300                                 break;
 301                         case 132:
 302                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 303                                 break;
 304                         }
 305                 } else
 306                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 307         } else
 308                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 309
 310         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 311                 sclk_cntl &= ~FORCE_HDP;
 312         else
 313                 sclk_cntl |= FORCE_HDP;
 314
 315         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 316         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 317         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 318
 319         /* set pcie lanes */
 320         if ((rdev->flags & RADEON_IS_PCIE) &&
 321             !(rdev->flags & RADEON_IS_IGP) &&
 322             rdev->asic->set_pcie_lanes &&
 323             (ps->pcie_lanes !=
 324              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 325                 radeon_set_pcie_lanes(rdev,
 326                                       ps->pcie_lanes);
 327                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 328         }
 329 }
 330
 331 void r100_pm_prepare(struct radeon_device *rdev)
 332 {
 333         struct drm_device *ddev = rdev->ddev;
 334         struct drm_crtc *crtc;
 335         struct radeon_crtc *radeon_crtc;
 336         u32 tmp;
 337
 338         /* disable any active CRTCs */
 339         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 340                 radeon_crtc = to_radeon_crtc(crtc);
 341                 if (radeon_crtc->enabled) {
 342                         if (radeon_crtc->crtc_id) {
 343                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 344                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 345                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 346                         } else {
 347                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 348                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 349                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 350                         }
 351                 }
 352         }
 353 }
 354
 355 void r100_pm_finish(struct radeon_device *rdev)
 356 {
 357         struct drm_device *ddev = rdev->ddev;
 358         struct drm_crtc *crtc;
 359         struct radeon_crtc *radeon_crtc;
 360         u32 tmp;
 361
 362         /* enable any active CRTCs */
 363         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 364                 radeon_crtc = to_radeon_crtc(crtc);
 365                 if (radeon_crtc->enabled) {
 366                         if (radeon_crtc->crtc_id) {
 367                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 368                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 369                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 370                         } else {
 371                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 372                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 373                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 374                         }
 375                 }
 376         }
 377 }
 378
 379 bool r100_gui_idle(struct radeon_device *rdev)
 380 {
 381         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 382                 return false;
 383         else
 384                 return true;
 385 }
 386
 387 /* hpd for digital panel detect/disconnect */
 388 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 389 {
 390         bool connected = false;
 391
 392         switch (hpd) {
 393         case RADEON_HPD_1:
 394                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 395                         connected = true;
 396                 break;
 397         case RADEON_HPD_2:
 398                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 399                         connected = true;
 400                 break;
 401         default:
 402                 break;
 403         }
 404         return connected;
 405 }
 406
 407 void r100_hpd_set_polarity(struct radeon_device *rdev,
 408                            enum radeon_hpd_id hpd)
 409 {
 410         u32 tmp;
 411         bool connected = r100_hpd_sense(rdev, hpd);
 412
 413         switch (hpd) {
 414         case RADEON_HPD_1:
 415                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 416                 if (connected)
 417                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 418                 else
 419                         tmp |= RADEON_FP_DETECT_INT_POL;
 420                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 421                 break;
 422         case RADEON_HPD_2:
 423                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 424                 if (connected)
 425                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 426                 else
 427                         tmp |= RADEON_FP2_DETECT_INT_POL;
 428                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 429                 break;
 430         default:
 431                 break;
 432         }
 433 }
 434
 435 void r100_hpd_init(struct radeon_device *rdev)
 436 {
 437         struct drm_device *dev = rdev->ddev;
 438         struct drm_connector *connector;
 439
 440         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 441                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 442                 switch (radeon_connector->hpd.hpd) {
 443                 case RADEON_HPD_1:
 444                         rdev->irq.hpd[0] = true;
 445                         break;
 446                 case RADEON_HPD_2:
 447                         rdev->irq.hpd[1] = true;
 448                         break;
 449                 default:
 450                         break;
 451                 }
 452         }
 453         if (rdev->irq.installed)
 454                 r100_irq_set(rdev);
 455 }
 456
 457 void r100_hpd_fini(struct radeon_device *rdev)
 458 {
 459         struct drm_device *dev = rdev->ddev;
 460         struct drm_connector *connector;
 461
 462         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 463                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 464                 switch (radeon_connector->hpd.hpd) {
 465                 case RADEON_HPD_1:
 466                         rdev->irq.hpd[0] = false;
 467                         break;
 468                 case RADEON_HPD_2:
 469                         rdev->irq.hpd[1] = false;
 470                         break;
 471                 default:
 472                         break;
 473                 }
 474         }
 475 }
 476
 477 /*
 478  * PCI GART
 479  */
 480 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 481 {
 482         /* TODO: can we do somethings here ? */
 483         /* It seems hw only cache one entry so we should discard this
 484          * entry otherwise if first GPU GART read hit this entry it
 485          * could end up in wrong address. */
 486 }
 487
 488 int r100_pci_gart_init(struct radeon_device *rdev)
 489 {
 490         int r;
 491
 492         if (rdev->gart.table.ram.ptr) {
 493                 WARN(1, "R100 PCI GART already initialized\n");
 494                 return 0;
 495         }
 496         /* Initialize common gart structure */
 497         r = radeon_gart_init(rdev);
 498         if (r)
 499                 return r;
 500         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 501         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
 502         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
 503         return radeon_gart_table_ram_alloc(rdev);
 504 }
 505
 506 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 507 void r100_enable_bm(struct radeon_device *rdev)
 508 {
 509         uint32_t tmp;
 510         /* Enable bus mastering */
 511         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 512         WREG32(RADEON_BUS_CNTL, tmp);
 513 }
 514
 515 int r100_pci_gart_enable(struct radeon_device *rdev)
 516 {
 517         uint32_t tmp;
 518
 519         radeon_gart_restore(rdev);
 520         /* discard memory request outside of configured range */
 521         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 522         WREG32(RADEON_AIC_CNTL, tmp);
 523         /* set address range for PCI address translate */
 524         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 525         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 526         /* set PCI GART page-table base address */
 527         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 528         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 529         WREG32(RADEON_AIC_CNTL, tmp);
 530         r100_pci_gart_tlb_flush(rdev);
 531         rdev->gart.ready = true;
 532         return 0;
 533 }
 534
 535 void r100_pci_gart_disable(struct radeon_device *rdev)
 536 {
 537         uint32_t tmp;
 538
 539         /* discard memory request outside of configured range */
 540         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 541         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 542         WREG32(RADEON_AIC_LO_ADDR, 0);
 543         WREG32(RADEON_AIC_HI_ADDR, 0);
 544 }
 545
 546 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 547 {
 548         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 549                 return -EINVAL;
 550         }
 551         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
 552         return 0;
 553 }
 554
 555 void r100_pci_gart_fini(struct radeon_device *rdev)
 556 {
 557         radeon_gart_fini(rdev);
 558         r100_pci_gart_disable(rdev);
 559         radeon_gart_table_ram_free(rdev);
 560 }
 561
 562 int r100_irq_set(struct radeon_device *rdev)
 563 {
 564         uint32_t tmp = 0;
 565
 566         if (!rdev->irq.installed) {
 567                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 568                 WREG32(R_000040_GEN_INT_CNTL, 0);
 569                 return -EINVAL;
 570         }
 571         if (rdev->irq.sw_int) {
 572                 tmp |= RADEON_SW_INT_ENABLE;
 573         }
 574         if (rdev->irq.gui_idle) {
 575                 tmp |= RADEON_GUI_IDLE_MASK;
 576         }
 577         if (rdev->irq.crtc_vblank_int[0] ||
 578             rdev->irq.pflip[0]) {
 579                 tmp |= RADEON_CRTC_VBLANK_MASK;
 580         }
 581         if (rdev->irq.crtc_vblank_int[1] ||
 582             rdev->irq.pflip[1]) {
 583                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 584         }
 585         if (rdev->irq.hpd[0]) {
 586                 tmp |= RADEON_FP_DETECT_MASK;
 587         }
 588         if (rdev->irq.hpd[1]) {
 589                 tmp |= RADEON_FP2_DETECT_MASK;
 590         }
 591         WREG32(RADEON_GEN_INT_CNTL, tmp);
 592         return 0;
 593 }
 594
 595 void r100_irq_disable(struct radeon_device *rdev)
 596 {
 597         u32 tmp;
 598
 599         WREG32(R_000040_GEN_INT_CNTL, 0);
 600         /* Wait and acknowledge irq */
 601         mdelay(1);
 602         tmp = RREG32(R_000044_GEN_INT_STATUS);
 603         WREG32(R_000044_GEN_INT_STATUS, tmp);
 604 }
 605
 606 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
 607 {
 608         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 609         uint32_t irq_mask = RADEON_SW_INT_TEST |
 610                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 611                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 612
 613         /* the interrupt works, but the status bit is permanently asserted */
 614         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
 615                 if (!rdev->irq.gui_idle_acked)
 616                         irq_mask |= RADEON_GUI_IDLE_STAT;
 617         }
 618
 619         if (irqs) {
 620                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 621         }
 622         return irqs & irq_mask;
 623 }
 624
 625 int r100_irq_process(struct radeon_device *rdev)
 626 {
 627         uint32_t status, msi_rearm;
 628         bool queue_hotplug = false;
 629
 630         /* reset gui idle ack.  the status bit is broken */
 631         rdev->irq.gui_idle_acked = false;
 632
 633         status = r100_irq_ack(rdev);
 634         if (!status) {
 635                 return IRQ_NONE;
 636         }
 637         if (rdev->shutdown) {
 638                 return IRQ_NONE;
 639         }
 640         while (status) {
 641                 /* SW interrupt */
 642                 if (status & RADEON_SW_INT_TEST) {
 643                         radeon_fence_process(rdev);
 644                 }
 645                 /* gui idle interrupt */
 646                 if (status & RADEON_GUI_IDLE_STAT) {
 647                         rdev->irq.gui_idle_acked = true;
 648                         rdev->pm.gui_idle = true;
 649                         wake_up(&rdev->irq.idle_queue);
 650                 }
 651                 /* Vertical blank interrupts */
 652                 if (status & RADEON_CRTC_VBLANK_STAT) {
 653                         if (rdev->irq.crtc_vblank_int[0]) {
 654                                 drm_handle_vblank(rdev->ddev, 0);
 655                                 rdev->pm.vblank_sync = true;
 656                                 wake_up(&rdev->irq.vblank_queue);
 657                         }
 658                         if (rdev->irq.pflip[0])
 659                                 radeon_crtc_handle_flip(rdev, 0);
 660                 }
 661                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 662                         if (rdev->irq.crtc_vblank_int[1]) {
 663                                 drm_handle_vblank(rdev->ddev, 1);
 664                                 rdev->pm.vblank_sync = true;
 665                                 wake_up(&rdev->irq.vblank_queue);
 666                         }
 667                         if (rdev->irq.pflip[1])
 668                                 radeon_crtc_handle_flip(rdev, 1);
 669                 }
 670                 if (status & RADEON_FP_DETECT_STAT) {
 671                         queue_hotplug = true;
 672                         DRM_DEBUG("HPD1\n");
 673                 }
 674                 if (status & RADEON_FP2_DETECT_STAT) {
 675                         queue_hotplug = true;
 676                         DRM_DEBUG("HPD2\n");
 677                 }
 678                 status = r100_irq_ack(rdev);
 679         }
 680         /* reset gui idle ack.  the status bit is broken */
 681         rdev->irq.gui_idle_acked = false;
 682         if (queue_hotplug)
 683                 queue_work(rdev->wq, &rdev->hotplug_work);
 684         if (rdev->msi_enabled) {
 685                 switch (rdev->family) {
 686                 case CHIP_RS400:
 687                 case CHIP_RS480:
 688                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 689                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 690                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 691                         break;
 692                 default:
 693                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
 694                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
 695                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
 696                         break;
 697                 }
 698         }
 699         return IRQ_HANDLED;
 700 }
 701
 702 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 703 {
 704         if (crtc == 0)
 705                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 706         else
 707                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 708 }
 709
 710 /* Who ever call radeon_fence_emit should call ring_lock and ask
 711  * for enough space (today caller are ib schedule and buffer move) */
 712 void r100_fence_ring_emit(struct radeon_device *rdev,
 713                           struct radeon_fence *fence)
 714 {
 715         /* We have to make sure that caches are flushed before
 716          * CPU might read something from VRAM. */
 717         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 718         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
 719         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 720         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
 721         /* Wait until IDLE & CLEAN */
 722         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 723         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 724         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 725         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
 726                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 727         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 728         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
 729         /* Emit fence sequence & fire IRQ */
 730         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
 731         radeon_ring_write(rdev, fence->seq);
 732         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
 733         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
 734 }
 735
 736 int r100_copy_blit(struct radeon_device *rdev,
 737                    uint64_t src_offset,
 738                    uint64_t dst_offset,
 739                    unsigned num_pages,
 740                    struct radeon_fence *fence)
 741 {
 742         uint32_t cur_pages;
 743         uint32_t stride_bytes = PAGE_SIZE;
 744         uint32_t pitch;
 745         uint32_t stride_pixels;
 746         unsigned ndw;
 747         int num_loops;
 748         int r = 0;
 749
 750         /* radeon limited to 16k stride */
 751         stride_bytes &= 0x3fff;
 752         /* radeon pitch is /64 */
 753         pitch = stride_bytes / 64;
 754         stride_pixels = stride_bytes / 4;
 755         num_loops = DIV_ROUND_UP(num_pages, 8191);
 756
 757         /* Ask for enough room for blit + flush + fence */
 758         ndw = 64 + (10 * num_loops);
 759         r = radeon_ring_lock(rdev, ndw);
 760         if (r) {
 761                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 762                 return -EINVAL;
 763         }
 764         while (num_pages > 0) {
 765                 cur_pages = num_pages;
 766                 if (cur_pages > 8191) {
 767                         cur_pages = 8191;
 768                 }
 769                 num_pages -= cur_pages;
 770
 771                 /* pages are in Y direction - height
 772                    page width in X direction - width */
 773                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
 774                 radeon_ring_write(rdev,
 775                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 776                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 777                                   RADEON_GMC_SRC_CLIPPING |
 778                                   RADEON_GMC_DST_CLIPPING |
 779                                   RADEON_GMC_BRUSH_NONE |
 780                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 781                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 782                                   RADEON_ROP3_S |
 783                                   RADEON_DP_SRC_SOURCE_MEMORY |
 784                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 785                                   RADEON_GMC_WR_MSK_DIS);
 786                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
 787                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
 788                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 789                 radeon_ring_write(rdev, 0);
 790                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
 791                 radeon_ring_write(rdev, num_pages);
 792                 radeon_ring_write(rdev, num_pages);
 793                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
 794         }
 795         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 796         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
 797         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
 798         radeon_ring_write(rdev,
 799                           RADEON_WAIT_2D_IDLECLEAN |
 800                           RADEON_WAIT_HOST_IDLECLEAN |
 801                           RADEON_WAIT_DMA_GUI_IDLE);
 802         if (fence) {
 803                 r = radeon_fence_emit(rdev, fence);
 804         }
 805         radeon_ring_unlock_commit(rdev);
 806         return r;
 807 }
 808
 809 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 810 {
 811         unsigned i;
 812         u32 tmp;
 813
 814         for (i = 0; i < rdev->usec_timeout; i++) {
 815                 tmp = RREG32(R_000E40_RBBM_STATUS);
 816                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 817                         return 0;
 818                 }
 819                 udelay(1);
 820         }
 821         return -1;
 822 }
 823
 824 void r100_ring_start(struct radeon_device *rdev)
 825 {
 826         int r;
 827
 828         r = radeon_ring_lock(rdev, 2);
 829         if (r) {
 830                 return;
 831         }
 832         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
 833         radeon_ring_write(rdev,
 834                           RADEON_ISYNC_ANY2D_IDLE3D |
 835                           RADEON_ISYNC_ANY3D_IDLE2D |
 836                           RADEON_ISYNC_WAIT_IDLEGUI |
 837                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 838         radeon_ring_unlock_commit(rdev);
 839 }
 840
 841
 842 /* Load the microcode for the CP */
 843 static int r100_cp_init_microcode(struct radeon_device *rdev)
 844 {
 845         struct platform_device *pdev;
 846         const char *fw_name = NULL;
 847         int err;
 848
 849         DRM_DEBUG_KMS("\n");
 850
 851         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 852         err = IS_ERR(pdev);
 853         if (err) {
 854                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 855                 return -EINVAL;
 856         }
 857         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 858             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 859             (rdev->family == CHIP_RS200)) {
 860                 DRM_INFO("Loading R100 Microcode\n");
 861                 fw_name = FIRMWARE_R100;
 862         } else if ((rdev->family == CHIP_R200) ||
 863                    (rdev->family == CHIP_RV250) ||
 864                    (rdev->family == CHIP_RV280) ||
 865                    (rdev->family == CHIP_RS300)) {
 866                 DRM_INFO("Loading R200 Microcode\n");
 867                 fw_name = FIRMWARE_R200;
 868         } else if ((rdev->family == CHIP_R300) ||
 869                    (rdev->family == CHIP_R350) ||
 870                    (rdev->family == CHIP_RV350) ||
 871                    (rdev->family == CHIP_RV380) ||
 872                    (rdev->family == CHIP_RS400) ||
 873                    (rdev->family == CHIP_RS480)) {
 874                 DRM_INFO("Loading R300 Microcode\n");
 875                 fw_name = FIRMWARE_R300;
 876         } else if ((rdev->family == CHIP_R420) ||
 877                    (rdev->family == CHIP_R423) ||
 878                    (rdev->family == CHIP_RV410)) {
 879                 DRM_INFO("Loading R400 Microcode\n");
 880                 fw_name = FIRMWARE_R420;
 881         } else if ((rdev->family == CHIP_RS690) ||
 882                    (rdev->family == CHIP_RS740)) {
 883                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 884                 fw_name = FIRMWARE_RS690;
 885         } else if (rdev->family == CHIP_RS600) {
 886                 DRM_INFO("Loading RS600 Microcode\n");
 887                 fw_name = FIRMWARE_RS600;
 888         } else if ((rdev->family == CHIP_RV515) ||
 889                    (rdev->family == CHIP_R520) ||
 890                    (rdev->family == CHIP_RV530) ||
 891                    (rdev->family == CHIP_R580) ||
 892                    (rdev->family == CHIP_RV560) ||
 893                    (rdev->family == CHIP_RV570)) {
 894                 DRM_INFO("Loading R500 Microcode\n");
 895                 fw_name = FIRMWARE_R520;
 896         }
 897
 898         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 899         platform_device_unregister(pdev);
 900         if (err) {
 901                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
 902                        fw_name);
 903         } else if (rdev->me_fw->size % 8) {
 904                 printk(KERN_ERR
 905                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
 906                        rdev->me_fw->size, fw_name);
 907                 err = -EINVAL;
 908                 release_firmware(rdev->me_fw);
 909                 rdev->me_fw = NULL;
 910         }
 911         return err;
 912 }
 913
 914 static void r100_cp_load_microcode(struct radeon_device *rdev)
 915 {
 916         const __be32 *fw_data;
 917         int i, size;
 918
 919         if (r100_gui_wait_for_idle(rdev)) {
 920                 printk(KERN_WARNING "Failed to wait GUI idle while "
 921                        "programming pipes. Bad things might happen.\n");
 922         }
 923
 924         if (rdev->me_fw) {
 925                 size = rdev->me_fw->size / 4;
 926                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
 927                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
 928                 for (i = 0; i < size; i += 2) {
 929                         WREG32(RADEON_CP_ME_RAM_DATAH,
 930                                be32_to_cpup(&fw_data[i]));
 931                         WREG32(RADEON_CP_ME_RAM_DATAL,
 932                                be32_to_cpup(&fw_data[i + 1]));
 933                 }
 934         }
 935 }
 936
 937 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
 938 {
 939         unsigned rb_bufsz;
 940         unsigned rb_blksz;
 941         unsigned max_fetch;
 942         unsigned pre_write_timer;
 943         unsigned pre_write_limit;
 944         unsigned indirect2_start;
 945         unsigned indirect1_start;
 946         uint32_t tmp;
 947         int r;
 948
 949         if (r100_debugfs_cp_init(rdev)) {
 950                 DRM_ERROR("Failed to register debugfs file for CP !\n");
 951         }
 952         if (!rdev->me_fw) {
 953                 r = r100_cp_init_microcode(rdev);
 954                 if (r) {
 955                         DRM_ERROR("Failed to load firmware!\n");
 956                         return r;
 957                 }
 958         }
 959
 960         /* Align ring size */
 961         rb_bufsz = drm_order(ring_size / 8);
 962         ring_size = (1 << (rb_bufsz + 1)) * 4;
 963         r100_cp_load_microcode(rdev);
 964         r = radeon_ring_init(rdev, ring_size);
 965         if (r) {
 966                 return r;
 967         }
 968         /* Each time the cp read 1024 bytes (16 dword/quadword) update
 969          * the rptr copy in system ram */
 970         rb_blksz = 9;
 971         /* cp will read 128bytes at a time (4 dwords) */
 972         max_fetch = 1;
 973         rdev->cp.align_mask = 16 - 1;
 974         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
 975         pre_write_timer = 64;
 976         /* Force CP_RB_WPTR write if written more than one time before the
 977          * delay expire
 978          */
 979         pre_write_limit = 0;
 980         /* Setup the cp cache like this (cache size is 96 dwords) :
 981          *      RING            0  to 15
 982          *      INDIRECT1       16 to 79
 983          *      INDIRECT2       80 to 95
 984          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 985          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
 986          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
 987          * Idea being that most of the gpu cmd will be through indirect1 buffer
 988          * so it gets the bigger cache.
 989          */
 990         indirect2_start = 80;
 991         indirect1_start = 16;
 992         /* cp setup */
 993         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
 994         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
 995                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
 996                REG_SET(RADEON_MAX_FETCH, max_fetch));
 997 #ifdef __BIG_ENDIAN
 998         tmp |= RADEON_BUF_SWAP_32BIT;
 999 #endif
1000         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1001
1002         /* Set ring address */
1003         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1004         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1005         /* Force read & write ptr to 0 */
1006         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1007         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1008         WREG32(RADEON_CP_RB_WPTR, 0);
1009
1010         /* set the wb address whether it's enabled or not */
1011         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1012                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1013         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1014
1015         if (rdev->wb.enabled)
1016                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1017         else {
1018                 tmp |= RADEON_RB_NO_UPDATE;
1019                 WREG32(R_000770_SCRATCH_UMSK, 0);
1020         }
1021
1022         WREG32(RADEON_CP_RB_CNTL, tmp);
1023         udelay(10);
1024         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1025         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
1026         /* protect against crazy HW on resume */
1027         rdev->cp.wptr &= rdev->cp.ptr_mask;
1028         /* Set cp mode to bus mastering & enable cp*/
1029         WREG32(RADEON_CP_CSQ_MODE,
1030                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1031                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1032         WREG32(0x718, 0);
1033         WREG32(0x744, 0x00004D4D);
1034         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1035         radeon_ring_start(rdev);
1036         r = radeon_ring_test(rdev);
1037         if (r) {
1038                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1039                 return r;
1040         }
1041         rdev->cp.ready = true;
1042         rdev->mc.active_vram_size = rdev->mc.real_vram_size;
1043         return 0;
1044 }
1045
1046 void r100_cp_fini(struct radeon_device *rdev)
1047 {
1048         if (r100_cp_wait_for_idle(rdev)) {
1049                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1050         }
1051         /* Disable ring */
1052         r100_cp_disable(rdev);
1053         radeon_ring_fini(rdev);
1054         DRM_INFO("radeon: cp finalized\n");
1055 }
1056
1057 void r100_cp_disable(struct radeon_device *rdev)
1058 {
1059         /* Disable ring */
1060         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1061         rdev->cp.ready = false;
1062         WREG32(RADEON_CP_CSQ_MODE, 0);
1063         WREG32(RADEON_CP_CSQ_CNTL, 0);
1064         WREG32(R_000770_SCRATCH_UMSK, 0);
1065         if (r100_gui_wait_for_idle(rdev)) {
1066                 printk(KERN_WARNING "Failed to wait GUI idle while "
1067                        "programming pipes. Bad things might happen.\n");
1068         }
1069 }
1070
1071 void r100_cp_commit(struct radeon_device *rdev)
1072 {
1073         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1074         (void)RREG32(RADEON_CP_RB_WPTR);
1075 }
1076
1077
1078 /*
1079  * CS functions
1080  */
1081 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1082                           struct radeon_cs_packet *pkt,
1083                           const unsigned *auth, unsigned n,
1084                           radeon_packet0_check_t check)
1085 {
1086         unsigned reg;
1087         unsigned i, j, m;
1088         unsigned idx;
1089         int r;
1090
1091         idx = pkt->idx + 1;
1092         reg = pkt->reg;
1093         /* Check that register fall into register range
1094          * determined by the number of entry (n) in the
1095          * safe register bitmap.
1096          */
1097         if (pkt->one_reg_wr) {
1098                 if ((reg >> 7) > n) {
1099                         return -EINVAL;
1100                 }
1101         } else {
1102                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1103                         return -EINVAL;
1104                 }
1105         }
1106         for (i = 0; i <= pkt->count; i++, idx++) {
1107                 j = (reg >> 7);
1108                 m = 1 << ((reg >> 2) & 31);
1109                 if (auth[j] & m) {
1110                         r = check(p, pkt, idx, reg);
1111                         if (r) {
1112                                 return r;
1113                         }
1114                 }
1115                 if (pkt->one_reg_wr) {
1116                         if (!(auth[j] & m)) {
1117                                 break;
1118                         }
1119                 } else {
1120                         reg += 4;
1121                 }
1122         }
1123         return 0;
1124 }
1125
1126 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1127                          struct radeon_cs_packet *pkt)
1128 {
1129         volatile uint32_t *ib;
1130         unsigned i;
1131         unsigned idx;
1132
1133         ib = p->ib->ptr;
1134         idx = pkt->idx;
1135         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1136                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1137         }
1138 }
1139
1140 /**
1141  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1142  * @parser:     parser structure holding parsing context.
1143  * @pkt:        where to store packet informations
1144  *
1145  * Assume that chunk_ib_index is properly set. Will return -EINVAL
1146  * if packet is bigger than remaining ib size. or if packets is unknown.
1147  **/
1148 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1149                          struct radeon_cs_packet *pkt,
1150                          unsigned idx)
1151 {
1152         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1153         uint32_t header;
1154
1155         if (idx >= ib_chunk->length_dw) {
1156                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1157                           idx, ib_chunk->length_dw);
1158                 return -EINVAL;
1159         }
1160         header = radeon_get_ib_value(p, idx);
1161         pkt->idx = idx;
1162         pkt->type = CP_PACKET_GET_TYPE(header);
1163         pkt->count = CP_PACKET_GET_COUNT(header);
1164         switch (pkt->type) {
1165         case PACKET_TYPE0:
1166                 pkt->reg = CP_PACKET0_GET_REG(header);
1167                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1168                 break;
1169         case PACKET_TYPE3:
1170                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1171                 break;
1172         case PACKET_TYPE2:
1173                 pkt->count = -1;
1174                 break;
1175         default:
1176                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1177                 return -EINVAL;
1178         }
1179         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1180                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1181                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1182                 return -EINVAL;
1183         }
1184         return 0;
1185 }
1186
1187 /**
1188  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1189  * @parser:             parser structure holding parsing context.
1190  *
1191  * Userspace sends a special sequence for VLINE waits.
1192  * PACKET0 - VLINE_START_END + value
1193  * PACKET0 - WAIT_UNTIL +_value
1194  * RELOC (P3) - crtc_id in reloc.
1195  *
1196  * This function parses this and relocates the VLINE START END
1197  * and WAIT UNTIL packets to the correct crtc.
1198  * It also detects a switched off crtc and nulls out the
1199  * wait in that case.
1200  */
1201 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1202 {
1203         struct drm_mode_object *obj;
1204         struct drm_crtc *crtc;
1205         struct radeon_crtc *radeon_crtc;
1206         struct radeon_cs_packet p3reloc, waitreloc;
1207         int crtc_id;
1208         int r;
1209         uint32_t header, h_idx, reg;
1210         volatile uint32_t *ib;
1211
1212         ib = p->ib->ptr;
1213
1214         /* parse the wait until */
1215         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1216         if (r)
1217                 return r;
1218
1219         /* check its a wait until and only 1 count */
1220         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1221             waitreloc.count != 0) {
1222                 DRM_ERROR("vline wait had illegal wait until segment\n");
1223                 r = -EINVAL;
1224                 return r;
1225         }
1226
1227         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1228                 DRM_ERROR("vline wait had illegal wait until\n");
1229                 r = -EINVAL;
1230                 return r;
1231         }
1232
1233         /* jump over the NOP */
1234         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1235         if (r)
1236                 return r;
1237
1238         h_idx = p->idx - 2;
1239         p->idx += waitreloc.count + 2;
1240         p->idx += p3reloc.count + 2;
1241
1242         header = radeon_get_ib_value(p, h_idx);
1243         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1244         reg = CP_PACKET0_GET_REG(header);
1245         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1246         if (!obj) {
1247                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1248                 r = -EINVAL;
1249                 goto out;
1250         }
1251         crtc = obj_to_crtc(obj);
1252         radeon_crtc = to_radeon_crtc(crtc);
1253         crtc_id = radeon_crtc->crtc_id;
1254
1255         if (!crtc->enabled) {
1256                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1257                 ib[h_idx + 2] = PACKET2(0);
1258                 ib[h_idx + 3] = PACKET2(0);
1259         } else if (crtc_id == 1) {
1260                 switch (reg) {
1261                 case AVIVO_D1MODE_VLINE_START_END:
1262                         header &= ~R300_CP_PACKET0_REG_MASK;
1263                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1264                         break;
1265                 case RADEON_CRTC_GUI_TRIG_VLINE:
1266                         header &= ~R300_CP_PACKET0_REG_MASK;
1267                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1268                         break;
1269                 default:
1270                         DRM_ERROR("unknown crtc reloc\n");
1271                         r = -EINVAL;
1272                         goto out;
1273                 }
1274                 ib[h_idx] = header;
1275                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1276         }
1277 out:
1278         return r;
1279 }
1280
1281 /**
1282  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1283  * @parser:             parser structure holding parsing context.
1284  * @data:               pointer to relocation data
1285  * @offset_start:       starting offset
1286  * @offset_mask:        offset mask (to align start offset on)
1287  * @reloc:              reloc informations
1288  *
1289  * Check next packet is relocation packet3, do bo validation and compute
1290  * GPU offset using the provided start.
1291  **/
1292 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1293                               struct radeon_cs_reloc **cs_reloc)
1294 {
1295         struct radeon_cs_chunk *relocs_chunk;
1296         struct radeon_cs_packet p3reloc;
1297         unsigned idx;
1298         int r;
1299
1300         if (p->chunk_relocs_idx == -1) {
1301                 DRM_ERROR("No relocation chunk !\n");
1302                 return -EINVAL;
1303         }
1304         *cs_reloc = NULL;
1305         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1306         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1307         if (r) {
1308                 return r;
1309         }
1310         p->idx += p3reloc.count + 2;
1311         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1312                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1313                           p3reloc.idx);
1314                 r100_cs_dump_packet(p, &p3reloc);
1315                 return -EINVAL;
1316         }
1317         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1318         if (idx >= relocs_chunk->length_dw) {
1319                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1320                           idx, relocs_chunk->length_dw);
1321                 r100_cs_dump_packet(p, &p3reloc);
1322                 return -EINVAL;
1323         }
1324         /* FIXME: we assume reloc size is 4 dwords */
1325         *cs_reloc = p->relocs_ptr[(idx / 4)];
1326         return 0;
1327 }
1328
1329 static int r100_get_vtx_size(uint32_t vtx_fmt)
1330 {
1331         int vtx_size;
1332         vtx_size = 2;
1333         /* ordered according to bits in spec */
1334         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1335                 vtx_size++;
1336         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1337                 vtx_size += 3;
1338         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1339                 vtx_size++;
1340         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1341                 vtx_size++;
1342         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1343                 vtx_size += 3;
1344         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1345                 vtx_size++;
1346         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1347                 vtx_size++;
1348         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1349                 vtx_size += 2;
1350         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1351                 vtx_size += 2;
1352         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1353                 vtx_size++;
1354         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1355                 vtx_size += 2;
1356         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1357                 vtx_size++;
1358         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1359                 vtx_size += 2;
1360         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1361                 vtx_size++;
1362         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1363                 vtx_size++;
1364         /* blend weight */
1365         if (vtx_fmt & (0x7 << 15))
1366                 vtx_size += (vtx_fmt >> 15) & 0x7;
1367         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1368                 vtx_size += 3;
1369         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1370                 vtx_size += 2;
1371         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1372                 vtx_size++;
1373         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1374                 vtx_size++;
1375         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1376                 vtx_size++;
1377         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1378                 vtx_size++;
1379         return vtx_size;
1380 }
1381
1382 static int r100_packet0_check(struct radeon_cs_parser *p,
1383                               struct radeon_cs_packet *pkt,
1384                               unsigned idx, unsigned reg)
1385 {
1386         struct radeon_cs_reloc *reloc;
1387         struct r100_cs_track *track;
1388         volatile uint32_t *ib;
1389         uint32_t tmp;
1390         int r;
1391         int i, face;
1392         u32 tile_flags = 0;
1393         u32 idx_value;
1394
1395         ib = p->ib->ptr;
1396         track = (struct r100_cs_track *)p->track;
1397
1398         idx_value = radeon_get_ib_value(p, idx);
1399
1400         switch (reg) {
1401         case RADEON_CRTC_GUI_TRIG_VLINE:
1402                 r = r100_cs_packet_parse_vline(p);
1403                 if (r) {
1404                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1405                                   idx, reg);
1406                         r100_cs_dump_packet(p, pkt);
1407                         return r;
1408                 }
1409                 break;
1410                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1411                  * range access */
1412         case RADEON_DST_PITCH_OFFSET:
1413         case RADEON_SRC_PITCH_OFFSET:
1414                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1415                 if (r)
1416                         return r;
1417                 break;
1418         case RADEON_RB3D_DEPTHOFFSET:
1419                 r = r100_cs_packet_next_reloc(p, &reloc);
1420                 if (r) {
1421                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1422                                   idx, reg);
1423                         r100_cs_dump_packet(p, pkt);
1424                         return r;
1425                 }
1426                 track->zb.robj = reloc->robj;
1427                 track->zb.offset = idx_value;
1428                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1429                 break;
1430         case RADEON_RB3D_COLOROFFSET:
1431                 r = r100_cs_packet_next_reloc(p, &reloc);
1432                 if (r) {
1433                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1434                                   idx, reg);
1435                         r100_cs_dump_packet(p, pkt);
1436                         return r;
1437                 }
1438                 track->cb[0].robj = reloc->robj;
1439                 track->cb[0].offset = idx_value;
1440                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1441                 break;
1442         case RADEON_PP_TXOFFSET_0:
1443         case RADEON_PP_TXOFFSET_1:
1444         case RADEON_PP_TXOFFSET_2:
1445                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1446                 r = r100_cs_packet_next_reloc(p, &reloc);
1447                 if (r) {
1448                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1449                                   idx, reg);
1450                         r100_cs_dump_packet(p, pkt);
1451                         return r;
1452                 }
1453                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1454                 track->textures[i].robj = reloc->robj;
1455                 break;
1456         case RADEON_PP_CUBIC_OFFSET_T0_0:
1457         case RADEON_PP_CUBIC_OFFSET_T0_1:
1458         case RADEON_PP_CUBIC_OFFSET_T0_2:
1459         case RADEON_PP_CUBIC_OFFSET_T0_3:
1460         case RADEON_PP_CUBIC_OFFSET_T0_4:
1461                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1462                 r = r100_cs_packet_next_reloc(p, &reloc);
1463                 if (r) {
1464                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1465                                   idx, reg);
1466                         r100_cs_dump_packet(p, pkt);
1467                         return r;
1468                 }
1469                 track->textures[0].cube_info[i].offset = idx_value;
1470                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1471                 track->textures[0].cube_info[i].robj = reloc->robj;
1472                 break;
1473         case RADEON_PP_CUBIC_OFFSET_T1_0:
1474         case RADEON_PP_CUBIC_OFFSET_T1_1:
1475         case RADEON_PP_CUBIC_OFFSET_T1_2:
1476         case RADEON_PP_CUBIC_OFFSET_T1_3:
1477         case RADEON_PP_CUBIC_OFFSET_T1_4:
1478                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1479                 r = r100_cs_packet_next_reloc(p, &reloc);
1480                 if (r) {
1481                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1482                                   idx, reg);
1483                         r100_cs_dump_packet(p, pkt);
1484                         return r;
1485                 }
1486                 track->textures[1].cube_info[i].offset = idx_value;
1487                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1488                 track->textures[1].cube_info[i].robj = reloc->robj;
1489                 break;
1490         case RADEON_PP_CUBIC_OFFSET_T2_0:
1491         case RADEON_PP_CUBIC_OFFSET_T2_1:
1492         case RADEON_PP_CUBIC_OFFSET_T2_2:
1493         case RADEON_PP_CUBIC_OFFSET_T2_3:
1494         case RADEON_PP_CUBIC_OFFSET_T2_4:
1495                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1496                 r = r100_cs_packet_next_reloc(p, &reloc);
1497                 if (r) {
1498                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1499                                   idx, reg);
1500                         r100_cs_dump_packet(p, pkt);
1501                         return r;
1502                 }
1503                 track->textures[2].cube_info[i].offset = idx_value;
1504                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1505                 track->textures[2].cube_info[i].robj = reloc->robj;
1506                 break;
1507         case RADEON_RE_WIDTH_HEIGHT:
1508                 track->maxy = ((idx_value >> 16) & 0x7FF);
1509                 break;
1510         case RADEON_RB3D_COLORPITCH:
1511                 r = r100_cs_packet_next_reloc(p, &reloc);
1512                 if (r) {
1513                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1514                                   idx, reg);
1515                         r100_cs_dump_packet(p, pkt);
1516                         return r;
1517                 }
1518
1519                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1520                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1521                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1522                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1523
1524                 tmp = idx_value & ~(0x7 << 16);
1525                 tmp |= tile_flags;
1526                 ib[idx] = tmp;
1527
1528                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1529                 break;
1530         case RADEON_RB3D_DEPTHPITCH:
1531                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1532                 break;
1533         case RADEON_RB3D_CNTL:
1534                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1535                 case 7:
1536                 case 8:
1537                 case 9:
1538                 case 11:
1539                 case 12:
1540                         track->cb[0].cpp = 1;
1541                         break;
1542                 case 3:
1543                 case 4:
1544                 case 15:
1545                         track->cb[0].cpp = 2;
1546                         break;
1547                 case 6:
1548                         track->cb[0].cpp = 4;
1549                         break;
1550                 default:
1551                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1552                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1553                         return -EINVAL;
1554                 }
1555                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1556                 break;
1557         case RADEON_RB3D_ZSTENCILCNTL:
1558                 switch (idx_value & 0xf) {
1559                 case 0:
1560                         track->zb.cpp = 2;
1561                         break;
1562                 case 2:
1563                 case 3:
1564                 case 4:
1565                 case 5:
1566                 case 9:
1567                 case 11:
1568                         track->zb.cpp = 4;
1569                         break;
1570                 default:
1571                         break;
1572                 }
1573                 break;
1574         case RADEON_RB3D_ZPASS_ADDR:
1575                 r = r100_cs_packet_next_reloc(p, &reloc);
1576                 if (r) {
1577                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1578                                   idx, reg);
1579                         r100_cs_dump_packet(p, pkt);
1580                         return r;
1581                 }
1582                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1583                 break;
1584         case RADEON_PP_CNTL:
1585                 {
1586                         uint32_t temp = idx_value >> 4;
1587                         for (i = 0; i < track->num_texture; i++)
1588                                 track->textures[i].enabled = !!(temp & (1 << i));
1589                 }
1590                 break;
1591         case RADEON_SE_VF_CNTL:
1592                 track->vap_vf_cntl = idx_value;
1593                 break;
1594         case RADEON_SE_VTX_FMT:
1595                 track->vtx_size = r100_get_vtx_size(idx_value);
1596                 break;
1597         case RADEON_PP_TEX_SIZE_0:
1598         case RADEON_PP_TEX_SIZE_1:
1599         case RADEON_PP_TEX_SIZE_2:
1600                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1601                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1602                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1603                 break;
1604         case RADEON_PP_TEX_PITCH_0:
1605         case RADEON_PP_TEX_PITCH_1:
1606         case RADEON_PP_TEX_PITCH_2:
1607                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1608                 track->textures[i].pitch = idx_value + 32;
1609                 break;
1610         case RADEON_PP_TXFILTER_0:
1611         case RADEON_PP_TXFILTER_1:
1612         case RADEON_PP_TXFILTER_2:
1613                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1614                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1615                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1616                 tmp = (idx_value >> 23) & 0x7;
1617                 if (tmp == 2 || tmp == 6)
1618                         track->textures[i].roundup_w = false;
1619                 tmp = (idx_value >> 27) & 0x7;
1620                 if (tmp == 2 || tmp == 6)
1621                         track->textures[i].roundup_h = false;
1622                 break;
1623         case RADEON_PP_TXFORMAT_0:
1624         case RADEON_PP_TXFORMAT_1:
1625         case RADEON_PP_TXFORMAT_2:
1626                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1627                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1628                         track->textures[i].use_pitch = 1;
1629                 } else {
1630                         track->textures[i].use_pitch = 0;
1631                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1632                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1633                 }
1634                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1635                         track->textures[i].tex_coord_type = 2;
1636                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1637                 case RADEON_TXFORMAT_I8:
1638                 case RADEON_TXFORMAT_RGB332:
1639                 case RADEON_TXFORMAT_Y8:
1640                         track->textures[i].cpp = 1;
1641                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1642                         break;
1643                 case RADEON_TXFORMAT_AI88:
1644                 case RADEON_TXFORMAT_ARGB1555:
1645                 case RADEON_TXFORMAT_RGB565:
1646                 case RADEON_TXFORMAT_ARGB4444:
1647                 case RADEON_TXFORMAT_VYUY422:
1648                 case RADEON_TXFORMAT_YVYU422:
1649                 case RADEON_TXFORMAT_SHADOW16:
1650                 case RADEON_TXFORMAT_LDUDV655:
1651                 case RADEON_TXFORMAT_DUDV88:
1652                         track->textures[i].cpp = 2;
1653                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1654                         break;
1655                 case RADEON_TXFORMAT_ARGB8888:
1656                 case RADEON_TXFORMAT_RGBA8888:
1657                 case RADEON_TXFORMAT_SHADOW32:
1658                 case RADEON_TXFORMAT_LDUDUV8888:
1659                         track->textures[i].cpp = 4;
1660                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1661                         break;
1662                 case RADEON_TXFORMAT_DXT1:
1663                         track->textures[i].cpp = 1;
1664                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1665                         break;
1666                 case RADEON_TXFORMAT_DXT23:
1667                 case RADEON_TXFORMAT_DXT45:
1668                         track->textures[i].cpp = 1;
1669                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1670                         break;
1671                 }
1672                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1673                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1674                 break;
1675         case RADEON_PP_CUBIC_FACES_0:
1676         case RADEON_PP_CUBIC_FACES_1:
1677         case RADEON_PP_CUBIC_FACES_2:
1678                 tmp = idx_value;
1679                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1680                 for (face = 0; face < 4; face++) {
1681                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1682                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1683                 }
1684                 break;
1685         default:
1686                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1687                        reg, idx);
1688                 return -EINVAL;
1689         }
1690         return 0;
1691 }
1692
1693 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1694                                          struct radeon_cs_packet *pkt,
1695                                          struct radeon_bo *robj)
1696 {
1697         unsigned idx;
1698         u32 value;
1699         idx = pkt->idx + 1;
1700         value = radeon_get_ib_value(p, idx + 2);
1701         if ((value + 1) > radeon_bo_size(robj)) {
1702                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1703                           "(need %u have %lu) !\n",
1704                           value + 1,
1705                           radeon_bo_size(robj));
1706                 return -EINVAL;
1707         }
1708         return 0;
1709 }
1710
1711 static int r100_packet3_check(struct radeon_cs_parser *p,
1712                               struct radeon_cs_packet *pkt)
1713 {
1714         struct radeon_cs_reloc *reloc;
1715         struct r100_cs_track *track;
1716         unsigned idx;
1717         volatile uint32_t *ib;
1718         int r;
1719
1720         ib = p->ib->ptr;
1721         idx = pkt->idx + 1;
1722         track = (struct r100_cs_track *)p->track;
1723         switch (pkt->opcode) {
1724         case PACKET3_3D_LOAD_VBPNTR:
1725                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1726                 if (r)
1727                         return r;
1728                 break;
1729         case PACKET3_INDX_BUFFER:
1730                 r = r100_cs_packet_next_reloc(p, &reloc);
1731                 if (r) {
1732                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1733                         r100_cs_dump_packet(p, pkt);
1734                         return r;
1735                 }
1736                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1737                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1738                 if (r) {
1739                         return r;
1740                 }
1741                 break;
1742         case 0x23:
1743                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1744                 r = r100_cs_packet_next_reloc(p, &reloc);
1745                 if (r) {
1746                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1747                         r100_cs_dump_packet(p, pkt);
1748                         return r;
1749                 }
1750                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1751                 track->num_arrays = 1;
1752                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1753
1754                 track->arrays[0].robj = reloc->robj;
1755                 track->arrays[0].esize = track->vtx_size;
1756
1757                 track->max_indx = radeon_get_ib_value(p, idx+1);
1758
1759                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1760                 track->immd_dwords = pkt->count - 1;
1761                 r = r100_cs_track_check(p->rdev, track);
1762                 if (r)
1763                         return r;
1764                 break;
1765         case PACKET3_3D_DRAW_IMMD:
1766                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1767                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1768                         return -EINVAL;
1769                 }
1770                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1771                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1772                 track->immd_dwords = pkt->count - 1;
1773                 r = r100_cs_track_check(p->rdev, track);
1774                 if (r)
1775                         return r;
1776                 break;
1777                 /* triggers drawing using in-packet vertex data */
1778         case PACKET3_3D_DRAW_IMMD_2:
1779                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1780                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1781                         return -EINVAL;
1782                 }
1783                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1784                 track->immd_dwords = pkt->count;
1785                 r = r100_cs_track_check(p->rdev, track);
1786                 if (r)
1787                         return r;
1788                 break;
1789                 /* triggers drawing using in-packet vertex data */
1790         case PACKET3_3D_DRAW_VBUF_2:
1791                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1792                 r = r100_cs_track_check(p->rdev, track);
1793                 if (r)
1794                         return r;
1795                 break;
1796                 /* triggers drawing of vertex buffers setup elsewhere */
1797         case PACKET3_3D_DRAW_INDX_2:
1798                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1799                 r = r100_cs_track_check(p->rdev, track);
1800                 if (r)
1801                         return r;
1802                 break;
1803                 /* triggers drawing using indices to vertex buffer */
1804         case PACKET3_3D_DRAW_VBUF:
1805                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1806                 r = r100_cs_track_check(p->rdev, track);
1807                 if (r)
1808                         return r;
1809                 break;
1810                 /* triggers drawing of vertex buffers setup elsewhere */
1811         case PACKET3_3D_DRAW_INDX:
1812                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1813                 r = r100_cs_track_check(p->rdev, track);
1814                 if (r)
1815                         return r;
1816                 break;
1817                 /* triggers drawing using indices to vertex buffer */
1818         case PACKET3_3D_CLEAR_HIZ:
1819         case PACKET3_3D_CLEAR_ZMASK:
1820                 if (p->rdev->hyperz_filp != p->filp)
1821                         return -EINVAL;
1822                 break;
1823         case PACKET3_NOP:
1824                 break;
1825         default:
1826                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1827                 return -EINVAL;
1828         }
1829         return 0;
1830 }
1831
1832 int r100_cs_parse(struct radeon_cs_parser *p)
1833 {
1834         struct radeon_cs_packet pkt;
1835         struct r100_cs_track *track;
1836         int r;
1837
1838         track = kzalloc(sizeof(*track), GFP_KERNEL);
1839         r100_cs_track_clear(p->rdev, track);
1840         p->track = track;
1841         do {
1842                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1843                 if (r) {
1844                         return r;
1845                 }
1846                 p->idx += pkt.count + 2;
1847                 switch (pkt.type) {
1848                         case PACKET_TYPE0:
1849                                 if (p->rdev->family >= CHIP_R200)
1850                                         r = r100_cs_parse_packet0(p, &pkt,
1851                                                                   p->rdev->config.r100.reg_safe_bm,
1852                                                                   p->rdev->config.r100.reg_safe_bm_size,
1853                                                                   &r200_packet0_check);
1854                                 else
1855                                         r = r100_cs_parse_packet0(p, &pkt,
1856                                                                   p->rdev->config.r100.reg_safe_bm,
1857                                                                   p->rdev->config.r100.reg_safe_bm_size,
1858                                                                   &r100_packet0_check);
1859                                 break;
1860                         case PACKET_TYPE2:
1861                                 break;
1862                         case PACKET_TYPE3:
1863                                 r = r100_packet3_check(p, &pkt);
1864                                 break;
1865                         default:
1866                                 DRM_ERROR("Unknown packet type %d !\n",
1867                                           pkt.type);
1868                                 return -EINVAL;
1869                 }
1870                 if (r) {
1871                         return r;
1872                 }
1873         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1874         return 0;
1875 }
1876
1877
1878 /*
1879  * Global GPU functions
1880  */
1881 void r100_errata(struct radeon_device *rdev)
1882 {
1883         rdev->pll_errata = 0;
1884
1885         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1886                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1887         }
1888
1889         if (rdev->family == CHIP_RV100 ||
1890             rdev->family == CHIP_RS100 ||
1891             rdev->family == CHIP_RS200) {
1892                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1893         }
1894 }
1895
1896 /* Wait for vertical sync on primary CRTC */
1897 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1898 {
1899         uint32_t crtc_gen_cntl, tmp;
1900         int i;
1901
1902         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1903         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1904             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1905                 return;
1906         }
1907         /* Clear the CRTC_VBLANK_SAVE bit */
1908         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1909         for (i = 0; i < rdev->usec_timeout; i++) {
1910                 tmp = RREG32(RADEON_CRTC_STATUS);
1911                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1912                         return;
1913                 }
1914                 DRM_UDELAY(1);
1915         }
1916 }
1917
1918 /* Wait for vertical sync on secondary CRTC */
1919 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1920 {
1921         uint32_t crtc2_gen_cntl, tmp;
1922         int i;
1923
1924         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1925         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1926             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1927                 return;
1928
1929         /* Clear the CRTC_VBLANK_SAVE bit */
1930         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1931         for (i = 0; i < rdev->usec_timeout; i++) {
1932                 tmp = RREG32(RADEON_CRTC2_STATUS);
1933                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1934                         return;
1935                 }
1936                 DRM_UDELAY(1);
1937         }
1938 }
1939
1940 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1941 {
1942         unsigned i;
1943         uint32_t tmp;
1944
1945         for (i = 0; i < rdev->usec_timeout; i++) {
1946                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1947                 if (tmp >= n) {
1948                         return 0;
1949                 }
1950                 DRM_UDELAY(1);
1951         }
1952         return -1;
1953 }
1954
1955 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1956 {
1957         unsigned i;
1958         uint32_t tmp;
1959
1960         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1961                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1962                        " Bad things might happen.\n");
1963         }
1964         for (i = 0; i < rdev->usec_timeout; i++) {
1965                 tmp = RREG32(RADEON_RBBM_STATUS);
1966                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1967                         return 0;
1968                 }
1969                 DRM_UDELAY(1);
1970         }
1971         return -1;
1972 }
1973
1974 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1975 {
1976         unsigned i;
1977         uint32_t tmp;
1978
1979         for (i = 0; i < rdev->usec_timeout; i++) {
1980                 /* read MC_STATUS */
1981                 tmp = RREG32(RADEON_MC_STATUS);
1982                 if (tmp & RADEON_MC_IDLE) {
1983                         return 0;
1984                 }
1985                 DRM_UDELAY(1);
1986         }
1987         return -1;
1988 }
1989
1990 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1991 {
1992         lockup->last_cp_rptr = cp->rptr;
1993         lockup->last_jiffies = jiffies;
1994 }
1995
1996 /**
1997  * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
1998  * @rdev:       radeon device structure
1999  * @lockup:     r100_gpu_lockup structure holding CP lockup tracking informations
2000  * @cp:         radeon_cp structure holding CP information
2001  *
2002  * We don't need to initialize the lockup tracking information as we will either
2003  * have CP rptr to a different value of jiffies wrap around which will force
2004  * initialization of the lockup tracking informations.
2005  *
2006  * A possible false positivie is if we get call after while and last_cp_rptr ==
2007  * the current CP rptr, even if it's unlikely it might happen. To avoid this
2008  * if the elapsed time since last call is bigger than 2 second than we return
2009  * false and update the tracking information. Due to this the caller must call
2010  * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2011  * the fencing code should be cautious about that.
2012  *
2013  * Caller should write to the ring to force CP to do something so we don't get
2014  * false positive when CP is just gived nothing to do.
2015  *
2016  **/
2017 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2018 {
2019         unsigned long cjiffies, elapsed;
2020
2021         cjiffies = jiffies;
2022         if (!time_after(cjiffies, lockup->last_jiffies)) {
2023                 /* likely a wrap around */
2024                 lockup->last_cp_rptr = cp->rptr;
2025                 lockup->last_jiffies = jiffies;
2026                 return false;
2027         }
2028         if (cp->rptr != lockup->last_cp_rptr) {
2029                 /* CP is still working no lockup */
2030                 lockup->last_cp_rptr = cp->rptr;
2031                 lockup->last_jiffies = jiffies;
2032                 return false;
2033         }
2034         elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2035         if (elapsed >= 10000) {
2036                 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2037                 return true;
2038         }
2039         /* give a chance to the GPU ... */
2040         return false;
2041 }
2042
2043 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2044 {
2045         u32 rbbm_status;
2046         int r;
2047
2048         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2049         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2050                 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2051                 return false;
2052         }
2053         /* force CP activities */
2054         r = radeon_ring_lock(rdev, 2);
2055         if (!r) {
2056                 /* PACKET2 NOP */
2057                 radeon_ring_write(rdev, 0x80000000);
2058                 radeon_ring_write(rdev, 0x80000000);
2059                 radeon_ring_unlock_commit(rdev);
2060         }
2061         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2062         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2063 }
2064
2065 void r100_bm_disable(struct radeon_device *rdev)
2066 {
2067         u32 tmp;
2068
2069         /* disable bus mastering */
2070         tmp = RREG32(R_000030_BUS_CNTL);
2071         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2072         mdelay(1);
2073         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2074         mdelay(1);
2075         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2076         tmp = RREG32(RADEON_BUS_CNTL);
2077         mdelay(1);
2078         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
2079         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
2080         mdelay(1);
2081 }
2082
2083 int r100_asic_reset(struct radeon_device *rdev)
2084 {
2085         struct r100_mc_save save;
2086         u32 status, tmp;
2087
2088         r100_mc_stop(rdev, &save);
2089         status = RREG32(R_000E40_RBBM_STATUS);
2090         if (!G_000E40_GUI_ACTIVE(status)) {
2091                 return 0;
2092         }
2093         status = RREG32(R_000E40_RBBM_STATUS);
2094         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2095         /* stop CP */
2096         WREG32(RADEON_CP_CSQ_CNTL, 0);
2097         tmp = RREG32(RADEON_CP_RB_CNTL);
2098         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2099         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2100         WREG32(RADEON_CP_RB_WPTR, 0);
2101         WREG32(RADEON_CP_RB_CNTL, tmp);
2102         /* save PCI state */
2103         pci_save_state(rdev->pdev);
2104         /* disable bus mastering */
2105         r100_bm_disable(rdev);
2106         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2107                                         S_0000F0_SOFT_RESET_RE(1) |
2108                                         S_0000F0_SOFT_RESET_PP(1) |
2109                                         S_0000F0_SOFT_RESET_RB(1));
2110         RREG32(R_0000F0_RBBM_SOFT_RESET);
2111         mdelay(500);
2112         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2113         mdelay(1);
2114         status = RREG32(R_000E40_RBBM_STATUS);
2115         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2116         /* reset CP */
2117         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2118         RREG32(R_0000F0_RBBM_SOFT_RESET);
2119         mdelay(500);
2120         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2121         mdelay(1);
2122         status = RREG32(R_000E40_RBBM_STATUS);
2123         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2124         /* restore PCI & busmastering */
2125         pci_restore_state(rdev->pdev);
2126         r100_enable_bm(rdev);
2127         /* Check if GPU is idle */
2128         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2129                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2130                 dev_err(rdev->dev, "failed to reset GPU\n");
2131                 rdev->gpu_lockup = true;
2132                 return -1;
2133         }
2134         r100_mc_resume(rdev, &save);
2135         dev_info(rdev->dev, "GPU reset succeed\n");
2136         return 0;
2137 }
2138
2139 void r100_set_common_regs(struct radeon_device *rdev)
2140 {
2141         struct drm_device *dev = rdev->ddev;
2142         bool force_dac2 = false;
2143         u32 tmp;
2144
2145         /* set these so they don't interfere with anything */
2146         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2147         WREG32(RADEON_SUBPIC_CNTL, 0);
2148         WREG32(RADEON_VIPH_CONTROL, 0);
2149         WREG32(RADEON_I2C_CNTL_1, 0);
2150         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2151         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2152         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2153
2154         /* always set up dac2 on rn50 and some rv100 as lots
2155          * of servers seem to wire it up to a VGA port but
2156          * don't report it in the bios connector
2157          * table.
2158          */
2159         switch (dev->pdev->device) {
2160                 /* RN50 */
2161         case 0x515e:
2162         case 0x5969:
2163                 force_dac2 = true;
2164                 break;
2165                 /* RV100*/
2166         case 0x5159:
2167         case 0x515a:
2168                 /* DELL triple head servers */
2169                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2170                     ((dev->pdev->subsystem_device == 0x016c) ||
2171                      (dev->pdev->subsystem_device == 0x016d) ||
2172                      (dev->pdev->subsystem_device == 0x016e) ||
2173                      (dev->pdev->subsystem_device == 0x016f) ||
2174                      (dev->pdev->subsystem_device == 0x0170) ||
2175                      (dev->pdev->subsystem_device == 0x017d) ||
2176                      (dev->pdev->subsystem_device == 0x017e) ||
2177                      (dev->pdev->subsystem_device == 0x0183) ||
2178                      (dev->pdev->subsystem_device == 0x018a) ||
2179                      (dev->pdev->subsystem_device == 0x019a)))
2180                         force_dac2 = true;
2181                 break;
2182         }
2183
2184         if (force_dac2) {
2185                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2186                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2187                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2188
2189                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2190                    enable it, even it's detected.
2191                 */
2192
2193                 /* force it to crtc0 */
2194                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2195                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2196                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2197
2198                 /* set up the TV DAC */
2199                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2200                                  RADEON_TV_DAC_STD_MASK |
2201                                  RADEON_TV_DAC_RDACPD |
2202                                  RADEON_TV_DAC_GDACPD |
2203                                  RADEON_TV_DAC_BDACPD |
2204                                  RADEON_TV_DAC_BGADJ_MASK |
2205                                  RADEON_TV_DAC_DACADJ_MASK);
2206                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2207                                 RADEON_TV_DAC_NHOLD |
2208                                 RADEON_TV_DAC_STD_PS2 |
2209                                 (0x58 << 16));
2210
2211                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2212                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2213                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2214         }
2215
2216         /* switch PM block to ACPI mode */
2217         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2218         tmp &= ~RADEON_PM_MODE_SEL;
2219         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2220
2221 }
2222
2223 /*
2224  * VRAM info
2225  */
2226 static void r100_vram_get_type(struct radeon_device *rdev)
2227 {
2228         uint32_t tmp;
2229
2230         rdev->mc.vram_is_ddr = false;
2231         if (rdev->flags & RADEON_IS_IGP)
2232                 rdev->mc.vram_is_ddr = true;
2233         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2234                 rdev->mc.vram_is_ddr = true;
2235         if ((rdev->family == CHIP_RV100) ||
2236             (rdev->family == CHIP_RS100) ||
2237             (rdev->family == CHIP_RS200)) {
2238                 tmp = RREG32(RADEON_MEM_CNTL);
2239                 if (tmp & RV100_HALF_MODE) {
2240                         rdev->mc.vram_width = 32;
2241                 } else {
2242                         rdev->mc.vram_width = 64;
2243                 }
2244                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2245                         rdev->mc.vram_width /= 4;
2246                         rdev->mc.vram_is_ddr = true;
2247                 }
2248         } else if (rdev->family <= CHIP_RV280) {
2249                 tmp = RREG32(RADEON_MEM_CNTL);
2250                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2251                         rdev->mc.vram_width = 128;
2252                 } else {
2253                         rdev->mc.vram_width = 64;
2254                 }
2255         } else {
2256                 /* newer IGPs */
2257                 rdev->mc.vram_width = 128;
2258         }
2259 }
2260
2261 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2262 {
2263         u32 aper_size;
2264         u8 byte;
2265
2266         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2267
2268         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2269          * that is has the 2nd generation multifunction PCI interface
2270          */
2271         if (rdev->family == CHIP_RV280 ||
2272             rdev->family >= CHIP_RV350) {
2273                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2274                        ~RADEON_HDP_APER_CNTL);
2275                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2276                 return aper_size * 2;
2277         }
2278
2279         /* Older cards have all sorts of funny issues to deal with. First
2280          * check if it's a multifunction card by reading the PCI config
2281          * header type... Limit those to one aperture size
2282          */
2283         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2284         if (byte & 0x80) {
2285                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2286                 DRM_INFO("Limiting VRAM to one aperture\n");
2287                 return aper_size;
2288         }
2289
2290         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2291          * have set it up. We don't write this as it's broken on some ASICs but
2292          * we expect the BIOS to have done the right thing (might be too optimistic...)
2293          */
2294         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2295                 return aper_size * 2;
2296         return aper_size;
2297 }
2298
2299 void r100_vram_init_sizes(struct radeon_device *rdev)
2300 {
2301         u64 config_aper_size;
2302
2303         /* work out accessible VRAM */
2304         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2305         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2306         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2307         /* FIXME we don't use the second aperture yet when we could use it */
2308         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2309                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2310         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2311         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2312         if (rdev->flags & RADEON_IS_IGP) {
2313                 uint32_t tom;
2314                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2315                 tom = RREG32(RADEON_NB_TOM);
2316                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2317                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2318                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2319         } else {
2320                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2321                 /* Some production boards of m6 will report 0
2322                  * if it's 8 MB
2323                  */
2324                 if (rdev->mc.real_vram_size == 0) {
2325                         rdev->mc.real_vram_size = 8192 * 1024;
2326                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2327                 }
2328                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2329                  * Novell bug 204882 + along with lots of ubuntu ones
2330                  */
2331                 if (rdev->mc.aper_size > config_aper_size)
2332                         config_aper_size = rdev->mc.aper_size;
2333
2334                 if (config_aper_size > rdev->mc.real_vram_size)
2335                         rdev->mc.mc_vram_size = config_aper_size;
2336                 else
2337                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2338         }
2339 }
2340
2341 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2342 {
2343         uint32_t temp;
2344
2345         temp = RREG32(RADEON_CONFIG_CNTL);
2346         if (state == false) {
2347                 temp &= ~(1<<8);
2348                 temp |= (1<<9);
2349         } else {
2350                 temp &= ~(1<<9);
2351         }
2352         WREG32(RADEON_CONFIG_CNTL, temp);
2353 }
2354
2355 void r100_mc_init(struct radeon_device *rdev)
2356 {
2357         u64 base;
2358
2359         r100_vram_get_type(rdev);
2360         r100_vram_init_sizes(rdev);
2361         base = rdev->mc.aper_base;
2362         if (rdev->flags & RADEON_IS_IGP)
2363                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2364         radeon_vram_location(rdev, &rdev->mc, base);
2365         rdev->mc.gtt_base_align = 0;
2366         if (!(rdev->flags & RADEON_IS_AGP))
2367                 radeon_gtt_location(rdev, &rdev->mc);
2368         radeon_update_bandwidth_info(rdev);
2369 }
2370
2371
2372 /*
2373  * Indirect registers accessor
2374  */
2375 void r100_pll_errata_after_index(struct radeon_device *rdev)
2376 {
2377         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2378                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2379                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2380         }
2381 }
2382
2383 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2384 {
2385         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2386          * or the chip could hang on a subsequent access
2387          */
2388         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2389                 udelay(5000);
2390         }
2391
2392         /* This function is required to workaround a hardware bug in some (all?)
2393          * revisions of the R300.  This workaround should be called after every
2394          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2395          * may not be correct.
2396          */
2397         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2398                 uint32_t save, tmp;
2399
2400                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2401                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2402                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2403                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2404                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2405         }
2406 }
2407
2408 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2409 {
2410         uint32_t data;
2411
2412         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2413         r100_pll_errata_after_index(rdev);
2414         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2415         r100_pll_errata_after_data(rdev);
2416         return data;
2417 }
2418
2419 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2420 {
2421         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2422         r100_pll_errata_after_index(rdev);
2423         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2424         r100_pll_errata_after_data(rdev);
2425 }
2426
2427 void r100_set_safe_registers(struct radeon_device *rdev)
2428 {
2429         if (ASIC_IS_RN50(rdev)) {
2430                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2431                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2432         } else if (rdev->family < CHIP_R200) {
2433                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2434                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2435         } else {
2436                 r200_set_safe_registers(rdev);
2437         }
2438 }
2439
2440 /*
2441  * Debugfs info
2442  */
2443 #if defined(CONFIG_DEBUG_FS)
2444 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2445 {
2446         struct drm_info_node *node = (struct drm_info_node *) m->private;
2447         struct drm_device *dev = node->minor->dev;
2448         struct radeon_device *rdev = dev->dev_private;
2449         uint32_t reg, value;
2450         unsigned i;
2451
2452         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2453         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2454         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2455         for (i = 0; i < 64; i++) {
2456                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2457                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2458                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2459                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2460                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2461         }
2462         return 0;
2463 }
2464
2465 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2466 {
2467         struct drm_info_node *node = (struct drm_info_node *) m->private;
2468         struct drm_device *dev = node->minor->dev;
2469         struct radeon_device *rdev = dev->dev_private;
2470         uint32_t rdp, wdp;
2471         unsigned count, i, j;
2472
2473         radeon_ring_free_size(rdev);
2474         rdp = RREG32(RADEON_CP_RB_RPTR);
2475         wdp = RREG32(RADEON_CP_RB_WPTR);
2476         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2477         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2478         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2479         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2480         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2481         seq_printf(m, "%u dwords in ring\n", count);
2482         for (j = 0; j <= count; j++) {
2483                 i = (rdp + j) & rdev->cp.ptr_mask;
2484                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2485         }
2486         return 0;
2487 }
2488
2489
2490 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2491 {
2492         struct drm_info_node *node = (struct drm_info_node *) m->private;
2493         struct drm_device *dev = node->minor->dev;
2494         struct radeon_device *rdev = dev->dev_private;
2495         uint32_t csq_stat, csq2_stat, tmp;
2496         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2497         unsigned i;
2498
2499         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2500         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2501         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2502         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2503         r_rptr = (csq_stat >> 0) & 0x3ff;
2504         r_wptr = (csq_stat >> 10) & 0x3ff;
2505         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2506         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2507         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2508         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2509         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2510         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2511         seq_printf(m, "Ring rptr %u\n", r_rptr);
2512         seq_printf(m, "Ring wptr %u\n", r_wptr);
2513         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2514         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2515         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2516         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2517         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2518          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2519         seq_printf(m, "Ring fifo:\n");
2520         for (i = 0; i < 256; i++) {
2521                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2522                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2523                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2524         }
2525         seq_printf(m, "Indirect1 fifo:\n");
2526         for (i = 256; i <= 512; i++) {
2527                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2528                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2529                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2530         }
2531         seq_printf(m, "Indirect2 fifo:\n");
2532         for (i = 640; i < ib1_wptr; i++) {
2533                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2534                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2535                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2536         }
2537         return 0;
2538 }
2539
2540 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2541 {
2542         struct drm_info_node *node = (struct drm_info_node *) m->private;
2543         struct drm_device *dev = node->minor->dev;
2544         struct radeon_device *rdev = dev->dev_private;
2545         uint32_t tmp;
2546
2547         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2548         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2549         tmp = RREG32(RADEON_MC_FB_LOCATION);
2550         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2551         tmp = RREG32(RADEON_BUS_CNTL);
2552         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2553         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2554         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2555         tmp = RREG32(RADEON_AGP_BASE);
2556         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2557         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2558         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2559         tmp = RREG32(0x01D0);
2560         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2561         tmp = RREG32(RADEON_AIC_LO_ADDR);
2562         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2563         tmp = RREG32(RADEON_AIC_HI_ADDR);
2564         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2565         tmp = RREG32(0x01E4);
2566         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2567         return 0;
2568 }
2569
2570 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2571         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2572 };
2573
2574 static struct drm_info_list r100_debugfs_cp_list[] = {
2575         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2576         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2577 };
2578
2579 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2580         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2581 };
2582 #endif
2583
2584 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2585 {
2586 #if defined(CONFIG_DEBUG_FS)
2587         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2588 #else
2589         return 0;
2590 #endif
2591 }
2592
2593 int r100_debugfs_cp_init(struct radeon_device *rdev)
2594 {
2595 #if defined(CONFIG_DEBUG_FS)
2596         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2597 #else
2598         return 0;
2599 #endif
2600 }
2601
2602 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2603 {
2604 #if defined(CONFIG_DEBUG_FS)
2605         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2606 #else
2607         return 0;
2608 #endif
2609 }
2610
2611 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2612                          uint32_t tiling_flags, uint32_t pitch,
2613                          uint32_t offset, uint32_t obj_size)
2614 {
2615         int surf_index = reg * 16;
2616         int flags = 0;
2617
2618         if (rdev->family <= CHIP_RS200) {
2619                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2620                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2621                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2622                 if (tiling_flags & RADEON_TILING_MACRO)
2623                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2624         } else if (rdev->family <= CHIP_RV280) {
2625                 if (tiling_flags & (RADEON_TILING_MACRO))
2626                         flags |= R200_SURF_TILE_COLOR_MACRO;
2627                 if (tiling_flags & RADEON_TILING_MICRO)
2628                         flags |= R200_SURF_TILE_COLOR_MICRO;
2629         } else {
2630                 if (tiling_flags & RADEON_TILING_MACRO)
2631                         flags |= R300_SURF_TILE_MACRO;
2632                 if (tiling_flags & RADEON_TILING_MICRO)
2633                         flags |= R300_SURF_TILE_MICRO;
2634         }
2635
2636         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2637                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2638         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2639                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2640
2641         /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2642         if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2643                 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2644                         if (ASIC_IS_RN50(rdev))
2645                                 pitch /= 16;
2646         }
2647
2648         /* r100/r200 divide by 16 */
2649         if (rdev->family < CHIP_R300)
2650                 flags |= pitch / 16;
2651         else
2652                 flags |= pitch / 8;
2653
2654
2655         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2656         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2657         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2658         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2659         return 0;
2660 }
2661
2662 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2663 {
2664         int surf_index = reg * 16;
2665         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2666 }
2667
2668 void r100_bandwidth_update(struct radeon_device *rdev)
2669 {
2670         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2671         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2672         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2673         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2674         fixed20_12 memtcas_ff[8] = {
2675                 dfixed_init(1),
2676                 dfixed_init(2),
2677                 dfixed_init(3),
2678                 dfixed_init(0),
2679                 dfixed_init_half(1),
2680                 dfixed_init_half(2),
2681                 dfixed_init(0),
2682         };
2683         fixed20_12 memtcas_rs480_ff[8] = {
2684                 dfixed_init(0),
2685                 dfixed_init(1),
2686                 dfixed_init(2),
2687                 dfixed_init(3),
2688                 dfixed_init(0),
2689                 dfixed_init_half(1),
2690                 dfixed_init_half(2),
2691                 dfixed_init_half(3),
2692         };
2693         fixed20_12 memtcas2_ff[8] = {
2694                 dfixed_init(0),
2695                 dfixed_init(1),
2696                 dfixed_init(2),
2697                 dfixed_init(3),
2698                 dfixed_init(4),
2699                 dfixed_init(5),
2700                 dfixed_init(6),
2701                 dfixed_init(7),
2702         };
2703         fixed20_12 memtrbs[8] = {
2704                 dfixed_init(1),
2705                 dfixed_init_half(1),
2706                 dfixed_init(2),
2707                 dfixed_init_half(2),
2708                 dfixed_init(3),
2709                 dfixed_init_half(3),
2710                 dfixed_init(4),
2711                 dfixed_init_half(4)
2712         };
2713         fixed20_12 memtrbs_r4xx[8] = {
2714                 dfixed_init(4),
2715                 dfixed_init(5),
2716                 dfixed_init(6),
2717                 dfixed_init(7),
2718                 dfixed_init(8),
2719                 dfixed_init(9),
2720                 dfixed_init(10),
2721                 dfixed_init(11)
2722         };
2723         fixed20_12 min_mem_eff;
2724         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2725         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2726         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2727                 disp_drain_rate2, read_return_rate;
2728         fixed20_12 time_disp1_drop_priority;
2729         int c;
2730         int cur_size = 16;       /* in octawords */
2731         int critical_point = 0, critical_point2;
2732 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2733         int stop_req, max_stop_req;
2734         struct drm_display_mode *mode1 = NULL;
2735         struct drm_display_mode *mode2 = NULL;
2736         uint32_t pixel_bytes1 = 0;
2737         uint32_t pixel_bytes2 = 0;
2738
2739         radeon_update_display_priority(rdev);
2740
2741         if (rdev->mode_info.crtcs[0]->base.enabled) {
2742                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2743                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2744         }
2745         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2746                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2747                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2748                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2749                 }
2750         }
2751
2752         min_mem_eff.full = dfixed_const_8(0);
2753         /* get modes */
2754         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2755                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2756                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2757                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2758                 /* check crtc enables */
2759                 if (mode2)
2760                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2761                 if (mode1)
2762                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2763                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2764         }
2765
2766         /*
2767          * determine is there is enough bw for current mode
2768          */
2769         sclk_ff = rdev->pm.sclk;
2770         mclk_ff = rdev->pm.mclk;
2771
2772         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2773         temp_ff.full = dfixed_const(temp);
2774         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2775
2776         pix_clk.full = 0;
2777         pix_clk2.full = 0;
2778         peak_disp_bw.full = 0;
2779         if (mode1) {
2780                 temp_ff.full = dfixed_const(1000);
2781                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2782                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2783                 temp_ff.full = dfixed_const(pixel_bytes1);
2784                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2785         }
2786         if (mode2) {
2787                 temp_ff.full = dfixed_const(1000);
2788                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2789                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2790                 temp_ff.full = dfixed_const(pixel_bytes2);
2791                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2792         }
2793
2794         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2795         if (peak_disp_bw.full >= mem_bw.full) {
2796                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2797                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2798         }
2799
2800         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2801         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2802         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2803                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2804                 mem_trp  = ((temp & 0x3)) + 1;
2805                 mem_tras = ((temp & 0x70) >> 4) + 1;
2806         } else if (rdev->family == CHIP_R300 ||
2807                    rdev->family == CHIP_R350) { /* r300, r350 */
2808                 mem_trcd = (temp & 0x7) + 1;
2809                 mem_trp = ((temp >> 8) & 0x7) + 1;
2810                 mem_tras = ((temp >> 11) & 0xf) + 4;
2811         } else if (rdev->family == CHIP_RV350 ||
2812                    rdev->family <= CHIP_RV380) {
2813                 /* rv3x0 */
2814                 mem_trcd = (temp & 0x7) + 3;
2815                 mem_trp = ((temp >> 8) & 0x7) + 3;
2816                 mem_tras = ((temp >> 11) & 0xf) + 6;
2817         } else if (rdev->family == CHIP_R420 ||
2818                    rdev->family == CHIP_R423 ||
2819                    rdev->family == CHIP_RV410) {
2820                 /* r4xx */
2821                 mem_trcd = (temp & 0xf) + 3;
2822                 if (mem_trcd > 15)
2823                         mem_trcd = 15;
2824                 mem_trp = ((temp >> 8) & 0xf) + 3;
2825                 if (mem_trp > 15)
2826                         mem_trp = 15;
2827                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2828                 if (mem_tras > 31)
2829                         mem_tras = 31;
2830         } else { /* RV200, R200 */
2831                 mem_trcd = (temp & 0x7) + 1;
2832                 mem_trp = ((temp >> 8) & 0x7) + 1;
2833                 mem_tras = ((temp >> 12) & 0xf) + 4;
2834         }
2835         /* convert to FF */
2836         trcd_ff.full = dfixed_const(mem_trcd);
2837         trp_ff.full = dfixed_const(mem_trp);
2838         tras_ff.full = dfixed_const(mem_tras);
2839
2840         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2841         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2842         data = (temp & (7 << 20)) >> 20;
2843         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2844                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2845                         tcas_ff = memtcas_rs480_ff[data];
2846                 else
2847                         tcas_ff = memtcas_ff[data];
2848         } else
2849                 tcas_ff = memtcas2_ff[data];
2850
2851         if (rdev->family == CHIP_RS400 ||
2852             rdev->family == CHIP_RS480) {
2853                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2854                 data = (temp >> 23) & 0x7;
2855                 if (data < 5)
2856                         tcas_ff.full += dfixed_const(data);
2857         }
2858
2859         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2860                 /* on the R300, Tcas is included in Trbs.
2861                  */
2862                 temp = RREG32(RADEON_MEM_CNTL);
2863                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2864                 if (data == 1) {
2865                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2866                                 temp = RREG32(R300_MC_IND_INDEX);
2867                                 temp &= ~R300_MC_IND_ADDR_MASK;
2868                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2869                                 WREG32(R300_MC_IND_INDEX, temp);
2870                                 temp = RREG32(R300_MC_IND_DATA);
2871                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2872                         } else {
2873                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2874                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2875                         }
2876                 } else {
2877                         temp = RREG32(R300_MC_READ_CNTL_AB);
2878                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2879                 }
2880                 if (rdev->family == CHIP_RV410 ||
2881                     rdev->family == CHIP_R420 ||
2882                     rdev->family == CHIP_R423)
2883                         trbs_ff = memtrbs_r4xx[data];
2884                 else
2885                         trbs_ff = memtrbs[data];
2886                 tcas_ff.full += trbs_ff.full;
2887         }
2888
2889         sclk_eff_ff.full = sclk_ff.full;
2890
2891         if (rdev->flags & RADEON_IS_AGP) {
2892                 fixed20_12 agpmode_ff;
2893                 agpmode_ff.full = dfixed_const(radeon_agpmode);
2894                 temp_ff.full = dfixed_const_666(16);
2895                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2896         }
2897         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2898
2899         if (ASIC_IS_R300(rdev)) {
2900                 sclk_delay_ff.full = dfixed_const(250);
2901         } else {
2902                 if ((rdev->family == CHIP_RV100) ||
2903                     rdev->flags & RADEON_IS_IGP) {
2904                         if (rdev->mc.vram_is_ddr)
2905                                 sclk_delay_ff.full = dfixed_const(41);
2906                         else
2907                                 sclk_delay_ff.full = dfixed_const(33);
2908                 } else {
2909                         if (rdev->mc.vram_width == 128)
2910                                 sclk_delay_ff.full = dfixed_const(57);
2911                         else
2912                                 sclk_delay_ff.full = dfixed_const(41);
2913                 }
2914         }
2915
2916         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
2917
2918         if (rdev->mc.vram_is_ddr) {
2919                 if (rdev->mc.vram_width == 32) {
2920                         k1.full = dfixed_const(40);
2921                         c  = 3;
2922                 } else {
2923                         k1.full = dfixed_const(20);
2924                         c  = 1;
2925                 }
2926         } else {
2927                 k1.full = dfixed_const(40);
2928                 c  = 3;
2929         }
2930
2931         temp_ff.full = dfixed_const(2);
2932         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2933         temp_ff.full = dfixed_const(c);
2934         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2935         temp_ff.full = dfixed_const(4);
2936         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2937         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
2938         mc_latency_mclk.full += k1.full;
2939
2940         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2941         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
2942
2943         /*
2944           HW cursor time assuming worst case of full size colour cursor.
2945         */
2946         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2947         temp_ff.full += trcd_ff.full;
2948         if (temp_ff.full < tras_ff.full)
2949                 temp_ff.full = tras_ff.full;
2950         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
2951
2952         temp_ff.full = dfixed_const(cur_size);
2953         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
2954         /*
2955           Find the total latency for the display data.
2956         */
2957         disp_latency_overhead.full = dfixed_const(8);
2958         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
2959         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2960         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2961
2962         if (mc_latency_mclk.full > mc_latency_sclk.full)
2963                 disp_latency.full = mc_latency_mclk.full;
2964         else
2965                 disp_latency.full = mc_latency_sclk.full;
2966
2967         /* setup Max GRPH_STOP_REQ default value */
2968         if (ASIC_IS_RV100(rdev))
2969                 max_stop_req = 0x5c;
2970         else
2971                 max_stop_req = 0x7c;
2972
2973         if (mode1) {
2974                 /*  CRTC1
2975                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2976                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2977                 */
2978                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2979
2980                 if (stop_req > max_stop_req)
2981                         stop_req = max_stop_req;
2982
2983                 /*
2984                   Find the drain rate of the display buffer.
2985                 */
2986                 temp_ff.full = dfixed_const((16/pixel_bytes1));
2987                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
2988
2989                 /*
2990                   Find the critical point of the display buffer.
2991                 */
2992                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
2993                 crit_point_ff.full += dfixed_const_half(0);
2994
2995                 critical_point = dfixed_trunc(crit_point_ff);
2996
2997                 if (rdev->disp_priority == 2) {
2998                         critical_point = 0;
2999                 }
3000
3001                 /*
3002                   The critical point should never be above max_stop_req-4.  Setting
3003                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3004                 */
3005                 if (max_stop_req - critical_point < 4)
3006                         critical_point = 0;
3007
3008                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3009                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3010                         critical_point = 0x10;
3011                 }
3012
3013                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3014                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3015                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3016                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3017                 if ((rdev->family == CHIP_R350) &&
3018                     (stop_req > 0x15)) {
3019                         stop_req -= 0x10;
3020                 }
3021                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3022                 temp |= RADEON_GRPH_BUFFER_SIZE;
3023                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3024                           RADEON_GRPH_CRITICAL_AT_SOF |
3025                           RADEON_GRPH_STOP_CNTL);
3026                 /*
3027                   Write the result into the register.
3028                 */
3029                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3030                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3031
3032 #if 0
3033                 if ((rdev->family == CHIP_RS400) ||
3034                     (rdev->family == CHIP_RS480)) {
3035                         /* attempt to program RS400 disp regs correctly ??? */
3036                         temp = RREG32(RS400_DISP1_REG_CNTL);
3037                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3038                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3039                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3040                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3041                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3042                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3043                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3044                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3045                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3046                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3047                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3048                 }
3049 #endif
3050
3051                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3052                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3053                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3054         }
3055
3056         if (mode2) {
3057                 u32 grph2_cntl;
3058                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3059
3060                 if (stop_req > max_stop_req)
3061                         stop_req = max_stop_req;
3062
3063                 /*
3064                   Find the drain rate of the display buffer.
3065                 */
3066                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3067                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3068
3069                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3070                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3071                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3072                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3073                 if ((rdev->family == CHIP_R350) &&
3074                     (stop_req > 0x15)) {
3075                         stop_req -= 0x10;
3076                 }
3077                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3078                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3079                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3080                           RADEON_GRPH_CRITICAL_AT_SOF |
3081                           RADEON_GRPH_STOP_CNTL);
3082
3083                 if ((rdev->family == CHIP_RS100) ||
3084                     (rdev->family == CHIP_RS200))
3085                         critical_point2 = 0;
3086                 else {
3087                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3088                         temp_ff.full = dfixed_const(temp);
3089                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3090                         if (sclk_ff.full < temp_ff.full)
3091                                 temp_ff.full = sclk_ff.full;
3092
3093                         read_return_rate.full = temp_ff.full;
3094
3095                         if (mode1) {
3096                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3097                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3098                         } else {
3099                                 time_disp1_drop_priority.full = 0;
3100                         }
3101                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3102                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3103                         crit_point_ff.full += dfixed_const_half(0);
3104
3105                         critical_point2 = dfixed_trunc(crit_point_ff);
3106
3107                         if (rdev->disp_priority == 2) {
3108                                 critical_point2 = 0;
3109                         }
3110
3111                         if (max_stop_req - critical_point2 < 4)
3112                                 critical_point2 = 0;
3113
3114                 }
3115
3116                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3117                         /* some R300 cards have problem with this set to 0 */
3118                         critical_point2 = 0x10;
3119                 }
3120
3121                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3122                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3123
3124                 if ((rdev->family == CHIP_RS400) ||
3125                     (rdev->family == CHIP_RS480)) {
3126 #if 0
3127                         /* attempt to program RS400 disp2 regs correctly ??? */
3128                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3129                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3130                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3131                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3132                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3133                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3134                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3135                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3136                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3137                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3138                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3139                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3140 #endif
3141                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3142                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3143                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3144                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3145                 }
3146
3147                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3148                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3149         }
3150 }
3151
3152 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3153 {
3154         DRM_ERROR("pitch                      %d\n", t->pitch);
3155         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
3156         DRM_ERROR("width                      %d\n", t->width);
3157         DRM_ERROR("width_11                   %d\n", t->width_11);
3158         DRM_ERROR("height                     %d\n", t->height);
3159         DRM_ERROR("height_11                  %d\n", t->height_11);
3160         DRM_ERROR("num levels                 %d\n", t->num_levels);
3161         DRM_ERROR("depth                      %d\n", t->txdepth);
3162         DRM_ERROR("bpp                        %d\n", t->cpp);
3163         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
3164         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
3165         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3166         DRM_ERROR("compress format            %d\n", t->compress_format);
3167 }
3168
3169 static int r100_track_compress_size(int compress_format, int w, int h)
3170 {
3171         int block_width, block_height, block_bytes;
3172         int wblocks, hblocks;
3173         int min_wblocks;
3174         int sz;
3175
3176         block_width = 4;
3177         block_height = 4;
3178
3179         switch (compress_format) {
3180         case R100_TRACK_COMP_DXT1:
3181                 block_bytes = 8;
3182                 min_wblocks = 4;
3183                 break;
3184         default:
3185         case R100_TRACK_COMP_DXT35:
3186                 block_bytes = 16;
3187                 min_wblocks = 2;
3188                 break;
3189         }
3190
3191         hblocks = (h + block_height - 1) / block_height;
3192         wblocks = (w + block_width - 1) / block_width;
3193         if (wblocks < min_wblocks)
3194                 wblocks = min_wblocks;
3195         sz = wblocks * hblocks * block_bytes;
3196         return sz;
3197 }
3198
3199 static int r100_cs_track_cube(struct radeon_device *rdev,
3200                               struct r100_cs_track *track, unsigned idx)
3201 {
3202         unsigned face, w, h;
3203         struct radeon_bo *cube_robj;
3204         unsigned long size;
3205         unsigned compress_format = track->textures[idx].compress_format;
3206
3207         for (face = 0; face < 5; face++) {
3208                 cube_robj = track->textures[idx].cube_info[face].robj;
3209                 w = track->textures[idx].cube_info[face].width;
3210                 h = track->textures[idx].cube_info[face].height;
3211
3212                 if (compress_format) {
3213                         size = r100_track_compress_size(compress_format, w, h);
3214                 } else
3215                         size = w * h;
3216                 size *= track->textures[idx].cpp;
3217
3218                 size += track->textures[idx].cube_info[face].offset;
3219
3220                 if (size > radeon_bo_size(cube_robj)) {
3221                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3222                                   size, radeon_bo_size(cube_robj));
3223                         r100_cs_track_texture_print(&track->textures[idx]);
3224                         return -1;
3225                 }
3226         }
3227         return 0;
3228 }
3229
3230 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3231                                        struct r100_cs_track *track)
3232 {
3233         struct radeon_bo *robj;
3234         unsigned long size;
3235         unsigned u, i, w, h, d;
3236         int ret;
3237
3238         for (u = 0; u < track->num_texture; u++) {
3239                 if (!track->textures[u].enabled)
3240                         continue;
3241                 if (track->textures[u].lookup_disable)
3242                         continue;
3243                 robj = track->textures[u].robj;
3244                 if (robj == NULL) {
3245                         DRM_ERROR("No texture bound to unit %u\n", u);
3246                         return -EINVAL;
3247                 }
3248                 size = 0;
3249                 for (i = 0; i <= track->textures[u].num_levels; i++) {
3250                         if (track->textures[u].use_pitch) {
3251                                 if (rdev->family < CHIP_R300)
3252                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3253                                 else
3254                                         w = track->textures[u].pitch / (1 << i);
3255                         } else {
3256                                 w = track->textures[u].width;
3257                                 if (rdev->family >= CHIP_RV515)
3258                                         w |= track->textures[u].width_11;
3259                                 w = w / (1 << i);
3260                                 if (track->textures[u].roundup_w)
3261                                         w = roundup_pow_of_two(w);
3262                         }
3263                         h = track->textures[u].height;
3264                         if (rdev->family >= CHIP_RV515)
3265                                 h |= track->textures[u].height_11;
3266                         h = h / (1 << i);
3267                         if (track->textures[u].roundup_h)
3268                                 h = roundup_pow_of_two(h);
3269                         if (track->textures[u].tex_coord_type == 1) {
3270                                 d = (1 << track->textures[u].txdepth) / (1 << i);
3271                                 if (!d)
3272                                         d = 1;
3273                         } else {
3274                                 d = 1;
3275                         }
3276                         if (track->textures[u].compress_format) {
3277
3278                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3279                                 /* compressed textures are block based */
3280                         } else
3281                                 size += w * h * d;
3282                 }
3283                 size *= track->textures[u].cpp;
3284
3285                 switch (track->textures[u].tex_coord_type) {
3286                 case 0:
3287                 case 1:
3288                         break;
3289                 case 2:
3290                         if (track->separate_cube) {
3291                                 ret = r100_cs_track_cube(rdev, track, u);
3292                                 if (ret)
3293                                         return ret;
3294                         } else
3295                                 size *= 6;
3296                         break;
3297                 default:
3298                         DRM_ERROR("Invalid texture coordinate type %u for unit "
3299                                   "%u\n", track->textures[u].tex_coord_type, u);
3300                         return -EINVAL;
3301                 }
3302                 if (size > radeon_bo_size(robj)) {
3303                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3304                                   "%lu\n", u, size, radeon_bo_size(robj));
3305                         r100_cs_track_texture_print(&track->textures[u]);
3306                         return -EINVAL;
3307                 }
3308         }
3309         return 0;
3310 }
3311
3312 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3313 {
3314         unsigned i;
3315         unsigned long size;
3316         unsigned prim_walk;
3317         unsigned nverts;
3318         unsigned num_cb = track->num_cb;
3319
3320         if (!track->zb_cb_clear && !track->color_channel_mask &&
3321             !track->blend_read_enable)
3322                 num_cb = 0;
3323
3324         for (i = 0; i < num_cb; i++) {
3325                 if (track->cb[i].robj == NULL) {
3326                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3327                         return -EINVAL;
3328                 }
3329                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3330                 size += track->cb[i].offset;
3331                 if (size > radeon_bo_size(track->cb[i].robj)) {
3332                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
3333                                   "(need %lu have %lu) !\n", i, size,
3334                                   radeon_bo_size(track->cb[i].robj));
3335                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3336                                   i, track->cb[i].pitch, track->cb[i].cpp,
3337                                   track->cb[i].offset, track->maxy);
3338                         return -EINVAL;
3339                 }
3340         }
3341         if (track->z_enabled) {
3342                 if (track->zb.robj == NULL) {
3343                         DRM_ERROR("[drm] No buffer for z buffer !\n");
3344                         return -EINVAL;
3345                 }
3346                 size = track->zb.pitch * track->zb.cpp * track->maxy;
3347                 size += track->zb.offset;
3348                 if (size > radeon_bo_size(track->zb.robj)) {
3349                         DRM_ERROR("[drm] Buffer too small for z buffer "
3350                                   "(need %lu have %lu) !\n", size,
3351                                   radeon_bo_size(track->zb.robj));
3352                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3353                                   track->zb.pitch, track->zb.cpp,
3354                                   track->zb.offset, track->maxy);
3355                         return -EINVAL;
3356                 }
3357         }
3358         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3359         if (track->vap_vf_cntl & (1 << 14)) {
3360                 nverts = track->vap_alt_nverts;
3361         } else {
3362                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3363         }
3364         switch (prim_walk) {
3365         case 1:
3366                 for (i = 0; i < track->num_arrays; i++) {
3367                         size = track->arrays[i].esize * track->max_indx * 4;
3368                         if (track->arrays[i].robj == NULL) {
3369                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3370                                           "bound\n", prim_walk, i);
3371                                 return -EINVAL;
3372                         }
3373                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3374                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3375                                         "need %lu dwords have %lu dwords\n",
3376                                         prim_walk, i, size >> 2,
3377                                         radeon_bo_size(track->arrays[i].robj)
3378                                         >> 2);
3379                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3380                                 return -EINVAL;
3381                         }
3382                 }
3383                 break;
3384         case 2:
3385                 for (i = 0; i < track->num_arrays; i++) {
3386                         size = track->arrays[i].esize * (nverts - 1) * 4;
3387                         if (track->arrays[i].robj == NULL) {
3388                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3389                                           "bound\n", prim_walk, i);
3390                                 return -EINVAL;
3391                         }
3392                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3393                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3394                                         "need %lu dwords have %lu dwords\n",
3395                                         prim_walk, i, size >> 2,
3396                                         radeon_bo_size(track->arrays[i].robj)
3397                                         >> 2);
3398                                 return -EINVAL;
3399                         }
3400                 }
3401                 break;
3402         case 3:
3403                 size = track->vtx_size * nverts;
3404                 if (size != track->immd_dwords) {
3405                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3406                                   track->immd_dwords, size);
3407                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3408                                   nverts, track->vtx_size);
3409                         return -EINVAL;
3410                 }
3411                 break;
3412         default:
3413                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3414                           prim_walk);
3415                 return -EINVAL;
3416         }
3417         return r100_cs_track_texture_check(rdev, track);
3418 }
3419
3420 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3421 {
3422         unsigned i, face;
3423
3424         if (rdev->family < CHIP_R300) {
3425                 track->num_cb = 1;
3426                 if (rdev->family <= CHIP_RS200)
3427                         track->num_texture = 3;
3428                 else
3429                         track->num_texture = 6;
3430                 track->maxy = 2048;
3431                 track->separate_cube = 1;
3432         } else {
3433                 track->num_cb = 4;
3434                 track->num_texture = 16;
3435                 track->maxy = 4096;
3436                 track->separate_cube = 0;
3437         }
3438
3439         for (i = 0; i < track->num_cb; i++) {
3440                 track->cb[i].robj = NULL;
3441                 track->cb[i].pitch = 8192;
3442                 track->cb[i].cpp = 16;
3443                 track->cb[i].offset = 0;
3444         }
3445         track->z_enabled = true;
3446         track->zb.robj = NULL;
3447         track->zb.pitch = 8192;
3448         track->zb.cpp = 4;
3449         track->zb.offset = 0;
3450         track->vtx_size = 0x7F;
3451         track->immd_dwords = 0xFFFFFFFFUL;
3452         track->num_arrays = 11;
3453         track->max_indx = 0x00FFFFFFUL;
3454         for (i = 0; i < track->num_arrays; i++) {
3455                 track->arrays[i].robj = NULL;
3456                 track->arrays[i].esize = 0x7F;
3457         }
3458         for (i = 0; i < track->num_texture; i++) {
3459                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3460                 track->textures[i].pitch = 16536;
3461                 track->textures[i].width = 16536;
3462                 track->textures[i].height = 16536;
3463                 track->textures[i].width_11 = 1 << 11;
3464                 track->textures[i].height_11 = 1 << 11;
3465                 track->textures[i].num_levels = 12;
3466                 if (rdev->family <= CHIP_RS200) {
3467                         track->textures[i].tex_coord_type = 0;
3468                         track->textures[i].txdepth = 0;
3469                 } else {
3470                         track->textures[i].txdepth = 16;
3471                         track->textures[i].tex_coord_type = 1;
3472                 }
3473                 track->textures[i].cpp = 64;
3474                 track->textures[i].robj = NULL;
3475                 /* CS IB emission code makes sure texture unit are disabled */
3476                 track->textures[i].enabled = false;
3477                 track->textures[i].lookup_disable = false;
3478                 track->textures[i].roundup_w = true;
3479                 track->textures[i].roundup_h = true;
3480                 if (track->separate_cube)
3481                         for (face = 0; face < 5; face++) {
3482                                 track->textures[i].cube_info[face].robj = NULL;
3483                                 track->textures[i].cube_info[face].width = 16536;
3484                                 track->textures[i].cube_info[face].height = 16536;
3485                                 track->textures[i].cube_info[face].offset = 0;
3486                         }
3487         }
3488 }
3489
3490 int r100_ring_test(struct radeon_device *rdev)
3491 {
3492         uint32_t scratch;
3493         uint32_t tmp = 0;
3494         unsigned i;
3495         int r;
3496
3497         r = radeon_scratch_get(rdev, &scratch);
3498         if (r) {
3499                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3500                 return r;
3501         }
3502         WREG32(scratch, 0xCAFEDEAD);
3503         r = radeon_ring_lock(rdev, 2);
3504         if (r) {
3505                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3506                 radeon_scratch_free(rdev, scratch);
3507                 return r;
3508         }
3509         radeon_ring_write(rdev, PACKET0(scratch, 0));
3510         radeon_ring_write(rdev, 0xDEADBEEF);
3511         radeon_ring_unlock_commit(rdev);
3512         for (i = 0; i < rdev->usec_timeout; i++) {
3513                 tmp = RREG32(scratch);
3514                 if (tmp == 0xDEADBEEF) {
3515                         break;
3516                 }
3517                 DRM_UDELAY(1);
3518         }
3519         if (i < rdev->usec_timeout) {
3520                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3521         } else {
3522                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3523                           scratch, tmp);
3524                 r = -EINVAL;
3525         }
3526         radeon_scratch_free(rdev, scratch);
3527         return r;
3528 }
3529
3530 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3531 {
3532         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3533         radeon_ring_write(rdev, ib->gpu_addr);
3534         radeon_ring_write(rdev, ib->length_dw);
3535 }
3536
3537 int r100_ib_test(struct radeon_device *rdev)
3538 {
3539         struct radeon_ib *ib;
3540         uint32_t scratch;
3541         uint32_t tmp = 0;
3542         unsigned i;
3543         int r;
3544
3545         r = radeon_scratch_get(rdev, &scratch);
3546         if (r) {
3547                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3548                 return r;
3549         }
3550         WREG32(scratch, 0xCAFEDEAD);
3551         r = radeon_ib_get(rdev, &ib);
3552         if (r) {
3553                 return r;
3554         }
3555         ib->ptr[0] = PACKET0(scratch, 0);
3556         ib->ptr[1] = 0xDEADBEEF;
3557         ib->ptr[2] = PACKET2(0);
3558         ib->ptr[3] = PACKET2(0);
3559         ib->ptr[4] = PACKET2(0);
3560         ib->ptr[5] = PACKET2(0);
3561         ib->ptr[6] = PACKET2(0);
3562         ib->ptr[7] = PACKET2(0);
3563         ib->length_dw = 8;
3564         r = radeon_ib_schedule(rdev, ib);
3565         if (r) {
3566                 radeon_scratch_free(rdev, scratch);
3567                 radeon_ib_free(rdev, &ib);
3568                 return r;
3569         }
3570         r = radeon_fence_wait(ib->fence, false);
3571         if (r) {
3572                 return r;
3573         }
3574         for (i = 0; i < rdev->usec_timeout; i++) {
3575                 tmp = RREG32(scratch);
3576                 if (tmp == 0xDEADBEEF) {
3577                         break;
3578                 }
3579                 DRM_UDELAY(1);
3580         }
3581         if (i < rdev->usec_timeout) {
3582                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3583         } else {
3584                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3585                           scratch, tmp);
3586                 r = -EINVAL;
3587         }
3588         radeon_scratch_free(rdev, scratch);
3589         radeon_ib_free(rdev, &ib);
3590         return r;
3591 }
3592
3593 void r100_ib_fini(struct radeon_device *rdev)
3594 {
3595         radeon_ib_pool_fini(rdev);
3596 }
3597
3598 int r100_ib_init(struct radeon_device *rdev)
3599 {
3600         int r;
3601
3602         r = radeon_ib_pool_init(rdev);
3603         if (r) {
3604                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3605                 r100_ib_fini(rdev);
3606                 return r;
3607         }
3608         r = r100_ib_test(rdev);
3609         if (r) {
3610                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3611                 r100_ib_fini(rdev);
3612                 return r;
3613         }
3614         return 0;
3615 }
3616
3617 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3618 {
3619         /* Shutdown CP we shouldn't need to do that but better be safe than
3620          * sorry
3621          */
3622         rdev->cp.ready = false;
3623         WREG32(R_000740_CP_CSQ_CNTL, 0);
3624
3625         /* Save few CRTC registers */
3626         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3627         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3628         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3629         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3630         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3631                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3632                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3633         }
3634
3635         /* Disable VGA aperture access */
3636         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3637         /* Disable cursor, overlay, crtc */
3638         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3639         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3640                                         S_000054_CRTC_DISPLAY_DIS(1));
3641         WREG32(R_000050_CRTC_GEN_CNTL,
3642                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3643                         S_000050_CRTC_DISP_REQ_EN_B(1));
3644         WREG32(R_000420_OV0_SCALE_CNTL,
3645                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3646         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3647         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3648                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3649                                                 S_000360_CUR2_LOCK(1));
3650                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3651                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3652                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3653                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3654                 WREG32(R_000360_CUR2_OFFSET,
3655                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3656         }
3657 }
3658
3659 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3660 {
3661         /* Update base address for crtc */
3662         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3663         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3664                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3665         }
3666         /* Restore CRTC registers */
3667         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3668         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3669         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3670         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3671                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3672         }
3673 }
3674
3675 void r100_vga_render_disable(struct radeon_device *rdev)
3676 {
3677         u32 tmp;
3678
3679         tmp = RREG8(R_0003C2_GENMO_WT);
3680         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3681 }
3682
3683 static void r100_debugfs(struct radeon_device *rdev)
3684 {
3685         int r;
3686
3687         r = r100_debugfs_mc_info_init(rdev);
3688         if (r)
3689                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3690 }
3691
3692 static void r100_mc_program(struct radeon_device *rdev)
3693 {
3694         struct r100_mc_save save;
3695
3696         /* Stops all mc clients */
3697         r100_mc_stop(rdev, &save);
3698         if (rdev->flags & RADEON_IS_AGP) {
3699                 WREG32(R_00014C_MC_AGP_LOCATION,
3700                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3701                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3702                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3703                 if (rdev->family > CHIP_RV200)
3704                         WREG32(R_00015C_AGP_BASE_2,
3705                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3706         } else {
3707                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3708                 WREG32(R_000170_AGP_BASE, 0);
3709                 if (rdev->family > CHIP_RV200)
3710                         WREG32(R_00015C_AGP_BASE_2, 0);
3711         }
3712         /* Wait for mc idle */
3713         if (r100_mc_wait_for_idle(rdev))
3714                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3715         /* Program MC, should be a 32bits limited address space */
3716         WREG32(R_000148_MC_FB_LOCATION,
3717                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3718                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3719         r100_mc_resume(rdev, &save);
3720 }
3721
3722 void r100_clock_startup(struct radeon_device *rdev)
3723 {
3724         u32 tmp;
3725
3726         if (radeon_dynclks != -1 && radeon_dynclks)
3727                 radeon_legacy_set_clock_gating(rdev, 1);
3728         /* We need to force on some of the block */
3729         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3730         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3731         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3732                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3733         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3734 }
3735
3736 static int r100_startup(struct radeon_device *rdev)
3737 {
3738         int r;
3739
3740         /* set common regs */
3741         r100_set_common_regs(rdev);
3742         /* program mc */
3743         r100_mc_program(rdev);
3744         /* Resume clock */
3745         r100_clock_startup(rdev);
3746         /* Initialize GPU configuration (# pipes, ...) */
3747 //      r100_gpu_init(rdev);
3748         /* Initialize GART (initialize after TTM so we can allocate
3749          * memory through TTM but finalize after TTM) */
3750         r100_enable_bm(rdev);
3751         if (rdev->flags & RADEON_IS_PCI) {
3752                 r = r100_pci_gart_enable(rdev);
3753                 if (r)
3754                         return r;
3755         }
3756
3757         /* allocate wb buffer */
3758         r = radeon_wb_init(rdev);
3759         if (r)
3760                 return r;
3761
3762         /* Enable IRQ */
3763         r100_irq_set(rdev);
3764         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3765         /* 1M ring buffer */
3766         r = r100_cp_init(rdev, 1024 * 1024);
3767         if (r) {
3768                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3769                 return r;
3770         }
3771         r = r100_ib_init(rdev);
3772         if (r) {
3773                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3774                 return r;
3775         }
3776         return 0;
3777 }
3778
3779 int r100_resume(struct radeon_device *rdev)
3780 {
3781         /* Make sur GART are not working */
3782         if (rdev->flags & RADEON_IS_PCI)
3783                 r100_pci_gart_disable(rdev);
3784         /* Resume clock before doing reset */
3785         r100_clock_startup(rdev);
3786         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3787         if (radeon_asic_reset(rdev)) {
3788                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3789                         RREG32(R_000E40_RBBM_STATUS),
3790                         RREG32(R_0007C0_CP_STAT));
3791         }
3792         /* post */
3793         radeon_combios_asic_init(rdev->ddev);
3794         /* Resume clock after posting */
3795         r100_clock_startup(rdev);
3796         /* Initialize surface registers */
3797         radeon_surface_init(rdev);
3798         return r100_startup(rdev);
3799 }
3800
3801 int r100_suspend(struct radeon_device *rdev)
3802 {
3803         r100_cp_disable(rdev);
3804         radeon_wb_disable(rdev);
3805         r100_irq_disable(rdev);
3806         if (rdev->flags & RADEON_IS_PCI)
3807                 r100_pci_gart_disable(rdev);
3808         return 0;
3809 }
3810
3811 void r100_fini(struct radeon_device *rdev)
3812 {
3813         r100_cp_fini(rdev);
3814         radeon_wb_fini(rdev);
3815         r100_ib_fini(rdev);
3816         radeon_gem_fini(rdev);
3817         if (rdev->flags & RADEON_IS_PCI)
3818                 r100_pci_gart_fini(rdev);
3819         radeon_agp_fini(rdev);
3820         radeon_irq_kms_fini(rdev);
3821         radeon_fence_driver_fini(rdev);
3822         radeon_bo_fini(rdev);
3823         radeon_atombios_fini(rdev);
3824         kfree(rdev->bios);
3825         rdev->bios = NULL;
3826 }
3827
3828 /*
3829  * Due to how kexec works, it can leave the hw fully initialised when it
3830  * boots the new kernel. However doing our init sequence with the CP and
3831  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3832  * do some quick sanity checks and restore sane values to avoid this
3833  * problem.
3834  */
3835 void r100_restore_sanity(struct radeon_device *rdev)
3836 {
3837         u32 tmp;
3838
3839         tmp = RREG32(RADEON_CP_CSQ_CNTL);
3840         if (tmp) {
3841                 WREG32(RADEON_CP_CSQ_CNTL, 0);
3842         }
3843         tmp = RREG32(RADEON_CP_RB_CNTL);
3844         if (tmp) {
3845                 WREG32(RADEON_CP_RB_CNTL, 0);
3846         }
3847         tmp = RREG32(RADEON_SCRATCH_UMSK);
3848         if (tmp) {
3849                 WREG32(RADEON_SCRATCH_UMSK, 0);
3850         }
3851 }
3852
3853 int r100_init(struct radeon_device *rdev)
3854 {
3855         int r;
3856
3857         /* Register debugfs file specific to this group of asics */
3858         r100_debugfs(rdev);
3859         /* Disable VGA */
3860         r100_vga_render_disable(rdev);
3861         /* Initialize scratch registers */
3862         radeon_scratch_init(rdev);
3863         /* Initialize surface registers */
3864         radeon_surface_init(rdev);
3865         /* sanity check some register to avoid hangs like after kexec */
3866         r100_restore_sanity(rdev);
3867         /* TODO: disable VGA need to use VGA request */
3868         /* BIOS*/
3869         if (!radeon_get_bios(rdev)) {
3870                 if (ASIC_IS_AVIVO(rdev))
3871                         return -EINVAL;
3872         }
3873         if (rdev->is_atom_bios) {
3874                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3875                 return -EINVAL;
3876         } else {
3877                 r = radeon_combios_init(rdev);
3878                 if (r)
3879                         return r;
3880         }
3881         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3882         if (radeon_asic_reset(rdev)) {
3883                 dev_warn(rdev->dev,
3884                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3885                         RREG32(R_000E40_RBBM_STATUS),
3886                         RREG32(R_0007C0_CP_STAT));
3887         }
3888         /* check if cards are posted or not */
3889         if (radeon_boot_test_post_card(rdev) == false)
3890                 return -EINVAL;
3891         /* Set asic errata */
3892         r100_errata(rdev);
3893         /* Initialize clocks */
3894         radeon_get_clock_info(rdev->ddev);
3895         /* initialize AGP */
3896         if (rdev->flags & RADEON_IS_AGP) {
3897                 r = radeon_agp_init(rdev);
3898                 if (r) {
3899                         radeon_agp_disable(rdev);
3900                 }
3901         }
3902         /* initialize VRAM */
3903         r100_mc_init(rdev);
3904         /* Fence driver */
3905         r = radeon_fence_driver_init(rdev);
3906         if (r)
3907                 return r;
3908         r = radeon_irq_kms_init(rdev);
3909         if (r)
3910                 return r;
3911         /* Memory manager */
3912         r = radeon_bo_init(rdev);
3913         if (r)
3914                 return r;
3915         if (rdev->flags & RADEON_IS_PCI) {
3916                 r = r100_pci_gart_init(rdev);
3917                 if (r)
3918                         return r;
3919         }
3920         r100_set_safe_registers(rdev);
3921         rdev->accel_working = true;
3922         r = r100_startup(rdev);
3923         if (r) {
3924                 /* Somethings want wront with the accel init stop accel */
3925                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3926                 r100_cp_fini(rdev);
3927                 radeon_wb_fini(rdev);
3928                 r100_ib_fini(rdev);
3929                 radeon_irq_kms_fini(rdev);
3930                 if (rdev->flags & RADEON_IS_PCI)
3931                         r100_pci_gart_fini(rdev);
3932                 rdev->accel_working = false;
3933         }
3934         return 0;
3935 }