drivers/gpu/drm/radeon/r100.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/seq_file.h>
  29 #include <linux/slab.h>
  30 #include <drm/drmP.h>
  31 #include <drm/radeon_drm.h>
  32 #include "radeon_reg.h"
  33 #include "radeon.h"
  34 #include "radeon_asic.h"
  35 #include "r100d.h"
  36 #include "rs100d.h"
  37 #include "rv200d.h"
  38 #include "rv250d.h"
  39 #include "atom.h"
  40
  41 #include <linux/firmware.h>
  42 #include <linux/module.h>
  43
  44 #include "r100_reg_safe.h"
  45 #include "rn50_reg_safe.h"
  46
  47 /* Firmware Names */
  48 #define FIRMWARE_R100           "radeon/R100_cp.bin"
  49 #define FIRMWARE_R200           "radeon/R200_cp.bin"
  50 #define FIRMWARE_R300           "radeon/R300_cp.bin"
  51 #define FIRMWARE_R420           "radeon/R420_cp.bin"
  52 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
  53 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
  54 #define FIRMWARE_R520           "radeon/R520_cp.bin"
  55
  56 MODULE_FIRMWARE(FIRMWARE_R100);
  57 MODULE_FIRMWARE(FIRMWARE_R200);
  58 MODULE_FIRMWARE(FIRMWARE_R300);
  59 MODULE_FIRMWARE(FIRMWARE_R420);
  60 MODULE_FIRMWARE(FIRMWARE_RS690);
  61 MODULE_FIRMWARE(FIRMWARE_RS600);
  62 MODULE_FIRMWARE(FIRMWARE_R520);
  63
  64 #include "r100_track.h"
  65
  66 /* This files gather functions specifics to:
  67  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  68  * and others in some cases.
  69  */
  70
  71 static bool r100_is_in_vblank(struct radeon_device *rdev, int crtc)
  72 {
  73         if (crtc == 0) {
  74                 if (RREG32(RADEON_CRTC_STATUS) & RADEON_CRTC_VBLANK_CUR)
  75                         return true;
  76                 else
  77                         return false;
  78         } else {
  79                 if (RREG32(RADEON_CRTC2_STATUS) & RADEON_CRTC2_VBLANK_CUR)
  80                         return true;
  81                 else
  82                         return false;
  83         }
  84 }
  85
  86 static bool r100_is_counter_moving(struct radeon_device *rdev, int crtc)
  87 {
  88         u32 vline1, vline2;
  89
  90         if (crtc == 0) {
  91                 vline1 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  92                 vline2 = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  93         } else {
  94                 vline1 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  95                 vline2 = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
  96         }
  97         if (vline1 != vline2)
  98                 return true;
  99         else
 100                 return false;
 101 }
 102
 103 /**
 104  * r100_wait_for_vblank - vblank wait asic callback.
 105  *
 106  * @rdev: radeon_device pointer
 107  * @crtc: crtc to wait for vblank on
 108  *
 109  * Wait for vblank on the requested crtc (r1xx-r4xx).
 110  */
 111 void r100_wait_for_vblank(struct radeon_device *rdev, int crtc)
 112 {
 113         unsigned i = 0;
 114
 115         if (crtc >= rdev->num_crtc)
 116                 return;
 117
 118         if (crtc == 0) {
 119                 if (!(RREG32(RADEON_CRTC_GEN_CNTL) & RADEON_CRTC_EN))
 120                         return;
 121         } else {
 122                 if (!(RREG32(RADEON_CRTC2_GEN_CNTL) & RADEON_CRTC2_EN))
 123                         return;
 124         }
 125
 126         /* depending on when we hit vblank, we may be close to active; if so,
 127          * wait for another frame.
 128          */
 129         while (r100_is_in_vblank(rdev, crtc)) {
 130                 if (i++ % 100 == 0) {
 131                         if (!r100_is_counter_moving(rdev, crtc))
 132                                 break;
 133                 }
 134         }
 135
 136         while (!r100_is_in_vblank(rdev, crtc)) {
 137                 if (i++ % 100 == 0) {
 138                         if (!r100_is_counter_moving(rdev, crtc))
 139                                 break;
 140                 }
 141         }
 142 }
 143
 144 /**
 145  * r100_page_flip - pageflip callback.
 146  *
 147  * @rdev: radeon_device pointer
 148  * @crtc_id: crtc to cleanup pageflip on
 149  * @crtc_base: new address of the crtc (GPU MC address)
 150  *
 151  * Does the actual pageflip (r1xx-r4xx).
 152  * During vblank we take the crtc lock and wait for the update_pending
 153  * bit to go high, when it does, we release the lock, and allow the
 154  * double buffered update to take place.
 155  * Returns the current update pending status.
 156  */
 157 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 158 {
 159         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 160         u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
 161         int i;
 162
 163         /* Lock the graphics update lock */
 164         /* update the scanout addresses */
 165         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 166
 167         /* Wait for update_pending to go high. */
 168         for (i = 0; i < rdev->usec_timeout; i++) {
 169                 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
 170                         break;
 171                 udelay(1);
 172         }
 173         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 174
 175         /* Unlock the lock, so double-buffering can take place inside vblank */
 176         tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
 177         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
 178
 179         /* Return current update_pending status: */
 180         return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
 181 }
 182
 183 /**
 184  * r100_pm_get_dynpm_state - look up dynpm power state callback.
 185  *
 186  * @rdev: radeon_device pointer
 187  *
 188  * Look up the optimal power state based on the
 189  * current state of the GPU (r1xx-r5xx).
 190  * Used for dynpm only.
 191  */
 192 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
 193 {
 194         int i;
 195         rdev->pm.dynpm_can_upclock = true;
 196         rdev->pm.dynpm_can_downclock = true;
 197
 198         switch (rdev->pm.dynpm_planned_action) {
 199         case DYNPM_ACTION_MINIMUM:
 200                 rdev->pm.requested_power_state_index = 0;
 201                 rdev->pm.dynpm_can_downclock = false;
 202                 break;
 203         case DYNPM_ACTION_DOWNCLOCK:
 204                 if (rdev->pm.current_power_state_index == 0) {
 205                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 206                         rdev->pm.dynpm_can_downclock = false;
 207                 } else {
 208                         if (rdev->pm.active_crtc_count > 1) {
 209                                 for (i = 0; i < rdev->pm.num_power_states; i++) {
 210                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 211                                                 continue;
 212                                         else if (i >= rdev->pm.current_power_state_index) {
 213                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 214                                                 break;
 215                                         } else {
 216                                                 rdev->pm.requested_power_state_index = i;
 217                                                 break;
 218                                         }
 219                                 }
 220                         } else
 221                                 rdev->pm.requested_power_state_index =
 222                                         rdev->pm.current_power_state_index - 1;
 223                 }
 224                 /* don't use the power state if crtcs are active and no display flag is set */
 225                 if ((rdev->pm.active_crtc_count > 0) &&
 226                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
 227                      RADEON_PM_MODE_NO_DISPLAY)) {
 228                         rdev->pm.requested_power_state_index++;
 229                 }
 230                 break;
 231         case DYNPM_ACTION_UPCLOCK:
 232                 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 233                         rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 234                         rdev->pm.dynpm_can_upclock = false;
 235                 } else {
 236                         if (rdev->pm.active_crtc_count > 1) {
 237                                 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 238                                         if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 239                                                 continue;
 240                                         else if (i <= rdev->pm.current_power_state_index) {
 241                                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 242                                                 break;
 243                                         } else {
 244                                                 rdev->pm.requested_power_state_index = i;
 245                                                 break;
 246                                         }
 247                                 }
 248                         } else
 249                                 rdev->pm.requested_power_state_index =
 250                                         rdev->pm.current_power_state_index + 1;
 251                 }
 252                 break;
 253         case DYNPM_ACTION_DEFAULT:
 254                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 255                 rdev->pm.dynpm_can_upclock = false;
 256                 break;
 257         case DYNPM_ACTION_NONE:
 258         default:
 259                 DRM_ERROR("Requested mode for not defined action\n");
 260                 return;
 261         }
 262         /* only one clock mode per power state */
 263         rdev->pm.requested_clock_mode_index = 0;
 264
 265         DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
 266                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 267                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 268                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 269                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 270                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 271                   pcie_lanes);
 272 }
 273
 274 /**
 275  * r100_pm_init_profile - Initialize power profiles callback.
 276  *
 277  * @rdev: radeon_device pointer
 278  *
 279  * Initialize the power states used in profile mode
 280  * (r1xx-r3xx).
 281  * Used for profile mode only.
 282  */
 283 void r100_pm_init_profile(struct radeon_device *rdev)
 284 {
 285         /* default */
 286         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 287         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 288         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 289         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 290         /* low sh */
 291         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 292         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 293         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 294         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 295         /* mid sh */
 296         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 297         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 298         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 299         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 300         /* high sh */
 301         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 302         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 303         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 304         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 305         /* low mh */
 306         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 307         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 308         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 309         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 310         /* mid mh */
 311         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 312         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 313         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 314         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 315         /* high mh */
 316         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 317         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 318         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 319         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 320 }
 321
 322 /**
 323  * r100_pm_misc - set additional pm hw parameters callback.
 324  *
 325  * @rdev: radeon_device pointer
 326  *
 327  * Set non-clock parameters associated with a power state
 328  * (voltage, pcie lanes, etc.) (r1xx-r4xx).
 329  */
 330 void r100_pm_misc(struct radeon_device *rdev)
 331 {
 332         int requested_index = rdev->pm.requested_power_state_index;
 333         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
 334         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
 335         u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
 336
 337         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
 338                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
 339                         tmp = RREG32(voltage->gpio.reg);
 340                         if (voltage->active_high)
 341                                 tmp |= voltage->gpio.mask;
 342                         else
 343                                 tmp &= ~(voltage->gpio.mask);
 344                         WREG32(voltage->gpio.reg, tmp);
 345                         if (voltage->delay)
 346                                 udelay(voltage->delay);
 347                 } else {
 348                         tmp = RREG32(voltage->gpio.reg);
 349                         if (voltage->active_high)
 350                                 tmp &= ~voltage->gpio.mask;
 351                         else
 352                                 tmp |= voltage->gpio.mask;
 353                         WREG32(voltage->gpio.reg, tmp);
 354                         if (voltage->delay)
 355                                 udelay(voltage->delay);
 356                 }
 357         }
 358
 359         sclk_cntl = RREG32_PLL(SCLK_CNTL);
 360         sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
 361         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
 362         sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
 363         sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
 364         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
 365                 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
 366                 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
 367                         sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
 368                 else
 369                         sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
 370                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
 371                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
 372                 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
 373                         sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
 374         } else
 375                 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
 376
 377         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
 378                 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
 379                 if (voltage->delay) {
 380                         sclk_more_cntl |= VOLTAGE_DROP_SYNC;
 381                         switch (voltage->delay) {
 382                         case 33:
 383                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
 384                                 break;
 385                         case 66:
 386                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
 387                                 break;
 388                         case 99:
 389                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
 390                                 break;
 391                         case 132:
 392                                 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
 393                                 break;
 394                         }
 395                 } else
 396                         sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
 397         } else
 398                 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
 399
 400         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
 401                 sclk_cntl &= ~FORCE_HDP;
 402         else
 403                 sclk_cntl |= FORCE_HDP;
 404
 405         WREG32_PLL(SCLK_CNTL, sclk_cntl);
 406         WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
 407         WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
 408
 409         /* set pcie lanes */
 410         if ((rdev->flags & RADEON_IS_PCIE) &&
 411             !(rdev->flags & RADEON_IS_IGP) &&
 412             rdev->asic->pm.set_pcie_lanes &&
 413             (ps->pcie_lanes !=
 414              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
 415                 radeon_set_pcie_lanes(rdev,
 416                                       ps->pcie_lanes);
 417                 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
 418         }
 419 }
 420
 421 /**
 422  * r100_pm_prepare - pre-power state change callback.
 423  *
 424  * @rdev: radeon_device pointer
 425  *
 426  * Prepare for a power state change (r1xx-r4xx).
 427  */
 428 void r100_pm_prepare(struct radeon_device *rdev)
 429 {
 430         struct drm_device *ddev = rdev->ddev;
 431         struct drm_crtc *crtc;
 432         struct radeon_crtc *radeon_crtc;
 433         u32 tmp;
 434
 435         /* disable any active CRTCs */
 436         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 437                 radeon_crtc = to_radeon_crtc(crtc);
 438                 if (radeon_crtc->enabled) {
 439                         if (radeon_crtc->crtc_id) {
 440                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 441                                 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
 442                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 443                         } else {
 444                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 445                                 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
 446                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 447                         }
 448                 }
 449         }
 450 }
 451
 452 /**
 453  * r100_pm_finish - post-power state change callback.
 454  *
 455  * @rdev: radeon_device pointer
 456  *
 457  * Clean up after a power state change (r1xx-r4xx).
 458  */
 459 void r100_pm_finish(struct radeon_device *rdev)
 460 {
 461         struct drm_device *ddev = rdev->ddev;
 462         struct drm_crtc *crtc;
 463         struct radeon_crtc *radeon_crtc;
 464         u32 tmp;
 465
 466         /* enable any active CRTCs */
 467         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
 468                 radeon_crtc = to_radeon_crtc(crtc);
 469                 if (radeon_crtc->enabled) {
 470                         if (radeon_crtc->crtc_id) {
 471                                 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
 472                                 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
 473                                 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
 474                         } else {
 475                                 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
 476                                 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
 477                                 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
 478                         }
 479                 }
 480         }
 481 }
 482
 483 /**
 484  * r100_gui_idle - gui idle callback.
 485  *
 486  * @rdev: radeon_device pointer
 487  *
 488  * Check of the GUI (2D/3D engines) are idle (r1xx-r5xx).
 489  * Returns true if idle, false if not.
 490  */
 491 bool r100_gui_idle(struct radeon_device *rdev)
 492 {
 493         if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
 494                 return false;
 495         else
 496                 return true;
 497 }
 498
 499 /* hpd for digital panel detect/disconnect */
 500 /**
 501  * r100_hpd_sense - hpd sense callback.
 502  *
 503  * @rdev: radeon_device pointer
 504  * @hpd: hpd (hotplug detect) pin
 505  *
 506  * Checks if a digital monitor is connected (r1xx-r4xx).
 507  * Returns true if connected, false if not connected.
 508  */
 509 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 510 {
 511         bool connected = false;
 512
 513         switch (hpd) {
 514         case RADEON_HPD_1:
 515                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
 516                         connected = true;
 517                 break;
 518         case RADEON_HPD_2:
 519                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
 520                         connected = true;
 521                 break;
 522         default:
 523                 break;
 524         }
 525         return connected;
 526 }
 527
 528 /**
 529  * r100_hpd_set_polarity - hpd set polarity callback.
 530  *
 531  * @rdev: radeon_device pointer
 532  * @hpd: hpd (hotplug detect) pin
 533  *
 534  * Set the polarity of the hpd pin (r1xx-r4xx).
 535  */
 536 void r100_hpd_set_polarity(struct radeon_device *rdev,
 537                            enum radeon_hpd_id hpd)
 538 {
 539         u32 tmp;
 540         bool connected = r100_hpd_sense(rdev, hpd);
 541
 542         switch (hpd) {
 543         case RADEON_HPD_1:
 544                 tmp = RREG32(RADEON_FP_GEN_CNTL);
 545                 if (connected)
 546                         tmp &= ~RADEON_FP_DETECT_INT_POL;
 547                 else
 548                         tmp |= RADEON_FP_DETECT_INT_POL;
 549                 WREG32(RADEON_FP_GEN_CNTL, tmp);
 550                 break;
 551         case RADEON_HPD_2:
 552                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
 553                 if (connected)
 554                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
 555                 else
 556                         tmp |= RADEON_FP2_DETECT_INT_POL;
 557                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
 558                 break;
 559         default:
 560                 break;
 561         }
 562 }
 563
 564 /**
 565  * r100_hpd_init - hpd setup callback.
 566  *
 567  * @rdev: radeon_device pointer
 568  *
 569  * Setup the hpd pins used by the card (r1xx-r4xx).
 570  * Set the polarity, and enable the hpd interrupts.
 571  */
 572 void r100_hpd_init(struct radeon_device *rdev)
 573 {
 574         struct drm_device *dev = rdev->ddev;
 575         struct drm_connector *connector;
 576         unsigned enable = 0;
 577
 578         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 579                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 580                 enable |= 1 << radeon_connector->hpd.hpd;
 581                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
 582         }
 583         radeon_irq_kms_enable_hpd(rdev, enable);
 584 }
 585
 586 /**
 587  * r100_hpd_fini - hpd tear down callback.
 588  *
 589  * @rdev: radeon_device pointer
 590  *
 591  * Tear down the hpd pins used by the card (r1xx-r4xx).
 592  * Disable the hpd interrupts.
 593  */
 594 void r100_hpd_fini(struct radeon_device *rdev)
 595 {
 596         struct drm_device *dev = rdev->ddev;
 597         struct drm_connector *connector;
 598         unsigned disable = 0;
 599
 600         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 601                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 602                 disable |= 1 << radeon_connector->hpd.hpd;
 603         }
 604         radeon_irq_kms_disable_hpd(rdev, disable);
 605 }
 606
 607 /*
 608  * PCI GART
 609  */
 610 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
 611 {
 612         /* TODO: can we do somethings here ? */
 613         /* It seems hw only cache one entry so we should discard this
 614          * entry otherwise if first GPU GART read hit this entry it
 615          * could end up in wrong address. */
 616 }
 617
 618 int r100_pci_gart_init(struct radeon_device *rdev)
 619 {
 620         int r;
 621
 622         if (rdev->gart.ptr) {
 623                 WARN(1, "R100 PCI GART already initialized\n");
 624                 return 0;
 625         }
 626         /* Initialize common gart structure */
 627         r = radeon_gart_init(rdev);
 628         if (r)
 629                 return r;
 630         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
 631         rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 632         rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 633         return radeon_gart_table_ram_alloc(rdev);
 634 }
 635
 636 int r100_pci_gart_enable(struct radeon_device *rdev)
 637 {
 638         uint32_t tmp;
 639
 640         radeon_gart_restore(rdev);
 641         /* discard memory request outside of configured range */
 642         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 643         WREG32(RADEON_AIC_CNTL, tmp);
 644         /* set address range for PCI address translate */
 645         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
 646         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
 647         /* set PCI GART page-table base address */
 648         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
 649         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
 650         WREG32(RADEON_AIC_CNTL, tmp);
 651         r100_pci_gart_tlb_flush(rdev);
 652         DRM_INFO("PCI GART of %uM enabled (table at 0x%016llX).\n",
 653                  (unsigned)(rdev->mc.gtt_size >> 20),
 654                  (unsigned long long)rdev->gart.table_addr);
 655         rdev->gart.ready = true;
 656         return 0;
 657 }
 658
 659 void r100_pci_gart_disable(struct radeon_device *rdev)
 660 {
 661         uint32_t tmp;
 662
 663         /* discard memory request outside of configured range */
 664         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
 665         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
 666         WREG32(RADEON_AIC_LO_ADDR, 0);
 667         WREG32(RADEON_AIC_HI_ADDR, 0);
 668 }
 669
 670 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
 671 {
 672         u32 *gtt = rdev->gart.ptr;
 673
 674         if (i < 0 || i > rdev->gart.num_gpu_pages) {
 675                 return -EINVAL;
 676         }
 677         gtt[i] = cpu_to_le32(lower_32_bits(addr));
 678         return 0;
 679 }
 680
 681 void r100_pci_gart_fini(struct radeon_device *rdev)
 682 {
 683         radeon_gart_fini(rdev);
 684         r100_pci_gart_disable(rdev);
 685         radeon_gart_table_ram_free(rdev);
 686 }
 687
 688 int r100_irq_set(struct radeon_device *rdev)
 689 {
 690         uint32_t tmp = 0;
 691
 692         if (!rdev->irq.installed) {
 693                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
 694                 WREG32(R_000040_GEN_INT_CNTL, 0);
 695                 return -EINVAL;
 696         }
 697         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
 698                 tmp |= RADEON_SW_INT_ENABLE;
 699         }
 700         if (rdev->irq.crtc_vblank_int[0] ||
 701             atomic_read(&rdev->irq.pflip[0])) {
 702                 tmp |= RADEON_CRTC_VBLANK_MASK;
 703         }
 704         if (rdev->irq.crtc_vblank_int[1] ||
 705             atomic_read(&rdev->irq.pflip[1])) {
 706                 tmp |= RADEON_CRTC2_VBLANK_MASK;
 707         }
 708         if (rdev->irq.hpd[0]) {
 709                 tmp |= RADEON_FP_DETECT_MASK;
 710         }
 711         if (rdev->irq.hpd[1]) {
 712                 tmp |= RADEON_FP2_DETECT_MASK;
 713         }
 714         WREG32(RADEON_GEN_INT_CNTL, tmp);
 715         return 0;
 716 }
 717
 718 void r100_irq_disable(struct radeon_device *rdev)
 719 {
 720         u32 tmp;
 721
 722         WREG32(R_000040_GEN_INT_CNTL, 0);
 723         /* Wait and acknowledge irq */
 724         mdelay(1);
 725         tmp = RREG32(R_000044_GEN_INT_STATUS);
 726         WREG32(R_000044_GEN_INT_STATUS, tmp);
 727 }
 728
 729 static uint32_t r100_irq_ack(struct radeon_device *rdev)
 730 {
 731         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
 732         uint32_t irq_mask = RADEON_SW_INT_TEST |
 733                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
 734                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
 735
 736         if (irqs) {
 737                 WREG32(RADEON_GEN_INT_STATUS, irqs);
 738         }
 739         return irqs & irq_mask;
 740 }
 741
 742 int r100_irq_process(struct radeon_device *rdev)
 743 {
 744         uint32_t status, msi_rearm;
 745         bool queue_hotplug = false;
 746
 747         status = r100_irq_ack(rdev);
 748         if (!status) {
 749                 return IRQ_NONE;
 750         }
 751         if (rdev->shutdown) {
 752                 return IRQ_NONE;
 753         }
 754         while (status) {
 755                 /* SW interrupt */
 756                 if (status & RADEON_SW_INT_TEST) {
 757                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
 758                 }
 759                 /* Vertical blank interrupts */
 760                 if (status & RADEON_CRTC_VBLANK_STAT) {
 761                         if (rdev->irq.crtc_vblank_int[0]) {
 762                                 drm_handle_vblank(rdev->ddev, 0);
 763                                 rdev->pm.vblank_sync = true;
 764                                 wake_up(&rdev->irq.vblank_queue);
 765                         }
 766                         if (atomic_read(&rdev->irq.pflip[0]))
 767                                 radeon_crtc_handle_flip(rdev, 0);
 768                 }
 769                 if (status & RADEON_CRTC2_VBLANK_STAT) {
 770                         if (rdev->irq.crtc_vblank_int[1]) {
 771                                 drm_handle_vblank(rdev->ddev, 1);
 772                                 rdev->pm.vblank_sync = true;
 773                                 wake_up(&rdev->irq.vblank_queue);
 774                         }
 775                         if (atomic_read(&rdev->irq.pflip[1]))
 776                                 radeon_crtc_handle_flip(rdev, 1);
 777                 }
 778                 if (status & RADEON_FP_DETECT_STAT) {
 779                         queue_hotplug = true;
 780                         DRM_DEBUG("HPD1\n");
 781                 }
 782                 if (status & RADEON_FP2_DETECT_STAT) {
 783                         queue_hotplug = true;
 784                         DRM_DEBUG("HPD2\n");
 785                 }
 786                 status = r100_irq_ack(rdev);
 787         }
 788         if (queue_hotplug)
 789                 schedule_work(&rdev->hotplug_work);
 790         if (rdev->msi_enabled) {
 791                 switch (rdev->family) {
 792                 case CHIP_RS400:
 793                 case CHIP_RS480:
 794                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
 795                         WREG32(RADEON_AIC_CNTL, msi_rearm);
 796                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
 797                         break;
 798                 default:
 799                         WREG32(RADEON_MSI_REARM_EN, RV370_MSI_REARM_EN);
 800                         break;
 801                 }
 802         }
 803         return IRQ_HANDLED;
 804 }
 805
 806 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
 807 {
 808         if (crtc == 0)
 809                 return RREG32(RADEON_CRTC_CRNT_FRAME);
 810         else
 811                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
 812 }
 813
 814 /* Who ever call radeon_fence_emit should call ring_lock and ask
 815  * for enough space (today caller are ib schedule and buffer move) */
 816 void r100_fence_ring_emit(struct radeon_device *rdev,
 817                           struct radeon_fence *fence)
 818 {
 819         struct radeon_ring *ring = &rdev->ring[fence->ring];
 820
 821         /* We have to make sure that caches are flushed before
 822          * CPU might read something from VRAM. */
 823         radeon_ring_write(ring, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
 824         radeon_ring_write(ring, RADEON_RB3D_DC_FLUSH_ALL);
 825         radeon_ring_write(ring, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
 826         radeon_ring_write(ring, RADEON_RB3D_ZC_FLUSH_ALL);
 827         /* Wait until IDLE & CLEAN */
 828         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 829         radeon_ring_write(ring, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
 830         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 831         radeon_ring_write(ring, rdev->config.r100.hdp_cntl |
 832                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
 833         radeon_ring_write(ring, PACKET0(RADEON_HOST_PATH_CNTL, 0));
 834         radeon_ring_write(ring, rdev->config.r100.hdp_cntl);
 835         /* Emit fence sequence & fire IRQ */
 836         radeon_ring_write(ring, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
 837         radeon_ring_write(ring, fence->seq);
 838         radeon_ring_write(ring, PACKET0(RADEON_GEN_INT_STATUS, 0));
 839         radeon_ring_write(ring, RADEON_SW_INT_FIRE);
 840 }
 841
 842 bool r100_semaphore_ring_emit(struct radeon_device *rdev,
 843                               struct radeon_ring *ring,
 844                               struct radeon_semaphore *semaphore,
 845                               bool emit_wait)
 846 {
 847         /* Unused on older asics, since we don't have semaphores or multiple rings */
 848         BUG();
 849         return false;
 850 }
 851
 852 int r100_copy_blit(struct radeon_device *rdev,
 853                    uint64_t src_offset,
 854                    uint64_t dst_offset,
 855                    unsigned num_gpu_pages,
 856                    struct radeon_fence **fence)
 857 {
 858         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
 859         uint32_t cur_pages;
 860         uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
 861         uint32_t pitch;
 862         uint32_t stride_pixels;
 863         unsigned ndw;
 864         int num_loops;
 865         int r = 0;
 866
 867         /* radeon limited to 16k stride */
 868         stride_bytes &= 0x3fff;
 869         /* radeon pitch is /64 */
 870         pitch = stride_bytes / 64;
 871         stride_pixels = stride_bytes / 4;
 872         num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
 873
 874         /* Ask for enough room for blit + flush + fence */
 875         ndw = 64 + (10 * num_loops);
 876         r = radeon_ring_lock(rdev, ring, ndw);
 877         if (r) {
 878                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
 879                 return -EINVAL;
 880         }
 881         while (num_gpu_pages > 0) {
 882                 cur_pages = num_gpu_pages;
 883                 if (cur_pages > 8191) {
 884                         cur_pages = 8191;
 885                 }
 886                 num_gpu_pages -= cur_pages;
 887
 888                 /* pages are in Y direction - height
 889                    page width in X direction - width */
 890                 radeon_ring_write(ring, PACKET3(PACKET3_BITBLT_MULTI, 8));
 891                 radeon_ring_write(ring,
 892                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
 893                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 894                                   RADEON_GMC_SRC_CLIPPING |
 895                                   RADEON_GMC_DST_CLIPPING |
 896                                   RADEON_GMC_BRUSH_NONE |
 897                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
 898                                   RADEON_GMC_SRC_DATATYPE_COLOR |
 899                                   RADEON_ROP3_S |
 900                                   RADEON_DP_SRC_SOURCE_MEMORY |
 901                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
 902                                   RADEON_GMC_WR_MSK_DIS);
 903                 radeon_ring_write(ring, (pitch << 22) | (src_offset >> 10));
 904                 radeon_ring_write(ring, (pitch << 22) | (dst_offset >> 10));
 905                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 906                 radeon_ring_write(ring, 0);
 907                 radeon_ring_write(ring, (0x1fff) | (0x1fff << 16));
 908                 radeon_ring_write(ring, num_gpu_pages);
 909                 radeon_ring_write(ring, num_gpu_pages);
 910                 radeon_ring_write(ring, cur_pages | (stride_pixels << 16));
 911         }
 912         radeon_ring_write(ring, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
 913         radeon_ring_write(ring, RADEON_RB2D_DC_FLUSH_ALL);
 914         radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
 915         radeon_ring_write(ring,
 916                           RADEON_WAIT_2D_IDLECLEAN |
 917                           RADEON_WAIT_HOST_IDLECLEAN |
 918                           RADEON_WAIT_DMA_GUI_IDLE);
 919         if (fence) {
 920                 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
 921         }
 922         radeon_ring_unlock_commit(rdev, ring);
 923         return r;
 924 }
 925
 926 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
 927 {
 928         unsigned i;
 929         u32 tmp;
 930
 931         for (i = 0; i < rdev->usec_timeout; i++) {
 932                 tmp = RREG32(R_000E40_RBBM_STATUS);
 933                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
 934                         return 0;
 935                 }
 936                 udelay(1);
 937         }
 938         return -1;
 939 }
 940
 941 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
 942 {
 943         int r;
 944
 945         r = radeon_ring_lock(rdev, ring, 2);
 946         if (r) {
 947                 return;
 948         }
 949         radeon_ring_write(ring, PACKET0(RADEON_ISYNC_CNTL, 0));
 950         radeon_ring_write(ring,
 951                           RADEON_ISYNC_ANY2D_IDLE3D |
 952                           RADEON_ISYNC_ANY3D_IDLE2D |
 953                           RADEON_ISYNC_WAIT_IDLEGUI |
 954                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 955         radeon_ring_unlock_commit(rdev, ring);
 956 }
 957
 958
 959 /* Load the microcode for the CP */
 960 static int r100_cp_init_microcode(struct radeon_device *rdev)
 961 {
 962         const char *fw_name = NULL;
 963         int err;
 964
 965         DRM_DEBUG_KMS("\n");
 966
 967         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
 968             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
 969             (rdev->family == CHIP_RS200)) {
 970                 DRM_INFO("Loading R100 Microcode\n");
 971                 fw_name = FIRMWARE_R100;
 972         } else if ((rdev->family == CHIP_R200) ||
 973                    (rdev->family == CHIP_RV250) ||
 974                    (rdev->family == CHIP_RV280) ||
 975                    (rdev->family == CHIP_RS300)) {
 976                 DRM_INFO("Loading R200 Microcode\n");
 977                 fw_name = FIRMWARE_R200;
 978         } else if ((rdev->family == CHIP_R300) ||
 979                    (rdev->family == CHIP_R350) ||
 980                    (rdev->family == CHIP_RV350) ||
 981                    (rdev->family == CHIP_RV380) ||
 982                    (rdev->family == CHIP_RS400) ||
 983                    (rdev->family == CHIP_RS480)) {
 984                 DRM_INFO("Loading R300 Microcode\n");
 985                 fw_name = FIRMWARE_R300;
 986         } else if ((rdev->family == CHIP_R420) ||
 987                    (rdev->family == CHIP_R423) ||
 988                    (rdev->family == CHIP_RV410)) {
 989                 DRM_INFO("Loading R400 Microcode\n");
 990                 fw_name = FIRMWARE_R420;
 991         } else if ((rdev->family == CHIP_RS690) ||
 992                    (rdev->family == CHIP_RS740)) {
 993                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 994                 fw_name = FIRMWARE_RS690;
 995         } else if (rdev->family == CHIP_RS600) {
 996                 DRM_INFO("Loading RS600 Microcode\n");
 997                 fw_name = FIRMWARE_RS600;
 998         } else if ((rdev->family == CHIP_RV515) ||
 999                    (rdev->family == CHIP_R520) ||
1000                    (rdev->family == CHIP_RV530) ||
1001                    (rdev->family == CHIP_R580) ||
1002                    (rdev->family == CHIP_RV560) ||
1003                    (rdev->family == CHIP_RV570)) {
1004                 DRM_INFO("Loading R500 Microcode\n");
1005                 fw_name = FIRMWARE_R520;
1006         }
1007
1008         err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
1009         if (err) {
1010                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
1011                        fw_name);
1012         } else if (rdev->me_fw->size % 8) {
1013                 printk(KERN_ERR
1014                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
1015                        rdev->me_fw->size, fw_name);
1016                 err = -EINVAL;
1017                 release_firmware(rdev->me_fw);
1018                 rdev->me_fw = NULL;
1019         }
1020         return err;
1021 }
1022
1023 u32 r100_gfx_get_rptr(struct radeon_device *rdev,
1024                       struct radeon_ring *ring)
1025 {
1026         u32 rptr;
1027
1028         if (rdev->wb.enabled)
1029                 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
1030         else
1031                 rptr = RREG32(RADEON_CP_RB_RPTR);
1032
1033         return rptr;
1034 }
1035
1036 u32 r100_gfx_get_wptr(struct radeon_device *rdev,
1037                       struct radeon_ring *ring)
1038 {
1039         u32 wptr;
1040
1041         wptr = RREG32(RADEON_CP_RB_WPTR);
1042
1043         return wptr;
1044 }
1045
1046 void r100_gfx_set_wptr(struct radeon_device *rdev,
1047                        struct radeon_ring *ring)
1048 {
1049         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1050         (void)RREG32(RADEON_CP_RB_WPTR);
1051 }
1052
1053 static void r100_cp_load_microcode(struct radeon_device *rdev)
1054 {
1055         const __be32 *fw_data;
1056         int i, size;
1057
1058         if (r100_gui_wait_for_idle(rdev)) {
1059                 printk(KERN_WARNING "Failed to wait GUI idle while "
1060                        "programming pipes. Bad things might happen.\n");
1061         }
1062
1063         if (rdev->me_fw) {
1064                 size = rdev->me_fw->size / 4;
1065                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
1066                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
1067                 for (i = 0; i < size; i += 2) {
1068                         WREG32(RADEON_CP_ME_RAM_DATAH,
1069                                be32_to_cpup(&fw_data[i]));
1070                         WREG32(RADEON_CP_ME_RAM_DATAL,
1071                                be32_to_cpup(&fw_data[i + 1]));
1072                 }
1073         }
1074 }
1075
1076 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1077 {
1078         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1079         unsigned rb_bufsz;
1080         unsigned rb_blksz;
1081         unsigned max_fetch;
1082         unsigned pre_write_timer;
1083         unsigned pre_write_limit;
1084         unsigned indirect2_start;
1085         unsigned indirect1_start;
1086         uint32_t tmp;
1087         int r;
1088
1089         if (r100_debugfs_cp_init(rdev)) {
1090                 DRM_ERROR("Failed to register debugfs file for CP !\n");
1091         }
1092         if (!rdev->me_fw) {
1093                 r = r100_cp_init_microcode(rdev);
1094                 if (r) {
1095                         DRM_ERROR("Failed to load firmware!\n");
1096                         return r;
1097                 }
1098         }
1099
1100         /* Align ring size */
1101         rb_bufsz = order_base_2(ring_size / 8);
1102         ring_size = (1 << (rb_bufsz + 1)) * 4;
1103         r100_cp_load_microcode(rdev);
1104         r = radeon_ring_init(rdev, ring, ring_size, RADEON_WB_CP_RPTR_OFFSET,
1105                              RADEON_CP_PACKET2);
1106         if (r) {
1107                 return r;
1108         }
1109         /* Each time the cp read 1024 bytes (16 dword/quadword) update
1110          * the rptr copy in system ram */
1111         rb_blksz = 9;
1112         /* cp will read 128bytes at a time (4 dwords) */
1113         max_fetch = 1;
1114         ring->align_mask = 16 - 1;
1115         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1116         pre_write_timer = 64;
1117         /* Force CP_RB_WPTR write if written more than one time before the
1118          * delay expire
1119          */
1120         pre_write_limit = 0;
1121         /* Setup the cp cache like this (cache size is 96 dwords) :
1122          *      RING            0  to 15
1123          *      INDIRECT1       16 to 79
1124          *      INDIRECT2       80 to 95
1125          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1126          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
1127          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
1128          * Idea being that most of the gpu cmd will be through indirect1 buffer
1129          * so it gets the bigger cache.
1130          */
1131         indirect2_start = 80;
1132         indirect1_start = 16;
1133         /* cp setup */
1134         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
1135         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
1136                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1137                REG_SET(RADEON_MAX_FETCH, max_fetch));
1138 #ifdef __BIG_ENDIAN
1139         tmp |= RADEON_BUF_SWAP_32BIT;
1140 #endif
1141         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1142
1143         /* Set ring address */
1144         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)ring->gpu_addr);
1145         WREG32(RADEON_CP_RB_BASE, ring->gpu_addr);
1146         /* Force read & write ptr to 0 */
1147         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1148         WREG32(RADEON_CP_RB_RPTR_WR, 0);
1149         ring->wptr = 0;
1150         WREG32(RADEON_CP_RB_WPTR, ring->wptr);
1151
1152         /* set the wb address whether it's enabled or not */
1153         WREG32(R_00070C_CP_RB_RPTR_ADDR,
1154                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1155         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1156
1157         if (rdev->wb.enabled)
1158                 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1159         else {
1160                 tmp |= RADEON_RB_NO_UPDATE;
1161                 WREG32(R_000770_SCRATCH_UMSK, 0);
1162         }
1163
1164         WREG32(RADEON_CP_RB_CNTL, tmp);
1165         udelay(10);
1166         /* Set cp mode to bus mastering & enable cp*/
1167         WREG32(RADEON_CP_CSQ_MODE,
1168                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1169                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1170         WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1171         WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1172         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1173
1174         /* at this point everything should be setup correctly to enable master */
1175         pci_set_master(rdev->pdev);
1176
1177         radeon_ring_start(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1178         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1179         if (r) {
1180                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1181                 return r;
1182         }
1183         ring->ready = true;
1184         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1185
1186         if (!ring->rptr_save_reg /* not resuming from suspend */
1187             && radeon_ring_supports_scratch_reg(rdev, ring)) {
1188                 r = radeon_scratch_get(rdev, &ring->rptr_save_reg);
1189                 if (r) {
1190                         DRM_ERROR("failed to get scratch reg for rptr save (%d).\n", r);
1191                         ring->rptr_save_reg = 0;
1192                 }
1193         }
1194         return 0;
1195 }
1196
1197 void r100_cp_fini(struct radeon_device *rdev)
1198 {
1199         if (r100_cp_wait_for_idle(rdev)) {
1200                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1201         }
1202         /* Disable ring */
1203         r100_cp_disable(rdev);
1204         radeon_scratch_free(rdev, rdev->ring[RADEON_RING_TYPE_GFX_INDEX].rptr_save_reg);
1205         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1206         DRM_INFO("radeon: cp finalized\n");
1207 }
1208
1209 void r100_cp_disable(struct radeon_device *rdev)
1210 {
1211         /* Disable ring */
1212         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1213         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1214         WREG32(RADEON_CP_CSQ_MODE, 0);
1215         WREG32(RADEON_CP_CSQ_CNTL, 0);
1216         WREG32(R_000770_SCRATCH_UMSK, 0);
1217         if (r100_gui_wait_for_idle(rdev)) {
1218                 printk(KERN_WARNING "Failed to wait GUI idle while "
1219                        "programming pipes. Bad things might happen.\n");
1220         }
1221 }
1222
1223 /*
1224  * CS functions
1225  */
1226 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1227                             struct radeon_cs_packet *pkt,
1228                             unsigned idx,
1229                             unsigned reg)
1230 {
1231         int r;
1232         u32 tile_flags = 0;
1233         u32 tmp;
1234         struct radeon_cs_reloc *reloc;
1235         u32 value;
1236
1237         r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1238         if (r) {
1239                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1240                           idx, reg);
1241                 radeon_cs_dump_packet(p, pkt);
1242                 return r;
1243         }
1244
1245         value = radeon_get_ib_value(p, idx);
1246         tmp = value & 0x003fffff;
1247         tmp += (((u32)reloc->gpu_offset) >> 10);
1248
1249         if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1250                 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1251                         tile_flags |= RADEON_DST_TILE_MACRO;
1252                 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1253                         if (reg == RADEON_SRC_PITCH_OFFSET) {
1254                                 DRM_ERROR("Cannot src blit from microtiled surface\n");
1255                                 radeon_cs_dump_packet(p, pkt);
1256                                 return -EINVAL;
1257                         }
1258                         tile_flags |= RADEON_DST_TILE_MICRO;
1259                 }
1260
1261                 tmp |= tile_flags;
1262                 p->ib.ptr[idx] = (value & 0x3fc00000) | tmp;
1263         } else
1264                 p->ib.ptr[idx] = (value & 0xffc00000) | tmp;
1265         return 0;
1266 }
1267
1268 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1269                              struct radeon_cs_packet *pkt,
1270                              int idx)
1271 {
1272         unsigned c, i;
1273         struct radeon_cs_reloc *reloc;
1274         struct r100_cs_track *track;
1275         int r = 0;
1276         volatile uint32_t *ib;
1277         u32 idx_value;
1278
1279         ib = p->ib.ptr;
1280         track = (struct r100_cs_track *)p->track;
1281         c = radeon_get_ib_value(p, idx++) & 0x1F;
1282         if (c > 16) {
1283             DRM_ERROR("Only 16 vertex buffers are allowed %d\n",
1284                       pkt->opcode);
1285             radeon_cs_dump_packet(p, pkt);
1286             return -EINVAL;
1287         }
1288         track->num_arrays = c;
1289         for (i = 0; i < (c - 1); i+=2, idx+=3) {
1290                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1291                 if (r) {
1292                         DRM_ERROR("No reloc for packet3 %d\n",
1293                                   pkt->opcode);
1294                         radeon_cs_dump_packet(p, pkt);
1295                         return r;
1296                 }
1297                 idx_value = radeon_get_ib_value(p, idx);
1298                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1299
1300                 track->arrays[i + 0].esize = idx_value >> 8;
1301                 track->arrays[i + 0].robj = reloc->robj;
1302                 track->arrays[i + 0].esize &= 0x7F;
1303                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1304                 if (r) {
1305                         DRM_ERROR("No reloc for packet3 %d\n",
1306                                   pkt->opcode);
1307                         radeon_cs_dump_packet(p, pkt);
1308                         return r;
1309                 }
1310                 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1311                 track->arrays[i + 1].robj = reloc->robj;
1312                 track->arrays[i + 1].esize = idx_value >> 24;
1313                 track->arrays[i + 1].esize &= 0x7F;
1314         }
1315         if (c & 1) {
1316                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1317                 if (r) {
1318                         DRM_ERROR("No reloc for packet3 %d\n",
1319                                           pkt->opcode);
1320                         radeon_cs_dump_packet(p, pkt);
1321                         return r;
1322                 }
1323                 idx_value = radeon_get_ib_value(p, idx);
1324                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1325                 track->arrays[i + 0].robj = reloc->robj;
1326                 track->arrays[i + 0].esize = idx_value >> 8;
1327                 track->arrays[i + 0].esize &= 0x7F;
1328         }
1329         return r;
1330 }
1331
1332 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1333                           struct radeon_cs_packet *pkt,
1334                           const unsigned *auth, unsigned n,
1335                           radeon_packet0_check_t check)
1336 {
1337         unsigned reg;
1338         unsigned i, j, m;
1339         unsigned idx;
1340         int r;
1341
1342         idx = pkt->idx + 1;
1343         reg = pkt->reg;
1344         /* Check that register fall into register range
1345          * determined by the number of entry (n) in the
1346          * safe register bitmap.
1347          */
1348         if (pkt->one_reg_wr) {
1349                 if ((reg >> 7) > n) {
1350                         return -EINVAL;
1351                 }
1352         } else {
1353                 if (((reg + (pkt->count << 2)) >> 7) > n) {
1354                         return -EINVAL;
1355                 }
1356         }
1357         for (i = 0; i <= pkt->count; i++, idx++) {
1358                 j = (reg >> 7);
1359                 m = 1 << ((reg >> 2) & 31);
1360                 if (auth[j] & m) {
1361                         r = check(p, pkt, idx, reg);
1362                         if (r) {
1363                                 return r;
1364                         }
1365                 }
1366                 if (pkt->one_reg_wr) {
1367                         if (!(auth[j] & m)) {
1368                                 break;
1369                         }
1370                 } else {
1371                         reg += 4;
1372                 }
1373         }
1374         return 0;
1375 }
1376
1377 /**
1378  * r100_cs_packet_next_vline() - parse userspace VLINE packet
1379  * @parser:             parser structure holding parsing context.
1380  *
1381  * Userspace sends a special sequence for VLINE waits.
1382  * PACKET0 - VLINE_START_END + value
1383  * PACKET0 - WAIT_UNTIL +_value
1384  * RELOC (P3) - crtc_id in reloc.
1385  *
1386  * This function parses this and relocates the VLINE START END
1387  * and WAIT UNTIL packets to the correct crtc.
1388  * It also detects a switched off crtc and nulls out the
1389  * wait in that case.
1390  */
1391 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1392 {
1393         struct drm_mode_object *obj;
1394         struct drm_crtc *crtc;
1395         struct radeon_crtc *radeon_crtc;
1396         struct radeon_cs_packet p3reloc, waitreloc;
1397         int crtc_id;
1398         int r;
1399         uint32_t header, h_idx, reg;
1400         volatile uint32_t *ib;
1401
1402         ib = p->ib.ptr;
1403
1404         /* parse the wait until */
1405         r = radeon_cs_packet_parse(p, &waitreloc, p->idx);
1406         if (r)
1407                 return r;
1408
1409         /* check its a wait until and only 1 count */
1410         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1411             waitreloc.count != 0) {
1412                 DRM_ERROR("vline wait had illegal wait until segment\n");
1413                 return -EINVAL;
1414         }
1415
1416         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1417                 DRM_ERROR("vline wait had illegal wait until\n");
1418                 return -EINVAL;
1419         }
1420
1421         /* jump over the NOP */
1422         r = radeon_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1423         if (r)
1424                 return r;
1425
1426         h_idx = p->idx - 2;
1427         p->idx += waitreloc.count + 2;
1428         p->idx += p3reloc.count + 2;
1429
1430         header = radeon_get_ib_value(p, h_idx);
1431         crtc_id = radeon_get_ib_value(p, h_idx + 5);
1432         reg = R100_CP_PACKET0_GET_REG(header);
1433         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1434         if (!obj) {
1435                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1436                 return -ENOENT;
1437         }
1438         crtc = obj_to_crtc(obj);
1439         radeon_crtc = to_radeon_crtc(crtc);
1440         crtc_id = radeon_crtc->crtc_id;
1441
1442         if (!crtc->enabled) {
1443                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1444                 ib[h_idx + 2] = PACKET2(0);
1445                 ib[h_idx + 3] = PACKET2(0);
1446         } else if (crtc_id == 1) {
1447                 switch (reg) {
1448                 case AVIVO_D1MODE_VLINE_START_END:
1449                         header &= ~R300_CP_PACKET0_REG_MASK;
1450                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1451                         break;
1452                 case RADEON_CRTC_GUI_TRIG_VLINE:
1453                         header &= ~R300_CP_PACKET0_REG_MASK;
1454                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1455                         break;
1456                 default:
1457                         DRM_ERROR("unknown crtc reloc\n");
1458                         return -EINVAL;
1459                 }
1460                 ib[h_idx] = header;
1461                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1462         }
1463
1464         return 0;
1465 }
1466
1467 static int r100_get_vtx_size(uint32_t vtx_fmt)
1468 {
1469         int vtx_size;
1470         vtx_size = 2;
1471         /* ordered according to bits in spec */
1472         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1473                 vtx_size++;
1474         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1475                 vtx_size += 3;
1476         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1477                 vtx_size++;
1478         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1479                 vtx_size++;
1480         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1481                 vtx_size += 3;
1482         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1483                 vtx_size++;
1484         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1485                 vtx_size++;
1486         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1487                 vtx_size += 2;
1488         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1489                 vtx_size += 2;
1490         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1491                 vtx_size++;
1492         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1493                 vtx_size += 2;
1494         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1495                 vtx_size++;
1496         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1497                 vtx_size += 2;
1498         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1499                 vtx_size++;
1500         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1501                 vtx_size++;
1502         /* blend weight */
1503         if (vtx_fmt & (0x7 << 15))
1504                 vtx_size += (vtx_fmt >> 15) & 0x7;
1505         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1506                 vtx_size += 3;
1507         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1508                 vtx_size += 2;
1509         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1510                 vtx_size++;
1511         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1512                 vtx_size++;
1513         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1514                 vtx_size++;
1515         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1516                 vtx_size++;
1517         return vtx_size;
1518 }
1519
1520 static int r100_packet0_check(struct radeon_cs_parser *p,
1521                               struct radeon_cs_packet *pkt,
1522                               unsigned idx, unsigned reg)
1523 {
1524         struct radeon_cs_reloc *reloc;
1525         struct r100_cs_track *track;
1526         volatile uint32_t *ib;
1527         uint32_t tmp;
1528         int r;
1529         int i, face;
1530         u32 tile_flags = 0;
1531         u32 idx_value;
1532
1533         ib = p->ib.ptr;
1534         track = (struct r100_cs_track *)p->track;
1535
1536         idx_value = radeon_get_ib_value(p, idx);
1537
1538         switch (reg) {
1539         case RADEON_CRTC_GUI_TRIG_VLINE:
1540                 r = r100_cs_packet_parse_vline(p);
1541                 if (r) {
1542                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1543                                   idx, reg);
1544                         radeon_cs_dump_packet(p, pkt);
1545                         return r;
1546                 }
1547                 break;
1548                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1549                  * range access */
1550         case RADEON_DST_PITCH_OFFSET:
1551         case RADEON_SRC_PITCH_OFFSET:
1552                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1553                 if (r)
1554                         return r;
1555                 break;
1556         case RADEON_RB3D_DEPTHOFFSET:
1557                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1558                 if (r) {
1559                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1560                                   idx, reg);
1561                         radeon_cs_dump_packet(p, pkt);
1562                         return r;
1563                 }
1564                 track->zb.robj = reloc->robj;
1565                 track->zb.offset = idx_value;
1566                 track->zb_dirty = true;
1567                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1568                 break;
1569         case RADEON_RB3D_COLOROFFSET:
1570                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1571                 if (r) {
1572                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1573                                   idx, reg);
1574                         radeon_cs_dump_packet(p, pkt);
1575                         return r;
1576                 }
1577                 track->cb[0].robj = reloc->robj;
1578                 track->cb[0].offset = idx_value;
1579                 track->cb_dirty = true;
1580                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1581                 break;
1582         case RADEON_PP_TXOFFSET_0:
1583         case RADEON_PP_TXOFFSET_1:
1584         case RADEON_PP_TXOFFSET_2:
1585                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1586                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1587                 if (r) {
1588                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1589                                   idx, reg);
1590                         radeon_cs_dump_packet(p, pkt);
1591                         return r;
1592                 }
1593                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1594                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
1595                                 tile_flags |= RADEON_TXO_MACRO_TILE;
1596                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
1597                                 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1598
1599                         tmp = idx_value & ~(0x7 << 2);
1600                         tmp |= tile_flags;
1601                         ib[idx] = tmp + ((u32)reloc->gpu_offset);
1602                 } else
1603                         ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1604                 track->textures[i].robj = reloc->robj;
1605                 track->tex_dirty = true;
1606                 break;
1607         case RADEON_PP_CUBIC_OFFSET_T0_0:
1608         case RADEON_PP_CUBIC_OFFSET_T0_1:
1609         case RADEON_PP_CUBIC_OFFSET_T0_2:
1610         case RADEON_PP_CUBIC_OFFSET_T0_3:
1611         case RADEON_PP_CUBIC_OFFSET_T0_4:
1612                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1613                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1614                 if (r) {
1615                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1616                                   idx, reg);
1617                         radeon_cs_dump_packet(p, pkt);
1618                         return r;
1619                 }
1620                 track->textures[0].cube_info[i].offset = idx_value;
1621                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1622                 track->textures[0].cube_info[i].robj = reloc->robj;
1623                 track->tex_dirty = true;
1624                 break;
1625         case RADEON_PP_CUBIC_OFFSET_T1_0:
1626         case RADEON_PP_CUBIC_OFFSET_T1_1:
1627         case RADEON_PP_CUBIC_OFFSET_T1_2:
1628         case RADEON_PP_CUBIC_OFFSET_T1_3:
1629         case RADEON_PP_CUBIC_OFFSET_T1_4:
1630                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1631                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1632                 if (r) {
1633                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1634                                   idx, reg);
1635                         radeon_cs_dump_packet(p, pkt);
1636                         return r;
1637                 }
1638                 track->textures[1].cube_info[i].offset = idx_value;
1639                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1640                 track->textures[1].cube_info[i].robj = reloc->robj;
1641                 track->tex_dirty = true;
1642                 break;
1643         case RADEON_PP_CUBIC_OFFSET_T2_0:
1644         case RADEON_PP_CUBIC_OFFSET_T2_1:
1645         case RADEON_PP_CUBIC_OFFSET_T2_2:
1646         case RADEON_PP_CUBIC_OFFSET_T2_3:
1647         case RADEON_PP_CUBIC_OFFSET_T2_4:
1648                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1649                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1650                 if (r) {
1651                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1652                                   idx, reg);
1653                         radeon_cs_dump_packet(p, pkt);
1654                         return r;
1655                 }
1656                 track->textures[2].cube_info[i].offset = idx_value;
1657                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1658                 track->textures[2].cube_info[i].robj = reloc->robj;
1659                 track->tex_dirty = true;
1660                 break;
1661         case RADEON_RE_WIDTH_HEIGHT:
1662                 track->maxy = ((idx_value >> 16) & 0x7FF);
1663                 track->cb_dirty = true;
1664                 track->zb_dirty = true;
1665                 break;
1666         case RADEON_RB3D_COLORPITCH:
1667                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1668                 if (r) {
1669                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1670                                   idx, reg);
1671                         radeon_cs_dump_packet(p, pkt);
1672                         return r;
1673                 }
1674                 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1675                         if (reloc->tiling_flags & RADEON_TILING_MACRO)
1676                                 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1677                         if (reloc->tiling_flags & RADEON_TILING_MICRO)
1678                                 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1679
1680                         tmp = idx_value & ~(0x7 << 16);
1681                         tmp |= tile_flags;
1682                         ib[idx] = tmp;
1683                 } else
1684                         ib[idx] = idx_value;
1685
1686                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1687                 track->cb_dirty = true;
1688                 break;
1689         case RADEON_RB3D_DEPTHPITCH:
1690                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1691                 track->zb_dirty = true;
1692                 break;
1693         case RADEON_RB3D_CNTL:
1694                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1695                 case 7:
1696                 case 8:
1697                 case 9:
1698                 case 11:
1699                 case 12:
1700                         track->cb[0].cpp = 1;
1701                         break;
1702                 case 3:
1703                 case 4:
1704                 case 15:
1705                         track->cb[0].cpp = 2;
1706                         break;
1707                 case 6:
1708                         track->cb[0].cpp = 4;
1709                         break;
1710                 default:
1711                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1712                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1713                         return -EINVAL;
1714                 }
1715                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1716                 track->cb_dirty = true;
1717                 track->zb_dirty = true;
1718                 break;
1719         case RADEON_RB3D_ZSTENCILCNTL:
1720                 switch (idx_value & 0xf) {
1721                 case 0:
1722                         track->zb.cpp = 2;
1723                         break;
1724                 case 2:
1725                 case 3:
1726                 case 4:
1727                 case 5:
1728                 case 9:
1729                 case 11:
1730                         track->zb.cpp = 4;
1731                         break;
1732                 default:
1733                         break;
1734                 }
1735                 track->zb_dirty = true;
1736                 break;
1737         case RADEON_RB3D_ZPASS_ADDR:
1738                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1739                 if (r) {
1740                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1741                                   idx, reg);
1742                         radeon_cs_dump_packet(p, pkt);
1743                         return r;
1744                 }
1745                 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1746                 break;
1747         case RADEON_PP_CNTL:
1748                 {
1749                         uint32_t temp = idx_value >> 4;
1750                         for (i = 0; i < track->num_texture; i++)
1751                                 track->textures[i].enabled = !!(temp & (1 << i));
1752                         track->tex_dirty = true;
1753                 }
1754                 break;
1755         case RADEON_SE_VF_CNTL:
1756                 track->vap_vf_cntl = idx_value;
1757                 break;
1758         case RADEON_SE_VTX_FMT:
1759                 track->vtx_size = r100_get_vtx_size(idx_value);
1760                 break;
1761         case RADEON_PP_TEX_SIZE_0:
1762         case RADEON_PP_TEX_SIZE_1:
1763         case RADEON_PP_TEX_SIZE_2:
1764                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1765                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1766                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1767                 track->tex_dirty = true;
1768                 break;
1769         case RADEON_PP_TEX_PITCH_0:
1770         case RADEON_PP_TEX_PITCH_1:
1771         case RADEON_PP_TEX_PITCH_2:
1772                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1773                 track->textures[i].pitch = idx_value + 32;
1774                 track->tex_dirty = true;
1775                 break;
1776         case RADEON_PP_TXFILTER_0:
1777         case RADEON_PP_TXFILTER_1:
1778         case RADEON_PP_TXFILTER_2:
1779                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1780                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1781                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1782                 tmp = (idx_value >> 23) & 0x7;
1783                 if (tmp == 2 || tmp == 6)
1784                         track->textures[i].roundup_w = false;
1785                 tmp = (idx_value >> 27) & 0x7;
1786                 if (tmp == 2 || tmp == 6)
1787                         track->textures[i].roundup_h = false;
1788                 track->tex_dirty = true;
1789                 break;
1790         case RADEON_PP_TXFORMAT_0:
1791         case RADEON_PP_TXFORMAT_1:
1792         case RADEON_PP_TXFORMAT_2:
1793                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1794                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1795                         track->textures[i].use_pitch = 1;
1796                 } else {
1797                         track->textures[i].use_pitch = 0;
1798                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1799                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1800                 }
1801                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1802                         track->textures[i].tex_coord_type = 2;
1803                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1804                 case RADEON_TXFORMAT_I8:
1805                 case RADEON_TXFORMAT_RGB332:
1806                 case RADEON_TXFORMAT_Y8:
1807                         track->textures[i].cpp = 1;
1808                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1809                         break;
1810                 case RADEON_TXFORMAT_AI88:
1811                 case RADEON_TXFORMAT_ARGB1555:
1812                 case RADEON_TXFORMAT_RGB565:
1813                 case RADEON_TXFORMAT_ARGB4444:
1814                 case RADEON_TXFORMAT_VYUY422:
1815                 case RADEON_TXFORMAT_YVYU422:
1816                 case RADEON_TXFORMAT_SHADOW16:
1817                 case RADEON_TXFORMAT_LDUDV655:
1818                 case RADEON_TXFORMAT_DUDV88:
1819                         track->textures[i].cpp = 2;
1820                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1821                         break;
1822                 case RADEON_TXFORMAT_ARGB8888:
1823                 case RADEON_TXFORMAT_RGBA8888:
1824                 case RADEON_TXFORMAT_SHADOW32:
1825                 case RADEON_TXFORMAT_LDUDUV8888:
1826                         track->textures[i].cpp = 4;
1827                         track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1828                         break;
1829                 case RADEON_TXFORMAT_DXT1:
1830                         track->textures[i].cpp = 1;
1831                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1832                         break;
1833                 case RADEON_TXFORMAT_DXT23:
1834                 case RADEON_TXFORMAT_DXT45:
1835                         track->textures[i].cpp = 1;
1836                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1837                         break;
1838                 }
1839                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1840                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1841                 track->tex_dirty = true;
1842                 break;
1843         case RADEON_PP_CUBIC_FACES_0:
1844         case RADEON_PP_CUBIC_FACES_1:
1845         case RADEON_PP_CUBIC_FACES_2:
1846                 tmp = idx_value;
1847                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1848                 for (face = 0; face < 4; face++) {
1849                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1850                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1851                 }
1852                 track->tex_dirty = true;
1853                 break;
1854         default:
1855                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1856                        reg, idx);
1857                 return -EINVAL;
1858         }
1859         return 0;
1860 }
1861
1862 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1863                                          struct radeon_cs_packet *pkt,
1864                                          struct radeon_bo *robj)
1865 {
1866         unsigned idx;
1867         u32 value;
1868         idx = pkt->idx + 1;
1869         value = radeon_get_ib_value(p, idx + 2);
1870         if ((value + 1) > radeon_bo_size(robj)) {
1871                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1872                           "(need %u have %lu) !\n",
1873                           value + 1,
1874                           radeon_bo_size(robj));
1875                 return -EINVAL;
1876         }
1877         return 0;
1878 }
1879
1880 static int r100_packet3_check(struct radeon_cs_parser *p,
1881                               struct radeon_cs_packet *pkt)
1882 {
1883         struct radeon_cs_reloc *reloc;
1884         struct r100_cs_track *track;
1885         unsigned idx;
1886         volatile uint32_t *ib;
1887         int r;
1888
1889         ib = p->ib.ptr;
1890         idx = pkt->idx + 1;
1891         track = (struct r100_cs_track *)p->track;
1892         switch (pkt->opcode) {
1893         case PACKET3_3D_LOAD_VBPNTR:
1894                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1895                 if (r)
1896                         return r;
1897                 break;
1898         case PACKET3_INDX_BUFFER:
1899                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1900                 if (r) {
1901                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1902                         radeon_cs_dump_packet(p, pkt);
1903                         return r;
1904                 }
1905                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1906                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1907                 if (r) {
1908                         return r;
1909                 }
1910                 break;
1911         case 0x23:
1912                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1913                 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
1914                 if (r) {
1915                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1916                         radeon_cs_dump_packet(p, pkt);
1917                         return r;
1918                 }
1919                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1920                 track->num_arrays = 1;
1921                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1922
1923                 track->arrays[0].robj = reloc->robj;
1924                 track->arrays[0].esize = track->vtx_size;
1925
1926                 track->max_indx = radeon_get_ib_value(p, idx+1);
1927
1928                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1929                 track->immd_dwords = pkt->count - 1;
1930                 r = r100_cs_track_check(p->rdev, track);
1931                 if (r)
1932                         return r;
1933                 break;
1934         case PACKET3_3D_DRAW_IMMD:
1935                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1936                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1937                         return -EINVAL;
1938                 }
1939                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1940                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1941                 track->immd_dwords = pkt->count - 1;
1942                 r = r100_cs_track_check(p->rdev, track);
1943                 if (r)
1944                         return r;
1945                 break;
1946                 /* triggers drawing using in-packet vertex data */
1947         case PACKET3_3D_DRAW_IMMD_2:
1948                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1949                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1950                         return -EINVAL;
1951                 }
1952                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1953                 track->immd_dwords = pkt->count;
1954                 r = r100_cs_track_check(p->rdev, track);
1955                 if (r)
1956                         return r;
1957                 break;
1958                 /* triggers drawing using in-packet vertex data */
1959         case PACKET3_3D_DRAW_VBUF_2:
1960                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1961                 r = r100_cs_track_check(p->rdev, track);
1962                 if (r)
1963                         return r;
1964                 break;
1965                 /* triggers drawing of vertex buffers setup elsewhere */
1966         case PACKET3_3D_DRAW_INDX_2:
1967                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1968                 r = r100_cs_track_check(p->rdev, track);
1969                 if (r)
1970                         return r;
1971                 break;
1972                 /* triggers drawing using indices to vertex buffer */
1973         case PACKET3_3D_DRAW_VBUF:
1974                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1975                 r = r100_cs_track_check(p->rdev, track);
1976                 if (r)
1977                         return r;
1978                 break;
1979                 /* triggers drawing of vertex buffers setup elsewhere */
1980         case PACKET3_3D_DRAW_INDX:
1981                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1982                 r = r100_cs_track_check(p->rdev, track);
1983                 if (r)
1984                         return r;
1985                 break;
1986                 /* triggers drawing using indices to vertex buffer */
1987         case PACKET3_3D_CLEAR_HIZ:
1988         case PACKET3_3D_CLEAR_ZMASK:
1989                 if (p->rdev->hyperz_filp != p->filp)
1990                         return -EINVAL;
1991                 break;
1992         case PACKET3_NOP:
1993                 break;
1994         default:
1995                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1996                 return -EINVAL;
1997         }
1998         return 0;
1999 }
2000
2001 int r100_cs_parse(struct radeon_cs_parser *p)
2002 {
2003         struct radeon_cs_packet pkt;
2004         struct r100_cs_track *track;
2005         int r;
2006
2007         track = kzalloc(sizeof(*track), GFP_KERNEL);
2008         if (!track)
2009                 return -ENOMEM;
2010         r100_cs_track_clear(p->rdev, track);
2011         p->track = track;
2012         do {
2013                 r = radeon_cs_packet_parse(p, &pkt, p->idx);
2014                 if (r) {
2015                         return r;
2016                 }
2017                 p->idx += pkt.count + 2;
2018                 switch (pkt.type) {
2019                 case RADEON_PACKET_TYPE0:
2020                         if (p->rdev->family >= CHIP_R200)
2021                                 r = r100_cs_parse_packet0(p, &pkt,
2022                                         p->rdev->config.r100.reg_safe_bm,
2023                                         p->rdev->config.r100.reg_safe_bm_size,
2024                                         &r200_packet0_check);
2025                         else
2026                                 r = r100_cs_parse_packet0(p, &pkt,
2027                                         p->rdev->config.r100.reg_safe_bm,
2028                                         p->rdev->config.r100.reg_safe_bm_size,
2029                                         &r100_packet0_check);
2030                         break;
2031                 case RADEON_PACKET_TYPE2:
2032                         break;
2033                 case RADEON_PACKET_TYPE3:
2034                         r = r100_packet3_check(p, &pkt);
2035                         break;
2036                 default:
2037                         DRM_ERROR("Unknown packet type %d !\n",
2038                                   pkt.type);
2039                         return -EINVAL;
2040                 }
2041                 if (r)
2042                         return r;
2043         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
2044         return 0;
2045 }
2046
2047 static void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2048 {
2049         DRM_ERROR("pitch                      %d\n", t->pitch);
2050         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2051         DRM_ERROR("width                      %d\n", t->width);
2052         DRM_ERROR("width_11                   %d\n", t->width_11);
2053         DRM_ERROR("height                     %d\n", t->height);
2054         DRM_ERROR("height_11                  %d\n", t->height_11);
2055         DRM_ERROR("num levels                 %d\n", t->num_levels);
2056         DRM_ERROR("depth                      %d\n", t->txdepth);
2057         DRM_ERROR("bpp                        %d\n", t->cpp);
2058         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2059         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2060         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2061         DRM_ERROR("compress format            %d\n", t->compress_format);
2062 }
2063
2064 static int r100_track_compress_size(int compress_format, int w, int h)
2065 {
2066         int block_width, block_height, block_bytes;
2067         int wblocks, hblocks;
2068         int min_wblocks;
2069         int sz;
2070
2071         block_width = 4;
2072         block_height = 4;
2073
2074         switch (compress_format) {
2075         case R100_TRACK_COMP_DXT1:
2076                 block_bytes = 8;
2077                 min_wblocks = 4;
2078                 break;
2079         default:
2080         case R100_TRACK_COMP_DXT35:
2081                 block_bytes = 16;
2082                 min_wblocks = 2;
2083                 break;
2084         }
2085
2086         hblocks = (h + block_height - 1) / block_height;
2087         wblocks = (w + block_width - 1) / block_width;
2088         if (wblocks < min_wblocks)
2089                 wblocks = min_wblocks;
2090         sz = wblocks * hblocks * block_bytes;
2091         return sz;
2092 }
2093
2094 static int r100_cs_track_cube(struct radeon_device *rdev,
2095                               struct r100_cs_track *track, unsigned idx)
2096 {
2097         unsigned face, w, h;
2098         struct radeon_bo *cube_robj;
2099         unsigned long size;
2100         unsigned compress_format = track->textures[idx].compress_format;
2101
2102         for (face = 0; face < 5; face++) {
2103                 cube_robj = track->textures[idx].cube_info[face].robj;
2104                 w = track->textures[idx].cube_info[face].width;
2105                 h = track->textures[idx].cube_info[face].height;
2106
2107                 if (compress_format) {
2108                         size = r100_track_compress_size(compress_format, w, h);
2109                 } else
2110                         size = w * h;
2111                 size *= track->textures[idx].cpp;
2112
2113                 size += track->textures[idx].cube_info[face].offset;
2114
2115                 if (size > radeon_bo_size(cube_robj)) {
2116                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2117                                   size, radeon_bo_size(cube_robj));
2118                         r100_cs_track_texture_print(&track->textures[idx]);
2119                         return -1;
2120                 }
2121         }
2122         return 0;
2123 }
2124
2125 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2126                                        struct r100_cs_track *track)
2127 {
2128         struct radeon_bo *robj;
2129         unsigned long size;
2130         unsigned u, i, w, h, d;
2131         int ret;
2132
2133         for (u = 0; u < track->num_texture; u++) {
2134                 if (!track->textures[u].enabled)
2135                         continue;
2136                 if (track->textures[u].lookup_disable)
2137                         continue;
2138                 robj = track->textures[u].robj;
2139                 if (robj == NULL) {
2140                         DRM_ERROR("No texture bound to unit %u\n", u);
2141                         return -EINVAL;
2142                 }
2143                 size = 0;
2144                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2145                         if (track->textures[u].use_pitch) {
2146                                 if (rdev->family < CHIP_R300)
2147                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2148                                 else
2149                                         w = track->textures[u].pitch / (1 << i);
2150                         } else {
2151                                 w = track->textures[u].width;
2152                                 if (rdev->family >= CHIP_RV515)
2153                                         w |= track->textures[u].width_11;
2154                                 w = w / (1 << i);
2155                                 if (track->textures[u].roundup_w)
2156                                         w = roundup_pow_of_two(w);
2157                         }
2158                         h = track->textures[u].height;
2159                         if (rdev->family >= CHIP_RV515)
2160                                 h |= track->textures[u].height_11;
2161                         h = h / (1 << i);
2162                         if (track->textures[u].roundup_h)
2163                                 h = roundup_pow_of_two(h);
2164                         if (track->textures[u].tex_coord_type == 1) {
2165                                 d = (1 << track->textures[u].txdepth) / (1 << i);
2166                                 if (!d)
2167                                         d = 1;
2168                         } else {
2169                                 d = 1;
2170                         }
2171                         if (track->textures[u].compress_format) {
2172
2173                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
2174                                 /* compressed textures are block based */
2175                         } else
2176                                 size += w * h * d;
2177                 }
2178                 size *= track->textures[u].cpp;
2179
2180                 switch (track->textures[u].tex_coord_type) {
2181                 case 0:
2182                 case 1:
2183                         break;
2184                 case 2:
2185                         if (track->separate_cube) {
2186                                 ret = r100_cs_track_cube(rdev, track, u);
2187                                 if (ret)
2188                                         return ret;
2189                         } else
2190                                 size *= 6;
2191                         break;
2192                 default:
2193                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2194                                   "%u\n", track->textures[u].tex_coord_type, u);
2195                         return -EINVAL;
2196                 }
2197                 if (size > radeon_bo_size(robj)) {
2198                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2199                                   "%lu\n", u, size, radeon_bo_size(robj));
2200                         r100_cs_track_texture_print(&track->textures[u]);
2201                         return -EINVAL;
2202                 }
2203         }
2204         return 0;
2205 }
2206
2207 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2208 {
2209         unsigned i;
2210         unsigned long size;
2211         unsigned prim_walk;
2212         unsigned nverts;
2213         unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
2214
2215         if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
2216             !track->blend_read_enable)
2217                 num_cb = 0;
2218
2219         for (i = 0; i < num_cb; i++) {
2220                 if (track->cb[i].robj == NULL) {
2221                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2222                         return -EINVAL;
2223                 }
2224                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2225                 size += track->cb[i].offset;
2226                 if (size > radeon_bo_size(track->cb[i].robj)) {
2227                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2228                                   "(need %lu have %lu) !\n", i, size,
2229                                   radeon_bo_size(track->cb[i].robj));
2230                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2231                                   i, track->cb[i].pitch, track->cb[i].cpp,
2232                                   track->cb[i].offset, track->maxy);
2233                         return -EINVAL;
2234                 }
2235         }
2236         track->cb_dirty = false;
2237
2238         if (track->zb_dirty && track->z_enabled) {
2239                 if (track->zb.robj == NULL) {
2240                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2241                         return -EINVAL;
2242                 }
2243                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2244                 size += track->zb.offset;
2245                 if (size > radeon_bo_size(track->zb.robj)) {
2246                         DRM_ERROR("[drm] Buffer too small for z buffer "
2247                                   "(need %lu have %lu) !\n", size,
2248                                   radeon_bo_size(track->zb.robj));
2249                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2250                                   track->zb.pitch, track->zb.cpp,
2251                                   track->zb.offset, track->maxy);
2252                         return -EINVAL;
2253                 }
2254         }
2255         track->zb_dirty = false;
2256
2257         if (track->aa_dirty && track->aaresolve) {
2258                 if (track->aa.robj == NULL) {
2259                         DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
2260                         return -EINVAL;
2261                 }
2262                 /* I believe the format comes from colorbuffer0. */
2263                 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
2264                 size += track->aa.offset;
2265                 if (size > radeon_bo_size(track->aa.robj)) {
2266                         DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
2267                                   "(need %lu have %lu) !\n", i, size,
2268                                   radeon_bo_size(track->aa.robj));
2269                         DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
2270                                   i, track->aa.pitch, track->cb[0].cpp,
2271                                   track->aa.offset, track->maxy);
2272                         return -EINVAL;
2273                 }
2274         }
2275         track->aa_dirty = false;
2276
2277         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2278         if (track->vap_vf_cntl & (1 << 14)) {
2279                 nverts = track->vap_alt_nverts;
2280         } else {
2281                 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2282         }
2283         switch (prim_walk) {
2284         case 1:
2285                 for (i = 0; i < track->num_arrays; i++) {
2286                         size = track->arrays[i].esize * track->max_indx * 4;
2287                         if (track->arrays[i].robj == NULL) {
2288                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2289                                           "bound\n", prim_walk, i);
2290                                 return -EINVAL;
2291                         }
2292                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2293                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2294                                         "need %lu dwords have %lu dwords\n",
2295                                         prim_walk, i, size >> 2,
2296                                         radeon_bo_size(track->arrays[i].robj)
2297                                         >> 2);
2298                                 DRM_ERROR("Max indices %u\n", track->max_indx);
2299                                 return -EINVAL;
2300                         }
2301                 }
2302                 break;
2303         case 2:
2304                 for (i = 0; i < track->num_arrays; i++) {
2305                         size = track->arrays[i].esize * (nverts - 1) * 4;
2306                         if (track->arrays[i].robj == NULL) {
2307                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
2308                                           "bound\n", prim_walk, i);
2309                                 return -EINVAL;
2310                         }
2311                         if (size > radeon_bo_size(track->arrays[i].robj)) {
2312                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
2313                                         "need %lu dwords have %lu dwords\n",
2314                                         prim_walk, i, size >> 2,
2315                                         radeon_bo_size(track->arrays[i].robj)
2316                                         >> 2);
2317                                 return -EINVAL;
2318                         }
2319                 }
2320                 break;
2321         case 3:
2322                 size = track->vtx_size * nverts;
2323                 if (size != track->immd_dwords) {
2324                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
2325                                   track->immd_dwords, size);
2326                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
2327                                   nverts, track->vtx_size);
2328                         return -EINVAL;
2329                 }
2330                 break;
2331         default:
2332                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
2333                           prim_walk);
2334                 return -EINVAL;
2335         }
2336
2337         if (track->tex_dirty) {
2338                 track->tex_dirty = false;
2339                 return r100_cs_track_texture_check(rdev, track);
2340         }
2341         return 0;
2342 }
2343
2344 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
2345 {
2346         unsigned i, face;
2347
2348         track->cb_dirty = true;
2349         track->zb_dirty = true;
2350         track->tex_dirty = true;
2351         track->aa_dirty = true;
2352
2353         if (rdev->family < CHIP_R300) {
2354                 track->num_cb = 1;
2355                 if (rdev->family <= CHIP_RS200)
2356                         track->num_texture = 3;
2357                 else
2358                         track->num_texture = 6;
2359                 track->maxy = 2048;
2360                 track->separate_cube = 1;
2361         } else {
2362                 track->num_cb = 4;
2363                 track->num_texture = 16;
2364                 track->maxy = 4096;
2365                 track->separate_cube = 0;
2366                 track->aaresolve = false;
2367                 track->aa.robj = NULL;
2368         }
2369
2370         for (i = 0; i < track->num_cb; i++) {
2371                 track->cb[i].robj = NULL;
2372                 track->cb[i].pitch = 8192;
2373                 track->cb[i].cpp = 16;
2374                 track->cb[i].offset = 0;
2375         }
2376         track->z_enabled = true;
2377         track->zb.robj = NULL;
2378         track->zb.pitch = 8192;
2379         track->zb.cpp = 4;
2380         track->zb.offset = 0;
2381         track->vtx_size = 0x7F;
2382         track->immd_dwords = 0xFFFFFFFFUL;
2383         track->num_arrays = 11;
2384         track->max_indx = 0x00FFFFFFUL;
2385         for (i = 0; i < track->num_arrays; i++) {
2386                 track->arrays[i].robj = NULL;
2387                 track->arrays[i].esize = 0x7F;
2388         }
2389         for (i = 0; i < track->num_texture; i++) {
2390                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
2391                 track->textures[i].pitch = 16536;
2392                 track->textures[i].width = 16536;
2393                 track->textures[i].height = 16536;
2394                 track->textures[i].width_11 = 1 << 11;
2395                 track->textures[i].height_11 = 1 << 11;
2396                 track->textures[i].num_levels = 12;
2397                 if (rdev->family <= CHIP_RS200) {
2398                         track->textures[i].tex_coord_type = 0;
2399                         track->textures[i].txdepth = 0;
2400                 } else {
2401                         track->textures[i].txdepth = 16;
2402                         track->textures[i].tex_coord_type = 1;
2403                 }
2404                 track->textures[i].cpp = 64;
2405                 track->textures[i].robj = NULL;
2406                 /* CS IB emission code makes sure texture unit are disabled */
2407                 track->textures[i].enabled = false;
2408                 track->textures[i].lookup_disable = false;
2409                 track->textures[i].roundup_w = true;
2410                 track->textures[i].roundup_h = true;
2411                 if (track->separate_cube)
2412                         for (face = 0; face < 5; face++) {
2413                                 track->textures[i].cube_info[face].robj = NULL;
2414                                 track->textures[i].cube_info[face].width = 16536;
2415                                 track->textures[i].cube_info[face].height = 16536;
2416                                 track->textures[i].cube_info[face].offset = 0;
2417                         }
2418         }
2419 }
2420
2421 /*
2422  * Global GPU functions
2423  */
2424 static void r100_errata(struct radeon_device *rdev)
2425 {
2426         rdev->pll_errata = 0;
2427
2428         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
2429                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2430         }
2431
2432         if (rdev->family == CHIP_RV100 ||
2433             rdev->family == CHIP_RS100 ||
2434             rdev->family == CHIP_RS200) {
2435                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
2436         }
2437 }
2438
2439 static int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
2440 {
2441         unsigned i;
2442         uint32_t tmp;
2443
2444         for (i = 0; i < rdev->usec_timeout; i++) {
2445                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
2446                 if (tmp >= n) {
2447                         return 0;
2448                 }
2449                 DRM_UDELAY(1);
2450         }
2451         return -1;
2452 }
2453
2454 int r100_gui_wait_for_idle(struct radeon_device *rdev)
2455 {
2456         unsigned i;
2457         uint32_t tmp;
2458
2459         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
2460                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
2461                        " Bad things might happen.\n");
2462         }
2463         for (i = 0; i < rdev->usec_timeout; i++) {
2464                 tmp = RREG32(RADEON_RBBM_STATUS);
2465                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
2466                         return 0;
2467                 }
2468                 DRM_UDELAY(1);
2469         }
2470         return -1;
2471 }
2472
2473 int r100_mc_wait_for_idle(struct radeon_device *rdev)
2474 {
2475         unsigned i;
2476         uint32_t tmp;
2477
2478         for (i = 0; i < rdev->usec_timeout; i++) {
2479                 /* read MC_STATUS */
2480                 tmp = RREG32(RADEON_MC_STATUS);
2481                 if (tmp & RADEON_MC_IDLE) {
2482                         return 0;
2483                 }
2484                 DRM_UDELAY(1);
2485         }
2486         return -1;
2487 }
2488
2489 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2490 {
2491         u32 rbbm_status;
2492
2493         rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2494         if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2495                 radeon_ring_lockup_update(rdev, ring);
2496                 return false;
2497         }
2498         return radeon_ring_test_lockup(rdev, ring);
2499 }
2500
2501 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
2502 void r100_enable_bm(struct radeon_device *rdev)
2503 {
2504         uint32_t tmp;
2505         /* Enable bus mastering */
2506         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
2507         WREG32(RADEON_BUS_CNTL, tmp);
2508 }
2509
2510 void r100_bm_disable(struct radeon_device *rdev)
2511 {
2512         u32 tmp;
2513
2514         /* disable bus mastering */
2515         tmp = RREG32(R_000030_BUS_CNTL);
2516         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2517         mdelay(1);
2518         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2519         mdelay(1);
2520         WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2521         tmp = RREG32(RADEON_BUS_CNTL);
2522         mdelay(1);
2523         pci_clear_master(rdev->pdev);
2524         mdelay(1);
2525 }
2526
2527 int r100_asic_reset(struct radeon_device *rdev)
2528 {
2529         struct r100_mc_save save;
2530         u32 status, tmp;
2531         int ret = 0;
2532
2533         status = RREG32(R_000E40_RBBM_STATUS);
2534         if (!G_000E40_GUI_ACTIVE(status)) {
2535                 return 0;
2536         }
2537         r100_mc_stop(rdev, &save);
2538         status = RREG32(R_000E40_RBBM_STATUS);
2539         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2540         /* stop CP */
2541         WREG32(RADEON_CP_CSQ_CNTL, 0);
2542         tmp = RREG32(RADEON_CP_RB_CNTL);
2543         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2544         WREG32(RADEON_CP_RB_RPTR_WR, 0);
2545         WREG32(RADEON_CP_RB_WPTR, 0);
2546         WREG32(RADEON_CP_RB_CNTL, tmp);
2547         /* save PCI state */
2548         pci_save_state(rdev->pdev);
2549         /* disable bus mastering */
2550         r100_bm_disable(rdev);
2551         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2552                                         S_0000F0_SOFT_RESET_RE(1) |
2553                                         S_0000F0_SOFT_RESET_PP(1) |
2554                                         S_0000F0_SOFT_RESET_RB(1));
2555         RREG32(R_0000F0_RBBM_SOFT_RESET);
2556         mdelay(500);
2557         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2558         mdelay(1);
2559         status = RREG32(R_000E40_RBBM_STATUS);
2560         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2561         /* reset CP */
2562         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2563         RREG32(R_0000F0_RBBM_SOFT_RESET);
2564         mdelay(500);
2565         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2566         mdelay(1);
2567         status = RREG32(R_000E40_RBBM_STATUS);
2568         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2569         /* restore PCI & busmastering */
2570         pci_restore_state(rdev->pdev);
2571         r100_enable_bm(rdev);
2572         /* Check if GPU is idle */
2573         if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2574                 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2575                 dev_err(rdev->dev, "failed to reset GPU\n");
2576                 ret = -1;
2577         } else
2578                 dev_info(rdev->dev, "GPU reset succeed\n");
2579         r100_mc_resume(rdev, &save);
2580         return ret;
2581 }
2582
2583 void r100_set_common_regs(struct radeon_device *rdev)
2584 {
2585         struct drm_device *dev = rdev->ddev;
2586         bool force_dac2 = false;
2587         u32 tmp;
2588
2589         /* set these so they don't interfere with anything */
2590         WREG32(RADEON_OV0_SCALE_CNTL, 0);
2591         WREG32(RADEON_SUBPIC_CNTL, 0);
2592         WREG32(RADEON_VIPH_CONTROL, 0);
2593         WREG32(RADEON_I2C_CNTL_1, 0);
2594         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2595         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2596         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2597
2598         /* always set up dac2 on rn50 and some rv100 as lots
2599          * of servers seem to wire it up to a VGA port but
2600          * don't report it in the bios connector
2601          * table.
2602          */
2603         switch (dev->pdev->device) {
2604                 /* RN50 */
2605         case 0x515e:
2606         case 0x5969:
2607                 force_dac2 = true;
2608                 break;
2609                 /* RV100*/
2610         case 0x5159:
2611         case 0x515a:
2612                 /* DELL triple head servers */
2613                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2614                     ((dev->pdev->subsystem_device == 0x016c) ||
2615                      (dev->pdev->subsystem_device == 0x016d) ||
2616                      (dev->pdev->subsystem_device == 0x016e) ||
2617                      (dev->pdev->subsystem_device == 0x016f) ||
2618                      (dev->pdev->subsystem_device == 0x0170) ||
2619                      (dev->pdev->subsystem_device == 0x017d) ||
2620                      (dev->pdev->subsystem_device == 0x017e) ||
2621                      (dev->pdev->subsystem_device == 0x0183) ||
2622                      (dev->pdev->subsystem_device == 0x018a) ||
2623                      (dev->pdev->subsystem_device == 0x019a)))
2624                         force_dac2 = true;
2625                 break;
2626         }
2627
2628         if (force_dac2) {
2629                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2630                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2631                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2632
2633                 /* For CRT on DAC2, don't turn it on if BIOS didn't
2634                    enable it, even it's detected.
2635                 */
2636
2637                 /* force it to crtc0 */
2638                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2639                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2640                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2641
2642                 /* set up the TV DAC */
2643                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2644                                  RADEON_TV_DAC_STD_MASK |
2645                                  RADEON_TV_DAC_RDACPD |
2646                                  RADEON_TV_DAC_GDACPD |
2647                                  RADEON_TV_DAC_BDACPD |
2648                                  RADEON_TV_DAC_BGADJ_MASK |
2649                                  RADEON_TV_DAC_DACADJ_MASK);
2650                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2651                                 RADEON_TV_DAC_NHOLD |
2652                                 RADEON_TV_DAC_STD_PS2 |
2653                                 (0x58 << 16));
2654
2655                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2656                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2657                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2658         }
2659
2660         /* switch PM block to ACPI mode */
2661         tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2662         tmp &= ~RADEON_PM_MODE_SEL;
2663         WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2664
2665 }
2666
2667 /*
2668  * VRAM info
2669  */
2670 static void r100_vram_get_type(struct radeon_device *rdev)
2671 {
2672         uint32_t tmp;
2673
2674         rdev->mc.vram_is_ddr = false;
2675         if (rdev->flags & RADEON_IS_IGP)
2676                 rdev->mc.vram_is_ddr = true;
2677         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2678                 rdev->mc.vram_is_ddr = true;
2679         if ((rdev->family == CHIP_RV100) ||
2680             (rdev->family == CHIP_RS100) ||
2681             (rdev->family == CHIP_RS200)) {
2682                 tmp = RREG32(RADEON_MEM_CNTL);
2683                 if (tmp & RV100_HALF_MODE) {
2684                         rdev->mc.vram_width = 32;
2685                 } else {
2686                         rdev->mc.vram_width = 64;
2687                 }
2688                 if (rdev->flags & RADEON_SINGLE_CRTC) {
2689                         rdev->mc.vram_width /= 4;
2690                         rdev->mc.vram_is_ddr = true;
2691                 }
2692         } else if (rdev->family <= CHIP_RV280) {
2693                 tmp = RREG32(RADEON_MEM_CNTL);
2694                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2695                         rdev->mc.vram_width = 128;
2696                 } else {
2697                         rdev->mc.vram_width = 64;
2698                 }
2699         } else {
2700                 /* newer IGPs */
2701                 rdev->mc.vram_width = 128;
2702         }
2703 }
2704
2705 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2706 {
2707         u32 aper_size;
2708         u8 byte;
2709
2710         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2711
2712         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2713          * that is has the 2nd generation multifunction PCI interface
2714          */
2715         if (rdev->family == CHIP_RV280 ||
2716             rdev->family >= CHIP_RV350) {
2717                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2718                        ~RADEON_HDP_APER_CNTL);
2719                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2720                 return aper_size * 2;
2721         }
2722
2723         /* Older cards have all sorts of funny issues to deal with. First
2724          * check if it's a multifunction card by reading the PCI config
2725          * header type... Limit those to one aperture size
2726          */
2727         pci_read_config_byte(rdev->pdev, 0xe, &byte);
2728         if (byte & 0x80) {
2729                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2730                 DRM_INFO("Limiting VRAM to one aperture\n");
2731                 return aper_size;
2732         }
2733
2734         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2735          * have set it up. We don't write this as it's broken on some ASICs but
2736          * we expect the BIOS to have done the right thing (might be too optimistic...)
2737          */
2738         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2739                 return aper_size * 2;
2740         return aper_size;
2741 }
2742
2743 void r100_vram_init_sizes(struct radeon_device *rdev)
2744 {
2745         u64 config_aper_size;
2746
2747         /* work out accessible VRAM */
2748         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2749         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2750         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2751         /* FIXME we don't use the second aperture yet when we could use it */
2752         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2753                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2754         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2755         if (rdev->flags & RADEON_IS_IGP) {
2756                 uint32_t tom;
2757                 /* read NB_TOM to get the amount of ram stolen for the GPU */
2758                 tom = RREG32(RADEON_NB_TOM);
2759                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2760                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2761                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2762         } else {
2763                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2764                 /* Some production boards of m6 will report 0
2765                  * if it's 8 MB
2766                  */
2767                 if (rdev->mc.real_vram_size == 0) {
2768                         rdev->mc.real_vram_size = 8192 * 1024;
2769                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2770                 }
2771                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2772                  * Novell bug 204882 + along with lots of ubuntu ones
2773                  */
2774                 if (rdev->mc.aper_size > config_aper_size)
2775                         config_aper_size = rdev->mc.aper_size;
2776
2777                 if (config_aper_size > rdev->mc.real_vram_size)
2778                         rdev->mc.mc_vram_size = config_aper_size;
2779                 else
2780                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2781         }
2782 }
2783
2784 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2785 {
2786         uint32_t temp;
2787
2788         temp = RREG32(RADEON_CONFIG_CNTL);
2789         if (state == false) {
2790                 temp &= ~RADEON_CFG_VGA_RAM_EN;
2791                 temp |= RADEON_CFG_VGA_IO_DIS;
2792         } else {
2793                 temp &= ~RADEON_CFG_VGA_IO_DIS;
2794         }
2795         WREG32(RADEON_CONFIG_CNTL, temp);
2796 }
2797
2798 static void r100_mc_init(struct radeon_device *rdev)
2799 {
2800         u64 base;
2801
2802         r100_vram_get_type(rdev);
2803         r100_vram_init_sizes(rdev);
2804         base = rdev->mc.aper_base;
2805         if (rdev->flags & RADEON_IS_IGP)
2806                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2807         radeon_vram_location(rdev, &rdev->mc, base);
2808         rdev->mc.gtt_base_align = 0;
2809         if (!(rdev->flags & RADEON_IS_AGP))
2810                 radeon_gtt_location(rdev, &rdev->mc);
2811         radeon_update_bandwidth_info(rdev);
2812 }
2813
2814
2815 /*
2816  * Indirect registers accessor
2817  */
2818 void r100_pll_errata_after_index(struct radeon_device *rdev)
2819 {
2820         if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2821                 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2822                 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2823         }
2824 }
2825
2826 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2827 {
2828         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2829          * or the chip could hang on a subsequent access
2830          */
2831         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2832                 mdelay(5);
2833         }
2834
2835         /* This function is required to workaround a hardware bug in some (all?)
2836          * revisions of the R300.  This workaround should be called after every
2837          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2838          * may not be correct.
2839          */
2840         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2841                 uint32_t save, tmp;
2842
2843                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2844                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2845                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2846                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2847                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2848         }
2849 }
2850
2851 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2852 {
2853         unsigned long flags;
2854         uint32_t data;
2855
2856         spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2857         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2858         r100_pll_errata_after_index(rdev);
2859         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2860         r100_pll_errata_after_data(rdev);
2861         spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2862         return data;
2863 }
2864
2865 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2866 {
2867         unsigned long flags;
2868
2869         spin_lock_irqsave(&rdev->pll_idx_lock, flags);
2870         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2871         r100_pll_errata_after_index(rdev);
2872         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2873         r100_pll_errata_after_data(rdev);
2874         spin_unlock_irqrestore(&rdev->pll_idx_lock, flags);
2875 }
2876
2877 static void r100_set_safe_registers(struct radeon_device *rdev)
2878 {
2879         if (ASIC_IS_RN50(rdev)) {
2880                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2881                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2882         } else if (rdev->family < CHIP_R200) {
2883                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2884                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2885         } else {
2886                 r200_set_safe_registers(rdev);
2887         }
2888 }
2889
2890 /*
2891  * Debugfs info
2892  */
2893 #if defined(CONFIG_DEBUG_FS)
2894 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2895 {
2896         struct drm_info_node *node = (struct drm_info_node *) m->private;
2897         struct drm_device *dev = node->minor->dev;
2898         struct radeon_device *rdev = dev->dev_private;
2899         uint32_t reg, value;
2900         unsigned i;
2901
2902         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2903         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2904         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2905         for (i = 0; i < 64; i++) {
2906                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2907                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2908                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2909                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2910                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2911         }
2912         return 0;
2913 }
2914
2915 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2916 {
2917         struct drm_info_node *node = (struct drm_info_node *) m->private;
2918         struct drm_device *dev = node->minor->dev;
2919         struct radeon_device *rdev = dev->dev_private;
2920         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2921         uint32_t rdp, wdp;
2922         unsigned count, i, j;
2923
2924         radeon_ring_free_size(rdev, ring);
2925         rdp = RREG32(RADEON_CP_RB_RPTR);
2926         wdp = RREG32(RADEON_CP_RB_WPTR);
2927         count = (rdp + ring->ring_size - wdp) & ring->ptr_mask;
2928         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2929         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2930         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2931         seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
2932         seq_printf(m, "%u dwords in ring\n", count);
2933         if (ring->ready) {
2934                 for (j = 0; j <= count; j++) {
2935                         i = (rdp + j) & ring->ptr_mask;
2936                         seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
2937                 }
2938         }
2939         return 0;
2940 }
2941
2942
2943 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2944 {
2945         struct drm_info_node *node = (struct drm_info_node *) m->private;
2946         struct drm_device *dev = node->minor->dev;
2947         struct radeon_device *rdev = dev->dev_private;
2948         uint32_t csq_stat, csq2_stat, tmp;
2949         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2950         unsigned i;
2951
2952         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2953         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2954         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2955         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2956         r_rptr = (csq_stat >> 0) & 0x3ff;
2957         r_wptr = (csq_stat >> 10) & 0x3ff;
2958         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2959         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2960         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2961         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2962         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2963         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2964         seq_printf(m, "Ring rptr %u\n", r_rptr);
2965         seq_printf(m, "Ring wptr %u\n", r_wptr);
2966         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2967         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2968         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2969         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2970         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2971          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2972         seq_printf(m, "Ring fifo:\n");
2973         for (i = 0; i < 256; i++) {
2974                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2975                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2976                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2977         }
2978         seq_printf(m, "Indirect1 fifo:\n");
2979         for (i = 256; i <= 512; i++) {
2980                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2981                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2982                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2983         }
2984         seq_printf(m, "Indirect2 fifo:\n");
2985         for (i = 640; i < ib1_wptr; i++) {
2986                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2987                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2988                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2989         }
2990         return 0;
2991 }
2992
2993 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2994 {
2995         struct drm_info_node *node = (struct drm_info_node *) m->private;
2996         struct drm_device *dev = node->minor->dev;
2997         struct radeon_device *rdev = dev->dev_private;
2998         uint32_t tmp;
2999
3000         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
3001         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
3002         tmp = RREG32(RADEON_MC_FB_LOCATION);
3003         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
3004         tmp = RREG32(RADEON_BUS_CNTL);
3005         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
3006         tmp = RREG32(RADEON_MC_AGP_LOCATION);
3007         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
3008         tmp = RREG32(RADEON_AGP_BASE);
3009         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
3010         tmp = RREG32(RADEON_HOST_PATH_CNTL);
3011         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
3012         tmp = RREG32(0x01D0);
3013         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
3014         tmp = RREG32(RADEON_AIC_LO_ADDR);
3015         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
3016         tmp = RREG32(RADEON_AIC_HI_ADDR);
3017         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
3018         tmp = RREG32(0x01E4);
3019         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
3020         return 0;
3021 }
3022
3023 static struct drm_info_list r100_debugfs_rbbm_list[] = {
3024         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
3025 };
3026
3027 static struct drm_info_list r100_debugfs_cp_list[] = {
3028         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
3029         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
3030 };
3031
3032 static struct drm_info_list r100_debugfs_mc_info_list[] = {
3033         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
3034 };
3035 #endif
3036
3037 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
3038 {
3039 #if defined(CONFIG_DEBUG_FS)
3040         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
3041 #else
3042         return 0;
3043 #endif
3044 }
3045
3046 int r100_debugfs_cp_init(struct radeon_device *rdev)
3047 {
3048 #if defined(CONFIG_DEBUG_FS)
3049         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
3050 #else
3051         return 0;
3052 #endif
3053 }
3054
3055 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
3056 {
3057 #if defined(CONFIG_DEBUG_FS)
3058         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
3059 #else
3060         return 0;
3061 #endif
3062 }
3063
3064 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
3065                          uint32_t tiling_flags, uint32_t pitch,
3066                          uint32_t offset, uint32_t obj_size)
3067 {
3068         int surf_index = reg * 16;
3069         int flags = 0;
3070
3071         if (rdev->family <= CHIP_RS200) {
3072                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3073                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3074                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
3075                 if (tiling_flags & RADEON_TILING_MACRO)
3076                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
3077                 /* setting pitch to 0 disables tiling */
3078                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
3079                                 == 0)
3080                         pitch = 0;
3081         } else if (rdev->family <= CHIP_RV280) {
3082                 if (tiling_flags & (RADEON_TILING_MACRO))
3083                         flags |= R200_SURF_TILE_COLOR_MACRO;
3084                 if (tiling_flags & RADEON_TILING_MICRO)
3085                         flags |= R200_SURF_TILE_COLOR_MICRO;
3086         } else {
3087                 if (tiling_flags & RADEON_TILING_MACRO)
3088                         flags |= R300_SURF_TILE_MACRO;
3089                 if (tiling_flags & RADEON_TILING_MICRO)
3090                         flags |= R300_SURF_TILE_MICRO;
3091         }
3092
3093         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
3094                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
3095         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
3096                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
3097
3098         /* r100/r200 divide by 16 */
3099         if (rdev->family < CHIP_R300)
3100                 flags |= pitch / 16;
3101         else
3102                 flags |= pitch / 8;
3103
3104
3105         DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
3106         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
3107         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
3108         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
3109         return 0;
3110 }
3111
3112 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
3113 {
3114         int surf_index = reg * 16;
3115         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
3116 }
3117
3118 void r100_bandwidth_update(struct radeon_device *rdev)
3119 {
3120         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
3121         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
3122         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
3123         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
3124         fixed20_12 memtcas_ff[8] = {
3125                 dfixed_init(1),
3126                 dfixed_init(2),
3127                 dfixed_init(3),
3128                 dfixed_init(0),
3129                 dfixed_init_half(1),
3130                 dfixed_init_half(2),
3131                 dfixed_init(0),
3132         };
3133         fixed20_12 memtcas_rs480_ff[8] = {
3134                 dfixed_init(0),
3135                 dfixed_init(1),
3136                 dfixed_init(2),
3137                 dfixed_init(3),
3138                 dfixed_init(0),
3139                 dfixed_init_half(1),
3140                 dfixed_init_half(2),
3141                 dfixed_init_half(3),
3142         };
3143         fixed20_12 memtcas2_ff[8] = {
3144                 dfixed_init(0),
3145                 dfixed_init(1),
3146                 dfixed_init(2),
3147                 dfixed_init(3),
3148                 dfixed_init(4),
3149                 dfixed_init(5),
3150                 dfixed_init(6),
3151                 dfixed_init(7),
3152         };
3153         fixed20_12 memtrbs[8] = {
3154                 dfixed_init(1),
3155                 dfixed_init_half(1),
3156                 dfixed_init(2),
3157                 dfixed_init_half(2),
3158                 dfixed_init(3),
3159                 dfixed_init_half(3),
3160                 dfixed_init(4),
3161                 dfixed_init_half(4)
3162         };
3163         fixed20_12 memtrbs_r4xx[8] = {
3164                 dfixed_init(4),
3165                 dfixed_init(5),
3166                 dfixed_init(6),
3167                 dfixed_init(7),
3168                 dfixed_init(8),
3169                 dfixed_init(9),
3170                 dfixed_init(10),
3171                 dfixed_init(11)
3172         };
3173         fixed20_12 min_mem_eff;
3174         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
3175         fixed20_12 cur_latency_mclk, cur_latency_sclk;
3176         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
3177                 disp_drain_rate2, read_return_rate;
3178         fixed20_12 time_disp1_drop_priority;
3179         int c;
3180         int cur_size = 16;       /* in octawords */
3181         int critical_point = 0, critical_point2;
3182 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
3183         int stop_req, max_stop_req;
3184         struct drm_display_mode *mode1 = NULL;
3185         struct drm_display_mode *mode2 = NULL;
3186         uint32_t pixel_bytes1 = 0;
3187         uint32_t pixel_bytes2 = 0;
3188
3189         radeon_update_display_priority(rdev);
3190
3191         if (rdev->mode_info.crtcs[0]->base.enabled) {
3192                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
3193                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.primary->fb->bits_per_pixel / 8;
3194         }
3195         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3196                 if (rdev->mode_info.crtcs[1]->base.enabled) {
3197                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
3198                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.primary->fb->bits_per_pixel / 8;
3199                 }
3200         }
3201
3202         min_mem_eff.full = dfixed_const_8(0);
3203         /* get modes */
3204         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
3205                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
3206                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
3207                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
3208                 /* check crtc enables */
3209                 if (mode2)
3210                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
3211                 if (mode1)
3212                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
3213                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
3214         }
3215
3216         /*
3217          * determine is there is enough bw for current mode
3218          */
3219         sclk_ff = rdev->pm.sclk;
3220         mclk_ff = rdev->pm.mclk;
3221
3222         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
3223         temp_ff.full = dfixed_const(temp);
3224         mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
3225
3226         pix_clk.full = 0;
3227         pix_clk2.full = 0;
3228         peak_disp_bw.full = 0;
3229         if (mode1) {
3230                 temp_ff.full = dfixed_const(1000);
3231                 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
3232                 pix_clk.full = dfixed_div(pix_clk, temp_ff);
3233                 temp_ff.full = dfixed_const(pixel_bytes1);
3234                 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
3235         }
3236         if (mode2) {
3237                 temp_ff.full = dfixed_const(1000);
3238                 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
3239                 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
3240                 temp_ff.full = dfixed_const(pixel_bytes2);
3241                 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
3242         }
3243
3244         mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
3245         if (peak_disp_bw.full >= mem_bw.full) {
3246                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
3247                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
3248         }
3249
3250         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
3251         temp = RREG32(RADEON_MEM_TIMING_CNTL);
3252         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
3253                 mem_trcd = ((temp >> 2) & 0x3) + 1;
3254                 mem_trp  = ((temp & 0x3)) + 1;
3255                 mem_tras = ((temp & 0x70) >> 4) + 1;
3256         } else if (rdev->family == CHIP_R300 ||
3257                    rdev->family == CHIP_R350) { /* r300, r350 */
3258                 mem_trcd = (temp & 0x7) + 1;
3259                 mem_trp = ((temp >> 8) & 0x7) + 1;
3260                 mem_tras = ((temp >> 11) & 0xf) + 4;
3261         } else if (rdev->family == CHIP_RV350 ||
3262                    rdev->family <= CHIP_RV380) {
3263                 /* rv3x0 */
3264                 mem_trcd = (temp & 0x7) + 3;
3265                 mem_trp = ((temp >> 8) & 0x7) + 3;
3266                 mem_tras = ((temp >> 11) & 0xf) + 6;
3267         } else if (rdev->family == CHIP_R420 ||
3268                    rdev->family == CHIP_R423 ||
3269                    rdev->family == CHIP_RV410) {
3270                 /* r4xx */
3271                 mem_trcd = (temp & 0xf) + 3;
3272                 if (mem_trcd > 15)
3273                         mem_trcd = 15;
3274                 mem_trp = ((temp >> 8) & 0xf) + 3;
3275                 if (mem_trp > 15)
3276                         mem_trp = 15;
3277                 mem_tras = ((temp >> 12) & 0x1f) + 6;
3278                 if (mem_tras > 31)
3279                         mem_tras = 31;
3280         } else { /* RV200, R200 */
3281                 mem_trcd = (temp & 0x7) + 1;
3282                 mem_trp = ((temp >> 8) & 0x7) + 1;
3283                 mem_tras = ((temp >> 12) & 0xf) + 4;
3284         }
3285         /* convert to FF */
3286         trcd_ff.full = dfixed_const(mem_trcd);
3287         trp_ff.full = dfixed_const(mem_trp);
3288         tras_ff.full = dfixed_const(mem_tras);
3289
3290         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
3291         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
3292         data = (temp & (7 << 20)) >> 20;
3293         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
3294                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
3295                         tcas_ff = memtcas_rs480_ff[data];
3296                 else
3297                         tcas_ff = memtcas_ff[data];
3298         } else
3299                 tcas_ff = memtcas2_ff[data];
3300
3301         if (rdev->family == CHIP_RS400 ||
3302             rdev->family == CHIP_RS480) {
3303                 /* extra cas latency stored in bits 23-25 0-4 clocks */
3304                 data = (temp >> 23) & 0x7;
3305                 if (data < 5)
3306                         tcas_ff.full += dfixed_const(data);
3307         }
3308
3309         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
3310                 /* on the R300, Tcas is included in Trbs.
3311                  */
3312                 temp = RREG32(RADEON_MEM_CNTL);
3313                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
3314                 if (data == 1) {
3315                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
3316                                 temp = RREG32(R300_MC_IND_INDEX);
3317                                 temp &= ~R300_MC_IND_ADDR_MASK;
3318                                 temp |= R300_MC_READ_CNTL_CD_mcind;
3319                                 WREG32(R300_MC_IND_INDEX, temp);
3320                                 temp = RREG32(R300_MC_IND_DATA);
3321                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
3322                         } else {
3323                                 temp = RREG32(R300_MC_READ_CNTL_AB);
3324                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3325                         }
3326                 } else {
3327                         temp = RREG32(R300_MC_READ_CNTL_AB);
3328                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
3329                 }
3330                 if (rdev->family == CHIP_RV410 ||
3331                     rdev->family == CHIP_R420 ||
3332                     rdev->family == CHIP_R423)
3333                         trbs_ff = memtrbs_r4xx[data];
3334                 else
3335                         trbs_ff = memtrbs[data];
3336                 tcas_ff.full += trbs_ff.full;
3337         }
3338
3339         sclk_eff_ff.full = sclk_ff.full;
3340
3341         if (rdev->flags & RADEON_IS_AGP) {
3342                 fixed20_12 agpmode_ff;
3343                 agpmode_ff.full = dfixed_const(radeon_agpmode);
3344                 temp_ff.full = dfixed_const_666(16);
3345                 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
3346         }
3347         /* TODO PCIE lanes may affect this - agpmode == 16?? */
3348
3349         if (ASIC_IS_R300(rdev)) {
3350                 sclk_delay_ff.full = dfixed_const(250);
3351         } else {
3352                 if ((rdev->family == CHIP_RV100) ||
3353                     rdev->flags & RADEON_IS_IGP) {
3354                         if (rdev->mc.vram_is_ddr)
3355                                 sclk_delay_ff.full = dfixed_const(41);
3356                         else
3357                                 sclk_delay_ff.full = dfixed_const(33);
3358                 } else {
3359                         if (rdev->mc.vram_width == 128)
3360                                 sclk_delay_ff.full = dfixed_const(57);
3361                         else
3362                                 sclk_delay_ff.full = dfixed_const(41);
3363                 }
3364         }
3365
3366         mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
3367
3368         if (rdev->mc.vram_is_ddr) {
3369                 if (rdev->mc.vram_width == 32) {
3370                         k1.full = dfixed_const(40);
3371                         c  = 3;
3372                 } else {
3373                         k1.full = dfixed_const(20);
3374                         c  = 1;
3375                 }
3376         } else {
3377                 k1.full = dfixed_const(40);
3378                 c  = 3;
3379         }
3380
3381         temp_ff.full = dfixed_const(2);
3382         mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
3383         temp_ff.full = dfixed_const(c);
3384         mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
3385         temp_ff.full = dfixed_const(4);
3386         mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
3387         mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
3388         mc_latency_mclk.full += k1.full;
3389
3390         mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
3391         mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
3392
3393         /*
3394           HW cursor time assuming worst case of full size colour cursor.
3395         */
3396         temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
3397         temp_ff.full += trcd_ff.full;
3398         if (temp_ff.full < tras_ff.full)
3399                 temp_ff.full = tras_ff.full;
3400         cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
3401
3402         temp_ff.full = dfixed_const(cur_size);
3403         cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
3404         /*
3405           Find the total latency for the display data.
3406         */
3407         disp_latency_overhead.full = dfixed_const(8);
3408         disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
3409         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
3410         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
3411
3412         if (mc_latency_mclk.full > mc_latency_sclk.full)
3413                 disp_latency.full = mc_latency_mclk.full;
3414         else
3415                 disp_latency.full = mc_latency_sclk.full;
3416
3417         /* setup Max GRPH_STOP_REQ default value */
3418         if (ASIC_IS_RV100(rdev))
3419                 max_stop_req = 0x5c;
3420         else
3421                 max_stop_req = 0x7c;
3422
3423         if (mode1) {
3424                 /*  CRTC1
3425                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
3426                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
3427                 */
3428                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
3429
3430                 if (stop_req > max_stop_req)
3431                         stop_req = max_stop_req;
3432
3433                 /*
3434                   Find the drain rate of the display buffer.
3435                 */
3436                 temp_ff.full = dfixed_const((16/pixel_bytes1));
3437                 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
3438
3439                 /*
3440                   Find the critical point of the display buffer.
3441                 */
3442                 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
3443                 crit_point_ff.full += dfixed_const_half(0);
3444
3445                 critical_point = dfixed_trunc(crit_point_ff);
3446
3447                 if (rdev->disp_priority == 2) {
3448                         critical_point = 0;
3449                 }
3450
3451                 /*
3452                   The critical point should never be above max_stop_req-4.  Setting
3453                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3454                 */
3455                 if (max_stop_req - critical_point < 4)
3456                         critical_point = 0;
3457
3458                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3459                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3460                         critical_point = 0x10;
3461                 }
3462
3463                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3464                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3465                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3466                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3467                 if ((rdev->family == CHIP_R350) &&
3468                     (stop_req > 0x15)) {
3469                         stop_req -= 0x10;
3470                 }
3471                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3472                 temp |= RADEON_GRPH_BUFFER_SIZE;
3473                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3474                           RADEON_GRPH_CRITICAL_AT_SOF |
3475                           RADEON_GRPH_STOP_CNTL);
3476                 /*
3477                   Write the result into the register.
3478                 */
3479                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3480                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3481
3482 #if 0
3483                 if ((rdev->family == CHIP_RS400) ||
3484                     (rdev->family == CHIP_RS480)) {
3485                         /* attempt to program RS400 disp regs correctly ??? */
3486                         temp = RREG32(RS400_DISP1_REG_CNTL);
3487                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3488                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
3489                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3490                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3491                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3492                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
3493                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3494                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3495                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3496                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3497                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3498                 }
3499 #endif
3500
3501                 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3502                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
3503                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3504         }
3505
3506         if (mode2) {
3507                 u32 grph2_cntl;
3508                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3509
3510                 if (stop_req > max_stop_req)
3511                         stop_req = max_stop_req;
3512
3513                 /*
3514                   Find the drain rate of the display buffer.
3515                 */
3516                 temp_ff.full = dfixed_const((16/pixel_bytes2));
3517                 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3518
3519                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3520                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3521                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3522                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3523                 if ((rdev->family == CHIP_R350) &&
3524                     (stop_req > 0x15)) {
3525                         stop_req -= 0x10;
3526                 }
3527                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3528                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3529                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
3530                           RADEON_GRPH_CRITICAL_AT_SOF |
3531                           RADEON_GRPH_STOP_CNTL);
3532
3533                 if ((rdev->family == CHIP_RS100) ||
3534                     (rdev->family == CHIP_RS200))
3535                         critical_point2 = 0;
3536                 else {
3537                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3538                         temp_ff.full = dfixed_const(temp);
3539                         temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3540                         if (sclk_ff.full < temp_ff.full)
3541                                 temp_ff.full = sclk_ff.full;
3542
3543                         read_return_rate.full = temp_ff.full;
3544
3545                         if (mode1) {
3546                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3547                                 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3548                         } else {
3549                                 time_disp1_drop_priority.full = 0;
3550                         }
3551                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3552                         crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3553                         crit_point_ff.full += dfixed_const_half(0);
3554
3555                         critical_point2 = dfixed_trunc(crit_point_ff);
3556
3557                         if (rdev->disp_priority == 2) {
3558                                 critical_point2 = 0;
3559                         }
3560
3561                         if (max_stop_req - critical_point2 < 4)
3562                                 critical_point2 = 0;
3563
3564                 }
3565
3566                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3567                         /* some R300 cards have problem with this set to 0 */
3568                         critical_point2 = 0x10;
3569                 }
3570
3571                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3572                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3573
3574                 if ((rdev->family == CHIP_RS400) ||
3575                     (rdev->family == CHIP_RS480)) {
3576 #if 0
3577                         /* attempt to program RS400 disp2 regs correctly ??? */
3578                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
3579                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3580                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
3581                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3582                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3583                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3584                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
3585                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3586                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3587                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3588                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3589                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3590 #endif
3591                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3592                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3593                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
3594                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3595                 }
3596
3597                 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3598                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3599         }
3600 }
3601
3602 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
3603 {
3604         uint32_t scratch;
3605         uint32_t tmp = 0;
3606         unsigned i;
3607         int r;
3608
3609         r = radeon_scratch_get(rdev, &scratch);
3610         if (r) {
3611                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3612                 return r;
3613         }
3614         WREG32(scratch, 0xCAFEDEAD);
3615         r = radeon_ring_lock(rdev, ring, 2);
3616         if (r) {
3617                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3618                 radeon_scratch_free(rdev, scratch);
3619                 return r;
3620         }
3621         radeon_ring_write(ring, PACKET0(scratch, 0));
3622         radeon_ring_write(ring, 0xDEADBEEF);
3623         radeon_ring_unlock_commit(rdev, ring);
3624         for (i = 0; i < rdev->usec_timeout; i++) {
3625                 tmp = RREG32(scratch);
3626                 if (tmp == 0xDEADBEEF) {
3627                         break;
3628                 }
3629                 DRM_UDELAY(1);
3630         }
3631         if (i < rdev->usec_timeout) {
3632                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3633         } else {
3634                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3635                           scratch, tmp);
3636                 r = -EINVAL;
3637         }
3638         radeon_scratch_free(rdev, scratch);
3639         return r;
3640 }
3641
3642 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3643 {
3644         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3645
3646         if (ring->rptr_save_reg) {
3647                 u32 next_rptr = ring->wptr + 2 + 3;
3648                 radeon_ring_write(ring, PACKET0(ring->rptr_save_reg, 0));
3649                 radeon_ring_write(ring, next_rptr);
3650         }
3651
3652         radeon_ring_write(ring, PACKET0(RADEON_CP_IB_BASE, 1));
3653         radeon_ring_write(ring, ib->gpu_addr);
3654         radeon_ring_write(ring, ib->length_dw);
3655 }
3656
3657 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
3658 {
3659         struct radeon_ib ib;
3660         uint32_t scratch;
3661         uint32_t tmp = 0;
3662         unsigned i;
3663         int r;
3664
3665         r = radeon_scratch_get(rdev, &scratch);
3666         if (r) {
3667                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3668                 return r;
3669         }
3670         WREG32(scratch, 0xCAFEDEAD);
3671         r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib, NULL, 256);
3672         if (r) {
3673                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
3674                 goto free_scratch;
3675         }
3676         ib.ptr[0] = PACKET0(scratch, 0);
3677         ib.ptr[1] = 0xDEADBEEF;
3678         ib.ptr[2] = PACKET2(0);
3679         ib.ptr[3] = PACKET2(0);
3680         ib.ptr[4] = PACKET2(0);
3681         ib.ptr[5] = PACKET2(0);
3682         ib.ptr[6] = PACKET2(0);
3683         ib.ptr[7] = PACKET2(0);
3684         ib.length_dw = 8;
3685         r = radeon_ib_schedule(rdev, &ib, NULL);
3686         if (r) {
3687                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
3688                 goto free_ib;
3689         }
3690         r = radeon_fence_wait(ib.fence, false);
3691         if (r) {
3692                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
3693                 goto free_ib;
3694         }
3695         for (i = 0; i < rdev->usec_timeout; i++) {
3696                 tmp = RREG32(scratch);
3697                 if (tmp == 0xDEADBEEF) {
3698                         break;
3699                 }
3700                 DRM_UDELAY(1);
3701         }
3702         if (i < rdev->usec_timeout) {
3703                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3704         } else {
3705                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3706                           scratch, tmp);
3707                 r = -EINVAL;
3708         }
3709 free_ib:
3710         radeon_ib_free(rdev, &ib);
3711 free_scratch:
3712         radeon_scratch_free(rdev, scratch);
3713         return r;
3714 }
3715
3716 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3717 {
3718         /* Shutdown CP we shouldn't need to do that but better be safe than
3719          * sorry
3720          */
3721         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
3722         WREG32(R_000740_CP_CSQ_CNTL, 0);
3723
3724         /* Save few CRTC registers */
3725         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3726         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3727         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3728         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3729         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3730                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3731                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3732         }
3733
3734         /* Disable VGA aperture access */
3735         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3736         /* Disable cursor, overlay, crtc */
3737         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3738         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3739                                         S_000054_CRTC_DISPLAY_DIS(1));
3740         WREG32(R_000050_CRTC_GEN_CNTL,
3741                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3742                         S_000050_CRTC_DISP_REQ_EN_B(1));
3743         WREG32(R_000420_OV0_SCALE_CNTL,
3744                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3745         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3746         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3747                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3748                                                 S_000360_CUR2_LOCK(1));
3749                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3750                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3751                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3752                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3753                 WREG32(R_000360_CUR2_OFFSET,
3754                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3755         }
3756 }
3757
3758 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3759 {
3760         /* Update base address for crtc */
3761         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3762         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3763                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3764         }
3765         /* Restore CRTC registers */
3766         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3767         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3768         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3769         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3770                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3771         }
3772 }
3773
3774 void r100_vga_render_disable(struct radeon_device *rdev)
3775 {
3776         u32 tmp;
3777
3778         tmp = RREG8(R_0003C2_GENMO_WT);
3779         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3780 }
3781
3782 static void r100_debugfs(struct radeon_device *rdev)
3783 {
3784         int r;
3785
3786         r = r100_debugfs_mc_info_init(rdev);
3787         if (r)
3788                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3789 }
3790
3791 static void r100_mc_program(struct radeon_device *rdev)
3792 {
3793         struct r100_mc_save save;
3794
3795         /* Stops all mc clients */
3796         r100_mc_stop(rdev, &save);
3797         if (rdev->flags & RADEON_IS_AGP) {
3798                 WREG32(R_00014C_MC_AGP_LOCATION,
3799                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3800                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3801                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3802                 if (rdev->family > CHIP_RV200)
3803                         WREG32(R_00015C_AGP_BASE_2,
3804                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3805         } else {
3806                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3807                 WREG32(R_000170_AGP_BASE, 0);
3808                 if (rdev->family > CHIP_RV200)
3809                         WREG32(R_00015C_AGP_BASE_2, 0);
3810         }
3811         /* Wait for mc idle */
3812         if (r100_mc_wait_for_idle(rdev))
3813                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3814         /* Program MC, should be a 32bits limited address space */
3815         WREG32(R_000148_MC_FB_LOCATION,
3816                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3817                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3818         r100_mc_resume(rdev, &save);
3819 }
3820
3821 static void r100_clock_startup(struct radeon_device *rdev)
3822 {
3823         u32 tmp;
3824
3825         if (radeon_dynclks != -1 && radeon_dynclks)
3826                 radeon_legacy_set_clock_gating(rdev, 1);
3827         /* We need to force on some of the block */
3828         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3829         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3830         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3831                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3832         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3833 }
3834
3835 static int r100_startup(struct radeon_device *rdev)
3836 {
3837         int r;
3838
3839         /* set common regs */
3840         r100_set_common_regs(rdev);
3841         /* program mc */
3842         r100_mc_program(rdev);
3843         /* Resume clock */
3844         r100_clock_startup(rdev);
3845         /* Initialize GART (initialize after TTM so we can allocate
3846          * memory through TTM but finalize after TTM) */
3847         r100_enable_bm(rdev);
3848         if (rdev->flags & RADEON_IS_PCI) {
3849                 r = r100_pci_gart_enable(rdev);
3850                 if (r)
3851                         return r;
3852         }
3853
3854         /* allocate wb buffer */
3855         r = radeon_wb_init(rdev);
3856         if (r)
3857                 return r;
3858
3859         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3860         if (r) {
3861                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3862                 return r;
3863         }
3864
3865         /* Enable IRQ */
3866         if (!rdev->irq.installed) {
3867                 r = radeon_irq_kms_init(rdev);
3868                 if (r)
3869                         return r;
3870         }
3871
3872         r100_irq_set(rdev);
3873         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3874         /* 1M ring buffer */
3875         r = r100_cp_init(rdev, 1024 * 1024);
3876         if (r) {
3877                 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3878                 return r;
3879         }
3880
3881         r = radeon_ib_pool_init(rdev);
3882         if (r) {
3883                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3884                 return r;
3885         }
3886
3887         return 0;
3888 }
3889
3890 int r100_resume(struct radeon_device *rdev)
3891 {
3892         int r;
3893
3894         /* Make sur GART are not working */
3895         if (rdev->flags & RADEON_IS_PCI)
3896                 r100_pci_gart_disable(rdev);
3897         /* Resume clock before doing reset */
3898         r100_clock_startup(rdev);
3899         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3900         if (radeon_asic_reset(rdev)) {
3901                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3902                         RREG32(R_000E40_RBBM_STATUS),
3903                         RREG32(R_0007C0_CP_STAT));
3904         }
3905         /* post */
3906         radeon_combios_asic_init(rdev->ddev);
3907         /* Resume clock after posting */
3908         r100_clock_startup(rdev);
3909         /* Initialize surface registers */
3910         radeon_surface_init(rdev);
3911
3912         rdev->accel_working = true;
3913         r = r100_startup(rdev);
3914         if (r) {
3915                 rdev->accel_working = false;
3916         }
3917         return r;
3918 }
3919
3920 int r100_suspend(struct radeon_device *rdev)
3921 {
3922         radeon_pm_suspend(rdev);
3923         r100_cp_disable(rdev);
3924         radeon_wb_disable(rdev);
3925         r100_irq_disable(rdev);
3926         if (rdev->flags & RADEON_IS_PCI)
3927                 r100_pci_gart_disable(rdev);
3928         return 0;
3929 }
3930
3931 void r100_fini(struct radeon_device *rdev)
3932 {
3933         radeon_pm_fini(rdev);
3934         r100_cp_fini(rdev);
3935         radeon_wb_fini(rdev);
3936         radeon_ib_pool_fini(rdev);
3937         radeon_gem_fini(rdev);
3938         if (rdev->flags & RADEON_IS_PCI)
3939                 r100_pci_gart_fini(rdev);
3940         radeon_agp_fini(rdev);
3941         radeon_irq_kms_fini(rdev);
3942         radeon_fence_driver_fini(rdev);
3943         radeon_bo_fini(rdev);
3944         radeon_atombios_fini(rdev);
3945         kfree(rdev->bios);
3946         rdev->bios = NULL;
3947 }
3948
3949 /*
3950  * Due to how kexec works, it can leave the hw fully initialised when it
3951  * boots the new kernel. However doing our init sequence with the CP and
3952  * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3953  * do some quick sanity checks and restore sane values to avoid this
3954  * problem.
3955  */
3956 void r100_restore_sanity(struct radeon_device *rdev)
3957 {
3958         u32 tmp;
3959
3960         tmp = RREG32(RADEON_CP_CSQ_CNTL);
3961         if (tmp) {
3962                 WREG32(RADEON_CP_CSQ_CNTL, 0);
3963         }
3964         tmp = RREG32(RADEON_CP_RB_CNTL);
3965         if (tmp) {
3966                 WREG32(RADEON_CP_RB_CNTL, 0);
3967         }
3968         tmp = RREG32(RADEON_SCRATCH_UMSK);
3969         if (tmp) {
3970                 WREG32(RADEON_SCRATCH_UMSK, 0);
3971         }
3972 }
3973
3974 int r100_init(struct radeon_device *rdev)
3975 {
3976         int r;
3977
3978         /* Register debugfs file specific to this group of asics */
3979         r100_debugfs(rdev);
3980         /* Disable VGA */
3981         r100_vga_render_disable(rdev);
3982         /* Initialize scratch registers */
3983         radeon_scratch_init(rdev);
3984         /* Initialize surface registers */
3985         radeon_surface_init(rdev);
3986         /* sanity check some register to avoid hangs like after kexec */
3987         r100_restore_sanity(rdev);
3988         /* TODO: disable VGA need to use VGA request */
3989         /* BIOS*/
3990         if (!radeon_get_bios(rdev)) {
3991                 if (ASIC_IS_AVIVO(rdev))
3992                         return -EINVAL;
3993         }
3994         if (rdev->is_atom_bios) {
3995                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3996                 return -EINVAL;
3997         } else {
3998                 r = radeon_combios_init(rdev);
3999                 if (r)
4000                         return r;
4001         }
4002         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
4003         if (radeon_asic_reset(rdev)) {
4004                 dev_warn(rdev->dev,
4005                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
4006                         RREG32(R_000E40_RBBM_STATUS),
4007                         RREG32(R_0007C0_CP_STAT));
4008         }
4009         /* check if cards are posted or not */
4010         if (radeon_boot_test_post_card(rdev) == false)
4011                 return -EINVAL;
4012         /* Set asic errata */
4013         r100_errata(rdev);
4014         /* Initialize clocks */
4015         radeon_get_clock_info(rdev->ddev);
4016         /* initialize AGP */
4017         if (rdev->flags & RADEON_IS_AGP) {
4018                 r = radeon_agp_init(rdev);
4019                 if (r) {
4020                         radeon_agp_disable(rdev);
4021                 }
4022         }
4023         /* initialize VRAM */
4024         r100_mc_init(rdev);
4025         /* Fence driver */
4026         r = radeon_fence_driver_init(rdev);
4027         if (r)
4028                 return r;
4029         /* Memory manager */
4030         r = radeon_bo_init(rdev);
4031         if (r)
4032                 return r;
4033         if (rdev->flags & RADEON_IS_PCI) {
4034                 r = r100_pci_gart_init(rdev);
4035                 if (r)
4036                         return r;
4037         }
4038         r100_set_safe_registers(rdev);
4039
4040         /* Initialize power management */
4041         radeon_pm_init(rdev);
4042
4043         rdev->accel_working = true;
4044         r = r100_startup(rdev);
4045         if (r) {
4046                 /* Somethings want wront with the accel init stop accel */
4047                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
4048                 r100_cp_fini(rdev);
4049                 radeon_wb_fini(rdev);
4050                 radeon_ib_pool_fini(rdev);
4051                 radeon_irq_kms_fini(rdev);
4052                 if (rdev->flags & RADEON_IS_PCI)
4053                         r100_pci_gart_fini(rdev);
4054                 rdev->accel_working = false;
4055         }
4056         return 0;
4057 }
4058
4059 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg,
4060                       bool always_indirect)
4061 {
4062         if (reg < rdev->rmmio_size && !always_indirect)
4063                 return readl(((void __iomem *)rdev->rmmio) + reg);
4064         else {
4065                 unsigned long flags;
4066                 uint32_t ret;
4067
4068                 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4069                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4070                 ret = readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4071                 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4072
4073                 return ret;
4074         }
4075 }
4076
4077 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v,
4078                   bool always_indirect)
4079 {
4080         if (reg < rdev->rmmio_size && !always_indirect)
4081                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
4082         else {
4083                 unsigned long flags;
4084
4085                 spin_lock_irqsave(&rdev->mmio_idx_lock, flags);
4086                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
4087                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
4088                 spin_unlock_irqrestore(&rdev->mmio_idx_lock, flags);
4089         }
4090 }
4091
4092 u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
4093 {
4094         if (reg < rdev->rio_mem_size)
4095                 return ioread32(rdev->rio_mem + reg);
4096         else {
4097                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4098                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
4099         }
4100 }
4101
4102 void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
4103 {
4104         if (reg < rdev->rio_mem_size)
4105                 iowrite32(v, rdev->rio_mem + reg);
4106         else {
4107                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
4108                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
4109         }
4110 }