2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
35 #include "radeon_asic.h"
42 #include <linux/firmware.h>
43 #include <linux/platform_device.h>
45 #include "r100_reg_safe.h"
46 #include "rn50_reg_safe.h"
49 #define FIRMWARE_R100 "radeon/R100_cp.bin"
50 #define FIRMWARE_R200 "radeon/R200_cp.bin"
51 #define FIRMWARE_R300 "radeon/R300_cp.bin"
52 #define FIRMWARE_R420 "radeon/R420_cp.bin"
53 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
54 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
55 #define FIRMWARE_R520 "radeon/R520_cp.bin"
57 MODULE_FIRMWARE(FIRMWARE_R100);
58 MODULE_FIRMWARE(FIRMWARE_R200);
59 MODULE_FIRMWARE(FIRMWARE_R300);
60 MODULE_FIRMWARE(FIRMWARE_R420);
61 MODULE_FIRMWARE(FIRMWARE_RS690);
62 MODULE_FIRMWARE(FIRMWARE_RS600);
63 MODULE_FIRMWARE(FIRMWARE_R520);
65 #include "r100_track.h"
67 /* This files gather functions specifics to:
68 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
71 void r100_pre_page_flip(struct radeon_device *rdev, int crtc)
73 /* enable the pflip int */
74 radeon_irq_kms_pflip_irq_get(rdev, crtc);
77 void r100_post_page_flip(struct radeon_device *rdev, int crtc)
79 /* disable the pflip int */
80 radeon_irq_kms_pflip_irq_put(rdev, crtc);
83 u32 r100_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
85 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
86 u32 tmp = ((u32)crtc_base) | RADEON_CRTC_OFFSET__OFFSET_LOCK;
89 /* Lock the graphics update lock */
90 /* update the scanout addresses */
91 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
93 /* Wait for update_pending to go high. */
94 for (i = 0; i < rdev->usec_timeout; i++) {
95 if (RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET)
99 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
101 /* Unlock the lock, so double-buffering can take place inside vblank */
102 tmp &= ~RADEON_CRTC_OFFSET__OFFSET_LOCK;
103 WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, tmp);
105 /* Return current update_pending status: */
106 return RREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET;
109 void r100_pm_get_dynpm_state(struct radeon_device *rdev)
112 rdev->pm.dynpm_can_upclock = true;
113 rdev->pm.dynpm_can_downclock = true;
115 switch (rdev->pm.dynpm_planned_action) {
116 case DYNPM_ACTION_MINIMUM:
117 rdev->pm.requested_power_state_index = 0;
118 rdev->pm.dynpm_can_downclock = false;
120 case DYNPM_ACTION_DOWNCLOCK:
121 if (rdev->pm.current_power_state_index == 0) {
122 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
123 rdev->pm.dynpm_can_downclock = false;
125 if (rdev->pm.active_crtc_count > 1) {
126 for (i = 0; i < rdev->pm.num_power_states; i++) {
127 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
129 else if (i >= rdev->pm.current_power_state_index) {
130 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
133 rdev->pm.requested_power_state_index = i;
138 rdev->pm.requested_power_state_index =
139 rdev->pm.current_power_state_index - 1;
141 /* don't use the power state if crtcs are active and no display flag is set */
142 if ((rdev->pm.active_crtc_count > 0) &&
143 (rdev->pm.power_state[rdev->pm.requested_power_state_index].clock_info[0].flags &
144 RADEON_PM_MODE_NO_DISPLAY)) {
145 rdev->pm.requested_power_state_index++;
148 case DYNPM_ACTION_UPCLOCK:
149 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
150 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
151 rdev->pm.dynpm_can_upclock = false;
153 if (rdev->pm.active_crtc_count > 1) {
154 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
155 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
157 else if (i <= rdev->pm.current_power_state_index) {
158 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
161 rdev->pm.requested_power_state_index = i;
166 rdev->pm.requested_power_state_index =
167 rdev->pm.current_power_state_index + 1;
170 case DYNPM_ACTION_DEFAULT:
171 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
172 rdev->pm.dynpm_can_upclock = false;
174 case DYNPM_ACTION_NONE:
176 DRM_ERROR("Requested mode for not defined action\n");
179 /* only one clock mode per power state */
180 rdev->pm.requested_clock_mode_index = 0;
182 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
183 rdev->pm.power_state[rdev->pm.requested_power_state_index].
184 clock_info[rdev->pm.requested_clock_mode_index].sclk,
185 rdev->pm.power_state[rdev->pm.requested_power_state_index].
186 clock_info[rdev->pm.requested_clock_mode_index].mclk,
187 rdev->pm.power_state[rdev->pm.requested_power_state_index].
191 void r100_pm_init_profile(struct radeon_device *rdev)
194 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
195 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
196 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
197 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
199 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
200 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
201 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
202 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
204 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
205 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
206 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
207 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
209 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
210 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
211 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
212 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
214 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
215 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
216 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
217 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
219 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
220 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
221 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
222 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
224 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
225 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
226 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
227 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
230 void r100_pm_misc(struct radeon_device *rdev)
232 int requested_index = rdev->pm.requested_power_state_index;
233 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
234 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
235 u32 tmp, sclk_cntl, sclk_cntl2, sclk_more_cntl;
237 if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
238 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
239 tmp = RREG32(voltage->gpio.reg);
240 if (voltage->active_high)
241 tmp |= voltage->gpio.mask;
243 tmp &= ~(voltage->gpio.mask);
244 WREG32(voltage->gpio.reg, tmp);
246 udelay(voltage->delay);
248 tmp = RREG32(voltage->gpio.reg);
249 if (voltage->active_high)
250 tmp &= ~voltage->gpio.mask;
252 tmp |= voltage->gpio.mask;
253 WREG32(voltage->gpio.reg, tmp);
255 udelay(voltage->delay);
259 sclk_cntl = RREG32_PLL(SCLK_CNTL);
260 sclk_cntl2 = RREG32_PLL(SCLK_CNTL2);
261 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_SEL(3);
262 sclk_more_cntl = RREG32_PLL(SCLK_MORE_CNTL);
263 sclk_more_cntl &= ~VOLTAGE_DELAY_SEL(3);
264 if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
265 sclk_more_cntl |= REDUCED_SPEED_SCLK_EN;
266 if (ps->misc & ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE)
267 sclk_cntl2 |= REDUCED_SPEED_SCLK_MODE;
269 sclk_cntl2 &= ~REDUCED_SPEED_SCLK_MODE;
270 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2)
271 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(0);
272 else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4)
273 sclk_cntl2 |= REDUCED_SPEED_SCLK_SEL(2);
275 sclk_more_cntl &= ~REDUCED_SPEED_SCLK_EN;
277 if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
278 sclk_more_cntl |= IO_CG_VOLTAGE_DROP;
279 if (voltage->delay) {
280 sclk_more_cntl |= VOLTAGE_DROP_SYNC;
281 switch (voltage->delay) {
283 sclk_more_cntl |= VOLTAGE_DELAY_SEL(0);
286 sclk_more_cntl |= VOLTAGE_DELAY_SEL(1);
289 sclk_more_cntl |= VOLTAGE_DELAY_SEL(2);
292 sclk_more_cntl |= VOLTAGE_DELAY_SEL(3);
296 sclk_more_cntl &= ~VOLTAGE_DROP_SYNC;
298 sclk_more_cntl &= ~IO_CG_VOLTAGE_DROP;
300 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
301 sclk_cntl &= ~FORCE_HDP;
303 sclk_cntl |= FORCE_HDP;
305 WREG32_PLL(SCLK_CNTL, sclk_cntl);
306 WREG32_PLL(SCLK_CNTL2, sclk_cntl2);
307 WREG32_PLL(SCLK_MORE_CNTL, sclk_more_cntl);
310 if ((rdev->flags & RADEON_IS_PCIE) &&
311 !(rdev->flags & RADEON_IS_IGP) &&
312 rdev->asic->set_pcie_lanes &&
314 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
315 radeon_set_pcie_lanes(rdev,
317 DRM_DEBUG_DRIVER("Setting: p: %d\n", ps->pcie_lanes);
321 void r100_pm_prepare(struct radeon_device *rdev)
323 struct drm_device *ddev = rdev->ddev;
324 struct drm_crtc *crtc;
325 struct radeon_crtc *radeon_crtc;
328 /* disable any active CRTCs */
329 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
330 radeon_crtc = to_radeon_crtc(crtc);
331 if (radeon_crtc->enabled) {
332 if (radeon_crtc->crtc_id) {
333 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
334 tmp |= RADEON_CRTC2_DISP_REQ_EN_B;
335 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
337 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
338 tmp |= RADEON_CRTC_DISP_REQ_EN_B;
339 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
345 void r100_pm_finish(struct radeon_device *rdev)
347 struct drm_device *ddev = rdev->ddev;
348 struct drm_crtc *crtc;
349 struct radeon_crtc *radeon_crtc;
352 /* enable any active CRTCs */
353 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
354 radeon_crtc = to_radeon_crtc(crtc);
355 if (radeon_crtc->enabled) {
356 if (radeon_crtc->crtc_id) {
357 tmp = RREG32(RADEON_CRTC2_GEN_CNTL);
358 tmp &= ~RADEON_CRTC2_DISP_REQ_EN_B;
359 WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
361 tmp = RREG32(RADEON_CRTC_GEN_CNTL);
362 tmp &= ~RADEON_CRTC_DISP_REQ_EN_B;
363 WREG32(RADEON_CRTC_GEN_CNTL, tmp);
369 bool r100_gui_idle(struct radeon_device *rdev)
371 if (RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_ACTIVE)
377 /* hpd for digital panel detect/disconnect */
378 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
380 bool connected = false;
384 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
388 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
397 void r100_hpd_set_polarity(struct radeon_device *rdev,
398 enum radeon_hpd_id hpd)
401 bool connected = r100_hpd_sense(rdev, hpd);
405 tmp = RREG32(RADEON_FP_GEN_CNTL);
407 tmp &= ~RADEON_FP_DETECT_INT_POL;
409 tmp |= RADEON_FP_DETECT_INT_POL;
410 WREG32(RADEON_FP_GEN_CNTL, tmp);
413 tmp = RREG32(RADEON_FP2_GEN_CNTL);
415 tmp &= ~RADEON_FP2_DETECT_INT_POL;
417 tmp |= RADEON_FP2_DETECT_INT_POL;
418 WREG32(RADEON_FP2_GEN_CNTL, tmp);
425 void r100_hpd_init(struct radeon_device *rdev)
427 struct drm_device *dev = rdev->ddev;
428 struct drm_connector *connector;
430 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
431 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
432 switch (radeon_connector->hpd.hpd) {
434 rdev->irq.hpd[0] = true;
437 rdev->irq.hpd[1] = true;
442 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
444 if (rdev->irq.installed)
448 void r100_hpd_fini(struct radeon_device *rdev)
450 struct drm_device *dev = rdev->ddev;
451 struct drm_connector *connector;
453 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
454 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
455 switch (radeon_connector->hpd.hpd) {
457 rdev->irq.hpd[0] = false;
460 rdev->irq.hpd[1] = false;
471 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
473 /* TODO: can we do somethings here ? */
474 /* It seems hw only cache one entry so we should discard this
475 * entry otherwise if first GPU GART read hit this entry it
476 * could end up in wrong address. */
479 int r100_pci_gart_init(struct radeon_device *rdev)
483 if (rdev->gart.table.ram.ptr) {
484 WARN(1, "R100 PCI GART already initialized\n");
487 /* Initialize common gart structure */
488 r = radeon_gart_init(rdev);
491 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
492 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
493 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
494 return radeon_gart_table_ram_alloc(rdev);
497 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
498 void r100_enable_bm(struct radeon_device *rdev)
501 /* Enable bus mastering */
502 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
503 WREG32(RADEON_BUS_CNTL, tmp);
506 int r100_pci_gart_enable(struct radeon_device *rdev)
510 radeon_gart_restore(rdev);
511 /* discard memory request outside of configured range */
512 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
513 WREG32(RADEON_AIC_CNTL, tmp);
514 /* set address range for PCI address translate */
515 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
516 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
517 /* set PCI GART page-table base address */
518 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
519 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
520 WREG32(RADEON_AIC_CNTL, tmp);
521 r100_pci_gart_tlb_flush(rdev);
522 rdev->gart.ready = true;
526 void r100_pci_gart_disable(struct radeon_device *rdev)
530 /* discard memory request outside of configured range */
531 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
532 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
533 WREG32(RADEON_AIC_LO_ADDR, 0);
534 WREG32(RADEON_AIC_HI_ADDR, 0);
537 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
539 if (i < 0 || i > rdev->gart.num_gpu_pages) {
542 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
546 void r100_pci_gart_fini(struct radeon_device *rdev)
548 radeon_gart_fini(rdev);
549 r100_pci_gart_disable(rdev);
550 radeon_gart_table_ram_free(rdev);
553 int r100_irq_set(struct radeon_device *rdev)
557 if (!rdev->irq.installed) {
558 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
559 WREG32(R_000040_GEN_INT_CNTL, 0);
562 if (rdev->irq.sw_int) {
563 tmp |= RADEON_SW_INT_ENABLE;
565 if (rdev->irq.gui_idle) {
566 tmp |= RADEON_GUI_IDLE_MASK;
568 if (rdev->irq.crtc_vblank_int[0] ||
569 rdev->irq.pflip[0]) {
570 tmp |= RADEON_CRTC_VBLANK_MASK;
572 if (rdev->irq.crtc_vblank_int[1] ||
573 rdev->irq.pflip[1]) {
574 tmp |= RADEON_CRTC2_VBLANK_MASK;
576 if (rdev->irq.hpd[0]) {
577 tmp |= RADEON_FP_DETECT_MASK;
579 if (rdev->irq.hpd[1]) {
580 tmp |= RADEON_FP2_DETECT_MASK;
582 WREG32(RADEON_GEN_INT_CNTL, tmp);
586 void r100_irq_disable(struct radeon_device *rdev)
590 WREG32(R_000040_GEN_INT_CNTL, 0);
591 /* Wait and acknowledge irq */
593 tmp = RREG32(R_000044_GEN_INT_STATUS);
594 WREG32(R_000044_GEN_INT_STATUS, tmp);
597 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
599 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
600 uint32_t irq_mask = RADEON_SW_INT_TEST |
601 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
602 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
604 /* the interrupt works, but the status bit is permanently asserted */
605 if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
606 if (!rdev->irq.gui_idle_acked)
607 irq_mask |= RADEON_GUI_IDLE_STAT;
611 WREG32(RADEON_GEN_INT_STATUS, irqs);
613 return irqs & irq_mask;
616 int r100_irq_process(struct radeon_device *rdev)
618 uint32_t status, msi_rearm;
619 bool queue_hotplug = false;
621 /* reset gui idle ack. the status bit is broken */
622 rdev->irq.gui_idle_acked = false;
624 status = r100_irq_ack(rdev);
628 if (rdev->shutdown) {
633 if (status & RADEON_SW_INT_TEST) {
634 radeon_fence_process(rdev);
636 /* gui idle interrupt */
637 if (status & RADEON_GUI_IDLE_STAT) {
638 rdev->irq.gui_idle_acked = true;
639 rdev->pm.gui_idle = true;
640 wake_up(&rdev->irq.idle_queue);
642 /* Vertical blank interrupts */
643 if (status & RADEON_CRTC_VBLANK_STAT) {
644 if (rdev->irq.crtc_vblank_int[0]) {
645 drm_handle_vblank(rdev->ddev, 0);
646 rdev->pm.vblank_sync = true;
647 wake_up(&rdev->irq.vblank_queue);
649 if (rdev->irq.pflip[0])
650 radeon_crtc_handle_flip(rdev, 0);
652 if (status & RADEON_CRTC2_VBLANK_STAT) {
653 if (rdev->irq.crtc_vblank_int[1]) {
654 drm_handle_vblank(rdev->ddev, 1);
655 rdev->pm.vblank_sync = true;
656 wake_up(&rdev->irq.vblank_queue);
658 if (rdev->irq.pflip[1])
659 radeon_crtc_handle_flip(rdev, 1);
661 if (status & RADEON_FP_DETECT_STAT) {
662 queue_hotplug = true;
665 if (status & RADEON_FP2_DETECT_STAT) {
666 queue_hotplug = true;
669 status = r100_irq_ack(rdev);
671 /* reset gui idle ack. the status bit is broken */
672 rdev->irq.gui_idle_acked = false;
674 schedule_work(&rdev->hotplug_work);
675 if (rdev->msi_enabled) {
676 switch (rdev->family) {
679 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
680 WREG32(RADEON_AIC_CNTL, msi_rearm);
681 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
684 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
685 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
686 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
693 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
696 return RREG32(RADEON_CRTC_CRNT_FRAME);
698 return RREG32(RADEON_CRTC2_CRNT_FRAME);
701 /* Who ever call radeon_fence_emit should call ring_lock and ask
702 * for enough space (today caller are ib schedule and buffer move) */
703 void r100_fence_ring_emit(struct radeon_device *rdev,
704 struct radeon_fence *fence)
706 /* We have to make sure that caches are flushed before
707 * CPU might read something from VRAM. */
708 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
709 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
710 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
711 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
712 /* Wait until IDLE & CLEAN */
713 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
714 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
715 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
716 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
717 RADEON_HDP_READ_BUFFER_INVALIDATE);
718 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
719 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
720 /* Emit fence sequence & fire IRQ */
721 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
722 radeon_ring_write(rdev, fence->seq);
723 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
724 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
727 int r100_copy_blit(struct radeon_device *rdev,
730 unsigned num_gpu_pages,
731 struct radeon_fence *fence)
734 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
736 uint32_t stride_pixels;
741 /* radeon limited to 16k stride */
742 stride_bytes &= 0x3fff;
743 /* radeon pitch is /64 */
744 pitch = stride_bytes / 64;
745 stride_pixels = stride_bytes / 4;
746 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
748 /* Ask for enough room for blit + flush + fence */
749 ndw = 64 + (10 * num_loops);
750 r = radeon_ring_lock(rdev, ndw);
752 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
755 while (num_gpu_pages > 0) {
756 cur_pages = num_gpu_pages;
757 if (cur_pages > 8191) {
760 num_gpu_pages -= cur_pages;
762 /* pages are in Y direction - height
763 page width in X direction - width */
764 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
765 radeon_ring_write(rdev,
766 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
767 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
768 RADEON_GMC_SRC_CLIPPING |
769 RADEON_GMC_DST_CLIPPING |
770 RADEON_GMC_BRUSH_NONE |
771 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
772 RADEON_GMC_SRC_DATATYPE_COLOR |
774 RADEON_DP_SRC_SOURCE_MEMORY |
775 RADEON_GMC_CLR_CMP_CNTL_DIS |
776 RADEON_GMC_WR_MSK_DIS);
777 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
778 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
779 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
780 radeon_ring_write(rdev, 0);
781 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
782 radeon_ring_write(rdev, num_gpu_pages);
783 radeon_ring_write(rdev, num_gpu_pages);
784 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
786 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
787 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
788 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
789 radeon_ring_write(rdev,
790 RADEON_WAIT_2D_IDLECLEAN |
791 RADEON_WAIT_HOST_IDLECLEAN |
792 RADEON_WAIT_DMA_GUI_IDLE);
794 r = radeon_fence_emit(rdev, fence);
796 radeon_ring_unlock_commit(rdev);
800 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
805 for (i = 0; i < rdev->usec_timeout; i++) {
806 tmp = RREG32(R_000E40_RBBM_STATUS);
807 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
815 void r100_ring_start(struct radeon_device *rdev)
819 r = radeon_ring_lock(rdev, 2);
823 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
824 radeon_ring_write(rdev,
825 RADEON_ISYNC_ANY2D_IDLE3D |
826 RADEON_ISYNC_ANY3D_IDLE2D |
827 RADEON_ISYNC_WAIT_IDLEGUI |
828 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
829 radeon_ring_unlock_commit(rdev);
833 /* Load the microcode for the CP */
834 static int r100_cp_init_microcode(struct radeon_device *rdev)
836 struct platform_device *pdev;
837 const char *fw_name = NULL;
842 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
845 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
848 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
849 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
850 (rdev->family == CHIP_RS200)) {
851 DRM_INFO("Loading R100 Microcode\n");
852 fw_name = FIRMWARE_R100;
853 } else if ((rdev->family == CHIP_R200) ||
854 (rdev->family == CHIP_RV250) ||
855 (rdev->family == CHIP_RV280) ||
856 (rdev->family == CHIP_RS300)) {
857 DRM_INFO("Loading R200 Microcode\n");
858 fw_name = FIRMWARE_R200;
859 } else if ((rdev->family == CHIP_R300) ||
860 (rdev->family == CHIP_R350) ||
861 (rdev->family == CHIP_RV350) ||
862 (rdev->family == CHIP_RV380) ||
863 (rdev->family == CHIP_RS400) ||
864 (rdev->family == CHIP_RS480)) {
865 DRM_INFO("Loading R300 Microcode\n");
866 fw_name = FIRMWARE_R300;
867 } else if ((rdev->family == CHIP_R420) ||
868 (rdev->family == CHIP_R423) ||
869 (rdev->family == CHIP_RV410)) {
870 DRM_INFO("Loading R400 Microcode\n");
871 fw_name = FIRMWARE_R420;
872 } else if ((rdev->family == CHIP_RS690) ||
873 (rdev->family == CHIP_RS740)) {
874 DRM_INFO("Loading RS690/RS740 Microcode\n");
875 fw_name = FIRMWARE_RS690;
876 } else if (rdev->family == CHIP_RS600) {
877 DRM_INFO("Loading RS600 Microcode\n");
878 fw_name = FIRMWARE_RS600;
879 } else if ((rdev->family == CHIP_RV515) ||
880 (rdev->family == CHIP_R520) ||
881 (rdev->family == CHIP_RV530) ||
882 (rdev->family == CHIP_R580) ||
883 (rdev->family == CHIP_RV560) ||
884 (rdev->family == CHIP_RV570)) {
885 DRM_INFO("Loading R500 Microcode\n");
886 fw_name = FIRMWARE_R520;
889 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
890 platform_device_unregister(pdev);
892 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
894 } else if (rdev->me_fw->size % 8) {
896 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
897 rdev->me_fw->size, fw_name);
899 release_firmware(rdev->me_fw);
905 static void r100_cp_load_microcode(struct radeon_device *rdev)
907 const __be32 *fw_data;
910 if (r100_gui_wait_for_idle(rdev)) {
911 printk(KERN_WARNING "Failed to wait GUI idle while "
912 "programming pipes. Bad things might happen.\n");
916 size = rdev->me_fw->size / 4;
917 fw_data = (const __be32 *)&rdev->me_fw->data[0];
918 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
919 for (i = 0; i < size; i += 2) {
920 WREG32(RADEON_CP_ME_RAM_DATAH,
921 be32_to_cpup(&fw_data[i]));
922 WREG32(RADEON_CP_ME_RAM_DATAL,
923 be32_to_cpup(&fw_data[i + 1]));
928 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
933 unsigned pre_write_timer;
934 unsigned pre_write_limit;
935 unsigned indirect2_start;
936 unsigned indirect1_start;
940 if (r100_debugfs_cp_init(rdev)) {
941 DRM_ERROR("Failed to register debugfs file for CP !\n");
944 r = r100_cp_init_microcode(rdev);
946 DRM_ERROR("Failed to load firmware!\n");
951 /* Align ring size */
952 rb_bufsz = drm_order(ring_size / 8);
953 ring_size = (1 << (rb_bufsz + 1)) * 4;
954 r100_cp_load_microcode(rdev);
955 r = radeon_ring_init(rdev, ring_size);
959 /* Each time the cp read 1024 bytes (16 dword/quadword) update
960 * the rptr copy in system ram */
962 /* cp will read 128bytes at a time (4 dwords) */
964 rdev->cp.align_mask = 16 - 1;
965 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
966 pre_write_timer = 64;
967 /* Force CP_RB_WPTR write if written more than one time before the
971 /* Setup the cp cache like this (cache size is 96 dwords) :
975 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
976 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
977 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
978 * Idea being that most of the gpu cmd will be through indirect1 buffer
979 * so it gets the bigger cache.
981 indirect2_start = 80;
982 indirect1_start = 16;
984 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
985 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
986 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
987 REG_SET(RADEON_MAX_FETCH, max_fetch));
989 tmp |= RADEON_BUF_SWAP_32BIT;
991 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
993 /* Set ring address */
994 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
995 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
996 /* Force read & write ptr to 0 */
997 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
998 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1000 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1002 /* set the wb address whether it's enabled or not */
1003 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1004 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1005 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1007 if (rdev->wb.enabled)
1008 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1010 tmp |= RADEON_RB_NO_UPDATE;
1011 WREG32(R_000770_SCRATCH_UMSK, 0);
1014 WREG32(RADEON_CP_RB_CNTL, tmp);
1016 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1017 /* Set cp mode to bus mastering & enable cp*/
1018 WREG32(RADEON_CP_CSQ_MODE,
1019 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1020 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1021 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1022 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1023 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1024 radeon_ring_start(rdev);
1025 r = radeon_ring_test(rdev);
1027 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1030 rdev->cp.ready = true;
1031 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1035 void r100_cp_fini(struct radeon_device *rdev)
1037 if (r100_cp_wait_for_idle(rdev)) {
1038 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1041 r100_cp_disable(rdev);
1042 radeon_ring_fini(rdev);
1043 DRM_INFO("radeon: cp finalized\n");
1046 void r100_cp_disable(struct radeon_device *rdev)
1049 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1050 rdev->cp.ready = false;
1051 WREG32(RADEON_CP_CSQ_MODE, 0);
1052 WREG32(RADEON_CP_CSQ_CNTL, 0);
1053 WREG32(R_000770_SCRATCH_UMSK, 0);
1054 if (r100_gui_wait_for_idle(rdev)) {
1055 printk(KERN_WARNING "Failed to wait GUI idle while "
1056 "programming pipes. Bad things might happen.\n");
1060 void r100_cp_commit(struct radeon_device *rdev)
1062 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1063 (void)RREG32(RADEON_CP_RB_WPTR);
1070 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1071 struct radeon_cs_packet *pkt,
1072 const unsigned *auth, unsigned n,
1073 radeon_packet0_check_t check)
1082 /* Check that register fall into register range
1083 * determined by the number of entry (n) in the
1084 * safe register bitmap.
1086 if (pkt->one_reg_wr) {
1087 if ((reg >> 7) > n) {
1091 if (((reg + (pkt->count << 2)) >> 7) > n) {
1095 for (i = 0; i <= pkt->count; i++, idx++) {
1097 m = 1 << ((reg >> 2) & 31);
1099 r = check(p, pkt, idx, reg);
1104 if (pkt->one_reg_wr) {
1105 if (!(auth[j] & m)) {
1115 void r100_cs_dump_packet(struct radeon_cs_parser *p,
1116 struct radeon_cs_packet *pkt)
1118 volatile uint32_t *ib;
1124 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
1125 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
1130 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
1131 * @parser: parser structure holding parsing context.
1132 * @pkt: where to store packet informations
1134 * Assume that chunk_ib_index is properly set. Will return -EINVAL
1135 * if packet is bigger than remaining ib size. or if packets is unknown.
1137 int r100_cs_packet_parse(struct radeon_cs_parser *p,
1138 struct radeon_cs_packet *pkt,
1141 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
1144 if (idx >= ib_chunk->length_dw) {
1145 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
1146 idx, ib_chunk->length_dw);
1149 header = radeon_get_ib_value(p, idx);
1151 pkt->type = CP_PACKET_GET_TYPE(header);
1152 pkt->count = CP_PACKET_GET_COUNT(header);
1153 switch (pkt->type) {
1155 pkt->reg = CP_PACKET0_GET_REG(header);
1156 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
1159 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
1165 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
1168 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
1169 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
1170 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
1177 * r100_cs_packet_next_vline() - parse userspace VLINE packet
1178 * @parser: parser structure holding parsing context.
1180 * Userspace sends a special sequence for VLINE waits.
1181 * PACKET0 - VLINE_START_END + value
1182 * PACKET0 - WAIT_UNTIL +_value
1183 * RELOC (P3) - crtc_id in reloc.
1185 * This function parses this and relocates the VLINE START END
1186 * and WAIT UNTIL packets to the correct crtc.
1187 * It also detects a switched off crtc and nulls out the
1188 * wait in that case.
1190 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
1192 struct drm_mode_object *obj;
1193 struct drm_crtc *crtc;
1194 struct radeon_crtc *radeon_crtc;
1195 struct radeon_cs_packet p3reloc, waitreloc;
1198 uint32_t header, h_idx, reg;
1199 volatile uint32_t *ib;
1203 /* parse the wait until */
1204 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
1208 /* check its a wait until and only 1 count */
1209 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
1210 waitreloc.count != 0) {
1211 DRM_ERROR("vline wait had illegal wait until segment\n");
1215 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
1216 DRM_ERROR("vline wait had illegal wait until\n");
1220 /* jump over the NOP */
1221 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
1226 p->idx += waitreloc.count + 2;
1227 p->idx += p3reloc.count + 2;
1229 header = radeon_get_ib_value(p, h_idx);
1230 crtc_id = radeon_get_ib_value(p, h_idx + 5);
1231 reg = CP_PACKET0_GET_REG(header);
1232 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
1234 DRM_ERROR("cannot find crtc %d\n", crtc_id);
1237 crtc = obj_to_crtc(obj);
1238 radeon_crtc = to_radeon_crtc(crtc);
1239 crtc_id = radeon_crtc->crtc_id;
1241 if (!crtc->enabled) {
1242 /* if the CRTC isn't enabled - we need to nop out the wait until */
1243 ib[h_idx + 2] = PACKET2(0);
1244 ib[h_idx + 3] = PACKET2(0);
1245 } else if (crtc_id == 1) {
1247 case AVIVO_D1MODE_VLINE_START_END:
1248 header &= ~R300_CP_PACKET0_REG_MASK;
1249 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1251 case RADEON_CRTC_GUI_TRIG_VLINE:
1252 header &= ~R300_CP_PACKET0_REG_MASK;
1253 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1256 DRM_ERROR("unknown crtc reloc\n");
1260 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1267 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1268 * @parser: parser structure holding parsing context.
1269 * @data: pointer to relocation data
1270 * @offset_start: starting offset
1271 * @offset_mask: offset mask (to align start offset on)
1272 * @reloc: reloc informations
1274 * Check next packet is relocation packet3, do bo validation and compute
1275 * GPU offset using the provided start.
1277 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1278 struct radeon_cs_reloc **cs_reloc)
1280 struct radeon_cs_chunk *relocs_chunk;
1281 struct radeon_cs_packet p3reloc;
1285 if (p->chunk_relocs_idx == -1) {
1286 DRM_ERROR("No relocation chunk !\n");
1290 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1291 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1295 p->idx += p3reloc.count + 2;
1296 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1297 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1299 r100_cs_dump_packet(p, &p3reloc);
1302 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1303 if (idx >= relocs_chunk->length_dw) {
1304 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1305 idx, relocs_chunk->length_dw);
1306 r100_cs_dump_packet(p, &p3reloc);
1309 /* FIXME: we assume reloc size is 4 dwords */
1310 *cs_reloc = p->relocs_ptr[(idx / 4)];
1314 static int r100_get_vtx_size(uint32_t vtx_fmt)
1318 /* ordered according to bits in spec */
1319 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1321 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1323 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1325 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1327 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1329 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1331 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1333 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1335 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1337 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1339 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1341 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1343 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1345 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1347 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1350 if (vtx_fmt & (0x7 << 15))
1351 vtx_size += (vtx_fmt >> 15) & 0x7;
1352 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1354 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1356 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1358 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1360 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1362 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1367 static int r100_packet0_check(struct radeon_cs_parser *p,
1368 struct radeon_cs_packet *pkt,
1369 unsigned idx, unsigned reg)
1371 struct radeon_cs_reloc *reloc;
1372 struct r100_cs_track *track;
1373 volatile uint32_t *ib;
1381 track = (struct r100_cs_track *)p->track;
1383 idx_value = radeon_get_ib_value(p, idx);
1386 case RADEON_CRTC_GUI_TRIG_VLINE:
1387 r = r100_cs_packet_parse_vline(p);
1389 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1391 r100_cs_dump_packet(p, pkt);
1395 /* FIXME: only allow PACKET3 blit? easier to check for out of
1397 case RADEON_DST_PITCH_OFFSET:
1398 case RADEON_SRC_PITCH_OFFSET:
1399 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1403 case RADEON_RB3D_DEPTHOFFSET:
1404 r = r100_cs_packet_next_reloc(p, &reloc);
1406 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1408 r100_cs_dump_packet(p, pkt);
1411 track->zb.robj = reloc->robj;
1412 track->zb.offset = idx_value;
1413 track->zb_dirty = true;
1414 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1416 case RADEON_RB3D_COLOROFFSET:
1417 r = r100_cs_packet_next_reloc(p, &reloc);
1419 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1421 r100_cs_dump_packet(p, pkt);
1424 track->cb[0].robj = reloc->robj;
1425 track->cb[0].offset = idx_value;
1426 track->cb_dirty = true;
1427 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1429 case RADEON_PP_TXOFFSET_0:
1430 case RADEON_PP_TXOFFSET_1:
1431 case RADEON_PP_TXOFFSET_2:
1432 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1433 r = r100_cs_packet_next_reloc(p, &reloc);
1435 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1437 r100_cs_dump_packet(p, pkt);
1440 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1441 track->textures[i].robj = reloc->robj;
1442 track->tex_dirty = true;
1444 case RADEON_PP_CUBIC_OFFSET_T0_0:
1445 case RADEON_PP_CUBIC_OFFSET_T0_1:
1446 case RADEON_PP_CUBIC_OFFSET_T0_2:
1447 case RADEON_PP_CUBIC_OFFSET_T0_3:
1448 case RADEON_PP_CUBIC_OFFSET_T0_4:
1449 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1450 r = r100_cs_packet_next_reloc(p, &reloc);
1452 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1454 r100_cs_dump_packet(p, pkt);
1457 track->textures[0].cube_info[i].offset = idx_value;
1458 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1459 track->textures[0].cube_info[i].robj = reloc->robj;
1460 track->tex_dirty = true;
1462 case RADEON_PP_CUBIC_OFFSET_T1_0:
1463 case RADEON_PP_CUBIC_OFFSET_T1_1:
1464 case RADEON_PP_CUBIC_OFFSET_T1_2:
1465 case RADEON_PP_CUBIC_OFFSET_T1_3:
1466 case RADEON_PP_CUBIC_OFFSET_T1_4:
1467 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1468 r = r100_cs_packet_next_reloc(p, &reloc);
1470 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1472 r100_cs_dump_packet(p, pkt);
1475 track->textures[1].cube_info[i].offset = idx_value;
1476 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1477 track->textures[1].cube_info[i].robj = reloc->robj;
1478 track->tex_dirty = true;
1480 case RADEON_PP_CUBIC_OFFSET_T2_0:
1481 case RADEON_PP_CUBIC_OFFSET_T2_1:
1482 case RADEON_PP_CUBIC_OFFSET_T2_2:
1483 case RADEON_PP_CUBIC_OFFSET_T2_3:
1484 case RADEON_PP_CUBIC_OFFSET_T2_4:
1485 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1486 r = r100_cs_packet_next_reloc(p, &reloc);
1488 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1490 r100_cs_dump_packet(p, pkt);
1493 track->textures[2].cube_info[i].offset = idx_value;
1494 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1495 track->textures[2].cube_info[i].robj = reloc->robj;
1496 track->tex_dirty = true;
1498 case RADEON_RE_WIDTH_HEIGHT:
1499 track->maxy = ((idx_value >> 16) & 0x7FF);
1500 track->cb_dirty = true;
1501 track->zb_dirty = true;
1503 case RADEON_RB3D_COLORPITCH:
1504 r = r100_cs_packet_next_reloc(p, &reloc);
1506 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1508 r100_cs_dump_packet(p, pkt);
1512 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1513 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1514 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1515 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1517 tmp = idx_value & ~(0x7 << 16);
1521 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1522 track->cb_dirty = true;
1524 case RADEON_RB3D_DEPTHPITCH:
1525 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1526 track->zb_dirty = true;
1528 case RADEON_RB3D_CNTL:
1529 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1535 track->cb[0].cpp = 1;
1540 track->cb[0].cpp = 2;
1543 track->cb[0].cpp = 4;
1546 DRM_ERROR("Invalid color buffer format (%d) !\n",
1547 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1550 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1551 track->cb_dirty = true;
1552 track->zb_dirty = true;
1554 case RADEON_RB3D_ZSTENCILCNTL:
1555 switch (idx_value & 0xf) {
1570 track->zb_dirty = true;
1572 case RADEON_RB3D_ZPASS_ADDR:
1573 r = r100_cs_packet_next_reloc(p, &reloc);
1575 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1577 r100_cs_dump_packet(p, pkt);
1580 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1582 case RADEON_PP_CNTL:
1584 uint32_t temp = idx_value >> 4;
1585 for (i = 0; i < track->num_texture; i++)
1586 track->textures[i].enabled = !!(temp & (1 << i));
1587 track->tex_dirty = true;
1590 case RADEON_SE_VF_CNTL:
1591 track->vap_vf_cntl = idx_value;
1593 case RADEON_SE_VTX_FMT:
1594 track->vtx_size = r100_get_vtx_size(idx_value);
1596 case RADEON_PP_TEX_SIZE_0:
1597 case RADEON_PP_TEX_SIZE_1:
1598 case RADEON_PP_TEX_SIZE_2:
1599 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1600 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1601 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1602 track->tex_dirty = true;
1604 case RADEON_PP_TEX_PITCH_0:
1605 case RADEON_PP_TEX_PITCH_1:
1606 case RADEON_PP_TEX_PITCH_2:
1607 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1608 track->textures[i].pitch = idx_value + 32;
1609 track->tex_dirty = true;
1611 case RADEON_PP_TXFILTER_0:
1612 case RADEON_PP_TXFILTER_1:
1613 case RADEON_PP_TXFILTER_2:
1614 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1615 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1616 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1617 tmp = (idx_value >> 23) & 0x7;
1618 if (tmp == 2 || tmp == 6)
1619 track->textures[i].roundup_w = false;
1620 tmp = (idx_value >> 27) & 0x7;
1621 if (tmp == 2 || tmp == 6)
1622 track->textures[i].roundup_h = false;
1623 track->tex_dirty = true;
1625 case RADEON_PP_TXFORMAT_0:
1626 case RADEON_PP_TXFORMAT_1:
1627 case RADEON_PP_TXFORMAT_2:
1628 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1629 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1630 track->textures[i].use_pitch = 1;
1632 track->textures[i].use_pitch = 0;
1633 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1634 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1636 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1637 track->textures[i].tex_coord_type = 2;
1638 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1639 case RADEON_TXFORMAT_I8:
1640 case RADEON_TXFORMAT_RGB332:
1641 case RADEON_TXFORMAT_Y8:
1642 track->textures[i].cpp = 1;
1643 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1645 case RADEON_TXFORMAT_AI88:
1646 case RADEON_TXFORMAT_ARGB1555:
1647 case RADEON_TXFORMAT_RGB565:
1648 case RADEON_TXFORMAT_ARGB4444:
1649 case RADEON_TXFORMAT_VYUY422:
1650 case RADEON_TXFORMAT_YVYU422:
1651 case RADEON_TXFORMAT_SHADOW16:
1652 case RADEON_TXFORMAT_LDUDV655:
1653 case RADEON_TXFORMAT_DUDV88:
1654 track->textures[i].cpp = 2;
1655 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1657 case RADEON_TXFORMAT_ARGB8888:
1658 case RADEON_TXFORMAT_RGBA8888:
1659 case RADEON_TXFORMAT_SHADOW32:
1660 case RADEON_TXFORMAT_LDUDUV8888:
1661 track->textures[i].cpp = 4;
1662 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
1664 case RADEON_TXFORMAT_DXT1:
1665 track->textures[i].cpp = 1;
1666 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1668 case RADEON_TXFORMAT_DXT23:
1669 case RADEON_TXFORMAT_DXT45:
1670 track->textures[i].cpp = 1;
1671 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1674 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1675 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1676 track->tex_dirty = true;
1678 case RADEON_PP_CUBIC_FACES_0:
1679 case RADEON_PP_CUBIC_FACES_1:
1680 case RADEON_PP_CUBIC_FACES_2:
1682 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1683 for (face = 0; face < 4; face++) {
1684 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1685 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1687 track->tex_dirty = true;
1690 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1697 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1698 struct radeon_cs_packet *pkt,
1699 struct radeon_bo *robj)
1704 value = radeon_get_ib_value(p, idx + 2);
1705 if ((value + 1) > radeon_bo_size(robj)) {
1706 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1707 "(need %u have %lu) !\n",
1709 radeon_bo_size(robj));
1715 static int r100_packet3_check(struct radeon_cs_parser *p,
1716 struct radeon_cs_packet *pkt)
1718 struct radeon_cs_reloc *reloc;
1719 struct r100_cs_track *track;
1721 volatile uint32_t *ib;
1726 track = (struct r100_cs_track *)p->track;
1727 switch (pkt->opcode) {
1728 case PACKET3_3D_LOAD_VBPNTR:
1729 r = r100_packet3_load_vbpntr(p, pkt, idx);
1733 case PACKET3_INDX_BUFFER:
1734 r = r100_cs_packet_next_reloc(p, &reloc);
1736 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1737 r100_cs_dump_packet(p, pkt);
1740 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1741 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1747 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1748 r = r100_cs_packet_next_reloc(p, &reloc);
1750 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1751 r100_cs_dump_packet(p, pkt);
1754 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1755 track->num_arrays = 1;
1756 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1758 track->arrays[0].robj = reloc->robj;
1759 track->arrays[0].esize = track->vtx_size;
1761 track->max_indx = radeon_get_ib_value(p, idx+1);
1763 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1764 track->immd_dwords = pkt->count - 1;
1765 r = r100_cs_track_check(p->rdev, track);
1769 case PACKET3_3D_DRAW_IMMD:
1770 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1771 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1774 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1775 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1776 track->immd_dwords = pkt->count - 1;
1777 r = r100_cs_track_check(p->rdev, track);
1781 /* triggers drawing using in-packet vertex data */
1782 case PACKET3_3D_DRAW_IMMD_2:
1783 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1784 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1787 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1788 track->immd_dwords = pkt->count;
1789 r = r100_cs_track_check(p->rdev, track);
1793 /* triggers drawing using in-packet vertex data */
1794 case PACKET3_3D_DRAW_VBUF_2:
1795 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1796 r = r100_cs_track_check(p->rdev, track);
1800 /* triggers drawing of vertex buffers setup elsewhere */
1801 case PACKET3_3D_DRAW_INDX_2:
1802 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1803 r = r100_cs_track_check(p->rdev, track);
1807 /* triggers drawing using indices to vertex buffer */
1808 case PACKET3_3D_DRAW_VBUF:
1809 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1810 r = r100_cs_track_check(p->rdev, track);
1814 /* triggers drawing of vertex buffers setup elsewhere */
1815 case PACKET3_3D_DRAW_INDX:
1816 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1817 r = r100_cs_track_check(p->rdev, track);
1821 /* triggers drawing using indices to vertex buffer */
1822 case PACKET3_3D_CLEAR_HIZ:
1823 case PACKET3_3D_CLEAR_ZMASK:
1824 if (p->rdev->hyperz_filp != p->filp)
1830 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1836 int r100_cs_parse(struct radeon_cs_parser *p)
1838 struct radeon_cs_packet pkt;
1839 struct r100_cs_track *track;
1842 track = kzalloc(sizeof(*track), GFP_KERNEL);
1843 r100_cs_track_clear(p->rdev, track);
1846 r = r100_cs_packet_parse(p, &pkt, p->idx);
1850 p->idx += pkt.count + 2;
1853 if (p->rdev->family >= CHIP_R200)
1854 r = r100_cs_parse_packet0(p, &pkt,
1855 p->rdev->config.r100.reg_safe_bm,
1856 p->rdev->config.r100.reg_safe_bm_size,
1857 &r200_packet0_check);
1859 r = r100_cs_parse_packet0(p, &pkt,
1860 p->rdev->config.r100.reg_safe_bm,
1861 p->rdev->config.r100.reg_safe_bm_size,
1862 &r100_packet0_check);
1867 r = r100_packet3_check(p, &pkt);
1870 DRM_ERROR("Unknown packet type %d !\n",
1877 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1883 * Global GPU functions
1885 void r100_errata(struct radeon_device *rdev)
1887 rdev->pll_errata = 0;
1889 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1890 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1893 if (rdev->family == CHIP_RV100 ||
1894 rdev->family == CHIP_RS100 ||
1895 rdev->family == CHIP_RS200) {
1896 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1900 /* Wait for vertical sync on primary CRTC */
1901 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1903 uint32_t crtc_gen_cntl, tmp;
1906 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1907 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1908 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1911 /* Clear the CRTC_VBLANK_SAVE bit */
1912 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1913 for (i = 0; i < rdev->usec_timeout; i++) {
1914 tmp = RREG32(RADEON_CRTC_STATUS);
1915 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1922 /* Wait for vertical sync on secondary CRTC */
1923 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1925 uint32_t crtc2_gen_cntl, tmp;
1928 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1929 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1930 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1933 /* Clear the CRTC_VBLANK_SAVE bit */
1934 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1935 for (i = 0; i < rdev->usec_timeout; i++) {
1936 tmp = RREG32(RADEON_CRTC2_STATUS);
1937 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1944 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1949 for (i = 0; i < rdev->usec_timeout; i++) {
1950 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1959 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1964 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1965 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1966 " Bad things might happen.\n");
1968 for (i = 0; i < rdev->usec_timeout; i++) {
1969 tmp = RREG32(RADEON_RBBM_STATUS);
1970 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1978 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1983 for (i = 0; i < rdev->usec_timeout; i++) {
1984 /* read MC_STATUS */
1985 tmp = RREG32(RADEON_MC_STATUS);
1986 if (tmp & RADEON_MC_IDLE) {
1994 void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
1996 lockup->last_cp_rptr = cp->rptr;
1997 lockup->last_jiffies = jiffies;
2001 * r100_gpu_cp_is_lockup() - check if CP is lockup by recording information
2002 * @rdev: radeon device structure
2003 * @lockup: r100_gpu_lockup structure holding CP lockup tracking informations
2004 * @cp: radeon_cp structure holding CP information
2006 * We don't need to initialize the lockup tracking information as we will either
2007 * have CP rptr to a different value of jiffies wrap around which will force
2008 * initialization of the lockup tracking informations.
2010 * A possible false positivie is if we get call after while and last_cp_rptr ==
2011 * the current CP rptr, even if it's unlikely it might happen. To avoid this
2012 * if the elapsed time since last call is bigger than 2 second than we return
2013 * false and update the tracking information. Due to this the caller must call
2014 * r100_gpu_cp_is_lockup several time in less than 2sec for lockup to be reported
2015 * the fencing code should be cautious about that.
2017 * Caller should write to the ring to force CP to do something so we don't get
2018 * false positive when CP is just gived nothing to do.
2021 bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp)
2023 unsigned long cjiffies, elapsed;
2026 if (!time_after(cjiffies, lockup->last_jiffies)) {
2027 /* likely a wrap around */
2028 lockup->last_cp_rptr = cp->rptr;
2029 lockup->last_jiffies = jiffies;
2032 if (cp->rptr != lockup->last_cp_rptr) {
2033 /* CP is still working no lockup */
2034 lockup->last_cp_rptr = cp->rptr;
2035 lockup->last_jiffies = jiffies;
2038 elapsed = jiffies_to_msecs(cjiffies - lockup->last_jiffies);
2039 if (elapsed >= 10000) {
2040 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2043 /* give a chance to the GPU ... */
2047 bool r100_gpu_is_lockup(struct radeon_device *rdev)
2052 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2053 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2054 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2057 /* force CP activities */
2058 r = radeon_ring_lock(rdev, 2);
2061 radeon_ring_write(rdev, 0x80000000);
2062 radeon_ring_write(rdev, 0x80000000);
2063 radeon_ring_unlock_commit(rdev);
2065 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2066 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2069 void r100_bm_disable(struct radeon_device *rdev)
2074 /* disable bus mastering */
2075 tmp = RREG32(R_000030_BUS_CNTL);
2076 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000044);
2078 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000042);
2080 WREG32(R_000030_BUS_CNTL, (tmp & 0xFFFFFFFF) | 0x00000040);
2081 tmp = RREG32(RADEON_BUS_CNTL);
2083 pci_read_config_word(rdev->pdev, 0x4, &tmp16);
2084 pci_write_config_word(rdev->pdev, 0x4, tmp16 & 0xFFFB);
2088 int r100_asic_reset(struct radeon_device *rdev)
2090 struct r100_mc_save save;
2094 status = RREG32(R_000E40_RBBM_STATUS);
2095 if (!G_000E40_GUI_ACTIVE(status)) {
2098 r100_mc_stop(rdev, &save);
2099 status = RREG32(R_000E40_RBBM_STATUS);
2100 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2102 WREG32(RADEON_CP_CSQ_CNTL, 0);
2103 tmp = RREG32(RADEON_CP_RB_CNTL);
2104 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
2105 WREG32(RADEON_CP_RB_RPTR_WR, 0);
2106 WREG32(RADEON_CP_RB_WPTR, 0);
2107 WREG32(RADEON_CP_RB_CNTL, tmp);
2108 /* save PCI state */
2109 pci_save_state(rdev->pdev);
2110 /* disable bus mastering */
2111 r100_bm_disable(rdev);
2112 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_SE(1) |
2113 S_0000F0_SOFT_RESET_RE(1) |
2114 S_0000F0_SOFT_RESET_PP(1) |
2115 S_0000F0_SOFT_RESET_RB(1));
2116 RREG32(R_0000F0_RBBM_SOFT_RESET);
2118 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2120 status = RREG32(R_000E40_RBBM_STATUS);
2121 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2123 WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
2124 RREG32(R_0000F0_RBBM_SOFT_RESET);
2126 WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
2128 status = RREG32(R_000E40_RBBM_STATUS);
2129 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
2130 /* restore PCI & busmastering */
2131 pci_restore_state(rdev->pdev);
2132 r100_enable_bm(rdev);
2133 /* Check if GPU is idle */
2134 if (G_000E40_SE_BUSY(status) || G_000E40_RE_BUSY(status) ||
2135 G_000E40_TAM_BUSY(status) || G_000E40_PB_BUSY(status)) {
2136 dev_err(rdev->dev, "failed to reset GPU\n");
2137 rdev->gpu_lockup = true;
2140 dev_info(rdev->dev, "GPU reset succeed\n");
2141 r100_mc_resume(rdev, &save);
2145 void r100_set_common_regs(struct radeon_device *rdev)
2147 struct drm_device *dev = rdev->ddev;
2148 bool force_dac2 = false;
2151 /* set these so they don't interfere with anything */
2152 WREG32(RADEON_OV0_SCALE_CNTL, 0);
2153 WREG32(RADEON_SUBPIC_CNTL, 0);
2154 WREG32(RADEON_VIPH_CONTROL, 0);
2155 WREG32(RADEON_I2C_CNTL_1, 0);
2156 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
2157 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
2158 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
2160 /* always set up dac2 on rn50 and some rv100 as lots
2161 * of servers seem to wire it up to a VGA port but
2162 * don't report it in the bios connector
2165 switch (dev->pdev->device) {
2174 /* DELL triple head servers */
2175 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
2176 ((dev->pdev->subsystem_device == 0x016c) ||
2177 (dev->pdev->subsystem_device == 0x016d) ||
2178 (dev->pdev->subsystem_device == 0x016e) ||
2179 (dev->pdev->subsystem_device == 0x016f) ||
2180 (dev->pdev->subsystem_device == 0x0170) ||
2181 (dev->pdev->subsystem_device == 0x017d) ||
2182 (dev->pdev->subsystem_device == 0x017e) ||
2183 (dev->pdev->subsystem_device == 0x0183) ||
2184 (dev->pdev->subsystem_device == 0x018a) ||
2185 (dev->pdev->subsystem_device == 0x019a)))
2191 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
2192 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
2193 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
2195 /* For CRT on DAC2, don't turn it on if BIOS didn't
2196 enable it, even it's detected.
2199 /* force it to crtc0 */
2200 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
2201 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
2202 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
2204 /* set up the TV DAC */
2205 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
2206 RADEON_TV_DAC_STD_MASK |
2207 RADEON_TV_DAC_RDACPD |
2208 RADEON_TV_DAC_GDACPD |
2209 RADEON_TV_DAC_BDACPD |
2210 RADEON_TV_DAC_BGADJ_MASK |
2211 RADEON_TV_DAC_DACADJ_MASK);
2212 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
2213 RADEON_TV_DAC_NHOLD |
2214 RADEON_TV_DAC_STD_PS2 |
2217 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
2218 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
2219 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
2222 /* switch PM block to ACPI mode */
2223 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
2224 tmp &= ~RADEON_PM_MODE_SEL;
2225 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
2232 static void r100_vram_get_type(struct radeon_device *rdev)
2236 rdev->mc.vram_is_ddr = false;
2237 if (rdev->flags & RADEON_IS_IGP)
2238 rdev->mc.vram_is_ddr = true;
2239 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
2240 rdev->mc.vram_is_ddr = true;
2241 if ((rdev->family == CHIP_RV100) ||
2242 (rdev->family == CHIP_RS100) ||
2243 (rdev->family == CHIP_RS200)) {
2244 tmp = RREG32(RADEON_MEM_CNTL);
2245 if (tmp & RV100_HALF_MODE) {
2246 rdev->mc.vram_width = 32;
2248 rdev->mc.vram_width = 64;
2250 if (rdev->flags & RADEON_SINGLE_CRTC) {
2251 rdev->mc.vram_width /= 4;
2252 rdev->mc.vram_is_ddr = true;
2254 } else if (rdev->family <= CHIP_RV280) {
2255 tmp = RREG32(RADEON_MEM_CNTL);
2256 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
2257 rdev->mc.vram_width = 128;
2259 rdev->mc.vram_width = 64;
2263 rdev->mc.vram_width = 128;
2267 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
2272 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2274 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
2275 * that is has the 2nd generation multifunction PCI interface
2277 if (rdev->family == CHIP_RV280 ||
2278 rdev->family >= CHIP_RV350) {
2279 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
2280 ~RADEON_HDP_APER_CNTL);
2281 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
2282 return aper_size * 2;
2285 /* Older cards have all sorts of funny issues to deal with. First
2286 * check if it's a multifunction card by reading the PCI config
2287 * header type... Limit those to one aperture size
2289 pci_read_config_byte(rdev->pdev, 0xe, &byte);
2291 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
2292 DRM_INFO("Limiting VRAM to one aperture\n");
2296 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
2297 * have set it up. We don't write this as it's broken on some ASICs but
2298 * we expect the BIOS to have done the right thing (might be too optimistic...)
2300 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
2301 return aper_size * 2;
2305 void r100_vram_init_sizes(struct radeon_device *rdev)
2307 u64 config_aper_size;
2309 /* work out accessible VRAM */
2310 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2311 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2312 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
2313 /* FIXME we don't use the second aperture yet when we could use it */
2314 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
2315 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2316 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
2317 if (rdev->flags & RADEON_IS_IGP) {
2319 /* read NB_TOM to get the amount of ram stolen for the GPU */
2320 tom = RREG32(RADEON_NB_TOM);
2321 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
2322 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2323 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2325 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
2326 /* Some production boards of m6 will report 0
2329 if (rdev->mc.real_vram_size == 0) {
2330 rdev->mc.real_vram_size = 8192 * 1024;
2331 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
2333 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
2334 * Novell bug 204882 + along with lots of ubuntu ones
2336 if (rdev->mc.aper_size > config_aper_size)
2337 config_aper_size = rdev->mc.aper_size;
2339 if (config_aper_size > rdev->mc.real_vram_size)
2340 rdev->mc.mc_vram_size = config_aper_size;
2342 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
2346 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2350 temp = RREG32(RADEON_CONFIG_CNTL);
2351 if (state == false) {
2352 temp &= ~RADEON_CFG_VGA_RAM_EN;
2353 temp |= RADEON_CFG_VGA_IO_DIS;
2355 temp &= ~RADEON_CFG_VGA_IO_DIS;
2357 WREG32(RADEON_CONFIG_CNTL, temp);
2360 void r100_mc_init(struct radeon_device *rdev)
2364 r100_vram_get_type(rdev);
2365 r100_vram_init_sizes(rdev);
2366 base = rdev->mc.aper_base;
2367 if (rdev->flags & RADEON_IS_IGP)
2368 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2369 radeon_vram_location(rdev, &rdev->mc, base);
2370 rdev->mc.gtt_base_align = 0;
2371 if (!(rdev->flags & RADEON_IS_AGP))
2372 radeon_gtt_location(rdev, &rdev->mc);
2373 radeon_update_bandwidth_info(rdev);
2378 * Indirect registers accessor
2380 void r100_pll_errata_after_index(struct radeon_device *rdev)
2382 if (rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS) {
2383 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2384 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2388 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2390 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2391 * or the chip could hang on a subsequent access
2393 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2397 /* This function is required to workaround a hardware bug in some (all?)
2398 * revisions of the R300. This workaround should be called after every
2399 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2400 * may not be correct.
2402 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2405 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2406 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2407 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2408 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2409 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2413 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2417 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2418 r100_pll_errata_after_index(rdev);
2419 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2420 r100_pll_errata_after_data(rdev);
2424 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2426 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2427 r100_pll_errata_after_index(rdev);
2428 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2429 r100_pll_errata_after_data(rdev);
2432 void r100_set_safe_registers(struct radeon_device *rdev)
2434 if (ASIC_IS_RN50(rdev)) {
2435 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2436 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2437 } else if (rdev->family < CHIP_R200) {
2438 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2439 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2441 r200_set_safe_registers(rdev);
2448 #if defined(CONFIG_DEBUG_FS)
2449 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2451 struct drm_info_node *node = (struct drm_info_node *) m->private;
2452 struct drm_device *dev = node->minor->dev;
2453 struct radeon_device *rdev = dev->dev_private;
2454 uint32_t reg, value;
2457 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2458 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2459 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2460 for (i = 0; i < 64; i++) {
2461 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2462 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2463 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2464 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2465 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2470 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2472 struct drm_info_node *node = (struct drm_info_node *) m->private;
2473 struct drm_device *dev = node->minor->dev;
2474 struct radeon_device *rdev = dev->dev_private;
2476 unsigned count, i, j;
2478 radeon_ring_free_size(rdev);
2479 rdp = RREG32(RADEON_CP_RB_RPTR);
2480 wdp = RREG32(RADEON_CP_RB_WPTR);
2481 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2482 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2483 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2484 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2485 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2486 seq_printf(m, "%u dwords in ring\n", count);
2487 for (j = 0; j <= count; j++) {
2488 i = (rdp + j) & rdev->cp.ptr_mask;
2489 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2495 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2497 struct drm_info_node *node = (struct drm_info_node *) m->private;
2498 struct drm_device *dev = node->minor->dev;
2499 struct radeon_device *rdev = dev->dev_private;
2500 uint32_t csq_stat, csq2_stat, tmp;
2501 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2504 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2505 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2506 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2507 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2508 r_rptr = (csq_stat >> 0) & 0x3ff;
2509 r_wptr = (csq_stat >> 10) & 0x3ff;
2510 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2511 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2512 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2513 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2514 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2515 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2516 seq_printf(m, "Ring rptr %u\n", r_rptr);
2517 seq_printf(m, "Ring wptr %u\n", r_wptr);
2518 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2519 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2520 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2521 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2522 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2523 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2524 seq_printf(m, "Ring fifo:\n");
2525 for (i = 0; i < 256; i++) {
2526 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2527 tmp = RREG32(RADEON_CP_CSQ_DATA);
2528 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2530 seq_printf(m, "Indirect1 fifo:\n");
2531 for (i = 256; i <= 512; i++) {
2532 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2533 tmp = RREG32(RADEON_CP_CSQ_DATA);
2534 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2536 seq_printf(m, "Indirect2 fifo:\n");
2537 for (i = 640; i < ib1_wptr; i++) {
2538 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2539 tmp = RREG32(RADEON_CP_CSQ_DATA);
2540 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2545 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2547 struct drm_info_node *node = (struct drm_info_node *) m->private;
2548 struct drm_device *dev = node->minor->dev;
2549 struct radeon_device *rdev = dev->dev_private;
2552 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2553 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2554 tmp = RREG32(RADEON_MC_FB_LOCATION);
2555 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2556 tmp = RREG32(RADEON_BUS_CNTL);
2557 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2558 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2559 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2560 tmp = RREG32(RADEON_AGP_BASE);
2561 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2562 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2563 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2564 tmp = RREG32(0x01D0);
2565 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2566 tmp = RREG32(RADEON_AIC_LO_ADDR);
2567 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2568 tmp = RREG32(RADEON_AIC_HI_ADDR);
2569 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2570 tmp = RREG32(0x01E4);
2571 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2575 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2576 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2579 static struct drm_info_list r100_debugfs_cp_list[] = {
2580 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2581 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2584 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2585 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2589 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2591 #if defined(CONFIG_DEBUG_FS)
2592 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2598 int r100_debugfs_cp_init(struct radeon_device *rdev)
2600 #if defined(CONFIG_DEBUG_FS)
2601 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2607 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2609 #if defined(CONFIG_DEBUG_FS)
2610 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2616 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2617 uint32_t tiling_flags, uint32_t pitch,
2618 uint32_t offset, uint32_t obj_size)
2620 int surf_index = reg * 16;
2623 if (rdev->family <= CHIP_RS200) {
2624 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2625 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2626 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2627 if (tiling_flags & RADEON_TILING_MACRO)
2628 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2629 } else if (rdev->family <= CHIP_RV280) {
2630 if (tiling_flags & (RADEON_TILING_MACRO))
2631 flags |= R200_SURF_TILE_COLOR_MACRO;
2632 if (tiling_flags & RADEON_TILING_MICRO)
2633 flags |= R200_SURF_TILE_COLOR_MICRO;
2635 if (tiling_flags & RADEON_TILING_MACRO)
2636 flags |= R300_SURF_TILE_MACRO;
2637 if (tiling_flags & RADEON_TILING_MICRO)
2638 flags |= R300_SURF_TILE_MICRO;
2641 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2642 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2643 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2644 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2646 /* when we aren't tiling the pitch seems to needs to be furtherdivided down. - tested on power5 + rn50 server */
2647 if (tiling_flags & (RADEON_TILING_SWAP_16BIT | RADEON_TILING_SWAP_32BIT)) {
2648 if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO)))
2649 if (ASIC_IS_RN50(rdev))
2653 /* r100/r200 divide by 16 */
2654 if (rdev->family < CHIP_R300)
2655 flags |= pitch / 16;
2660 DRM_DEBUG_KMS("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2661 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2662 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2663 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2667 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2669 int surf_index = reg * 16;
2670 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2673 void r100_bandwidth_update(struct radeon_device *rdev)
2675 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2676 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2677 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2678 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2679 fixed20_12 memtcas_ff[8] = {
2684 dfixed_init_half(1),
2685 dfixed_init_half(2),
2688 fixed20_12 memtcas_rs480_ff[8] = {
2694 dfixed_init_half(1),
2695 dfixed_init_half(2),
2696 dfixed_init_half(3),
2698 fixed20_12 memtcas2_ff[8] = {
2708 fixed20_12 memtrbs[8] = {
2710 dfixed_init_half(1),
2712 dfixed_init_half(2),
2714 dfixed_init_half(3),
2718 fixed20_12 memtrbs_r4xx[8] = {
2728 fixed20_12 min_mem_eff;
2729 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2730 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2731 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2732 disp_drain_rate2, read_return_rate;
2733 fixed20_12 time_disp1_drop_priority;
2735 int cur_size = 16; /* in octawords */
2736 int critical_point = 0, critical_point2;
2737 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2738 int stop_req, max_stop_req;
2739 struct drm_display_mode *mode1 = NULL;
2740 struct drm_display_mode *mode2 = NULL;
2741 uint32_t pixel_bytes1 = 0;
2742 uint32_t pixel_bytes2 = 0;
2744 radeon_update_display_priority(rdev);
2746 if (rdev->mode_info.crtcs[0]->base.enabled) {
2747 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2748 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2750 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2751 if (rdev->mode_info.crtcs[1]->base.enabled) {
2752 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2753 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2757 min_mem_eff.full = dfixed_const_8(0);
2759 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2760 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2761 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2762 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2763 /* check crtc enables */
2765 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2767 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2768 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2772 * determine is there is enough bw for current mode
2774 sclk_ff = rdev->pm.sclk;
2775 mclk_ff = rdev->pm.mclk;
2777 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2778 temp_ff.full = dfixed_const(temp);
2779 mem_bw.full = dfixed_mul(mclk_ff, temp_ff);
2783 peak_disp_bw.full = 0;
2785 temp_ff.full = dfixed_const(1000);
2786 pix_clk.full = dfixed_const(mode1->clock); /* convert to fixed point */
2787 pix_clk.full = dfixed_div(pix_clk, temp_ff);
2788 temp_ff.full = dfixed_const(pixel_bytes1);
2789 peak_disp_bw.full += dfixed_mul(pix_clk, temp_ff);
2792 temp_ff.full = dfixed_const(1000);
2793 pix_clk2.full = dfixed_const(mode2->clock); /* convert to fixed point */
2794 pix_clk2.full = dfixed_div(pix_clk2, temp_ff);
2795 temp_ff.full = dfixed_const(pixel_bytes2);
2796 peak_disp_bw.full += dfixed_mul(pix_clk2, temp_ff);
2799 mem_bw.full = dfixed_mul(mem_bw, min_mem_eff);
2800 if (peak_disp_bw.full >= mem_bw.full) {
2801 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2802 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2805 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2806 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2807 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2808 mem_trcd = ((temp >> 2) & 0x3) + 1;
2809 mem_trp = ((temp & 0x3)) + 1;
2810 mem_tras = ((temp & 0x70) >> 4) + 1;
2811 } else if (rdev->family == CHIP_R300 ||
2812 rdev->family == CHIP_R350) { /* r300, r350 */
2813 mem_trcd = (temp & 0x7) + 1;
2814 mem_trp = ((temp >> 8) & 0x7) + 1;
2815 mem_tras = ((temp >> 11) & 0xf) + 4;
2816 } else if (rdev->family == CHIP_RV350 ||
2817 rdev->family <= CHIP_RV380) {
2819 mem_trcd = (temp & 0x7) + 3;
2820 mem_trp = ((temp >> 8) & 0x7) + 3;
2821 mem_tras = ((temp >> 11) & 0xf) + 6;
2822 } else if (rdev->family == CHIP_R420 ||
2823 rdev->family == CHIP_R423 ||
2824 rdev->family == CHIP_RV410) {
2826 mem_trcd = (temp & 0xf) + 3;
2829 mem_trp = ((temp >> 8) & 0xf) + 3;
2832 mem_tras = ((temp >> 12) & 0x1f) + 6;
2835 } else { /* RV200, R200 */
2836 mem_trcd = (temp & 0x7) + 1;
2837 mem_trp = ((temp >> 8) & 0x7) + 1;
2838 mem_tras = ((temp >> 12) & 0xf) + 4;
2841 trcd_ff.full = dfixed_const(mem_trcd);
2842 trp_ff.full = dfixed_const(mem_trp);
2843 tras_ff.full = dfixed_const(mem_tras);
2845 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2846 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2847 data = (temp & (7 << 20)) >> 20;
2848 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2849 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2850 tcas_ff = memtcas_rs480_ff[data];
2852 tcas_ff = memtcas_ff[data];
2854 tcas_ff = memtcas2_ff[data];
2856 if (rdev->family == CHIP_RS400 ||
2857 rdev->family == CHIP_RS480) {
2858 /* extra cas latency stored in bits 23-25 0-4 clocks */
2859 data = (temp >> 23) & 0x7;
2861 tcas_ff.full += dfixed_const(data);
2864 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2865 /* on the R300, Tcas is included in Trbs.
2867 temp = RREG32(RADEON_MEM_CNTL);
2868 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2870 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2871 temp = RREG32(R300_MC_IND_INDEX);
2872 temp &= ~R300_MC_IND_ADDR_MASK;
2873 temp |= R300_MC_READ_CNTL_CD_mcind;
2874 WREG32(R300_MC_IND_INDEX, temp);
2875 temp = RREG32(R300_MC_IND_DATA);
2876 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2878 temp = RREG32(R300_MC_READ_CNTL_AB);
2879 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2882 temp = RREG32(R300_MC_READ_CNTL_AB);
2883 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2885 if (rdev->family == CHIP_RV410 ||
2886 rdev->family == CHIP_R420 ||
2887 rdev->family == CHIP_R423)
2888 trbs_ff = memtrbs_r4xx[data];
2890 trbs_ff = memtrbs[data];
2891 tcas_ff.full += trbs_ff.full;
2894 sclk_eff_ff.full = sclk_ff.full;
2896 if (rdev->flags & RADEON_IS_AGP) {
2897 fixed20_12 agpmode_ff;
2898 agpmode_ff.full = dfixed_const(radeon_agpmode);
2899 temp_ff.full = dfixed_const_666(16);
2900 sclk_eff_ff.full -= dfixed_mul(agpmode_ff, temp_ff);
2902 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2904 if (ASIC_IS_R300(rdev)) {
2905 sclk_delay_ff.full = dfixed_const(250);
2907 if ((rdev->family == CHIP_RV100) ||
2908 rdev->flags & RADEON_IS_IGP) {
2909 if (rdev->mc.vram_is_ddr)
2910 sclk_delay_ff.full = dfixed_const(41);
2912 sclk_delay_ff.full = dfixed_const(33);
2914 if (rdev->mc.vram_width == 128)
2915 sclk_delay_ff.full = dfixed_const(57);
2917 sclk_delay_ff.full = dfixed_const(41);
2921 mc_latency_sclk.full = dfixed_div(sclk_delay_ff, sclk_eff_ff);
2923 if (rdev->mc.vram_is_ddr) {
2924 if (rdev->mc.vram_width == 32) {
2925 k1.full = dfixed_const(40);
2928 k1.full = dfixed_const(20);
2932 k1.full = dfixed_const(40);
2936 temp_ff.full = dfixed_const(2);
2937 mc_latency_mclk.full = dfixed_mul(trcd_ff, temp_ff);
2938 temp_ff.full = dfixed_const(c);
2939 mc_latency_mclk.full += dfixed_mul(tcas_ff, temp_ff);
2940 temp_ff.full = dfixed_const(4);
2941 mc_latency_mclk.full += dfixed_mul(tras_ff, temp_ff);
2942 mc_latency_mclk.full += dfixed_mul(trp_ff, temp_ff);
2943 mc_latency_mclk.full += k1.full;
2945 mc_latency_mclk.full = dfixed_div(mc_latency_mclk, mclk_ff);
2946 mc_latency_mclk.full += dfixed_div(temp_ff, sclk_eff_ff);
2949 HW cursor time assuming worst case of full size colour cursor.
2951 temp_ff.full = dfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2952 temp_ff.full += trcd_ff.full;
2953 if (temp_ff.full < tras_ff.full)
2954 temp_ff.full = tras_ff.full;
2955 cur_latency_mclk.full = dfixed_div(temp_ff, mclk_ff);
2957 temp_ff.full = dfixed_const(cur_size);
2958 cur_latency_sclk.full = dfixed_div(temp_ff, sclk_eff_ff);
2960 Find the total latency for the display data.
2962 disp_latency_overhead.full = dfixed_const(8);
2963 disp_latency_overhead.full = dfixed_div(disp_latency_overhead, sclk_ff);
2964 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2965 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2967 if (mc_latency_mclk.full > mc_latency_sclk.full)
2968 disp_latency.full = mc_latency_mclk.full;
2970 disp_latency.full = mc_latency_sclk.full;
2972 /* setup Max GRPH_STOP_REQ default value */
2973 if (ASIC_IS_RV100(rdev))
2974 max_stop_req = 0x5c;
2976 max_stop_req = 0x7c;
2980 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2981 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2983 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2985 if (stop_req > max_stop_req)
2986 stop_req = max_stop_req;
2989 Find the drain rate of the display buffer.
2991 temp_ff.full = dfixed_const((16/pixel_bytes1));
2992 disp_drain_rate.full = dfixed_div(pix_clk, temp_ff);
2995 Find the critical point of the display buffer.
2997 crit_point_ff.full = dfixed_mul(disp_drain_rate, disp_latency);
2998 crit_point_ff.full += dfixed_const_half(0);
3000 critical_point = dfixed_trunc(crit_point_ff);
3002 if (rdev->disp_priority == 2) {
3007 The critical point should never be above max_stop_req-4. Setting
3008 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
3010 if (max_stop_req - critical_point < 4)
3013 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
3014 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
3015 critical_point = 0x10;
3018 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
3019 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
3020 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3021 temp &= ~(RADEON_GRPH_START_REQ_MASK);
3022 if ((rdev->family == CHIP_R350) &&
3023 (stop_req > 0x15)) {
3026 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3027 temp |= RADEON_GRPH_BUFFER_SIZE;
3028 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
3029 RADEON_GRPH_CRITICAL_AT_SOF |
3030 RADEON_GRPH_STOP_CNTL);
3032 Write the result into the register.
3034 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3035 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3038 if ((rdev->family == CHIP_RS400) ||
3039 (rdev->family == CHIP_RS480)) {
3040 /* attempt to program RS400 disp regs correctly ??? */
3041 temp = RREG32(RS400_DISP1_REG_CNTL);
3042 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
3043 RS400_DISP1_STOP_REQ_LEVEL_MASK);
3044 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
3045 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3046 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3047 temp = RREG32(RS400_DMIF_MEM_CNTL1);
3048 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
3049 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
3050 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
3051 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
3052 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
3056 DRM_DEBUG_KMS("GRPH_BUFFER_CNTL from to %x\n",
3057 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
3058 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
3063 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
3065 if (stop_req > max_stop_req)
3066 stop_req = max_stop_req;
3069 Find the drain rate of the display buffer.
3071 temp_ff.full = dfixed_const((16/pixel_bytes2));
3072 disp_drain_rate2.full = dfixed_div(pix_clk2, temp_ff);
3074 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
3075 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
3076 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
3077 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
3078 if ((rdev->family == CHIP_R350) &&
3079 (stop_req > 0x15)) {
3082 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
3083 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
3084 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
3085 RADEON_GRPH_CRITICAL_AT_SOF |
3086 RADEON_GRPH_STOP_CNTL);
3088 if ((rdev->family == CHIP_RS100) ||
3089 (rdev->family == CHIP_RS200))
3090 critical_point2 = 0;
3092 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
3093 temp_ff.full = dfixed_const(temp);
3094 temp_ff.full = dfixed_mul(mclk_ff, temp_ff);
3095 if (sclk_ff.full < temp_ff.full)
3096 temp_ff.full = sclk_ff.full;
3098 read_return_rate.full = temp_ff.full;
3101 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
3102 time_disp1_drop_priority.full = dfixed_div(crit_point_ff, temp_ff);
3104 time_disp1_drop_priority.full = 0;
3106 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
3107 crit_point_ff.full = dfixed_mul(crit_point_ff, disp_drain_rate2);
3108 crit_point_ff.full += dfixed_const_half(0);
3110 critical_point2 = dfixed_trunc(crit_point_ff);
3112 if (rdev->disp_priority == 2) {
3113 critical_point2 = 0;
3116 if (max_stop_req - critical_point2 < 4)
3117 critical_point2 = 0;
3121 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
3122 /* some R300 cards have problem with this set to 0 */
3123 critical_point2 = 0x10;
3126 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
3127 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
3129 if ((rdev->family == CHIP_RS400) ||
3130 (rdev->family == CHIP_RS480)) {
3132 /* attempt to program RS400 disp2 regs correctly ??? */
3133 temp = RREG32(RS400_DISP2_REQ_CNTL1);
3134 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
3135 RS400_DISP2_STOP_REQ_LEVEL_MASK);
3136 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
3137 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
3138 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
3139 temp = RREG32(RS400_DISP2_REQ_CNTL2);
3140 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
3141 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
3142 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
3143 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
3144 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
3146 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
3147 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
3148 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
3149 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
3152 DRM_DEBUG_KMS("GRPH2_BUFFER_CNTL from to %x\n",
3153 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
3157 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
3159 DRM_ERROR("pitch %d\n", t->pitch);
3160 DRM_ERROR("use_pitch %d\n", t->use_pitch);
3161 DRM_ERROR("width %d\n", t->width);
3162 DRM_ERROR("width_11 %d\n", t->width_11);
3163 DRM_ERROR("height %d\n", t->height);
3164 DRM_ERROR("height_11 %d\n", t->height_11);
3165 DRM_ERROR("num levels %d\n", t->num_levels);
3166 DRM_ERROR("depth %d\n", t->txdepth);
3167 DRM_ERROR("bpp %d\n", t->cpp);
3168 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
3169 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
3170 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
3171 DRM_ERROR("compress format %d\n", t->compress_format);
3174 static int r100_track_compress_size(int compress_format, int w, int h)
3176 int block_width, block_height, block_bytes;
3177 int wblocks, hblocks;
3184 switch (compress_format) {
3185 case R100_TRACK_COMP_DXT1:
3190 case R100_TRACK_COMP_DXT35:
3196 hblocks = (h + block_height - 1) / block_height;
3197 wblocks = (w + block_width - 1) / block_width;
3198 if (wblocks < min_wblocks)
3199 wblocks = min_wblocks;
3200 sz = wblocks * hblocks * block_bytes;
3204 static int r100_cs_track_cube(struct radeon_device *rdev,
3205 struct r100_cs_track *track, unsigned idx)
3207 unsigned face, w, h;
3208 struct radeon_bo *cube_robj;
3210 unsigned compress_format = track->textures[idx].compress_format;
3212 for (face = 0; face < 5; face++) {
3213 cube_robj = track->textures[idx].cube_info[face].robj;
3214 w = track->textures[idx].cube_info[face].width;
3215 h = track->textures[idx].cube_info[face].height;
3217 if (compress_format) {
3218 size = r100_track_compress_size(compress_format, w, h);
3221 size *= track->textures[idx].cpp;
3223 size += track->textures[idx].cube_info[face].offset;
3225 if (size > radeon_bo_size(cube_robj)) {
3226 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
3227 size, radeon_bo_size(cube_robj));
3228 r100_cs_track_texture_print(&track->textures[idx]);
3235 static int r100_cs_track_texture_check(struct radeon_device *rdev,
3236 struct r100_cs_track *track)
3238 struct radeon_bo *robj;
3240 unsigned u, i, w, h, d;
3243 for (u = 0; u < track->num_texture; u++) {
3244 if (!track->textures[u].enabled)
3246 if (track->textures[u].lookup_disable)
3248 robj = track->textures[u].robj;
3250 DRM_ERROR("No texture bound to unit %u\n", u);
3254 for (i = 0; i <= track->textures[u].num_levels; i++) {
3255 if (track->textures[u].use_pitch) {
3256 if (rdev->family < CHIP_R300)
3257 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
3259 w = track->textures[u].pitch / (1 << i);
3261 w = track->textures[u].width;
3262 if (rdev->family >= CHIP_RV515)
3263 w |= track->textures[u].width_11;
3265 if (track->textures[u].roundup_w)
3266 w = roundup_pow_of_two(w);
3268 h = track->textures[u].height;
3269 if (rdev->family >= CHIP_RV515)
3270 h |= track->textures[u].height_11;
3272 if (track->textures[u].roundup_h)
3273 h = roundup_pow_of_two(h);
3274 if (track->textures[u].tex_coord_type == 1) {
3275 d = (1 << track->textures[u].txdepth) / (1 << i);
3281 if (track->textures[u].compress_format) {
3283 size += r100_track_compress_size(track->textures[u].compress_format, w, h) * d;
3284 /* compressed textures are block based */
3288 size *= track->textures[u].cpp;
3290 switch (track->textures[u].tex_coord_type) {
3295 if (track->separate_cube) {
3296 ret = r100_cs_track_cube(rdev, track, u);
3303 DRM_ERROR("Invalid texture coordinate type %u for unit "
3304 "%u\n", track->textures[u].tex_coord_type, u);
3307 if (size > radeon_bo_size(robj)) {
3308 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
3309 "%lu\n", u, size, radeon_bo_size(robj));
3310 r100_cs_track_texture_print(&track->textures[u]);
3317 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
3323 unsigned num_cb = track->cb_dirty ? track->num_cb : 0;
3325 if (num_cb && !track->zb_cb_clear && !track->color_channel_mask &&
3326 !track->blend_read_enable)
3329 for (i = 0; i < num_cb; i++) {
3330 if (track->cb[i].robj == NULL) {
3331 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
3334 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
3335 size += track->cb[i].offset;
3336 if (size > radeon_bo_size(track->cb[i].robj)) {
3337 DRM_ERROR("[drm] Buffer too small for color buffer %d "
3338 "(need %lu have %lu) !\n", i, size,
3339 radeon_bo_size(track->cb[i].robj));
3340 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
3341 i, track->cb[i].pitch, track->cb[i].cpp,
3342 track->cb[i].offset, track->maxy);
3346 track->cb_dirty = false;
3348 if (track->zb_dirty && track->z_enabled) {
3349 if (track->zb.robj == NULL) {
3350 DRM_ERROR("[drm] No buffer for z buffer !\n");
3353 size = track->zb.pitch * track->zb.cpp * track->maxy;
3354 size += track->zb.offset;
3355 if (size > radeon_bo_size(track->zb.robj)) {
3356 DRM_ERROR("[drm] Buffer too small for z buffer "
3357 "(need %lu have %lu) !\n", size,
3358 radeon_bo_size(track->zb.robj));
3359 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
3360 track->zb.pitch, track->zb.cpp,
3361 track->zb.offset, track->maxy);
3365 track->zb_dirty = false;
3367 if (track->aa_dirty && track->aaresolve) {
3368 if (track->aa.robj == NULL) {
3369 DRM_ERROR("[drm] No buffer for AA resolve buffer %d !\n", i);
3372 /* I believe the format comes from colorbuffer0. */
3373 size = track->aa.pitch * track->cb[0].cpp * track->maxy;
3374 size += track->aa.offset;
3375 if (size > radeon_bo_size(track->aa.robj)) {
3376 DRM_ERROR("[drm] Buffer too small for AA resolve buffer %d "
3377 "(need %lu have %lu) !\n", i, size,
3378 radeon_bo_size(track->aa.robj));
3379 DRM_ERROR("[drm] AA resolve buffer %d (%u %u %u %u)\n",
3380 i, track->aa.pitch, track->cb[0].cpp,
3381 track->aa.offset, track->maxy);
3385 track->aa_dirty = false;
3387 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
3388 if (track->vap_vf_cntl & (1 << 14)) {
3389 nverts = track->vap_alt_nverts;
3391 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
3393 switch (prim_walk) {
3395 for (i = 0; i < track->num_arrays; i++) {
3396 size = track->arrays[i].esize * track->max_indx * 4;
3397 if (track->arrays[i].robj == NULL) {
3398 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3399 "bound\n", prim_walk, i);
3402 if (size > radeon_bo_size(track->arrays[i].robj)) {
3403 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3404 "need %lu dwords have %lu dwords\n",
3405 prim_walk, i, size >> 2,
3406 radeon_bo_size(track->arrays[i].robj)
3408 DRM_ERROR("Max indices %u\n", track->max_indx);
3414 for (i = 0; i < track->num_arrays; i++) {
3415 size = track->arrays[i].esize * (nverts - 1) * 4;
3416 if (track->arrays[i].robj == NULL) {
3417 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3418 "bound\n", prim_walk, i);
3421 if (size > radeon_bo_size(track->arrays[i].robj)) {
3422 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3423 "need %lu dwords have %lu dwords\n",
3424 prim_walk, i, size >> 2,
3425 radeon_bo_size(track->arrays[i].robj)
3432 size = track->vtx_size * nverts;
3433 if (size != track->immd_dwords) {
3434 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3435 track->immd_dwords, size);
3436 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3437 nverts, track->vtx_size);
3442 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3447 if (track->tex_dirty) {
3448 track->tex_dirty = false;
3449 return r100_cs_track_texture_check(rdev, track);
3454 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3458 track->cb_dirty = true;
3459 track->zb_dirty = true;
3460 track->tex_dirty = true;
3461 track->aa_dirty = true;
3463 if (rdev->family < CHIP_R300) {
3465 if (rdev->family <= CHIP_RS200)
3466 track->num_texture = 3;
3468 track->num_texture = 6;
3470 track->separate_cube = 1;
3473 track->num_texture = 16;
3475 track->separate_cube = 0;
3476 track->aaresolve = false;
3477 track->aa.robj = NULL;
3480 for (i = 0; i < track->num_cb; i++) {
3481 track->cb[i].robj = NULL;
3482 track->cb[i].pitch = 8192;
3483 track->cb[i].cpp = 16;
3484 track->cb[i].offset = 0;
3486 track->z_enabled = true;
3487 track->zb.robj = NULL;
3488 track->zb.pitch = 8192;
3490 track->zb.offset = 0;
3491 track->vtx_size = 0x7F;
3492 track->immd_dwords = 0xFFFFFFFFUL;
3493 track->num_arrays = 11;
3494 track->max_indx = 0x00FFFFFFUL;
3495 for (i = 0; i < track->num_arrays; i++) {
3496 track->arrays[i].robj = NULL;
3497 track->arrays[i].esize = 0x7F;
3499 for (i = 0; i < track->num_texture; i++) {
3500 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3501 track->textures[i].pitch = 16536;
3502 track->textures[i].width = 16536;
3503 track->textures[i].height = 16536;
3504 track->textures[i].width_11 = 1 << 11;
3505 track->textures[i].height_11 = 1 << 11;
3506 track->textures[i].num_levels = 12;
3507 if (rdev->family <= CHIP_RS200) {
3508 track->textures[i].tex_coord_type = 0;
3509 track->textures[i].txdepth = 0;
3511 track->textures[i].txdepth = 16;
3512 track->textures[i].tex_coord_type = 1;
3514 track->textures[i].cpp = 64;
3515 track->textures[i].robj = NULL;
3516 /* CS IB emission code makes sure texture unit are disabled */
3517 track->textures[i].enabled = false;
3518 track->textures[i].lookup_disable = false;
3519 track->textures[i].roundup_w = true;
3520 track->textures[i].roundup_h = true;
3521 if (track->separate_cube)
3522 for (face = 0; face < 5; face++) {
3523 track->textures[i].cube_info[face].robj = NULL;
3524 track->textures[i].cube_info[face].width = 16536;
3525 track->textures[i].cube_info[face].height = 16536;
3526 track->textures[i].cube_info[face].offset = 0;
3531 int r100_ring_test(struct radeon_device *rdev)
3538 r = radeon_scratch_get(rdev, &scratch);
3540 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3543 WREG32(scratch, 0xCAFEDEAD);
3544 r = radeon_ring_lock(rdev, 2);
3546 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3547 radeon_scratch_free(rdev, scratch);
3550 radeon_ring_write(rdev, PACKET0(scratch, 0));
3551 radeon_ring_write(rdev, 0xDEADBEEF);
3552 radeon_ring_unlock_commit(rdev);
3553 for (i = 0; i < rdev->usec_timeout; i++) {
3554 tmp = RREG32(scratch);
3555 if (tmp == 0xDEADBEEF) {
3560 if (i < rdev->usec_timeout) {
3561 DRM_INFO("ring test succeeded in %d usecs\n", i);
3563 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
3567 radeon_scratch_free(rdev, scratch);
3571 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3573 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3574 radeon_ring_write(rdev, ib->gpu_addr);
3575 radeon_ring_write(rdev, ib->length_dw);
3578 int r100_ib_test(struct radeon_device *rdev)
3580 struct radeon_ib *ib;
3586 r = radeon_scratch_get(rdev, &scratch);
3588 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3591 WREG32(scratch, 0xCAFEDEAD);
3592 r = radeon_ib_get(rdev, &ib);
3596 ib->ptr[0] = PACKET0(scratch, 0);
3597 ib->ptr[1] = 0xDEADBEEF;
3598 ib->ptr[2] = PACKET2(0);
3599 ib->ptr[3] = PACKET2(0);
3600 ib->ptr[4] = PACKET2(0);
3601 ib->ptr[5] = PACKET2(0);
3602 ib->ptr[6] = PACKET2(0);
3603 ib->ptr[7] = PACKET2(0);
3605 r = radeon_ib_schedule(rdev, ib);
3607 radeon_scratch_free(rdev, scratch);
3608 radeon_ib_free(rdev, &ib);
3611 r = radeon_fence_wait(ib->fence, false);
3615 for (i = 0; i < rdev->usec_timeout; i++) {
3616 tmp = RREG32(scratch);
3617 if (tmp == 0xDEADBEEF) {
3622 if (i < rdev->usec_timeout) {
3623 DRM_INFO("ib test succeeded in %u usecs\n", i);
3625 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
3629 radeon_scratch_free(rdev, scratch);
3630 radeon_ib_free(rdev, &ib);
3634 void r100_ib_fini(struct radeon_device *rdev)
3636 radeon_ib_pool_fini(rdev);
3639 int r100_ib_init(struct radeon_device *rdev)
3643 r = radeon_ib_pool_init(rdev);
3645 dev_err(rdev->dev, "failed initializing IB pool (%d).\n", r);
3649 r = r100_ib_test(rdev);
3651 dev_err(rdev->dev, "failed testing IB (%d).\n", r);
3658 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3660 /* Shutdown CP we shouldn't need to do that but better be safe than
3663 rdev->cp.ready = false;
3664 WREG32(R_000740_CP_CSQ_CNTL, 0);
3666 /* Save few CRTC registers */
3667 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3668 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3669 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3670 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3671 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3672 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3673 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3676 /* Disable VGA aperture access */
3677 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3678 /* Disable cursor, overlay, crtc */
3679 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3680 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3681 S_000054_CRTC_DISPLAY_DIS(1));
3682 WREG32(R_000050_CRTC_GEN_CNTL,
3683 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3684 S_000050_CRTC_DISP_REQ_EN_B(1));
3685 WREG32(R_000420_OV0_SCALE_CNTL,
3686 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3687 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3688 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3689 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3690 S_000360_CUR2_LOCK(1));
3691 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3692 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3693 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3694 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3695 WREG32(R_000360_CUR2_OFFSET,
3696 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3700 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3702 /* Update base address for crtc */
3703 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3704 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3705 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3707 /* Restore CRTC registers */
3708 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3709 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3710 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3711 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3712 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3716 void r100_vga_render_disable(struct radeon_device *rdev)
3720 tmp = RREG8(R_0003C2_GENMO_WT);
3721 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3724 static void r100_debugfs(struct radeon_device *rdev)
3728 r = r100_debugfs_mc_info_init(rdev);
3730 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3733 static void r100_mc_program(struct radeon_device *rdev)
3735 struct r100_mc_save save;
3737 /* Stops all mc clients */
3738 r100_mc_stop(rdev, &save);
3739 if (rdev->flags & RADEON_IS_AGP) {
3740 WREG32(R_00014C_MC_AGP_LOCATION,
3741 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3742 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3743 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3744 if (rdev->family > CHIP_RV200)
3745 WREG32(R_00015C_AGP_BASE_2,
3746 upper_32_bits(rdev->mc.agp_base) & 0xff);
3748 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3749 WREG32(R_000170_AGP_BASE, 0);
3750 if (rdev->family > CHIP_RV200)
3751 WREG32(R_00015C_AGP_BASE_2, 0);
3753 /* Wait for mc idle */
3754 if (r100_mc_wait_for_idle(rdev))
3755 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3756 /* Program MC, should be a 32bits limited address space */
3757 WREG32(R_000148_MC_FB_LOCATION,
3758 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3759 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3760 r100_mc_resume(rdev, &save);
3763 void r100_clock_startup(struct radeon_device *rdev)
3767 if (radeon_dynclks != -1 && radeon_dynclks)
3768 radeon_legacy_set_clock_gating(rdev, 1);
3769 /* We need to force on some of the block */
3770 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3771 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3772 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3773 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3774 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3777 static int r100_startup(struct radeon_device *rdev)
3781 /* set common regs */
3782 r100_set_common_regs(rdev);
3784 r100_mc_program(rdev);
3786 r100_clock_startup(rdev);
3787 /* Initialize GART (initialize after TTM so we can allocate
3788 * memory through TTM but finalize after TTM) */
3789 r100_enable_bm(rdev);
3790 if (rdev->flags & RADEON_IS_PCI) {
3791 r = r100_pci_gart_enable(rdev);
3796 /* allocate wb buffer */
3797 r = radeon_wb_init(rdev);
3803 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3804 /* 1M ring buffer */
3805 r = r100_cp_init(rdev, 1024 * 1024);
3807 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
3810 r = r100_ib_init(rdev);
3812 dev_err(rdev->dev, "failed initializing IB (%d).\n", r);
3818 int r100_resume(struct radeon_device *rdev)
3820 /* Make sur GART are not working */
3821 if (rdev->flags & RADEON_IS_PCI)
3822 r100_pci_gart_disable(rdev);
3823 /* Resume clock before doing reset */
3824 r100_clock_startup(rdev);
3825 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3826 if (radeon_asic_reset(rdev)) {
3827 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3828 RREG32(R_000E40_RBBM_STATUS),
3829 RREG32(R_0007C0_CP_STAT));
3832 radeon_combios_asic_init(rdev->ddev);
3833 /* Resume clock after posting */
3834 r100_clock_startup(rdev);
3835 /* Initialize surface registers */
3836 radeon_surface_init(rdev);
3837 return r100_startup(rdev);
3840 int r100_suspend(struct radeon_device *rdev)
3842 r100_cp_disable(rdev);
3843 radeon_wb_disable(rdev);
3844 r100_irq_disable(rdev);
3845 if (rdev->flags & RADEON_IS_PCI)
3846 r100_pci_gart_disable(rdev);
3850 void r100_fini(struct radeon_device *rdev)
3853 radeon_wb_fini(rdev);
3855 radeon_gem_fini(rdev);
3856 if (rdev->flags & RADEON_IS_PCI)
3857 r100_pci_gart_fini(rdev);
3858 radeon_agp_fini(rdev);
3859 radeon_irq_kms_fini(rdev);
3860 radeon_fence_driver_fini(rdev);
3861 radeon_bo_fini(rdev);
3862 radeon_atombios_fini(rdev);
3868 * Due to how kexec works, it can leave the hw fully initialised when it
3869 * boots the new kernel. However doing our init sequence with the CP and
3870 * WB stuff setup causes GPU hangs on the RN50 at least. So at startup
3871 * do some quick sanity checks and restore sane values to avoid this
3874 void r100_restore_sanity(struct radeon_device *rdev)
3878 tmp = RREG32(RADEON_CP_CSQ_CNTL);
3880 WREG32(RADEON_CP_CSQ_CNTL, 0);
3882 tmp = RREG32(RADEON_CP_RB_CNTL);
3884 WREG32(RADEON_CP_RB_CNTL, 0);
3886 tmp = RREG32(RADEON_SCRATCH_UMSK);
3888 WREG32(RADEON_SCRATCH_UMSK, 0);
3892 int r100_init(struct radeon_device *rdev)
3896 /* Register debugfs file specific to this group of asics */
3899 r100_vga_render_disable(rdev);
3900 /* Initialize scratch registers */
3901 radeon_scratch_init(rdev);
3902 /* Initialize surface registers */
3903 radeon_surface_init(rdev);
3904 /* sanity check some register to avoid hangs like after kexec */
3905 r100_restore_sanity(rdev);
3906 /* TODO: disable VGA need to use VGA request */
3908 if (!radeon_get_bios(rdev)) {
3909 if (ASIC_IS_AVIVO(rdev))
3912 if (rdev->is_atom_bios) {
3913 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3916 r = radeon_combios_init(rdev);
3920 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3921 if (radeon_asic_reset(rdev)) {
3923 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3924 RREG32(R_000E40_RBBM_STATUS),
3925 RREG32(R_0007C0_CP_STAT));
3927 /* check if cards are posted or not */
3928 if (radeon_boot_test_post_card(rdev) == false)
3930 /* Set asic errata */
3932 /* Initialize clocks */
3933 radeon_get_clock_info(rdev->ddev);
3934 /* initialize AGP */
3935 if (rdev->flags & RADEON_IS_AGP) {
3936 r = radeon_agp_init(rdev);
3938 radeon_agp_disable(rdev);
3941 /* initialize VRAM */
3944 r = radeon_fence_driver_init(rdev);
3947 r = radeon_irq_kms_init(rdev);
3950 /* Memory manager */
3951 r = radeon_bo_init(rdev);
3954 if (rdev->flags & RADEON_IS_PCI) {
3955 r = r100_pci_gart_init(rdev);
3959 r100_set_safe_registers(rdev);
3960 rdev->accel_working = true;
3961 r = r100_startup(rdev);
3963 /* Somethings want wront with the accel init stop accel */
3964 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3966 radeon_wb_fini(rdev);
3968 radeon_irq_kms_fini(rdev);
3969 if (rdev->flags & RADEON_IS_PCI)
3970 r100_pci_gart_fini(rdev);
3971 rdev->accel_working = false;