2 #define R100_TRACK_MAX_TEXTURE 3
3 #define R200_TRACK_MAX_TEXTURE 6
4 #define R300_TRACK_MAX_TEXTURE 16
12 struct r100_cs_track_cb {
13 struct radeon_bo *robj;
19 struct r100_cs_track_array {
20 struct radeon_bo *robj;
24 struct r100_cs_cube_info {
25 struct radeon_bo *robj;
31 #define R100_TRACK_COMP_NONE 0
32 #define R100_TRACK_COMP_DXT1 1
33 #define R100_TRACK_COMP_DXT35 2
35 struct r100_cs_track_texture {
36 struct radeon_bo *robj;
37 struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */
43 unsigned tex_coord_type;
52 unsigned compress_format;
55 struct r100_cs_track {
61 unsigned vap_alt_nverts;
65 unsigned color_channel_mask;
66 struct r100_cs_track_array arrays[16];
67 struct r100_cs_track_cb cb[R300_MAX_CB];
68 struct r100_cs_track_cb zb;
69 struct r100_cs_track_cb aa;
70 struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE];
74 bool blend_read_enable;
82 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track);
83 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track);
85 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
87 int r200_packet0_check(struct radeon_cs_parser *p,
88 struct radeon_cs_packet *pkt,
89 unsigned idx, unsigned reg);
91 int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
92 struct radeon_cs_packet *pkt,
95 int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
96 struct radeon_cs_packet *pkt,